WO2000031783A1 - Fabrication de couches de nitrure de gallium sur du silicium - Google Patents

Fabrication de couches de nitrure de gallium sur du silicium Download PDF

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WO2000031783A1
WO2000031783A1 PCT/US1999/027358 US9927358W WO0031783A1 WO 2000031783 A1 WO2000031783 A1 WO 2000031783A1 US 9927358 W US9927358 W US 9927358W WO 0031783 A1 WO0031783 A1 WO 0031783A1
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layer
gallium nitride
silicon
silicon carbide
growing
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PCT/US1999/027358
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Kevin J. Linthicum
Thomas Gehrke
Robert F. Davis
Darren B. Thomson
Kieran M. Tracy
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North Carolina State University
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Priority to AU21520/00A priority Critical patent/AU2152000A/en
Publication of WO2000031783A1 publication Critical patent/WO2000031783A1/fr

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Definitions

  • This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
  • gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
  • a major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
  • This technique often is referred to as "Epitaxial Lateral Overgrowth" (ELO).
  • ELO Epiaxial Lateral Overgrowth
  • the layer of gallium nitride may be laterally grown until the gallium nitride coalesces on the mask to form a single layer on the mask.
  • a second mask may be formed on the laterally overgrown gallium nitride layer, that includes at least one opening that is offset from the underlying mask. ELO then again is performed through the openings in the second mask to thereby overgrow a second low defect density continuous gallium nitride layer. Microelectronic devices then may be formed in this second overgrown layer.
  • ELO of gallium nitride is described, for example, in the publications entitled Lateral Epitaxy of Low Defect Density GaN Layers Via Organometallic Vapor Phase Epitaxy to Nam et al., Appl. Phys. Lett. Vol. 71, No.
  • ELO and pendeoepitaxy can provide relatively large, low defect gallium nitride layers for microelectronic applications.
  • a major concern that may limit the mass production of gallium nitride devices is the growth of the gallium nitride layers on a silicon carbide substrate.
  • silicon carbide substrates still may be relatively expensive compared to conventional silicon substrates.
  • silicon carbide substrates generally are smaller than silicon substrates, which can reduce the number of devices that can be formed on a wafer.
  • large investments are being made in silicon carbide processing equipment, even larger investments already have been made in conventional silicon substrate processing equipment. Accordingly, the use of an underlying silicon carbide substrate for fabricating gallium nitride microelectronic structures may adversely impact the cost and/or availability of gallium nitride devices.
  • the present invention provides methods of fabricating a gallium nitride microelectronic layer by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer.
  • the silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide.
  • the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate.
  • the (111) silicon layer is a portion of a Silicon- On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate.
  • SOI Silicon- On-Insulator
  • the present invention can use conventional bulk silicon, SIMOX and SOI substrates as a base or platform for fabricating a gallium nitride microelectronic layer.
  • conventional silicon technology low cost and/or large area silicon substrates may be used and conventional silicon wafer processing systems also may be used. Accordingly, low cost and/or high volume production of gallium nitride microelectronic layers may be provided.
  • the surface of the (111) silicon layer preferably is converted to 3C-silicon carbide by chemically reacting the surface of the (111) silicon layer with a carbon containing precursor such as ethylene, to convert the surface of the (111) silicon layer to 3C-silicon carbide.
  • the layer of 3C-silicon carbide then may be epitaxially grown on the converted surface using standard vapor phase epitaxial techniques for silicon carbide. Alternatively, the layer of 3C-silicon carbide may be grown directly on the (111) silicon layer, without the need for conversion.
  • the epitaxially grown layer of 3C-silicon carbide may be thinned.
  • an aluminum nitride and/or gallium nitride buffer layer preferably is grown on the epitaxially grown layer of 3C-silicon carbide.
  • the gallium nitride then is grown on the buffer layer, opposite the epitaxially grown layer of 3C-silicon carbide.
  • Lateral growth of the layer of 2H-gallium nitride may be performed by ELO wherein a mask is formed on the layer of 2H-gallium nitride, the mask including at least one opening that exposes the layer of 2H-gallium nitride.
  • the layer of 2H- gallium nitride then is laterally grown through the at least one opening and onto the mask.
  • a second, offset mask also may be formed on the laterally grown layer of 2H- gallium nitride and a second laterally grown layer of 2H-gallium nitride may be overgrown onto the offset mask.
  • Lateral growth of the layer of 2H-gallium nitride also may be performed using pendeoepitaxial techniques wherein at least one trench and/or post is formed in a layer of 2H-gallium nitride to define at least one sidewall therein.
  • the layer of 2H-gallium nitride then is laterally grown from the at least one sidewall.
  • Pendeoepitaxial lateral growth preferably continues until the laterally grown sidewalls coalesce on the top of the posts or trenches.
  • the top of the posts and/or the trench floors may be masked to promote lateral growth and reduce nucleation and vertical growth.
  • the trenches preferably extend into the silicon carbide layer to also reduce nucleation and vertical growth.
  • the present invention can use bulk silicon substrates, SIMOX substrates or SOI substrates as a platform for gallium nitride fabrication. Preferred methods using each of these substrates now will be described.
  • the surface of the (1 11) silicon substrate preferably is converted to 3C-silicon carbide and a layer of 3C-silicon carbide then is epitaxially grown on the converted surface of the (111) silicon substrate.
  • the epitaxially grown layer of 3C-silicon carbide may be thinned.
  • An aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C- silicon carbide.
  • a layer of 2H-gallium nitride is grown on the buffer layer.
  • the layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer.
  • the lateral growth may proceed using ELO, pendeoepitaxy and/or other techniques.
  • oxygen is implanted into a (111) silicon substrate to form a buried silicon dioxide layer that defines a (1 1 1) silicon surface layer on the (111) silicon substrate. At least a portion of the (111) silicon surface layer, and preferably all of the (111) silicon surface layer, is converted to 3C-silicon carbide. A layer of 3C-silicon carbide then is epitaxially grown on the converted (1 1 1) silicon surface layer. The epitaxially grown layer of 3C-silicon carbide then may be thinned and an aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C-silicon carbide.
  • a layer of 2H-gallium nitride then is grown on the buffer layer.
  • the layer of 2H-gallium nitride then is laterally grown, using ELO, pendeoepitaxy and/or other techniques to produce the gallium nitride microelectronic layer.
  • a (111) silicon substrate is bonded to another substrate, preferably a (100) silicon substrate.
  • the (111) silicon substrate is thinned to define a (111) silicon layer on the (100) silicon substrate. At least a portion, and preferably all, of the (111) silicon layer is converted to 3C-silicon carbide.
  • a layer of 3C-silicon carbide is epitaxially grown on the converted (111) silicon layer.
  • the epitaxially grown layer of 3C-silicon carbide may be thinned and an aluminum nitride and/or gallium nitride buffer layer is grown on the epitaxially grown layer of 3C-silicon carbide.
  • a layer of 2H-gallium nitride then is grown on the buffer layer and the layer of 2H-gallium nitride is laterally grown, using ELO, pendeoepitaxy and/or other techniques to produce the gallium nitride microelectronic layer.
  • microelectronic devices also may be formed in the (100) silicon substrate, prior to or after forming the gallium nitride microelectronic layer.
  • a portion of the (11 1) silicon layer, the 3C-silicon carbide layer, the gallium nitride layer and the gallium nitride microelectronic layer may be removed to expose the microelectronic devices in the (100) silicon substrate.
  • an epitaxial silicon layer may be grown from the exposed portion of the (100) silicon substrate, and microelectronic devices may be formed in the epitaxial silicon layer.
  • the gallium nitride structures may be capped prior to forming the epitaxial silicon layer.
  • optoelectronic devices may be formed in the gallium nitride layer whereas conventional CMOS or other microelectronic devices may be formed in the (100) silicon substrate. Integrated optoelectronic substrates thereby may be formed.
  • gallium nitride microelectronic structures preferably comprise a (111) silicon layer, a 3C-silicon carbide layer on the (11 1) silicon layer, an underlying layer of 2H-gallium nitride on the 3C-silicon carbide layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H- gallium nitride.
  • the (111) silicon layer may comprise a surface of a (11 1) bulk silicon substrate, a surface of a (111) SIMOX substrate or a surface of a (111) SOI substrate.
  • a buffer layer of aluminum nitride and/or gallium nitride may be provided between the 3C-silicon carbide layer and the underlying layer of 2H-gallium nitride.
  • a mask may be provided on the underlying layer of 2H-gallium nitride, the mask including at least one opening that exposes the underlying layer of 2H-gallium nitride, and the lateral layer of 2H-gallium nitride extending through the at least one opening and onto the mask.
  • a second laterally offset mask and a second lateral layer of 2H-gallium nitride also may be provided.
  • At least one trench and/or post may be provided in the underlying layer of 2H-gallium nitride that defines at least one sidewall in the underlying layer of 2H-gallium nitride, and the lateral layer of 2H-gallium nitride may extend from the at least one sidewall.
  • the lateral layer of 2H-gallium nitride may extend onto the post tops, which may be masked or unmasked.
  • the trench bottoms also may be masked or the trench may extend through the aluminum nitride layer into the silicon carbide layer.
  • a preferred embodiment using a (111) bulk silicon substrate includes a 3C- silicon carbide layer on the (1 11) silicon substrate, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H- gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride.
  • a preferred embodiment using a SIMOX substrate includes a (111) silicon substrate, a silicon dioxide layer on the (11 1) silicon substrate, a 3C-silicon carbide layer on the silicon dioxide layer, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H-gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride.
  • a preferred embodiment using an SOI substrate includes a (100) silicon substrate, an insulating layer on the (100) silicon substrate, a 3C-silicon carbide layer on the insulating layer, a buffer layer of aluminum nitride and/or gallium nitride on the 3C-silicon carbide layer, an underlying layer of 2H-gallium nitride on the buffer layer and a lateral layer of 2H-gallium nitride on the underlying layer of 2H-gallium nitride.
  • a plurality of microelectronic devices preferably are formed in the (100) silicon substrate.
  • the 3C- silicon carbide layer, the layer of aluminum nitride, the underlying layer of 2H- gallium nitride and the lateral layer of 2H-gallium nitride preferably define a pedestal that exposes the plurality of microelectronic devices in the (100) silicon substrate.
  • the pedestal may expose the (100) silicon substrate, substrate, a (100) silicon layer may be included on the exposed portion of the (100) silicon substrate, and the microelectronic devices may be formed in the (100) silicon layer.
  • a layer of (1 11) silicon may be present between the insulating layer and the 3C-silicon carbide layer.
  • gallium nitride microelectronic structures may be formed on commonly used bulk silicon, SIMOX and SOI substrates. Low cost and/or high availability gallium nitride devices thereby may be provided. Integration with conventional CMOS or other silicon technologies also may be facilitated.
  • Figures 1-14 are cross-sectional views of first gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • Figures 16-26 are cross-sectional views of second gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • Figures 27-41 are cross-sectional views of third gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • Figures 42-43 are cross-sectional views of fourth gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • Figures 44-45 are cross-sectional views of fifth gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • Figure 46 is a cross-sectional view of sixth gallium nitride microelectronic structures according to the present invention.
  • Figures 47-49 are cross-sectional views of seventh gallium nitride microelectronic structures during intermediate fabrication steps, according to the present invention.
  • FIG. 1 first embodiments of methods of fabricating gallium nitride microelectronic layers and microelectronic structures formed thereby are illustrated.
  • a bulk silicon (1 11) substrate 102a is provided.
  • the crystallographic designation conventions used herein are well known to those having skill in the art, and need not be described further.
  • the surface of the (111) silicon substrate 102a preferably is converted to 3C-silicon carbide 102b.
  • the surface of the silicon substrate 102a may be converted to 3C-silicon carbide by exposure to one or more carbon-containing sources.
  • a converted layer of 3C-SiC may be formed by heating the bulk silicon substrate 102a using ethylene at about 925°C for about fifteen minutes at a pressure of about 5E-5 Torr. More preferably, an ethylene flow rate of about 0.5sccm is used while heating the substrate from room temperature to about 925°C at a ramp up rate of about 30°C per minute and holding at about 925°C for about fifteen minutes and at about 5E-5 Torr, resulting in a thin, 50 Angstrom, 3C-silicon carbide layer 102b.
  • a layer of 3C-silicon carbide 102c may be formed on the converted 3C-silicon carbide layer 102b using conventional vapor phase epitaxial techniques.
  • the silicon carbide layer may be grown using propane (about 15% in hydrogen) and silane (about 5% in hydrogen) at about 1360°C and about 760 Torr. More preferably, propane (about 15% in hydrogen) at about 25 seem, silane (about 5% in hydrogen) at about 100 seem and hydrogen gas at about 2500 seem at a temperature of about 1360°C and pressure of about 760 Torr may be used.
  • propane about 15% in hydrogen
  • silane about 5% in hydrogen
  • the surface of the silicon substrate need not be converted to 3C-silicon carbide prior to forming silicon carbide layer 102c. Rather, layer 102c may be formed directly on the silicon substrate 102a.
  • the epitaxially grown layer of 3C-silicon carbide 102c may be thinned, for example, to a thickness of about 0.5 ⁇ m, to form a thin layer 102c' of 3C-silicon carbide. Thinning may take place using chemical mechanical polishing. The thinning may promote the formation of a smooth, defect free nucleation surface for 2H-aluminum nitride as will be described below. However, it will be understood that the 3C-silicon carbide layer 102c need not be thinned.
  • a buffer layer of 2H-aluminum nitride and/or gallium nitride 102d then is grown on the epitaxially grown layer of 3C-silicon carbide 102c or 102c'.
  • the aluminum nitride layer 102d may be about 0.01 ⁇ m thick and may be formed using conventional techniques such as metalorganic vapor phase epitaxy. It also will be understood that the buffer layer of aluminum nitride and/or gallium nitride 102d need not be included, and gallium nitride may be formed directly on the epitaxially grown layer 102c/102c' of 3C-silicon carbide.
  • the combination of the (111) silicon substrate 102a, the silicon carbide layers 102b and 102c' and the buffer layer 102d forms a platform 102 upon which a gallium nitride microelectronic layer may be fabricated.
  • a gallium nitride microelectronic layer may be fabricated.
  • an underlying 2H-gallium nitride layer 104 is grown on the 2H-aluminum nitride layer 102d.
  • the gallium nitride layer 104 may be between about 0.5 and about 2.0 ⁇ m thick and may be grown at about 1000°C in a cold wall vertical and inductively heated metal organic vapor phase epitaxy system using triethyl gallium at about 26 m ⁇ mol/min, ammonia at about 1500 seem and about 3000 seem hydrogen diluent. Additional details of the growth technique for the aluminum nitride layer 102d and the gallium nitride layer 104 may be found in a publication by T. W. Weeks et al.
  • gallium nitride microelectronic layers may be fabricated on the underlying gallium nitride layer 104 using ELO. It also will be understood, however, that gallium nitride microelectronic layers may be fabricated using pendeoepitaxy as will be described in connection with other embodiments of the invention and/or using other techniques for fabricating gallium nitride microelectronic layers.
  • the underlying gallium nitride layer 104 is masked with a first mask 106 that includes a first array of openings 107 therein.
  • the first mask may comprise silicon dioxide at a thickness of 1000A and may be deposited using Low Pressure Chemical Vapor Deposition (LPCVD) at 410°C. Other masking materials may be used.
  • the first mask may be patterned using standard photolithography techniques and etching in a buffered HF solution.
  • the first openings 107 are 3 ⁇ m-wide openings that extend in parallel at distances of between 3 and 40 ⁇ m and that are oriented along the ⁇ 1 1 00 > direction on the underlying gallium nitride layer 104.
  • the structure Prior to further processing, the structure may be dipped in a 50% buffered hydrochloric acid (HCl) solution to remove surface oxides from the underlying gallium nitride layer 104.
  • HCl 50% buffered hydrochloric acid
  • the underlying gallium nitride layer 104 is grown through the first array of openings 107 to form first vertical gallium nitride layer 108a in the first openings.
  • Growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr.
  • the precursors TEG at 13-39 ⁇ mol/min and NH 3 at 1500 seem may be used in combination with a 3000 seem H diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used.
  • the first gallium nitride layer 108a grows vertically to the top of the first mask 106.
  • underlying gallium nitride layer 104 also may be grown laterally without using a mask 106, by appropriately controlling growth parameters and/or by appropriately patterning the underlying gallium nitride layer 104.
  • a patterned layer may be formed on the underlying gallium nitride layer after vertical growth or lateral growth, and need not function as a mask.
  • lateral growth in two dimensions may be used to form an overgrown gallium nitride semiconductor layer.
  • mask 106 may be patterned to include an array of openings 107 that extend along two orthogonal directions such as ⁇ 1100 > and ⁇ 1120 > .
  • the openings can form a rectangle of orthogonal striped patterns.
  • the ratio of the edges of the rectangle is preferably proportional to the ratio of the growth rates of the ⁇ 1120 ⁇ and
  • ⁇ 1101 ⁇ facets for example, in a ratio of 1.4: 1.
  • first gallium nitride layer 108a causes lateral overgrowth onto the first mask 106, to form first lateral gallium nitride layer 108b. Growth conditions for overgrowth may be maintained as was described in connection with Figure 8.
  • lateral overgrowth is optionally allowed to continue until the lateral growth fronts coalesce at first interfaces 108c, to form a first continuous gallium nitride layer 108.
  • the total growth time may be approximately 60 minutes.
  • Microelectronic devices may be formed in the first continuous gallium nitride layer 108.
  • the first vertical gallium nitride layer 108a is masked with a second mask 206 that includes a second array of openings 207 therein.
  • the second mask may be fabricated as was described in connection with the first mask.
  • the second mask may also be eliminated, as was described in connection with the first mask of Figure 8.
  • the second mask 206 preferably covers the entire first vertical gallium nitride layer 108a, so as to prevent defects therein from propagating vertically or laterally.
  • mask 206 may extend onto first lateral gallium nitride layer 108b as well.
  • the first lateral gallium nitride layer 108c is grown vertically through the second array of openings 207, to form second vertical gallium nitride layer 208a in the second openings. Growth may be obtained as was described in connection with Figure 8.
  • second gallium nitride layer 208a causes lateral overgrowth onto the second mask 206, to form second lateral gallium nitride layer 208b.
  • Lateral growth may be obtained as was described in connection with Figure 8.
  • lateral overgrowth preferably continues until the lateral growth fronts coalesce at second interfaces 208c to form a second continuous gallium nitride layer 208.
  • Total growth time may be approximately 60 minutes.
  • Microelectronic devices may then be formed in regions 208a and in regions 208b as shown in Figure 15, because both of these regions are of relatively low defect density. Devices may bridge these regions as well, as shown. Accordingly, a continuous device quality gallium nitride layer 208 may be formed.
  • the openings 107 and 207 in the masks are preferably rectangular stripes that preferably extend along the ⁇ 1120 > and/or ⁇ 1 1 00 > directions relative to the underlying gallium nitride layer 104.
  • Truncated triangular stripes having (1 1 01) slant facets and a narrow (0001) top facet may be obtained for mask openings 107 and 207 along the ⁇ 1120 > direction.
  • Rectangular stripes having a (0001) top facet, (1120) vertical side faces and (1 1 01) slant facets may be grown along the ⁇ 1 1 00 > direction. For growth times up to 3 minutes, similar morphologies may be obtained regardless of orientation. The stripes develop, into different shapes if the growth is continued.
  • the amount of lateral growth generally exhibits a strong dependence on stripe orientation.
  • the lateral growth rate of the ⁇ 1 1 00 > oriented stripes is generally much faster than those along ⁇ 1120 > . Accordingly, it is most preferred to orient the openings 107 and 207 so that they extend along the ⁇ 1 1 00 > direction of the underlying gallium nitride layer 104.
  • Stripes oriented along ⁇ 1 120 > may have wide (1 1 00) slant facets and either a very narrow or no (0001) top facet depending on the growth conditions.
  • (1 1 01) is the most stable plane in the gallium nitride wurtzite crystal structure, and the growth rate of this plane is lower than that of others.
  • the ⁇ 1 1 01 ⁇ planes of the ⁇ 1 1 00 > oriented stripes may be wavy, which implies the existence of more than one Miller index. It appears that competitive growth of selected ⁇ 1 1 01 ⁇ planes occurs during the deposition which causes these planes to become unstable and which causes their growth rate to increase relative to that of the (1 1 01) of stripes oriented along ⁇ 1120 >.
  • the morphologies of the gallium nitride layers selectively grown on openings oriented along ⁇ 1 1 00 > are also generally a strong function of the growth temperatures.
  • Layers grown at 1000°C may possess a truncated triangular shape. This morphology may gradually change to a rectangular cross-section as the growth temperature is increased. This shape change may occur as a result of the increase in the diffusion coefficient and therefore the flux of the gallium species along the (0001) top plane onto the ⁇ 1 1 01 ⁇ planes with an increase in growth temperature. This may result in a decrease in the growth rate of the (0001) plane and an increase in that of the ⁇ 1 1 01 ⁇ . This phenomenon has also been observed in the selective growth of gallium arsenide on silicon dioxide. Accordingly, temperatures of 1100°C appear to be most preferred.
  • the morphological development of the gallium nitride regions also appears to depend on the flow rate of the TEG.
  • An increase in the supply of TEG generally increases the growth rate of the stripes in both the lateral and the vertical directions.
  • the lateral/vertical growth rate ratio decrease from 1.7 at the TEG flow rate of 13 ⁇ mol/min to 0.86 at 39 ⁇ mol.min.
  • This increased influence on growth rate along ⁇ 0001> relative to that of ⁇ 1120 > with TEG flow rate may be related to the type of reactor employed, wherein the reactant gases flow vertically and pe ⁇ endicular to the substrate.
  • gallium nitride layers 108 and 208 may be obtained using 3 ⁇ m wide stripe openings 107 and 207 spaced 7 ⁇ m apart and oriented along ⁇ 1 1 00 > , at 1 100°C and a TEG flow rate of 26 ⁇ mol/min.
  • the overgrown gallium nitride layers 108b and 208b may include subsurface voids that form when two growth fronts coalesce.
  • the coalesced gallium nitride layers 108 and 208 may have a microscopically flat and pit-free surface.
  • the surfaces of the laterally grown gallium nitride layers may include a terrace structure having an average step height of 0.32nm. This terrace structure may be related to the laterally grown gallium nitride, because it is generally not included in much larger area films grown only on aluminum nitride buffer layers.
  • the average RMS roughness values may be similar to the values obtained for the underlying gallium nitride layers 104.
  • Threading dislocations originating from the interface between the gallium nitride underlayer 104 and the buffer layer 102b, appear to propagate to the top surface of the first vertical gallium nitride layer 108a within the first openings 107 of the first mask 106.
  • the dislocation density within these regions is approximately 10 cm " .
  • threading dislocations do not appear to readily propagate into the first overgrown regions 108b. Rather, the first overgrown gallium nitride regions 108b contain only a few dislocations. These few dislocations may be formed parallel to the (0001) plane via the extension of the vertical threading dislocations after a 90° bend in the regrown region.
  • both the second vertical gallium nitride layer 208a and the second lateral gallium nitride layer 208b propagate from the low defect first overgrown gallium nitride layer 108b, the entire layer 208 can have low defect density.
  • the formation mechanism of the selectively grown gallium nitride layer is lateral epitaxy.
  • the two main stages of this mechanism are vertical growth and lateral growth.
  • Ga or N atoms should not readily bond to the mask surface in numbers and for a time sufficient to cause gallium nitride nuclei to form. They would either evaporate or diffuse along the mask surface to the openings 107 or 207 in the masks or to the vertical gallium nitride surfaces 108a or 208a which have emerged. During lateral growth, the gallium nitride grows simultaneously both vertically and laterally over the mask from the material which emerges over the openings.
  • lateral cracking within the SiO may take place due to thermal stresses generated on cooling.
  • the viscosity (p) of the SiO at 1050°C is about 10 ' poise which is one order of magnitude greater than the strain point (about 10 1 ' poise) where stress relief in a bulk amo ⁇ hous material occurs within approximately six hours.
  • the SiO 2 mask may provide limited compliance on cooling.
  • chemical bonding may occur only when appropriate pairs of atoms are in close proximity. Extremely small relaxations of the silicon and oxygen and gallium and nitrogen atoms on the respective surfaces and/or within the bulk of the SiO may accommodate the gallium nitride and cause it to bond to the oxide.
  • regions of lateral epitaxial overgrowth through mask openings from an underlying gallium nitride layer may be achieved via MOVPE.
  • the growth may depend strongly on the opening orientation, growth temperature and TEG flow rate.
  • Coalescence of overgrown gallium nitride regions to form regions with both extremely low densities of dislocations and smooth and pit-free surfaces may be achieved through 3 ⁇ m wide mask openings spaced 7 ⁇ m apart and extending along the ⁇ 1 1 00 > direction, at 1100°C and a TEG flow rate of 26 ⁇ mol/min.
  • the lateral overgrowth of gallium nitride via MOVPE may be used to obtain low defect density continuous gallium nitride layers for microelectronic devices.
  • the embodiments of Figures 1-15 can use bulk (111) silicon substrate 102a, a 3C-silicon carbide layer 102b/102c' and a buffer layer 102d as a platform 102 on which to grow high quality gallium nitride microelectronic layers.
  • the silicon carbide layer 102b/102c' may be critical to the success of forming gallium nitride structures according to the present invention.
  • silicon carbide is a preferred material template on which to grow the buffer layer 102d and the gallium nitride semiconductor layer 104.
  • the silicon carbide layer may provide a diffusion barrier to prevent the interaction of silicon atoms with gallium and nitrogen species found in the growth environment.
  • the silicon atoms from the silicon substrate may have sufficient energy and mobility to diffuse to the surface of the aluminum nitride buffer layer and to react with the gallium and nitrogen species in the growth environment. This may result in the formation of large voids in the underlying silicon substrate and in the "poisoning" of the gallium nitride growth, which may result in the undesirable formation of poly crystalline gallium nitride-containing structures.
  • Figures 16-26 second embodiments of fabricating gallium nitride microelectronic layers according to the present invention will be described.
  • the embodiments of Figures 16-26 begin with a (111) silicon SIMOX substrate 202 including a buried layer of silicon dioxide 202b therein that define a (111) silicon surface layer 202c on an underlying (111) silicon substrate 202a. See Figure 16.
  • the buried layer of silicon dioxide may be fabricated by implanting oxygen into a (111) silicon substrate to define a (11 1) silicon surface layer on the (11 1) silicon substrate. This process generally is referred to as SIMOX and is described for example in a publication entitled Silicon-on-
  • a layer of 3C-silicon carbide 202d is epitaxially grown on the converted (111) silicon surface layer 202c' or directly on the (111) silicon surface layer 202c in a manner that was described above.
  • the epitaxially grown layer of 3C-silicon carbide 202d optionally is thinned to produce a thinned epitaxial layer of 3C-silicon carbide 202d'.
  • a 2H-aluminum nitride layer and/or gallium nitride buffer 202e then is grown on the thinned epitaxially grown layer of 3C-silicon carbide 202d'. Then, as shown in Figure 21 an underlying layer of 2H-gallium nitride
  • Figures 22-26 now will show the use of pendeoepitaxy to laterally grow the underlying layer of 2H-gallium nitride 204 to thereby produce a gallium nitride microelectronic layer.
  • epitaxial lateral overgrowth techniques of Figures 7-15, and/or other techniques may be used.
  • the underlying gallium nitride layer 204 includes a plurality of sidewalls 205 therein.
  • the sidewalls 205 may be thought of as being defined by a plurality of spaced apart posts 206, that also may be referred to as "mesas", “pedestals” or “columns”.
  • the sidewalls 205 also may be thought of as being defined by a plurality of trenches 207, also referred to as "wells" in the underlying gallium nitride layer 204.
  • the sidewalls 205 may also be thought of as being defined by a series of alternating trenches 207 and posts 206.
  • a single post 206 may be provided, that may be thought of as being defined by at least one trench 207 adjacent the single post. It will be understood that the posts 206 and the trenches 207 that define the sidewalls
  • the 205 may be fabricated by selective etching, selective epitaxial growth and/or other conventional techniques. Moreover, it also will be understood that the sidewalls need not be orthogonal to the substrate 202, but rather may be oblique thereto. Finally, it also will be understood that although the sidewalls 205 are shown in cross-section in Figure 22, the posts 206 and trenches 207 may define elongated regions that are straight, V-shaped or have other shapes. As shown in Figure 22, the trenches 207 may extend into the buffer layer 202e and into the silicon carbide layer 202c'/202d', so that subsequent gallium nitride growth occurs preferentially on the sidewalls 205 rather than on the trench floors.
  • the trenches may not extend into the silicon carbide layer 202c7202d', and also may not extend into buffer layer 202e, depending, for example, on the trench geometry and the lateral versus vertical growth rates of the gallium nitride.
  • the sidewalls 205 of the underlying gallium nitride layer 204 are laterally grown to form a lateral gallium nitride layer 208a in the trenches 207.
  • Lateral growth of gallium nitride may be obtained at 1000-1100°C and 45 Torr.
  • the precursors TEG at 13-39 ⁇ mol/min and NH 3 at 1500 seem may be used in combination with a 3000 seem H 2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, may also be used.
  • the term "lateral" means a direction that is orthogonal to the sidewalls 205. It will also be understood that some vertical growth on the posts 206 may also take place during the lateral growth from sidewalls 205.
  • the term “vertical” denotes a directional parallel to the sidewalls 205.
  • lateral gallium nitride layer 208a causes vertical growth onto the underlying gallium nitride layer 204, specifically onto the posts 206, to form a vertical gallium nitride layer 208b. Growth conditions for vertical growth may be maintained as was described in connection with Figure 23. As also shown in Figure 24, continued vertical growth into trenches 207 may take place at the bottom of the trenches.
  • growth is allowed to continue until the lateral growth fronts coalesce in the trenches 207 at the interfaces 208c, to form a continuous gallium nitride semiconductor layer in the trenches.
  • the total growth time may be approximately 60 minutes.
  • microelectronic devices 210 may then be formed in the lateral gallium nitride semiconductor layer 208a. Devices also may be formed in vertical gallium nitride layer 208b. It will be understood that in the embodiments of Figures 16-26, a mask need not be used to fabricate the gallium nitride semiconductor structures because lateral growth is directed from the sidewalls 205. However, as will be described in connection with Figures 27-41, a mask may be used.
  • an epitaxial lateral overgrowth then may be performed on the structure of Figure 26 using a mask as was described in connection with Figures 7-15. Laterally offset masks also may be used. Moreover, a second, laterally offset pendeoepitaxial process may be performed on the structure of Figure 26 by defining second trenches and/or posts. By performing two separate lateral growths, the defect density may be reduced considerably.
  • a silicon substrate containing a buried oxide layer such as a SIMOX wafer 202 is used.
  • the use of a SIMOX wafer can prevent or limit wa ⁇ ing of the substrate after formation of silicon carbide layers 202c'/202d'.
  • the structures when the structures are cooled after silicon carbide formation from growth temperatures to room temperature, the structures may wa ⁇ due to the large mismatches in the coefficients of thermal expansion between silicon and silicon carbide. This effect may be more pronounced when using large diameter silicon wafers.
  • using wafers with layers of oxide 202b may prevent or reduce the wa ⁇ ing by acting as a compliant substrate.
  • the oxide may undergo viscous flow and accommodate the mismatches in both the lattice parameters and the coefficient of thermal expansion between the silicon and the silicon carbide layers. On cooling, the oxide layer may then provide a mechanism of strain relief and limit the wa ⁇ ing of the substrate.
  • the silicon carbide 202c'/202d' is a preferred material template on which to grow the aluminum nitride buffer layer 202e and the gallium nitride semiconductor layers 204.
  • Pendeoepitaxial growth of gallium nitride may be obtained on silicon carbide, because under the growth conditions used for pendeoepitaxial growth, gallium and nitrogen atoms generally will not bond to the silicon carbide surface in numbers and in time sufficient to cause gallium nitride nuclei to form.
  • the silicon carbide layer may provide a diffusion barrier to prevent the interaction of silicon atoms with gallium and nitrogen species found in the growth environment. Referring now to Figures 27-41, third embodiments according to the present invention now will be described.
  • SOI Semiconductor-On- Insulator
  • microelectronic devices 301 including but not limited conventional CMOS devices, are fabricated in a (100) silicon substrate 302a using conventional techniques. It will be understood that the devices 301 may be formed later as well, as will be described in detail below. It also will be understood that microelectronic devices 301 may include optical and/or microelectromechanical (MEMS) devices as well.
  • MEMS microelectromechanical
  • the (100) silicon substrate 302a then is bonded to a (11 1) silicon substrate 302c using a bonding layer 302b and conventional bonding techniques.
  • the bonding layer may be a microelectronic epoxy, a layer of silicon dioxide and/or other conventional materials.
  • the (111) silicon substrate 302c is thinned to produce a (111) silicon layer 302c' on the (100) silicon substrate 302a.
  • the operations of Figures 27-29 may form a conventional silicon on insulator (SOI) substrate 302 except that microelectronic devices 301 are contained therein.
  • SOI silicon on insulator
  • At least part of the (111) silicon layer 302c' is converted to 3C-silicon carbide layer 302c". As shown in Figure 30, all of the layer 302c' is converted to silicon carbide layer 302c". Moreover, as was described above, the conversion step may be eliminated. Then, as shown in Figure 31, a layer of 3C- silicon carbide 302d may be epitaxially grown on the converted (111) silicon layer 302c".
  • the epitaxially grown layer of 3C-silicon carbide 302d is thinned to produce thinned layer 302d ⁇
  • An aluminum nitride layer 302e then is grown on a thinned epitaxially grown layer of 3C-silicon carbide 302d'. This provides a platform 302' for subsequent growth of gallium nitride.
  • a layer of 2H-gallium nitride 304 is grown on the aluminum nitride layer 302e.
  • masked pendeoepitaxy is performed to laterally grow the layer of 2H-gallium nitride 304 to produce a gallium nitride microelectronic layer.
  • maskless pendeoepitaxy, epitaxial lateral growth, other techniques and/or combinations thereof also may be used.
  • a mask such as silicon nitride mask 309 is provided on the underlying gallium nitride layer 304.
  • the mask 309 may have a thickness of about 1000 Angstroms and may be formed on the underlying gallium nitride layer 304 using low pressure chemical vapor deposition (CVD) at 410°C.
  • CVD low pressure chemical vapor deposition
  • the underlying gallium nitride layer 304 includes a plurality of sidewalls 105 therein.
  • the sidewalls 305 may be thought of as being defined by a plurality of spaced apart posts 306, that also may be referred to as "mesas",
  • the sidewalls 305 may also be thought of as being defined by a plurality of trenches 307, also referred to as "wells" in the underlying gallium nitride layer 304.
  • the sidewalls 305 may also be thought of as being defined by a series of alternating trenches 307 and posts 306. It will be understood that the posts 306 and the trenches 307 that define the sidewalls 305 may be fabricated by selective etching, selective epitaxial growth and/or other conventional techniques. Moreover, it also will be understood that the sidewalls need not be orthogonal to the substrate 302, but rather may be oblique thereto.
  • the posts 306 and trenches 307 may define elongated regions that are straight, V-shaped or have other shapes.
  • the trenches 307 preferably extend into the buffer layer 302e and into the silicon carbide layer 302d'/302c", so that subsequent gallium nitride growth occurs preferentially on the sidewalls 305 rather than on the trench floors.
  • the trenches may not extend into the silicon carbide layer 302d'/302c", and also may not extend into the buffer layer 302e.
  • the sidewalls 305 of the underlying gallium nitride layer 304 are laterally grown to form a lateral gallium nitride layer 308a in the trenches 307.
  • Lateral growth of gallium nitride may be obtained at about 1000- 1100°C and about 45 Torr.
  • the precursors TEG at about 13-39 ⁇ mol/min and NH 3 at about 1500 seem may be used in combination with about 3000 seem H 2 diluent. If gallium nitride alloys are formed, additional conventional precursors of aluminum or indium, for example, also may be used.
  • the term "lateral" means a direction that is parallel to the faces of the substrate 302'.
  • lateral gallium nitride 308a may also take place during the lateral growth from the sidewalls 305.
  • vertical denotes a directional parallel to the sidewalls 305.
  • Conditions for vertical growth may be maintained as was described above. As also shown in Figure 37, continued vertical growth into trenches 307 may take place at the bottom of the trenches.
  • lateral gallium nitride layer 308a causes lateral overgrowth onto the mask 309, to form lateral overgrowth gallium nitride layer 308b. Growth conditions for overgrowth may be maintained as was described above.
  • growth is allowed to continue until the lateral overgrowth fronts coalesce over the mask 309 at the interfaces 308d, to form a continuous gallium nitride semiconductor layer.
  • the total growth time may be approximately 60 minutes.
  • microelectronic devices 310 may then be formed in the lateral gallium nitride semiconductor layer 308a. Devices may also be formed in lateral overgrown gallium nitride layer 308b.
  • the microelectronic devices 301 in the (100) silicon substrate then may be electrically connected to the microelectronic devices 310 in the pendeoepitaxial gallium nitride layer to provide an integrated optical and electronic substrate.
  • the connection may use conventional metalization soldering and/or other techniques. Accordingly, high density integrated optoelectronic devices may be formed using conventional (100) silicon SOI substrates.
  • the silicon carbide layer 302d'/302c" may be critical to the success of forming gallium nitride structures because the silicon carbide is a preferred material template on which to grow the aluminum nitride layer 302e and the gallium nitride semiconductor layer 304. Moreover, under the growth conditions used for pendeoepitaxial growth, gallium and nitrogen atoms generally will not bond to the silicon carbide surface in numbers and times sufficient to cause gallium nitride nuclei to form. Alternatively, it will be understood that the bottom of the trenches 307 may be masked, for example with silicon nitride. The silicon carbide layer also may provide a diffusion barrier to prevent the interaction of silicon atoms with gallium and nitrogen species found in the growth environment.
  • the SOI wafers can prevent or limit wa ⁇ ing of the substrate after silicon carbide formation.
  • the bonding layer 302b may prevent or limit the wa ⁇ ing by acting as a compliant substrate.
  • the bonding layer 302b may also provide a mechanism of strain relief and may limit the wa ⁇ ing of the substrate.
  • FIGS 42-45 other embodiments of gallium nitride semiconductor structures and fabrication methods according to the present invention will now be described.
  • the structures use different spacings or dimensions for the posts and trenches.
  • a small post- width/trench width ratio is used.
  • discreet gallium nitride structures shown in Figure 42 may be obtained.
  • a large post-width/trench-width ratio is used so that gallium nitride structures shown in Figure 44 may be obtained.
  • gallium nitride semiconductor structures of Figure 42 are fabricated as was already described.
  • growth is allowed to continue until the lateral overgrowth fronts coalesce over the mask 309 at the interface 308b to form a continuous gallium nitride semiconductor layer over the mask 309.
  • the total growth time may be approximately 60 minutes.
  • microelectronic devices 310 may be formed in the lateral overgrowth gallium nitride layer 308d.
  • at least some of the discreet gallium nitride structures are removed to expose the microelectronic devices 301 in the (100) silicon substrate 302a.
  • Figure 44 using a large post- width/trench-width ratio, gallium nitride semiconductors structures of Figure 44 are fabricated as was already described.
  • growth is allowed to continue until the lateral overgrowth fronts coalesce in the trench 307 at the interfaces 308c to form a continuous gallium nitride semiconductor layer 308a over the trench 307.
  • the total growth time may be approximately 60 minutes.
  • microelectronic devices 310 may be formed in the pendeoepitaxial gallium nitride layer 308a.
  • at least a portion of the gallium nitride structure may be removed to thereby expose the underlying microelectronic devices 301, and was described above.
  • devices 301 are formed in the (100) silicon substrate 302a prior to forming the gallium nitride devices 310.
  • gallium nitride fabrication processes may occur at temperatures that are sufficiently high to destroy or degrade performance of the silicon devices 301 due to diffusion or other thermal effects. Accordingly, it may be desirable to form the microelectronic devices 301 in the (100) silicon substrate 302a after forming the gallium nitride layers and structures.
  • Figures 46-49 illustrate methods of forming microelectronic devices in the (100) silicon substrate after forming the gallium nitride layers and structures.
  • the structure of Figure 45 may be fabricated except that microelectronic devices 301 are not formed until after the gallium nitride structures are formed.
  • the face of the (100) silicon substrate 302a is exposed, and conventional microelectronic devices 301 may be formed in the exposed surface. It may be difficult to fabricate the microelectronic devices 301 within the trenches between the gallium nitride devices.
  • the embodiments of Figures 47-49 illustrate alternative fabrication techniques that need not fabricate the silicon microelectronic devices 301 at the bottom of the trenches.
  • the device of Figure 45 is fabricated except that microelectronic devices 301 are not fabricated in the (100) silicon substrate 302a.
  • a capping layer 320 for example silicon dioxide and/or silicon nitride, then is formed on the gallium nitride devices.
  • the (100) silicon substrate 302a is selectively epitaxially grown to form a (100) silicon layer 302a*.
  • Devices 301' then are formed in the epitaxially grown silicon layer 302a'.
  • the devices 301' may be formed at the surface of the structure rather than at the floor of a trench.
  • the capping layer 320 optionally may be removed to provide a free-standing silicon layer 302a' that is separated from the gallium nitride-based structures.
  • the devices may be connected using metallization at the top surface.
  • metallization within or on the (100) silicon substrate 302a may be provided.

Abstract

On fabrique une couche micro-électronique de nitrure de gallium par conversion d'une surface d'une couche de silicium (111) en carbure de silicium 3C. On exécute ensuite la croissance épitaxiale d'une couche de carbure de silicium 3C sur la surface convertie de la couche de silicium (111). On crée ensuite une couche de nitrure de gallium 2H sur la couche épitaxiale de carbure de silicium 3C. On constitue latéralement la couche de nitrure de gallium 2H afin de produire la couche micro-électronique de nitrure de gallium. Dans un mode de réalisation, la couche de silicium est un substrat de silicium (111) dont la surface est convertie en carbure de silicium 3C. Dans un autre mode de réalisation, la couche de silicium (111) fait partie d'un substrat de silicium de séparation par implantation d'oxygène (SIMOX) qui comprend une couche d'oxygène implanté définissant la couche (111) sur le substrat de silicium (111). Dans encore un autre mode de réalisation, la couche de silicium (111) consiste en une partie d'un substrat au silicium sur isolant (SOI) dans lequel une couche de silicium (111) adhère à un substrat. On peut effectuer la croissance latérale de la couche de nitrure de gallium 2H par supercroissance latérale épitaxiale (ELO), ce qui consiste à créer un masque sur la couche de nitrure de gallium 2H.
PCT/US1999/027358 1998-11-24 1999-11-18 Fabrication de couches de nitrure de gallium sur du silicium WO2000031783A1 (fr)

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US6177688B1 (en) 1998-11-24 2001-01-23 North Carolina State University Pendeoepitaxial gallium nitride semiconductor layers on silcon carbide substrates
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US6380108B1 (en) * 1999-12-21 2002-04-30 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
US6403451B1 (en) * 2000-02-09 2002-06-11 Noerh Carolina State University Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US20020158253A1 (en) * 2000-02-21 2002-10-31 Tetsuji Moku Light-emitting semiconductor device and method of fabrication
JP2003526203A (ja) * 2000-03-02 2003-09-02 アイクストロン、アーゲー ＩＩＩ族−Ｎ、（ＩＩＩ−Ｖ）族−Ｎおよび金属−窒素の所定成分による層構造をＳｉ基板上に作成する方法および装置
JP2001313259A (ja) * 2000-04-28 2001-11-09 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体基板の製造方法及び半導体素子
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
WO2002003437A1 (fr) * 2000-06-30 2002-01-10 Motorola, Inc., A Corporation Of The State Of Delaware Structure et dispositif de semi-conducteur hybride
US6590236B1 (en) 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
US7687888B2 (en) 2000-08-04 2010-03-30 The Regents Of The University Of California Method of controlling stress in gallium nitride films deposited on substrates
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6638838B1 (en) * 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6501121B1 (en) 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
JP2002222771A (ja) * 2000-11-21 2002-08-09 Ngk Insulators Ltd Ｉｉｉ族窒化物膜の製造方法、ｉｉｉ族窒化物膜の製造用下地膜、及びその下地膜の製造方法
KR100831751B1 (ko) 2000-11-30 2008-05-23 노쓰 캐롤라이나 스테이트 유니버시티 Ｍ'ｎ 물의 제조 방법 및 장치
AU2002235146A1 (en) 2000-11-30 2002-06-11 North Carolina State University Non-thermionic sputter material transport device, methods of use, and materials produced thereby
US6559471B2 (en) 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
US6649287B2 (en) 2000-12-14 2003-11-18 Nitronex Corporation Gallium nitride materials and methods
US6461944B2 (en) * 2001-02-07 2002-10-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Methods for growth of relatively large step-free SiC crystal surfaces
EP1367150B1 (fr) * 2001-02-14 2009-08-19 Toyoda Gosei Co., Ltd. Procede de production de cristal semi-conducteur et element lumineux semi-conducteur
US6611002B2 (en) 2001-02-23 2003-08-26 Nitronex Corporation Gallium nitride material devices and methods including backside vias
US6956250B2 (en) * 2001-02-23 2005-10-18 Nitronex Corporation Gallium nitride materials including thermally conductive regions
US7233028B2 (en) * 2001-02-23 2007-06-19 Nitronex Corporation Gallium nitride material devices and methods of forming the same
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
JP2002280314A (ja) * 2001-03-22 2002-09-27 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体の製造方法、及びそれに基づくｉｉｉ族窒化物系化合物半導体素子
EP1396878A4 (fr) * 2001-03-30 2008-09-03 Toyoda Gosei Kk Procede de fabrication pour substrat semi-conducteur et element semi-conducteur
US20040029365A1 (en) * 2001-05-07 2004-02-12 Linthicum Kevin J. Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby
US20040169192A1 (en) * 2001-06-04 2004-09-02 Hisaki Kato Method for producing group III nitride compounds semiconductor
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US7138291B2 (en) * 2003-01-30 2006-11-21 Cree, Inc. Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices
US20040104384A1 (en) * 2002-04-22 2004-06-03 Moustakas Theodore D. Growth of high temperature, high power, high speed electronics
US6783592B2 (en) * 2002-10-10 2004-08-31 The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration Lateral movement of screw dislocations during homoepitaxial growth and devices yielded therefrom free of the detrimental effects of screw dislocations
JP3905824B2 (ja) * 2002-11-25 2007-04-18 大阪府 単結晶窒化ガリウム局在基板及びその製造方法
US7115896B2 (en) * 2002-12-04 2006-10-03 Emcore Corporation Semiconductor structures for gallium nitride-based devices
DE60311678T2 (de) * 2002-12-20 2007-11-22 Cree, Inc. Verfahren zur herstellung von halbleitervorrichtungen mit mesastrukturen und vielfachen passivierungsschichten und verwandte vorrichtungen
GB2398672A (en) * 2003-02-19 2004-08-25 Qinetiq Ltd Group IIIA nitride buffer layers
US20060276043A1 (en) * 2003-03-21 2006-12-07 Johnson Mark A L Method and systems for single- or multi-period edge definition lithography
US7138716B2 (en) * 2003-06-27 2006-11-21 Intel Corporation Addition of metal layers with signal reallocation to a microprocessor for increased frequency and lower power
DE10335081A1 (de) * 2003-07-31 2005-03-03 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoeleketronischer Halbleiterchip
DE10335080A1 (de) * 2003-07-31 2005-03-03 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
US7135720B2 (en) * 2003-08-05 2006-11-14 Nitronex Corporation Gallium nitride material transistors and methods associated with the same
US7052942B1 (en) 2003-09-19 2006-05-30 Rf Micro Devices, Inc. Surface passivation of GaN devices in epitaxial growth chamber
US7803717B2 (en) * 2003-10-23 2010-09-28 North Carolina State University Growth and integration of epitaxial gallium nitride films with silicon-based devices
US20050112048A1 (en) * 2003-11-25 2005-05-26 Loucas Tsakalakos Elongated nano-structures and related devices
US20050145851A1 (en) * 2003-12-17 2005-07-07 Nitronex Corporation Gallium nitride material structures including isolation regions and methods
US7071498B2 (en) * 2003-12-17 2006-07-04 Nitronex Corporation Gallium nitride material devices including an electrode-defining layer and methods of forming the same
US7084441B2 (en) 2004-05-20 2006-08-01 Cree, Inc. Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
US7339205B2 (en) * 2004-06-28 2008-03-04 Nitronex Corporation Gallium nitride materials and methods associated with the same
US7361946B2 (en) * 2004-06-28 2008-04-22 Nitronex Corporation Semiconductor device-based sensors
US7687827B2 (en) * 2004-07-07 2010-03-30 Nitronex Corporation III-nitride materials including low dislocation densities and methods associated with the same
US20060017064A1 (en) * 2004-07-26 2006-01-26 Saxler Adam W Nitride-based transistors having laterally grown active region and methods of fabricating same
US7405002B2 (en) * 2004-08-04 2008-07-29 Agency For Science, Technology And Research Coated water-soluble nanoparticles comprising semiconductor core and silica coating
US7534489B2 (en) * 2004-09-24 2009-05-19 Agency For Science, Technology And Research Coated composites of magnetic material and quantum dots
JP2008519441A (ja) * 2004-10-28 2008-06-05 ニトロネックス コーポレイション 窒化ガリウム材料を用いるモノリシックマイクロ波集積回路
US7709859B2 (en) * 2004-11-23 2010-05-04 Cree, Inc. Cap layers including aluminum nitride for nitride-based transistors
US7456443B2 (en) * 2004-11-23 2008-11-25 Cree, Inc. Transistors having buried n-type and p-type regions beneath the source region
US7247889B2 (en) 2004-12-03 2007-07-24 Nitronex Corporation III-nitride material structures including silicon substrates
US7161194B2 (en) * 2004-12-06 2007-01-09 Cree, Inc. High power density and/or linearity transistors
US7355215B2 (en) * 2004-12-06 2008-04-08 Cree, Inc. Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies
US7465967B2 (en) * 2005-03-15 2008-12-16 Cree, Inc. Group III nitride field effect transistors (FETS) capable of withstanding high temperature reverse bias test conditions
US7687372B2 (en) * 2005-04-08 2010-03-30 Versatilis Llc System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor
US8575651B2 (en) 2005-04-11 2013-11-05 Cree, Inc. Devices having thick semi-insulating epitaxial gallium nitride layer
US7626217B2 (en) * 2005-04-11 2009-12-01 Cree, Inc. Composite substrates of conductive and insulating or semi-insulating group III-nitrides for group III-nitride devices
US7615774B2 (en) * 2005-04-29 2009-11-10 Cree.Inc. Aluminum free group III-nitride based high electron mobility transistors
US7544963B2 (en) * 2005-04-29 2009-06-09 Cree, Inc. Binary group III-nitride based high electron mobility transistors
US7365374B2 (en) 2005-05-03 2008-04-29 Nitronex Corporation Gallium nitride material structures including substrates and methods associated with the same
US20060267043A1 (en) * 2005-05-27 2006-11-30 Emerson David T Deep ultraviolet light emitting devices and methods of fabricating deep ultraviolet light emitting devices
US8866190B2 (en) * 2005-06-14 2014-10-21 International Rectifler Corporation Methods of combining silicon and III-nitride material on a single wafer
US8168000B2 (en) * 2005-06-15 2012-05-01 International Rectifier Corporation III-nitride semiconductor device fabrication
US9331192B2 (en) * 2005-06-29 2016-05-03 Cree, Inc. Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same
US20070018198A1 (en) * 2005-07-20 2007-01-25 Brandes George R High electron mobility electronic device structures comprising native substrates and methods for making the same
KR100750932B1 (ko) 2005-07-31 2007-08-22 삼성전자주식회사 기판 분해 방지막을 사용한 단결정 질화물계 반도체 성장및 이를 이용한 고품위 질화물계 발광소자 제작
JP4913375B2 (ja) * 2005-08-08 2012-04-11 昭和電工株式会社 半導体素子の製造方法
US20070202360A1 (en) * 2005-10-04 2007-08-30 Nitronex Corporation Gallium nitride material transistors and methods for wideband applications
EP1969635B1 (fr) 2005-12-02 2017-07-19 Infineon Technologies Americas Corp. Dispositifs en matériaux au nitrure de gallium et procédés associés
US7566913B2 (en) 2005-12-02 2009-07-28 Nitronex Corporation Gallium nitride material devices including conductive regions and methods associated with the same
US20070138505A1 (en) 2005-12-12 2007-06-21 Kyma Technologies, Inc. Low defect group III nitride films useful for electronic and optoelectronic devices and methods for making the same
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US7737500B2 (en) * 2006-04-26 2010-06-15 International Business Machines Corporation CMOS diodes with dual gate conductors, and methods for forming the same
TWI334164B (en) * 2006-06-07 2010-12-01 Ind Tech Res Inst Method of manufacturing nitride semiconductor substrate and composite material substrate
US20080035143A1 (en) * 2006-08-14 2008-02-14 Sievers Robert E Human-powered dry powder inhaler and dry powder inhaler compositions
JP2008091595A (ja) * 2006-10-02 2008-04-17 Eudyna Devices Inc 半導体装置およびその製造方法
WO2008073414A1 (fr) * 2006-12-12 2008-06-19 The Regents Of The University Of California Croissance de cristaux de plan m ou de plans semipolaires de (ai, in. ga. b)n sur différents substrats
US8476125B2 (en) * 2006-12-15 2013-07-02 University Of South Carolina Fabrication technique for high frequency, high power group III nitride electronic devices
US8338273B2 (en) * 2006-12-15 2012-12-25 University Of South Carolina Pulsed selective area lateral epitaxy for growth of III-nitride materials over non-polar and semi-polar substrates
EP2126963A4 (fr) * 2007-03-16 2011-03-16 Sebastian Lourdudoss Heterostructures semi-conductrices et fabrication de celles-ci
US20080314311A1 (en) * 2007-06-24 2008-12-25 Burrows Brian H Hvpe showerhead design
US7888248B2 (en) * 2007-07-13 2011-02-15 Northrop Grumman Systems Corporation Method of producing large area SiC substrates
US20090050939A1 (en) * 2007-07-17 2009-02-26 Briere Michael A Iii-nitride device
US7745848B1 (en) 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof
US8026581B2 (en) * 2008-02-05 2011-09-27 International Rectifier Corporation Gallium nitride material devices including diamond regions and methods associated with the same
US20090261346A1 (en) * 2008-04-16 2009-10-22 Ding-Yuan Chen Integrating CMOS and Optical Devices on a Same Chip
US8343824B2 (en) * 2008-04-29 2013-01-01 International Rectifier Corporation Gallium nitride material processing and related device structures
US7919780B2 (en) * 2008-08-05 2011-04-05 Dicon Fiberoptics, Inc. System for high efficiency solid-state light emissions and method of manufacture
KR101006480B1 (ko) 2008-09-08 2011-01-06 서울대학교산학협력단 반도체 박막 구조 및 그 형성 방법
CN102160145B (zh) * 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 通过外延层过成长的元件形成
JP4647020B2 (ja) 2009-07-30 2011-03-09 キヤノン株式会社 窒化物半導体の微細構造の製造方法
US8212294B2 (en) * 2010-01-28 2012-07-03 Raytheon Company Structure having silicon CMOS transistors with column III-V transistors on a common substrate
US9190560B2 (en) 2010-05-18 2015-11-17 Agency For Science Technology And Research Method of forming a light emitting diode structure and a light diode structure
JP6054620B2 (ja) * 2012-03-29 2016-12-27 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法
US9093420B2 (en) 2012-04-18 2015-07-28 Rf Micro Devices, Inc. Methods for fabricating high voltage field effect transistor finger terminations
US8796097B2 (en) 2012-04-26 2014-08-05 University Of South Carolina Selectively area regrown III-nitride high electron mobility transistor
US9124221B2 (en) 2012-07-16 2015-09-01 Rf Micro Devices, Inc. Wide bandwidth radio frequency amplier having dual gate transistors
US8884268B2 (en) * 2012-07-16 2014-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Diffusion barrier layer for group III nitride on silicon substrate
US9147632B2 (en) 2012-08-24 2015-09-29 Rf Micro Devices, Inc. Semiconductor device having improved heat dissipation
US9202874B2 (en) 2012-08-24 2015-12-01 Rf Micro Devices, Inc. Gallium nitride (GaN) device with leakage current-based over-voltage protection
US9142620B2 (en) 2012-08-24 2015-09-22 Rf Micro Devices, Inc. Power device packaging having backmetals couple the plurality of bond pads to the die backside
US9917080B2 (en) 2012-08-24 2018-03-13 Qorvo US. Inc. Semiconductor device with electrical overstress (EOS) protection
US8988097B2 (en) 2012-08-24 2015-03-24 Rf Micro Devices, Inc. Method for on-wafer high voltage testing of semiconductor devices
US9070761B2 (en) 2012-08-27 2015-06-30 Rf Micro Devices, Inc. Field effect transistor (FET) having fingers with rippled edges
WO2014035794A1 (fr) 2012-08-27 2014-03-06 Rf Micro Devices, Inc Dispositif latéral à semi-conducteur à région verticale de claquage
US9325281B2 (en) 2012-10-30 2016-04-26 Rf Micro Devices, Inc. Power amplifier controller
JP5928366B2 (ja) * 2013-02-13 2016-06-01 豊田合成株式会社 Ｉｉｉ族窒化物半導体の製造方法
US9048091B2 (en) * 2013-03-25 2015-06-02 Infineon Technologies Austria Ag Method and substrate for thick III-N epitaxy
US9330908B2 (en) * 2013-06-25 2016-05-03 Globalfoundries Inc. Semiconductor structure with aspect ratio trapping capabilities
US9455327B2 (en) 2014-06-06 2016-09-27 Qorvo Us, Inc. Schottky gated transistor with interfacial layer
JP2014237581A (ja) * 2014-07-01 2014-12-18 セイコーエプソン株式会社 立方晶炭化珪素半導体基板
JP6405784B2 (ja) * 2014-08-11 2018-10-17 富士通株式会社 光電変換素子
US9536803B2 (en) 2014-09-05 2017-01-03 Qorvo Us, Inc. Integrated power module with improved isolation and thermal conductivity
EP3198649A4 (fr) * 2014-09-25 2018-05-16 Intel Corporation Structures de dispositif d'épitaxie iii-n sur des structures mesa de silicium autoportants
US10062684B2 (en) 2015-02-04 2018-08-28 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US10615158B2 (en) 2015-02-04 2020-04-07 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US9704705B2 (en) 2015-09-08 2017-07-11 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation via reaction with active species
US9773898B2 (en) 2015-09-08 2017-09-26 Macom Technology Solutions Holdings, Inc. III-nitride semiconductor structures comprising spatially patterned implanted species
US9799520B2 (en) 2015-09-08 2017-10-24 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation via back side implantation
US9673281B2 (en) 2015-09-08 2017-06-06 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions
US9627473B2 (en) 2015-09-08 2017-04-18 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation in III-nitride material semiconductor structures
US10211294B2 (en) 2015-09-08 2019-02-19 Macom Technology Solutions Holdings, Inc. III-nitride semiconductor structures comprising low atomic mass species
US20170069721A1 (en) 2015-09-08 2017-03-09 M/A-Com Technology Solutions Holdings, Inc. Parasitic channel mitigation using silicon carbide diffusion barrier regions
US9806182B2 (en) 2015-09-08 2017-10-31 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using elemental diboride diffusion barrier regions
US9960127B2 (en) 2016-05-18 2018-05-01 Macom Technology Solutions Holdings, Inc. High-power amplifier package
US10134658B2 (en) 2016-08-10 2018-11-20 Macom Technology Solutions Holdings, Inc. High power transistors
US9917156B1 (en) 2016-09-02 2018-03-13 IQE, plc Nucleation layer for growth of III-nitride structures
EP3503163A1 (fr) * 2017-12-21 2019-06-26 EpiGan NV Procédé de formation d'un film de carbure de silicium sur un substrat de silicium
US11038023B2 (en) 2018-07-19 2021-06-15 Macom Technology Solutions Holdings, Inc. III-nitride material semiconductor structures on conductive silicon substrates

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786606A (en) * 1995-12-15 1998-07-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
WO1998047170A1 (fr) * 1997-04-11 1998-10-22 Nichia Chemical Industries, Ltd. Procede assurant la croissance de semi-conducteurs de nitrure, substrat semi-conducteur de nitrure et dispositif semi-conducteur au nitrure.

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147087A (en) 1976-06-01 1977-12-07 Mitsubishi Electric Corp Semiconductor light emitting display device
EP0049286B1 (fr) 1980-04-10 1988-03-02 Massachusetts Institute Of Technology Procede de production de feuilles d'un materiau cristallin et dispositifs fabriques a partir de ces feuilles
US4522661A (en) 1983-06-24 1985-06-11 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Low defect, high purity crystalline layers grown by selective deposition
US4651407A (en) 1985-05-08 1987-03-24 Gte Laboratories Incorporated Method of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formation
US5326716A (en) 1986-02-11 1994-07-05 Max Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Liquid phase epitaxial process for producing three-dimensional semiconductor structures by liquid phase expitaxy
US4876210A (en) 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
US4866005A (en) * 1987-10-26 1989-09-12 North Carolina State University Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide
US4912064A (en) * 1987-10-26 1990-03-27 North Carolina State University Homoepitaxial growth of alpha-SiC thin films and semiconductor devices fabricated thereon
US4865685A (en) * 1987-11-03 1989-09-12 North Carolina State University Dry etching of silicon carbide
US5156995A (en) * 1988-04-01 1992-10-20 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers
JP3026087B2 (ja) 1989-03-01 2000-03-27 豊田合成株式会社 窒化ガリウム系化合物半導体の気相成長方法
US5192477A (en) * 1989-06-14 1993-03-09 Basf Aktiengesellschaft Surface treatment of polyamide moldings
US4946547A (en) * 1989-10-13 1990-08-07 Cree Research, Inc. Method of preparing silicon carbide surfaces for crystal growth
JPH03132016A (ja) 1989-10-18 1991-06-05 Canon Inc 結晶の形成方法
JPH04188678A (ja) 1990-11-19 1992-07-07 Matsushita Electric Ind Co Ltd 半導体発光素子
JP3267983B2 (ja) 1991-02-14 2002-03-25 株式会社東芝 半導体発光素子及びその製造方法
JP2954743B2 (ja) 1991-05-30 1999-09-27 京セラ株式会社 半導体発光装置の製造方法
JP3352712B2 (ja) 1991-12-18 2002-12-03 浩 天野 窒化ガリウム系半導体素子及びその製造方法
JPH0818159A (ja) 1994-04-25 1996-01-19 Hitachi Ltd 半導体レーザ素子及びその作製方法
JPH0864791A (ja) 1994-08-23 1996-03-08 Matsushita Electric Ind Co Ltd エピタキシャル成長方法
US5631190A (en) 1994-10-07 1997-05-20 Cree Research, Inc. Method for producing high efficiency light-emitting diodes and resulting diode structures
JPH08116093A (ja) 1994-10-17 1996-05-07 Fujitsu Ltd 光半導体装置
JPH08125251A (ja) 1994-10-21 1996-05-17 Matsushita Electric Ind Co Ltd 六方晶半導体リング共振器
JP2953326B2 (ja) 1994-11-30 1999-09-27 日亜化学工業株式会社 窒化ガリウム系化合物半導体レーザ素子の製造方法
JP2795226B2 (ja) 1995-07-27 1998-09-10 日本電気株式会社 半導体発光素子及びその製造方法
US6377596B1 (en) 1995-09-18 2002-04-23 Hitachi, Ltd. Semiconductor materials, methods for fabricating semiconductor materials, and semiconductor devices
JPH0993315A (ja) 1995-09-20 1997-04-04 Iwatsu Electric Co Ltd 通信機器構造
JP3396356B2 (ja) 1995-12-11 2003-04-14 三菱電機株式会社 半導体装置，及びその製造方法
KR100214073B1 (ko) 1995-12-16 1999-08-02 김영환 비피에스지막 형성방법
JPH09174494A (ja) 1995-12-21 1997-07-08 Toyox Co Ltd 屋根材の角孔開け機
JP2982949B2 (ja) 1996-01-26 1999-11-29 油井 一夫 透明瓶内封入用揺動型マスコット人形、およびそれを使った置物
JPH09277448A (ja) 1996-04-15 1997-10-28 Fujikura Ltd プラスチックラミネート紙の接続方法
JPH09290098A (ja) 1996-04-26 1997-11-11 Sanyo Electric Co Ltd 衣類乾燥機
JPH09324997A (ja) 1996-06-05 1997-12-16 Toshiba Corp 熱交換器および熱交換器の製造方法
US5710057A (en) 1996-07-12 1998-01-20 Kenney; Donald M. SOI fabrication method
KR19980079320A (ko) 1997-03-24 1998-11-25 기다오까다까시 고품질 쥐에이엔계층의 선택성장방법, 고품질 쥐에이엔계층 성장기판 및 고품질 쥐에이엔계층 성장기판상에 제작하는 반도체디바이스
JPH10275936A (ja) * 1997-03-28 1998-10-13 Rohm Co Ltd 半導体発光素子の製法
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US5915194A (en) * 1997-07-03 1999-06-22 The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration Method for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereon
TW393785B (en) * 1997-09-19 2000-06-11 Siemens Ag Method to produce many semiconductor-bodies
JP3036495B2 (ja) 1997-11-07 2000-04-24 豊田合成株式会社 窒化ガリウム系化合物半導体の製造方法
US6051849A (en) * 1998-02-27 2000-04-18 North Carolina State University Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer
SE512259C2 (sv) * 1998-03-23 2000-02-21 Abb Research Ltd Halvledaranordning bestående av dopad kiselkarbid vilken innefattar en pn-övergång som uppvisar åtminstone en ihålig defekt och förfarande för dess framställning
US6500257B1 (en) 1998-04-17 2002-12-31 Agilent Technologies, Inc. Epitaxial material grown laterally within a trench and method for producing same
US6255198B1 (en) * 1998-11-24 2001-07-03 North Carolina State University Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786606A (en) * 1995-12-15 1998-07-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
WO1998047170A1 (fr) * 1997-04-11 1998-10-22 Nichia Chemical Industries, Ltd. Procede assurant la croissance de semi-conducteurs de nitrure, substrat semi-conducteur de nitrure et dispositif semi-conducteur au nitrure.
EP0942459A1 (fr) * 1997-04-11 1999-09-15 Nichia Chemical Industries, Ltd. Procede assurant la croissance de semi-conducteurs de nitrure, substrat semi-conducteur de nitrure et dispositif semi-conducteur au nitrure.

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BOO J-H ET AL: "Growth of hexagonal GaN thin films on Si(111) with cubic SiC buffer layers", SECOND INTERNATIONAL CONFERENCE ON NITRIDE SEMICONDUCTORS, TOKUSHIMA, JAPAN, 27-31 OCT. 1997, vol. 189-190, June 1998 (1998-06-01), Journal of Crystal Growth, Elsevier, Netherlands, pages 183 - 188, XP004148500, ISSN: 0022-0248 *
LINTHICUM K J ET AL: "Process routes for low defect-density GaN on various substrates employing pendeo-epitaxial growth techniques", MRS INTERNET JOURNAL OF NITRIDE SEMICONDUCTOR RESEARCH, 1999, vol. 4S1, no. G4.9, 30 November 1998 (1998-11-30) - 4 December 1998 (1998-12-04), Fall Meeting of the Materials Research Society, Boston, XP002117210, ISSN: 1092-5783 *
STECKL A J ET AL: "SiC rapid thermal carbonization of the (111)Si semiconductor-on-insulator structure and subsequent metalorganic chemical vapor deposition of GaN", APPLIED PHYSICS LETTERS, USA, vol. 69, no. 15, 7 October 1996 (1996-10-07), pages 2264 - 2266, XP002135597, ISSN: 0003-6951 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6582986B2 (en) 1999-10-14 2003-06-24 Cree, Inc. Single step pendeo-and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures
US6764932B2 (en) 1999-10-14 2004-07-20 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures
US6803602B2 (en) 1999-10-14 2004-10-12 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
US6812053B1 (en) 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
US6955977B2 (en) 1999-10-14 2005-10-18 Cree, Inc. Single step pendeo-and lateral epitaxial overgrowth of group III-nitride epitaxial layers with group III-nitride buffer layer and resulting structures
US7361576B2 (en) 2005-05-31 2008-04-22 The Regents Of The University Of California Defect reduction of non-polar and semi-polar III-Nitrides with sidewall lateral epitaxial overgrowth (SLEO)
US7955983B2 (en) 2005-05-31 2011-06-07 The Regents Of The University Of California Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO)
US9257342B2 (en) 2012-04-20 2016-02-09 Infineon Technologies Ag Methods of singulating substrates to form semiconductor devices using dummy material
US9741618B2 (en) 2012-04-20 2017-08-22 Infineon Technologies Ag Methods of forming semiconductor devices
CN105247665A (zh) * 2013-05-31 2016-01-13 三垦电气株式会社 半导体装置
US9406564B2 (en) 2013-11-21 2016-08-02 Infineon Technologies Ag Singulation through a masking structure surrounding expitaxial regions

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