WO1993014570A1 - Procede et dispositif de reglage d'un signal d'impulsions d'horloge generees de maniere interne - Google Patents

Procede et dispositif de reglage d'un signal d'impulsions d'horloge generees de maniere interne Download PDF

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Publication number
WO1993014570A1
WO1993014570A1 PCT/SE1993/000034 SE9300034W WO9314570A1 WO 1993014570 A1 WO1993014570 A1 WO 1993014570A1 SE 9300034 W SE9300034 W SE 9300034W WO 9314570 A1 WO9314570 A1 WO 9314570A1
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WIPO (PCT)
Prior art keywords
clk
frequency
clock pulse
pulse signal
signal
Prior art date
Application number
PCT/SE1993/000034
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English (en)
Inventor
Jan-Olov BERGSTRÖM
Lars Liljegren
Original Assignee
Asea Brown Boveri Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri Ab filed Critical Asea Brown Boveri Ab
Publication of WO1993014570A1 publication Critical patent/WO1993014570A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to a method and a device for obtaining an internal reference signal in an electronic circuit, realizable in a highly integrated circuit, a so- called ASIC circuit, for example applied to a logic circuit 10 which communicates via a databus with external reference units which deliver clock pulses stable in frequency.
  • the invention relates to a circuit which can be integrated on a chip and which has a so-called frequency-locked loop (FLL circuit) for generation and tuning of an internal clock pulse signal in an electronic slave unit connected to a superordinate electronic master unit where the circuit during communication between the slave unit and the master unit receives external clock signals, which are stable in frequency but noisy, in message packets, whereby a second clock pulse signal, a sampling signal, internally generated in the FLL circuit is compared with respect to phase with the external clock pulses in a phase-locked loop, whereupon, in dependence on the phase position of the sampling signal compared with the external clock pulses, control pulses are formed which influence the clock pulse generator for the sampling signal such that this is phase-locked to the external clock pulse signal.
  • FLL circuit frequency-locked loop
  • the internal clock pulse signal is compared with respect to frequency with the sampling signal, whereupon the internal clock pulse generator of the FLL circuit changes frequency in discrete small steps in the internal clock pulse signal without any disturbing phase shift until a desired fixed frequency ratio between the frequency for the internal clock pulse signal of the circuit and the frequency for the external clock pulse signal is achieved.
  • the circuit according to the invention is based on digital logic as well as analog low-pass filters and analog voltage- controlled oscillator (VCO) and does not employ crystal or ceramic oscillators and can therefore be fully integrated and miniaturized and thus be realized on microchips, for example in the form of ASIC circuits.
  • VCO voltage- controlled oscillator
  • the FLL circuit is preceded by a discriminator which recog ⁇ nizes the message packet with pulse frequencies of good accuracy. Adjustment of the frequency of the second internal clock signal of the circuit, the sampling circuit, takes place only when message packets accepted by the discrimi ⁇ nator occur.
  • the phase-locked loop in the FLL circuit is controlled via the clock pulse signal internally generated in the FLL circuit when message packets have not arrived via the databus. In this way, a faster building up of the phase- locked loop is obtained when message packets with good accuracy arrive.
  • the phase-locked loop is locked to the external clock pulse signal which is supplied to the FLL circuit when message packets occur, whereas it is locked to the clock pulse signal internally generated in the circuit when no such external message packets have been supplied.
  • phase detector In the implementation of the phase-locked loop a phase detector is included which is set to zero at the start of each message packet and each time the phase-locked loop is changed to become locked to the clock pulse signal inter ⁇ nally generated in the FLL circuit, which minimizes the phase errors in the phase-locked loop.
  • An internal reference clock in the form of the FLL circuit according to the invention occupies a considerably smaller surface on a printed-circuit board, results in lower cost and higher reliability than internal reference clocks where the prior art described above is used.
  • Figure 1 illustrates a simplified diagram of a master-slave communication system.
  • Figure 2 shows a block diagram of the FLL circuit according to the invention.
  • Figure 3 shows the function of the flank detector ED, whereas Figure 3d shows delay elements included in the flank detector ED.
  • Figure 4 illustrates the relationship between the signals CLK_SMP, EX_CLK and EX_EDGES.
  • Figure 5 shows a block diagram of the phase-locked loop or the PLL circuit.
  • Figure 6 illustrates the ratio of the UP/DOWN signals of the PLL circuit to the frequency characteristic of the sampling signal CLK_SMP.
  • FIG. 7 illustrates the generation of the signal TIME_OUT.
  • Figure 8 shows the appearance and the relation in time between the signals EX_EDGES, TIME_OUT, HOLD and INTERN.
  • Figure 9 illustrates a block diagram of the tuniig control TC.
  • Figure 10 shows a block diagram of the internal reference clock IRC.
  • Figure 11 illustrates a typical building up of tiie frequency of the internal clock.
  • Figure 1 shows the general configuration of a communication system, for example in the form of a process control system according to the conventional technique, with a master unit 1 which communicates via a databus 2 with slave units 3.
  • the master unit 1, or the master usually consists of a process computer whereas the slave units 3, the slaves, contain, inter alia, logic circuits for decoding information received.
  • Over the databus data is transmitted to and from the slaves by means of frequency-stable but noisy clock pulse signals in the form of frames.
  • These frames are of the types address frames and data frames, both types being at least 32 cycles long in the embodiment described.
  • the address frames are generated by the master and the signal frequency of the frames in the described embodiment is 1.5 Mbit/s. These frames will be referred to in the following as message packets.
  • both of these units must have access to an internal reference clock with good accuracy.
  • an FLL circuit a frequency-locked loop, will be described which, from frequency-stable address frames received, via the databus 2, generates an internal reference clock signal in the respective slave unit 3 without the use of crystal or ceramic oscillators.
  • the FLL circuit generally described above which is shown in a block diagram in Figure 2, comprises a phase-locked loop, hereinafter referred to as PLL only, or PLL circuit, and a control unit therefor, a PLL control unit PLL-C. Further, there are included a flank detector ED and a tuning control TC which controls an internal reference clock IRC.
  • External clock pulse signals EX_CLK are supplied to the flank detector ED, whereas the internal clock pulse reference signal CLK_IR, generated in the FLL circuit, is obtained at the output of the internal reference clock IRC.
  • the PLL circuit When no external clock pulse signals EX_CLK occur, that is, there is a pause in the communication via the databus, the PLL circuit is locked to the internal clock pulse frequency CLK_IR for the PLL circuit to be supplied with an approxi ⁇ mately correct reference frequency.
  • the PLL control unit PLL-C ensures that the PLL circuit is locked to the external clock pulse signal EX_CLK instead.
  • the PLL control unit PLL_C controls a multiplexor MUX at the input of the PLL circuit, where the multiplexor MUX exchanges the phase locking of the PLL circuit for one of the two above- mentioned reference signals.
  • the frequency of this signal is compared with the internal clock pulse signal CLK_IR in the tuning control TC. Then when the message packet is completed, the tuning control TC increases or reduces the frequency of the internal clock pulse signal CLK_IR depending on the result of the comparison.
  • the adjustments of the frequency of the internal clock pulse signal CLK_IR are carried out in steps involving a 0.10% change of the frequency in the upward or downward direction.
  • the FLL circuit compares in relation to all the message packets on the databus with the internal clock pulse signal CLK_IR.
  • the recognition of frequency-stable address message packets is taken care of by a discriminator which precedes the FLL circuit and will not be described further in this description. Adjustment of the frequency of the internal clock pulse signal CLK_IR is performed only after message packets which have been accepted by the discriminator.
  • flank detector ED The purpose of the flank detector ED is to sample the internal clock pulse signal CLK_IR, which in the example approximately has the frequency 6 MHz, and the external clock pulse signal EX_CLK. The flank detector ED will generate a short pulse caused by each falling flank of the external clock pulse signal EX_CLK and of the internal clock pulse signal CLK__IR, respectively.
  • the sampling clock for generating the second internal clock pulse signal consists of a 24 MHz clock pulse signal CLK_SMP generated by the PLL circuit.
  • CLK_SMP generated by the PLL circuit.
  • a negative pulse, a flank pulse EX_EDGES, with the pulse length of one CLK_SMP is created in the flank detec ⁇ tor ED (Fig. 3a) .
  • the flank detector ED has been designed according to Figure 3b with a plurality of parallel-connected delay elements 5. This results in the occurrence of a time lag of two CLK_SMP cycles between the incoming falling flank of the external clock pulse signal EX_CLK and the generated flank pulse EX_EDGES. This does not influence the function of the FLL circuit.
  • Figure 4 illustrates the time lag described.
  • the PLL circuit with the block diagram according to Figure 5 utilizes two different signals as references. These consist of either the flank pulses EX_EDGES with the frequency 1.5 MHz or of the flank pulses S_IR with the frequency 6 MHz obtained from the internal clock pulse signal CLK_IR at an output of the flank detector ED, where the internal clock pulse signal CLK_IR is sampled against the sampling signal CLK SMP.
  • the sampling signal CLK_SMP is obtained with a frequency in the order of 24 MHz in a voltage-controlled oscillator VCO.
  • the sampling signal CLK_SMP is fed back to a frequency divider 6, where the frequency of the sampling signal CLK_SMP is frequency-divided into two different signals, one, MOD4, with the frequency of the sampling signal divided by four and the other, MOD16, with the frequency of the sampling signal divided by 16..
  • the MOD4- and MODl ⁇ -signals consist of pulses with the duration of one CLK_SMP cycle.
  • the multiplexor MUX in the PLL circuit is controlled by the output signal INTERN of the PLL control circuit PLL-C, which output signal is passive, is kept at a low level, when a message packet has arrived.
  • the creation of the signal INTERN will be described below.
  • flank pulses S_IR are used as reference in the phase detector PD in the PLL circuit; if not, the flank pulses EX_EDGES are used as reference.
  • the signal INTERN is active, the internal flank pulses S_IR are used as reference in the phase detector PD in the PLL circuit; if not, the flank pulses EX_EDGES are used as reference.
  • the signal INTERN is active, the internal flank pulses S_IR are used as reference in the phase detector PD in the PLL circuit; if not, the flank pulses EX_EDGES are used as reference.
  • the signal INTERN the signal
  • flank pulses EX_EDGES are compared with the signal MOD16, whereupon the PLL circuit multiplies the. external clock pulse signal EX_CLK by 16.
  • the flank -pulses S_IR are compared with the signal MOD4, whereupon the PLL circuit multiplies the internal clock pulse signal CLK_IR by 4.
  • the signal HOLD from the PLL control unit PLL-C is active, that is, it is at a high level, which it is only during one CLK_SMP cycle, namely, at the start of a message packet and at the end of a message packet.
  • the creation of this signal HOLD will be described below.
  • a high level the frequency divider 6 and the phase detector PD are reset if the signal INTERN changes status. This means that the phase detector PD is set to zero at the start of each message packet and each time the phase detector is changed to locking to the internal clock pulse signal CLK IR, which at the same time entails a minimization of an initial phase error in the phase-locked PLL circuit.
  • the phase detector is a phase/frequency detector with a HOLD input supplied thereto. This restores the locking to recep ⁇ tion or transmission of the phase detector PD such that reception can start with a minimal phase error.
  • the output of the phase detector delivers the signals UP and DOWN or none of these signals, where the signal UP indicates that the frequency of the sampling signal CLK_SMP is to be increased, whereas the signal DOWN indicates that the frequency of the sampling signal CLK_SMP is to be reduced.
  • These two signals UP, DOWN control a current pump CP, which charges a capacitor C2 via a resistor R2 during the period when the signal UP or DOWN is present.
  • the voltage across the resistor and the capacitor constitutes control voltage for the voltage-controlled oscillator VCO.
  • the ratio of the UP and DOWN signals to the frequency characteristic of the sampling signal CLK_SMP is illustrated in Figure 6.
  • the interval 7 shows the frequency jump, whereas the curve 8 denotes the degree of frequency change of the sampling signal CLK_SMP at an active UP or DOWN signal.
  • the purpose of the PLL control unit PLL-C is that this should determine when a message packet starts and ends and, with information about this, generate control signals which are required in the PLL circuit and in the tuning control TC.
  • EX_EDGES of the external clock pulse signal EX_CLK If a counter is reset by the flank pulses EX_EDGES and is clocked by the flank pulses S_IR, the counter reaches the value 4, or 5 at the most if the internal clock is poorly adjusted, before the counter is again reset by a new EX_EDGES flank pulse. On the other hand, if the counter reaches the number 6, or possibly the number 7 if the clock is poorly adjusted, then it is known for certain that the message packet in question is terminated. In this case, in the circuit logic in the PLL control unit PLL-C, a pulse is generated in a signal designated TIME_OUT with a pulse length as in the internal clock pulse signal CLK_IR. Figure 7 illustrates an example of the formation of the signal TIME_OUT.
  • the signal INTERN which controls, inter alia, the multiplexor MUX in the PLL circuit is given a low level while a message packet is present. This low status level of the signal INTERN is initiated when the first new flank pulse EX_EDGES in a message packet occurs and returns when the signal TIME_0UT marks that a message packet is terminated.
  • the latter signal HOLD is high only during one sampling signal CLK_SMP cycle, namely, when the first new flank pulse EX_EDGES in a message packet occurs, and when the signal TIME_0UT marks that a message packet is terminated. The appearance and relation in time between these signals are illustrated in Figure 8.
  • the signals INTERN and HOLD are generated in a status device in the PLL control unit PLL-C.
  • the task of the tuning control TC is to compare the internal frequency with the external clock pulse frequency obtained via the databus 2 during the period when a message packet is present.
  • the tuning control TC emits a control signal to the internal reference clock IRC which increases or reduces the frequency of the internal reference clock IRC in steps of 0.10%.
  • the sampling signal CLK_SMP from the PLL circuit which is locked to the signal frequency of the external bus while a message packet is present, is compared with the frequency of the internal clock pulse signal CLK_IR.
  • the frequency of the sampling signal CLK_SMP is 16 times higher than the frequency of the external clock pulse signal EX__CLK, it must be divided by 4 to be adapted in frequency to the frequency of the flank pulses S_IR of the internal clock. This is achieved by a mode 4-counter M4, which generates a 6 MHz signal CY.
  • the counter M4 is preceded by a reset unit RS.
  • the reset unit RS When the first flank pulses S_IR arrive after a message packet has occurred, which is known through the signal INTERN, the reset unit RS generates a signal REL to the reset inputs of the counter M4 and the UP/DOWN counter U/D which starts the counter M4 and the UP/DOWN counter U/D. This signal REL is given a low level status when a message packet is terminated and resets the counters until the next message packet has arrived.
  • the UP/DOWN counter U/D counts up one step for each CY signal pulse and counts down one step for each fiank pulse S_IR. To avoid problems which may arise if a count-up and a count-down pulse occur simultaneously, the UP/DOWN counter U/D is preceded by a blocking circuit BL, which jcancels the pulses occurring simultaneously in the signals CY and S_IR.
  • the JP/DOWN counter U/D steps upwards or downwards. The most significant bit MSB will then show, at the end of the message packet, if " the internal frequency is to be increased or reduced.
  • a stop circuit SL has been introduced which generates a signal to the blocking circuit BL, which stop circuit then does not allow counting up or counting down in the UP/DOWN counter U/D for the remainder of the message packet if the counter has reached the number +3 or -3.
  • the TIME_OUT pulse forms seven S_IR pulses after the last flank pulse EX_EDGES in a message packet. Because of this, the PLL circuit, which normally receives a new flank pulse EX_EDGES for every fourth S_IR pulse, will reduce its frequency, the sampling frequency, which may entail an incorrect result in the frequency comparison according to the above. For this reason, a delay unit DEL is introduced in the tuning control TC. This delay unit delays the information about the most significant bit by four S_IR pulses.
  • a pulse generator PULSER creates either an F_UP pulse to increase or an F_DOWN pulse to reduce the frequency of the internal clock pulse signal CLK_IR, which is generated in the internal reference clock IRC. These pulses are synchronized by the sampling signal CLK_SMP, since it is possible that the output of the delay unit DEL changes status at the beginning of the TIME_OUT pulse.
  • the frequency of the internal reference clock IRC shall be digitally variable within ⁇ 10% from the centre frequency in steps of 0.10%.
  • a block diagram for the internal reference clock IRC is shown in Figure 10.
  • An 8-bit UP/DOWN counter U/D-IRC counts up by one or counts down by one when pulse F_UP or F_DOWN occurs.
  • a limiting circuit LIM and a blocking unit BL-IRC prevent the counter from being greater than the number 255 or lower than the number 0. This is a precautionary measure taken since the event should never occur if the frequency of the external clock pulse signal EX_CLK multiplied by 4 lies above the frequency interval for the voltage-controlled oscillator VCO-IRC.
  • the output signal of the UP/DOWN counter U/D-IRC is transformed into a voltage between IV and 3 in a D/A converter.
  • the voltage is transformed into the desired frequency by a linear voltage-controlled oscillator VCO-IRC.
  • Figure 11 shows a typical building up of the frequency of the internal clock.
  • the circuit logic in the functional blocks described above is realized with conventional digital function elements. This means that the entire phase-locked loop according to the invention can be built up in one single circuit, for example miniaturized in an ASIC circuit.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

On décrit un circuit qui peut être intégré sur des puces avec une boucle à verrouillage de phase (circuit FLL), destiné à générer et à régler un signal d'impulsions d'horloge internes (CLK-IR) dans une unité asservie électronique (3) reliée à une unité pilote électronique superordonnée (1). Le circuit (FLL), lors de la communication entre l'unité asservie (3) et l'unité pilote (1), reçoit des impulsions d'horloge externes à fréquences stables mais bruyantes (EX-CLK) sous la forme de paquets de messages, un second signal d'impulsions d'horloge générées de manière interne dans le circuit FLL, un signal d'échantillonnage (CLK-SMP), ladite fréquence étant comparée à la phase d'impulsions d'horloge externes (EX-CLK) dans une boucle à verrouillage de phase. En fonction de la position de phase du signal d'échantillonnage (CLK-SMP) comparé aux impulsions d'horloge externes (EX-CLK), des impulsions d'horloge sont formées et influencent le générateur d'impulsions d'horloge pour le signal d'échantillonnage (CLK-SMP) de telle façon que celui-ci est verrouillé en phase dans un rapport de fréquence défini par rapport au signal d'impulsions d'horloge externes (EX-CLK). Le signal d'impulsions d'horloge internes (CLK-IR) est comparé à la fréquence du signal d'échantillonnage (CLK-SMP); le générateur d'impulsions d'horloge internes (IRC) du circuit FLL modifie la fréquence en petites étapes discrètes dans le signal d'impulsions d'horloge internes (CLK-IR) sans décalage de phase perturbateur jusqu'à ce que la fréquence du signal d'impulsions d'horloge internes (CLK-IR) du circuit et la fréquence du signal d'impulsions d'horloge externes (EX-CLK) soient en accord.
PCT/SE1993/000034 1992-01-20 1993-01-19 Procede et dispositif de reglage d'un signal d'impulsions d'horloge generees de maniere interne WO1993014570A1 (fr)

Applications Claiming Priority (2)

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SE9200137-9 1992-01-20
SE9200137A SE502458C2 (sv) 1992-01-20 1992-01-20 Förfarande och anordning för avstämning av internt genererad klockpulssignal

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WO1993014570A1 true WO1993014570A1 (fr) 1993-07-22

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WO (1) WO1993014570A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726713A1 (fr) * 1994-11-09 1996-05-10 Sgs Thomson Microelectronics Circuit de transmission de donnees en mode asynchrone a frequence libre de reception calee sur la frequence d'emission
WO1998056135A2 (fr) * 1997-06-03 1998-12-10 Abb Research Ltd. Procede permettant une synchronisation temporelle dans un reseau
WO1999053639A1 (fr) * 1998-04-09 1999-10-21 Nokia Networks Oy Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131861A (en) * 1977-12-30 1978-12-26 International Business Machines Corporation Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
EP0224884A2 (fr) * 1985-12-02 1987-06-10 AT&T Corp. Circuit de synchronisation d'horloge
US4835481A (en) * 1986-09-30 1989-05-30 Siemens Aktiengesellschaft Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131861A (en) * 1977-12-30 1978-12-26 International Business Machines Corporation Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
EP0224884A2 (fr) * 1985-12-02 1987-06-10 AT&T Corp. Circuit de synchronisation d'horloge
US4835481A (en) * 1986-09-30 1989-05-30 Siemens Aktiengesellschaft Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726713A1 (fr) * 1994-11-09 1996-05-10 Sgs Thomson Microelectronics Circuit de transmission de donnees en mode asynchrone a frequence libre de reception calee sur la frequence d'emission
EP0712210A1 (fr) * 1994-11-09 1996-05-15 STMicroelectronics S.A. Circuit de transmission de données en mode asynchrone à fréquence libre de réception calée sur la fréquence d'émission
US5805650A (en) * 1994-11-09 1998-09-08 Sgs-Thomson Microelectronics S.A. Circuit for data transmission in asynchronous mode with a free reception frequency locked on the transmission frequency
WO1998056135A2 (fr) * 1997-06-03 1998-12-10 Abb Research Ltd. Procede permettant une synchronisation temporelle dans un reseau
WO1998056136A2 (fr) * 1997-06-03 1998-12-10 Abb Research Ltd. Procede servant a realiser une synchronisation dans le temps dans un reseau
WO1998056135A3 (fr) * 1997-06-03 1999-03-04 Abb Research Ltd Procede permettant une synchronisation temporelle dans un reseau
WO1998056136A3 (fr) * 1997-06-03 1999-03-04 Abb Research Ltd Procede servant a realiser une synchronisation dans le temps dans un reseau
WO1999053639A1 (fr) * 1998-04-09 1999-10-21 Nokia Networks Oy Unite de commande de noeud d'un noeud d'acces dans un reseau de telecommunication

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Publication number Publication date
SE9200137L (sv) 1993-07-21
SE502458C2 (sv) 1995-10-23
AU3413493A (en) 1993-08-03
SE9200137D0 (sv) 1992-01-20

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