WO1993014570A1

WO1993014570A1 - Method and device for tuning of an internal generated clock pulse signal

Info

Publication number: WO1993014570A1
Application number: PCT/SE1993/000034
Authority: WO
Inventors: Jan-Olov BERGSTRÖM; Lars Liljegren
Original assignee: Asea Brown Boveri Ab
Priority date: 1992-01-20
Filing date: 1993-01-19
Publication date: 1993-07-22
Also published as: AU3413493A; SE502458C2; SE9200137D0; SE9200137L

Abstract

A circuit, which can be integrated on chips, with a so-called phase-locked loop (FLL circuit) for generation and tuning of an internal clock pulse signal (CLK-IR) in an electronic slave unit (3) connected to a superordinate electronic master unit (1) where the circuit (FLL) during communication between the slave unit (3) and the master unit (1) receives external frequency-stable but noisy clock pulses (EX-CLK) in the form of message packets, a second clock pulse signal internally generated in the FLL circuit, a sampling signal (CLK-SMP), being compared with respect to phase with the external clock pulses (EX-CLK) in a phase-locked loop, whereupon, in dependence on the phase position of the sampling signal (CLK-SMP) compared with the external clock pulses (EX-CLK), control pulses are formed which influence the clock pulse generator for the sampling signal (CLK-SMP), such that this is locked in phase in a definite frequency ratio to the external clock pulse signal (EX-CLK). The internal clock pulse signal (CLK-IR) is compared with respect to frequency with the sampling signal (CLK-SMP), whereupon the internal clock pulse generator (IRC) of the FLL circuit changes frequency in discrete small steps in the internal clock pulse signal (CLK-IR) without any disturbing phase shift until the frequency of the internal clock pulse signal (CLK-IR) of the circuit and the frequency of the external clock pulse signal (EX-CLK) are in agreement.

Description

METHOD AND DEVICE FOR TUNING OF AN INTERNAL GENERATED CLOCK PULSE SIGNAL.

TECHNICAL FIELD 5

The present invention relates to a method and a device for obtaining an internal reference signal in an electronic circuit, realizable in a highly integrated circuit, a so- called ASIC circuit, for example applied to a logic circuit 10 which communicates via a databus with external reference units which deliver clock pulses stable in frequency.

BACKGROUND ART

15 In process control systems or corresponding electronic systems in which a superordinate electronic unit, a master, communicates with subordinate units, so-called slaves, via a communication link, for example by serial communication via a databus, it is necessary for the slaves to be equipped

20 with an internal clock, which generates clock pulse signals with the same frequency as, or with a multiple of the frequency of, the external clock with its frequency-stable • clock pulse signal in the superordinate unit to enable communication between the superordinate unit and the logic

25 circuits in the slaves. To control the digital logic in the slaves, above all when they are of synchronous design, a stable reference is also used, which may have another frequency than the previously mentioned one. Usually, these necessary frequency-stable clock pulses in both the master

30 unit and in the slaves are accomplished by providing them with crystal-controlled or ceramic oscillators to create stable reference frequencies for the logic circuits of both the master and the slaves.

5 As an example may be mentioned that in a process control system for monitoring of, for example, external transducers and actuators from a- superordinate central unit, usually a computer, where the communication between the central unit and the logic circuits of the transducers or the actuators in the associated slaves takes place by means of serial communication over a databus, it is common for the respec¬ tive slave to be equipped with a crystal oscillator which 5 generates a clock signal to the internal logic circuits of the slave, which clock signal is at the same time utilized as reference signal to a phase-locked loop which is used for signal synchronization when entering serial data from the superordinate central unit, or for such an oscillator with a 0 fixed frequency to be utilized in some other way as frequency reference in an internal clock frequency genera¬ tor. Examples of such technique can be found in the patent documents EP A2 224 884, EP Al 98 653, UA A 4 835 481.

5 When developing highly integrated logic circuits for use in miniaturized slave units, it is possible to realize simultaneous electronics on one single printed-circuit board, for example with only one or a few ASIC circuits. This causes problems when using conventional technique in 0 the form of crystal-controlled oscillators or ceramic oscillators to obtain the necessary frequency-stable reference signal, since these oscillators would take up too large a surface on a printed-circuit board. Such oscillators cannot be integrated o ) for example, the same ASIC circuit 5 if by integrated is meant, which is the case in this

• - description, that all the components associated with the circuit can be integrated in an IC without the need of connection or soldering of external components to the printed-circuit board or the printed-circuit pattern. In 0 addition, in a large process control system with up to several thousand slave units in one application, the technique of equipping each slave unit with an internal frequency-stable oscillator will be expensive. In addition, crystal or ceramic oscillators are both mechanically and 5 thermally sensitive. Besides, the reliability of such oscillators is not always sufficient. SUMMARY OF THE INVENTION

The invention relates to a circuit which can be integrated on a chip and which has a so-called frequency-locked loop (FLL circuit) for generation and tuning of an internal clock pulse signal in an electronic slave unit connected to a superordinate electronic master unit where the circuit during communication between the slave unit and the master unit receives external clock signals, which are stable in frequency but noisy, in message packets, whereby a second clock pulse signal, a sampling signal, internally generated in the FLL circuit is compared with respect to phase with the external clock pulses in a phase-locked loop, whereupon, in dependence on the phase position of the sampling signal compared with the external clock pulses, control pulses are formed which influence the clock pulse generator for the sampling signal such that this is phase-locked to the external clock pulse signal. The internal clock pulse signal is compared with respect to frequency with the sampling signal, whereupon the internal clock pulse generator of the FLL circuit changes frequency in discrete small steps in the internal clock pulse signal without any disturbing phase shift until a desired fixed frequency ratio between the frequency for the internal clock pulse signal of the circuit and the frequency for the external clock pulse signal is achieved.

The circuit according to the invention is based on digital logic as well as analog low-pass filters and analog voltage- controlled oscillator (VCO) and does not employ crystal or ceramic oscillators and can therefore be fully integrated and miniaturized and thus be realized on microchips, for example in the form of ASIC circuits.

The FLL circuit is preceded by a discriminator which recog¬ nizes the message packet with pulse frequencies of good accuracy. Adjustment of the frequency of the second internal clock signal of the circuit, the sampling circuit, takes place only when message packets accepted by the discrimi¬ nator occur.

The phase-locked loop in the FLL circuit is controlled via the clock pulse signal internally generated in the FLL circuit when message packets have not arrived via the databus. In this way, a faster building up of the phase- locked loop is obtained when message packets with good accuracy arrive.

The phase-locked loop is locked to the external clock pulse signal which is supplied to the FLL circuit when message packets occur, whereas it is locked to the clock pulse signal internally generated in the circuit when no such external message packets have been supplied.

In the implementation of the phase-locked loop a phase detector is included which is set to zero at the start of each message packet and each time the phase-locked loop is changed to become locked to the clock pulse signal inter¬ nally generated in the FLL circuit, which minimizes the phase errors in the phase-locked loop.

With the FLL circuit now described, it is consequently possible to generate an internal reference clock with a high accuracy for control of the digital synchronous logic of, for example, an ASIC while maintaining a correct symmetry of the clock such that the set-up and holding times of the internal flip-flops are not exceeded.

An internal reference clock in the form of the FLL circuit according to the invention occupies a considerably smaller surface on a printed-circuit board, results in lower cost and higher reliability than internal reference clocks where the prior art described above is used. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a simplified diagram of a master-slave communication system.

Figure 2 shows a block diagram of the FLL circuit according to the invention.

Figure 3 shows the function of the flank detector ED, whereas Figure 3d shows delay elements included in the flank detector ED.

Figure 4 illustrates the relationship between the signals CLK_SMP, EX_CLK and EX_EDGES.

Figure 5 shows a block diagram of the phase-locked loop or the PLL circuit.

Figure 6 illustrates the ratio of the UP/DOWN signals of the PLL circuit to the frequency characteristic of the sampling signal CLK_SMP.

Figure 7 illustrates the generation of the signal TIME_OUT.

Figure 8 shows the appearance and the relation in time between the signals EX_EDGES, TIME_OUT, HOLD and INTERN.

Figure 9 illustrates a block diagram of the tuniig control TC.

Figure 10 shows a block diagram of the internal reference clock IRC.

Figure 11 illustrates a typical building up of tiie frequency of the internal clock. DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference to the accompanying drawings.

Figure 1 shows the general configuration of a communication system, for example in the form of a process control system according to the conventional technique, with a master unit 1 which communicates via a databus 2 with slave units 3. The master unit 1, or the master, usually consists of a process computer whereas the slave units 3, the slaves, contain, inter alia, logic circuits for decoding information received. Over the databus, data is transmitted to and from the slaves by means of frequency-stable but noisy clock pulse signals in the form of frames. These frames are of the types address frames and data frames, both types being at least 32 cycles long in the embodiment described. The address frames are generated by the master and the signal frequency of the frames in the described embodiment is 1.5 Mbit/s. These frames will be referred to in the following as message packets.

To make possible communication between master 1 and slave 3, both of these units must have access to an internal reference clock with good accuracy. In the invention described, an FLL circuit, a frequency-locked loop, will be described which, from frequency-stable address frames received, via the databus 2, generates an internal reference clock signal in the respective slave unit 3 without the use of crystal or ceramic oscillators.

To be able to drive fast synchronous logic, there must be a stable reference clock which controls the logic within the slave unit.

The FLL circuit generally described above, which is shown in a block diagram in Figure 2, comprises a phase-locked loop, hereinafter referred to as PLL only, or PLL circuit, and a control unit therefor, a PLL control unit PLL-C. Further, there are included a flank detector ED and a tuning control TC which controls an internal reference clock IRC.

External clock pulse signals EX_CLK are supplied to the flank detector ED, whereas the internal clock pulse reference signal CLK_IR, generated in the FLL circuit, is obtained at the output of the internal reference clock IRC.

When no external clock pulse signals EX_CLK occur, that is, there is a pause in the communication via the databus, the PLL circuit is locked to the internal clock pulse frequency CLK_IR for the PLL circuit to be supplied with an approxi¬ mately correct reference frequency. When, on the other hand, a message packet occurs on the databus, the PLL control unit PLL-C ensures that the PLL circuit is locked to the external clock pulse signal EX_CLK instead. The PLL control unit PLL_C controls a multiplexor MUX at the input of the PLL circuit, where the multiplexor MUX exchanges the phase locking of the PLL circuit for one of the two above- mentioned reference signals.

If a message packet occurs such that the PLL circuit is phase-locked to the external clock pulse signal EX_CLK, the frequency of this signal is compared with the internal clock pulse signal CLK_IR in the tuning control TC. Then when the message packet is completed, the tuning control TC increases or reduces the frequency of the internal clock pulse signal CLK_IR depending on the result of the comparison. The adjustments of the frequency of the internal clock pulse signal CLK_IR are carried out in steps involving a 0.10% change of the frequency in the upward or downward direction.

The FLL circuit compares in relation to all the message packets on the databus with the internal clock pulse signal CLK_IR. The recognition of frequency-stable address message packets is taken care of by a discriminator which precedes the FLL circuit and will not be described further in this description. Adjustment of the frequency of the internal clock pulse signal CLK_IR is performed only after message packets which have been accepted by the discriminator.

The purpose of the flank detector ED is to sample the internal clock pulse signal CLK_IR, which in the example approximately has the frequency 6 MHz, and the external clock pulse signal EX_CLK. The flank detector ED will generate a short pulse caused by each falling flank of the external clock pulse signal EX_CLK and of the internal clock pulse signal CLK__IR, respectively.

The sampling clock for generating the second internal clock pulse signal, the sampling signal, consists of a 24 MHz clock pulse signal CLK_SMP generated by the PLL circuit. At each falling flank of the external clock pulse signal EX_CLK, a negative pulse, a flank pulse EX_EDGES, with the pulse length of one CLK_SMP, is created in the flank detec¬ tor ED (Fig. 3a) . The fact that the flank pulses EX_EDGES only last during one sampling cycle simplifies the logic in the PLL circuit to a considerable extent.

To avoid metastability, the flank detector ED has been designed according to Figure 3b with a plurality of parallel-connected delay elements 5. This results in the occurrence of a time lag of two CLK_SMP cycles between the incoming falling flank of the external clock pulse signal EX_CLK and the generated flank pulse EX_EDGES. This does not influence the function of the FLL circuit. Figure 4 illustrates the time lag described.

The PLL circuit with the block diagram according to Figure 5 utilizes two different signals as references. These consist of either the flank pulses EX_EDGES with the frequency 1.5 MHz or of the flank pulses S_IR with the frequency 6 MHz obtained from the internal clock pulse signal CLK_IR at an output of the flank detector ED, where the internal clock pulse signal CLK_IR is sampled against the sampling signal CLK SMP.

At the output from the PLL circuit, the phase-locked loop, the sampling signal CLK_SMP is obtained with a frequency in the order of 24 MHz in a voltage-controlled oscillator VCO.

The sampling signal CLK_SMP is fed back to a frequency divider 6, where the frequency of the sampling signal CLK_SMP is frequency-divided into two different signals, one, MOD4, with the frequency of the sampling signal divided by four and the other, MOD16, with the frequency of the sampling signal divided by 16..The MOD4- and MODlβ-signals consist of pulses with the duration of one CLK_SMP cycle.

The multiplexor MUX in the PLL circuit is controlled by the output signal INTERN of the PLL control circuit PLL-C, which output signal is passive, is kept at a low level, when a message packet has arrived. The creation of the signal INTERN will be described below.

If the signal INTERN is active, the internal flank pulses S_IR are used as reference in the phase detector PD in the PLL circuit; if not, the flank pulses EX_EDGES are used as reference. In case of an active signal INTERN, the signal

MOD4 is used as feedback, otherwise the signal MOD16 is used as feedback in the phase-locked loop. Thus, the flank pulses EX_EDGES are compared with the signal MOD16, whereupon the PLL circuit multiplies the. external clock pulse signal EX_CLK by 16. In a corresponding way, the flank -pulses S_IR are compared with the signal MOD4, whereupon the PLL circuit multiplies the internal clock pulse signal CLK_IR by 4.

The signal HOLD from the PLL control unit PLL-C is active, that is, it is at a high level, which it is only during one CLK_SMP cycle, namely, at the start of a message packet and at the end of a message packet. The creation of this signal HOLD will be described below. At an active HOLD signal, a high level, the frequency divider 6 and the phase detector PD are reset if the signal INTERN changes status. This means that the phase detector PD is set to zero at the start of each message packet and each time the phase detector is changed to locking to the internal clock pulse signal CLK IR, which at the same time entails a minimization of an initial phase error in the phase-locked PLL circuit.

The phase detector is a phase/frequency detector with a HOLD input supplied thereto. This restores the locking to recep¬ tion or transmission of the phase detector PD such that reception can start with a minimal phase error. The output of the phase detector delivers the signals UP and DOWN or none of these signals, where the signal UP indicates that the frequency of the sampling signal CLK_SMP is to be increased, whereas the signal DOWN indicates that the frequency of the sampling signal CLK_SMP is to be reduced. These two signals UP, DOWN control a current pump CP, which charges a capacitor C2 via a resistor R2 during the period when the signal UP or DOWN is present. The voltage across the resistor and the capacitor constitutes control voltage for the voltage-controlled oscillator VCO.

The ratio of the UP and DOWN signals to the frequency characteristic of the sampling signal CLK_SMP is illustrated in Figure 6. The interval 7 shows the frequency jump, whereas the curve 8 denotes the degree of frequency change of the sampling signal CLK_SMP at an active UP or DOWN signal.

The purpose of the PLL control unit PLL-C is that this should determine when a message packet starts and ends and, with information about this, generate control signals which are required in the PLL circuit and in the tuning control TC.

To establish when a message packet is initiated, it is sufficient to determine when the first pulse in the external . clock pulse signal EX_CLK occurs. When, on the other hand, the end of a message packet is to be detected, a signal TIME

OUT is introduced as an aid. The frequency of the internal clock pulse signal CLK_IR with its flank pulses S_IR is approximately four times higher than the flank pulses

EX_EDGES of the external clock pulse signal EX_CLK. If a counter is reset by the flank pulses EX_EDGES and is clocked by the flank pulses S_IR, the counter reaches the value 4, or 5 at the most if the internal clock is poorly adjusted, before the counter is again reset by a new EX_EDGES flank pulse. On the other hand, if the counter reaches the number 6, or possibly the number 7 if the clock is poorly adjusted, then it is known for certain that the message packet in question is terminated. In this case, in the circuit logic in the PLL control unit PLL-C, a pulse is generated in a signal designated TIME_OUT with a pulse length as in the internal clock pulse signal CLK_IR. Figure 7 illustrates an example of the formation of the signal TIME_OUT.

Two other signals INTERN and HOLD, mentioned above, are formed in the PLL control unit PLL-C. The signal INTERN, which controls, inter alia, the multiplexor MUX in the PLL circuit is given a low level while a message packet is present. This low status level of the signal INTERN is initiated when the first new flank pulse EX_EDGES in a message packet occurs and returns when the signal TIME_0UT marks that a message packet is terminated. The latter signal HOLD is high only during one sampling signal CLK_SMP cycle, namely, when the first new flank pulse EX_EDGES in a message packet occurs, and when the signal TIME_0UT marks that a message packet is terminated. The appearance and relation in time between these signals are illustrated in Figure 8. The signals INTERN and HOLD are generated in a status device in the PLL control unit PLL-C.

The task of the tuning control TC, shown in a block diagram in Figure 9, is to compare the internal frequency with the external clock pulse frequency obtained via the databus 2 during the period when a message packet is present. When the message packet is terminated, the tuning control TC emits a control signal to the internal reference clock IRC which increases or reduces the frequency of the internal reference clock IRC in steps of 0.10%.

The sampling signal CLK_SMP from the PLL circuit, which is locked to the signal frequency of the external bus while a message packet is present, is compared with the frequency of the internal clock pulse signal CLK_IR.

Since the frequency of the sampling signal CLK_SMP is 16 times higher than the frequency of the external clock pulse signal EX__CLK, it must be divided by 4 to be adapted in frequency to the frequency of the flank pulses S_IR of the internal clock. This is achieved by a mode 4-counter M4, which generates a 6 MHz signal CY. The counter M4 is preceded by a reset unit RS.

When the first flank pulses S_IR arrive after a message packet has occurred, which is known through the signal INTERN, the reset unit RS generates a signal REL to the reset inputs of the counter M4 and the UP/DOWN counter U/D which starts the counter M4 and the UP/DOWN counter U/D. This signal REL is given a low level status when a message packet is terminated and resets the counters until the next message packet has arrived.

The UP/DOWN counter U/D counts up one step for each CY signal pulse and counts down one step for each fiank pulse S_IR. To avoid problems which may arise if a count-up and a count-down pulse occur simultaneously, the UP/DOWN counter U/D is preceded by a blocking circuit BL, which jcancels the pulses occurring simultaneously in the signals CY and S_IR.

Depending on whether the frequency of the internal clock pulse signal CLK_IR is too high or too low, the JP/DOWN counter U/D steps upwards or downwards. The most significant bit MSB will then show, at the end of the message packet, if^" the internal frequency is to be increased or reduced.

If the difference in frequency between the signals S_IR and CY is greater than 1.6%, the UP/DOWN counter U/D would exceed the number OII₂ = +3 (or be lower than -IOO₂ = -4) , which would mean that the most significant bit carries incorrect information. To prevent this from happening, a stop circuit SL has been introduced which generates a signal to the blocking circuit BL, which stop circuit then does not allow counting up or counting down in the UP/DOWN counter U/D for the remainder of the message packet if the counter has reached the number +3 or -3.

As already described, the TIME_OUT pulse forms seven S_IR pulses after the last flank pulse EX_EDGES in a message packet. Because of this, the PLL circuit, which normally receives a new flank pulse EX_EDGES for every fourth S_IR pulse, will reduce its frequency, the sampling frequency, which may entail an incorrect result in the frequency comparison according to the above. For this reason, a delay unit DEL is introduced in the tuning control TC. This delay unit delays the information about the most significant bit by four S_IR pulses.

Finally, when the TIME_OUT pulse arrives, a pulse generator PULSER creates either an F_UP pulse to increase or an F_DOWN pulse to reduce the frequency of the internal clock pulse signal CLK_IR, which is generated in the internal reference clock IRC. These pulses are synchronized by the sampling signal CLK_SMP, since it is possible that the output of the delay unit DEL changes status at the beginning of the TIME_OUT pulse.

The frequency of the internal reference clock IRC shall be digitally variable within ±10% from the centre frequency in steps of 0.10%. A block diagram for the internal reference clock IRC is shown in Figure 10. An 8-bit UP/DOWN counter U/D-IRC counts up by one or counts down by one when pulse F_UP or F_DOWN occurs. A limiting circuit LIM and a blocking unit BL-IRC prevent the counter from being greater than the number 255 or lower than the number 0. This is a precautionary measure taken since the event should never occur if the frequency of the external clock pulse signal EX_CLK multiplied by 4 lies above the frequency interval for the voltage-controlled oscillator VCO-IRC.

The output signal of the UP/DOWN counter U/D-IRC is transformed into a voltage between IV and 3 in a D/A converter. The voltage, in turn, is transformed into the desired frequency by a linear voltage-controlled oscillator VCO-IRC. Figure 11 shows a typical building up of the frequency of the internal clock.

The circuit logic in the functional blocks described above is realized with conventional digital function elements. This means that the entire phase-locked loop according to the invention can be built up in one single circuit, for example miniaturized in an ASIC circuit.

Claims

1. A method for tuning of an internal clock pulse signal (CLK_IR) in a circuit, a frequency-locked loop (FLL circuit), in an electronic application (slave (3)) connected to a superordinate electronic system (master (1) ) , for example a process computer, from where the FLL circuit receives an external frequency-stable clock pulse signal (EX_CLK) in message packets via a serial databus (2), characterized in that the frequency of the internally generated clock pulse signal (CLK_IR) is compared with respect to frequency with a generated sampling signal (CLK_SMP) which, in turn, is compared with respect to phase and is phase-locked in a phase-locked loop (PLL circuit) in a certain frequency ratio to the external clock pulse signal (EX_CLK) when a message packet arrives, whereupon the frequency of the clock pulse signal (CLK_IR) generated in the circuit is adjusted upwards or downwards until a desired fixed frequency ratio of the internally generated clock pulse signal (CLK_IR) to the sampling signal is attained, whereupon the internal clock pulse signal (CLK_IR) is tuned in a fixed frequency ratio to the external frequency-stable clock pulse signal (EX_CLK) .

2. A method according to claim 1, characterized in that the frequency adjustment of the internal clock pulse signal (CLK_IR) is carried out in discrete steps.

3. A method according to claim 1, characterized in that the FLL circuit throughout only utilizes oscillators with a variable frequency for obtaining frequency reference signals.

4. A method according to claim 1, 2 or 3, characterized in that the FLL circuit comprises a tuning unit (TC) , which after a completed message packet emits a control signal (F_UP/F_DOWN) to an internal reference clock (IRC) for increasing or reducing the frequency of the internally generated clock pulse signal (CLK_IR) in dependence on a frequency comparison carried out in the tuning control (TC) between the frequency of the external clock pulse signal (EX_CLK) and the frequency of the sampling signal (CLK_SMP) .

5. A method according to claim 1, 2 or 3, characterized in that the sampling signal (CLK_SMP) is phase-compared in a phase-locked loop, a PLL circuit, with the internal clock pulse signal (CLK_IR) , when no message packet has arrived via the databus (2), whereby the building-up process of the PLL circuit takes place more rapidly than when a new message packet occurs.

6. A device for carrying out a method for tuning an internal clock pulse signal (CLK_IR) in a circuit, a frequency-locked loop (FLL circuit), in an electronic application (slave (3)) connected to a superordinate electronic system (master (1) ) , for example a process computer, from where the FLL circuit receives an external clock pulse signal (EX_CLK) with message packets, generated in a frequency-stable manner, via a serial databus (2), characterized in that the device, the FLL circuit, comprises

- an internal reference clock (IRC),

- a phase-locked loop (PLL circuit) for synchronization of a sampling signal (CLK_SMP) with the external clock pulse signal (EX_CLK) , and

- a tuning control (TC) which increases or reduces the frequency of the internal reference clock (IRC) in dependence on a frequency comparison between the internal clock pulse signal (CLK_IR) and the sampling signal (CLK_SMP) .

7. A device according to claim 6, characterized in that the FLL circuit can be integrated on/in an IC circuit, for example ASIC circuits.

8. A device according to claim 6, characterized in that the FLL circuit comprises a flank detector (ED) , to which are fed the external clock pulse signal (EX_CLK) and the internal clock pulse signal (CLK_IR) , these two signals being sampled with the sampling signal (CLK_SMP) , whereby the flank pulses (EX_EDGES) and the flank pulses (S_IR) , respectively, are obtained from the flank detector (ED) .

9. A device according to claim 8, characterized in that the PLL circuit of the FLL circuit utilizes the flank pulses (EX_EDGES) from the external clock pulse signal (EX_CLK) as reference when a message packet occurs and, at other times, utilizes the flank pulses (S_IR) of the internal clock pulse signal (CLK_IR) as reference. Switching between these references takes place by means of a multiplexor^' (MUX) , controlled by a PLL control unit (PLL-C) .

10. A device according to claim 9, characterized in that the PLL circuit comprises a phase detector (PD) , which is set to zero when switching from one reference signal to another. The phase detector (PD) emits the signal UP or the signal DOWN in dependence on the outcome of a phase comparison between the flank pulses (S_IR) and the flank pulses (EX_EDGES), which signals (UP/DOWN) influence a voltage-controlled oscillator (VCO) to increase or reduce the frequency of the sampling signal (CLK_SMP) .

11. A device according to any of claim 8, 9 or 10, characterized in that the FLL circuit comprises a PLL control unit (PLL-C) , which determines when a message packet is started and completed, respectively, and delivers information about this by means of control signals (INTERN, HOLD, TIME_OUT) to the PLL circuit and the tuning control (TC) .

12. A device according to claim 11, characterized in that the PLL control unit (PLL-C) generates a signal INTERN, which is active when a message packet has arrived.

13. A device according to claim 11, characterized in that the PLL control unit (PLL-C) generates a signal HOLD, which is active during a CLK_SMP cycle only at the beginning and at the end of a message packet, respectively.

14. A device according to claim 11, characterized in that the PLL control unit (PLL-C) generates a signal (TIME_OUT) which provides information that a message packet is terminated.