SE9200137D0 - PROCEDURE AND DEVICE FOR RECONCILIATION OF INTERNALLY GENERATED CLOCK PULSE SIGNAL - Google Patents

PROCEDURE AND DEVICE FOR RECONCILIATION OF INTERNALLY GENERATED CLOCK PULSE SIGNAL

Info

Publication number
SE9200137D0
SE9200137D0 SE9200137A SE9200137A SE9200137D0 SE 9200137 D0 SE9200137 D0 SE 9200137D0 SE 9200137 A SE9200137 A SE 9200137A SE 9200137 A SE9200137 A SE 9200137A SE 9200137 D0 SE9200137 D0 SE 9200137D0
Authority
SE
Sweden
Prior art keywords
clk
clock pulse
pulse signal
frequency
phase
Prior art date
Application number
SE9200137A
Other languages
Swedish (sv)
Other versions
SE9200137L (en
SE502458C2 (en
Inventor
J-O Bergstroem
Original Assignee
Asea Brown Boveri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri filed Critical Asea Brown Boveri
Priority to SE9200137A priority Critical patent/SE502458C2/en
Publication of SE9200137D0 publication Critical patent/SE9200137D0/en
Priority to AU34134/93A priority patent/AU3413493A/en
Priority to PCT/SE1993/000034 priority patent/WO1993014570A1/en
Publication of SE9200137L publication Critical patent/SE9200137L/en
Publication of SE502458C2 publication Critical patent/SE502458C2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A circuit, which can be integrated on chips, with a so-called phase-locked loop (FLL circuit) for generation and tuning of an internal clock pulse signal (CLK-IR) in an electronic slave unit (3) connected to a superordinate electronic master unit (1) where the circuit (FLL) during communication between the slave unit (3) and the master unit (1) receives external frequency-stable but noisy clock pulses (EX-CLK) in the form of message packets, a second clock pulse signal internally generated in the FLL circuit, a sampling signal (CLK-SMP), being compared with respect to phase with the external clock pulses (EX-CLK) in a phase-locked loop, whereupon, in dependence on the phase position of the sampling signal (CLK-SMP) compared with the external clock pulses (EX-CLK), control pulses are formed which influence the clock pulse generator for the sampling signal (CLK-SMP), such that this is locked in phase in a definite frequency ratio to the external clock pulse signal (EX-CLK). The internal clock pulse signal (CLK-IR) is compared with respect to frequency with the sampling signal (CLK-SMP), whereupon the internal clock pulse generator (IRC) of the FLL circuit changes frequency in discrete small steps in the internal clock pulse signal (CLK-IR) without any disturbing phase shift until the frequency of the internal clock pulse signal (CLK-IR) of the circuit and the frequency of the external clock pulse signal (EX-CLK) are in agreement.
SE9200137A 1992-01-20 1992-01-20 Method and apparatus for tuning internally generated clock pulse signal SE502458C2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE9200137A SE502458C2 (en) 1992-01-20 1992-01-20 Method and apparatus for tuning internally generated clock pulse signal
AU34134/93A AU3413493A (en) 1992-01-20 1993-01-19 Method and device for tuning of an internal generated clock pulse signal
PCT/SE1993/000034 WO1993014570A1 (en) 1992-01-20 1993-01-19 Method and device for tuning of an internal generated clock pulse signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9200137A SE502458C2 (en) 1992-01-20 1992-01-20 Method and apparatus for tuning internally generated clock pulse signal

Publications (3)

Publication Number Publication Date
SE9200137D0 true SE9200137D0 (en) 1992-01-20
SE9200137L SE9200137L (en) 1993-07-21
SE502458C2 SE502458C2 (en) 1995-10-23

Family

ID=20385051

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9200137A SE502458C2 (en) 1992-01-20 1992-01-20 Method and apparatus for tuning internally generated clock pulse signal

Country Status (3)

Country Link
AU (1) AU3413493A (en)
SE (1) SE502458C2 (en)
WO (1) WO1993014570A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726713B1 (en) * 1994-11-09 1997-01-24 Sgs Thomson Microelectronics CIRCUIT FOR DATA TRANSMISSION IN ASYNCHRONOUS MODE WITH FREQUENCY FREQUENCY OF RECEIVER SET ON THE TRANSMISSION FREQUENCY
NO307728B1 (en) * 1997-06-03 2000-05-15 Abb Research Ltd Steps to obtain time synchronization on a network
WO1999053639A1 (en) * 1998-04-09 1999-10-21 Nokia Networks Oy Node control unit of an access node in a telecommunications network

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131861A (en) * 1977-12-30 1978-12-26 International Business Machines Corporation Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
US4835481A (en) * 1986-09-30 1989-05-30 Siemens Aktiengesellschaft Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency

Also Published As

Publication number Publication date
SE9200137L (en) 1993-07-21
SE502458C2 (en) 1995-10-23
AU3413493A (en) 1993-08-03
WO1993014570A1 (en) 1993-07-22

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