WO1989004533A1 - Flat display unit and a method of driving the same - Google Patents

Flat display unit and a method of driving the same Download PDF

Info

Publication number
WO1989004533A1
WO1989004533A1 PCT/JP1988/001126 JP8801126W WO8904533A1 WO 1989004533 A1 WO1989004533 A1 WO 1989004533A1 JP 8801126 W JP8801126 W JP 8801126W WO 8904533 A1 WO8904533 A1 WO 8904533A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
flat panel
panel display
drive
signal
Prior art date
Application number
PCT/JP1988/001126
Other languages
French (fr)
Japanese (ja)
Inventor
Yoichi Imamura
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to EP88909834A priority Critical patent/EP0344323B1/en
Priority to KR1019890701273A priority patent/KR930005371B1/en
Priority to DE3853945T priority patent/DE3853945T2/en
Publication of WO1989004533A1 publication Critical patent/WO1989004533A1/en
Priority to US08/026,234 priority patent/US6091392A/en
Priority to US09/516,264 priority patent/US6232949B1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on

Definitions

  • the present invention relates to a flat panel display device having a plurality of display surface elements provided at intersections of scanning electrodes and signal electrodes arranged in a matrix and a driving method thereof, and is particularly effective for improving image quality of a liquid crystal display device. K to drive method.
  • a conventional flat panel display device has a driving surface connected to one end of a transparent electrode as shown in JP-A-53-38935 and JP-A-58-52686, and displays. It was driving the panel.
  • the purpose of this invention is to solve such problems.
  • the purpose is to drive the electrodes of the liquid crystal panel from the rain end to provide a high-quality liquid crystal display device with little unevenness in lightness. Is to do.
  • the scanning electrode and the signal electrode are mated.
  • a scanning electrode of the scanning electrode and the signal electrode is driven by a driving surface from a rain end of the electrode. It is configured so that:
  • the resistance of the transparent electrode becomes equivalently 1 ⁇ 2
  • the output resistance of the drive circuit becomes equivalent, and the influence of the voltage fluctuation of a certain pixel is measured from the electrode rain end. Since the load is shared, the effects of voltage fluctuations are less likely to propagate to the entire element connected to the electrode, and the image is greatly improved over single-sided drive.
  • FIG. 1 is a diagram showing one embodiment of a driving method according to the present invention.
  • FIG. 2 is a diagram illustrating shading unevenness in conventional LCD.
  • FIG. 3 is an equivalent area map of LCD.
  • FIG. 4 is a diagram showing an example of a liquid crystal drive circuit having a short current prevention surface.
  • FIG. 1 is a view showing a liquid crystal driving method according to an embodiment of the present invention, in which a liquid crystal panel 1 in which picture elements are formed in a matrix at opposing portions of signal electrodes and scanning electrodes.
  • the signal side drive circuit converts the display data XD into serial / parallel by the shift register 2 operated by the shift clock XSCL, synchronizes it to the signal LP by the latch 3, and outputs the signal through the level shifter 4. This is converted by the driver 5 into a liquid crystal drive waveform consisting of four values of voltage by the voltage averaging method.
  • the scanning drive circuit is
  • the output of the shift register 6 that operates by the shift clock in response to the 15- Ys YD is converted to a liquid crystal driving waveform composed of four values by the driver 8 via the level shifter 7.
  • the plane becomes unstable and the output voltage of the two driving planes connected via the transparent electrode may be different. Since the voltage is in the range of 20 to 40 V, a current of several 100 ⁇ ⁇ ⁇ to several m ⁇ flows per output, and this large current adversely affects the driving circuit and the liquid crystal panel. Therefore, the driver of the driving surface used in the liquid crystal display device of the present invention is provided with a surface for making the output the same during a predetermined period until the state of the driving surface is fixed when the power is applied by the inhibition signal INH. , When power is applied
  • FIG. 3 shows the equivalent surface area of a dot matrix liquid crystal display device.
  • the figure shows the case where the 5X3 matrix * panel is driven only on the rain side on the scanning electrode.
  • the pixels indicated by ® and ⁇ in the figure indicate the pixels located at the farthest position from the driving surface according to the present method and the conventional method, respectively. According to the conventional method ⁇ is on the left
  • Fig. 5 shows the case where one side is driven.
  • the resistance between the drive surface and points ® and ® at this time is shown below.
  • R s is the output resistance of the drive circuit
  • the use of the driving method of the present invention means that an image quality equivalent to that of the conventional driving method in which the resistance of the transparent electrode 15 is reduced can be obtained. . Conversely, if the image quality is the same as before, it means that a liquid crystal cell twice as large can be realized, and a higher resolution of the liquid crystal display device can be realized.
  • FIG. 4 shows an embodiment of eleven scanning-side drive paths.
  • the circuit enclosed by a broken line frame 42 indicates one bit of the drive circuit, and is used by connecting a plurality of cascades.
  • the portion indicated by a broken-line frame 43 indicates a surface that becomes a high-voltage portion with respect to the logic portion.
  • a D-type flip-flop 21 constitutes a shift register operated by a shift clock SCK.
  • the signal LP shown in FIG. 1 is input to the shift clock SCK. Accordingly, the output D n ⁇ I is input in accordance with the shift Tok lock S CK to D n of the next stage flip 25 Ppufu opening-up.
  • the start pulse YD is input to Q n —, of the flip-flop.
  • the output Q n of the full re Tsu Pufu drop 2 1 forces the driver output ⁇ UT by signal INH through N 0 R gate 2 i for the same potential, the level shifter 2 3 a of the input I, Ding Tell
  • the outputs ⁇ and ⁇ of the level shifter are connected to the gates of the complementary gates 26 and 27 of the complementary 5-transistor that outputs the selected potential, and are used to convert the non-selected potential to AC. Connected to one input of NOR gate 32 and NAND gate 31.
  • a signal obtained by combining the frame signal FR and the signal INH by the NOR gate 36 is input via the level shifter 23b and the inverter 38.
  • the outputs of gates 3 1 and 3 2 are respectively applied to the gates of transistor P 28 of the P channel transistor and transistor 29 of the N channel transistor. connected, unselected level V,, the output control of the V 4 performed.
  • the selection potentials (V., V 5 ) are the transfer 1 s gate 40, N channel of the P channel transistor which uses the FR signal given from the level shifter 23 b as the gate input. After being multiplexed by the transistor's transistor 41, it is supplied to the source electrodes of the complementary transistors 26 and 27.
  • Transistors 26 and 27 use the outputs ⁇ and ⁇ "of level shifter 23a as gate inputs, conduct only when the output of C of shift register 21 is, and output the selected level. 0 When the signal ⁇ ⁇ is input with ⁇ “ ⁇ ”, the input I of the level shifter 23 b becomes “H”, and the source potential of the transfer gates 26 and 27 becomes forcing the V 5 potential. on the other hand, if before the signal I NH as mentioned "H", the gate that is conducting of the tiger Nsufage DOO 2 6, 2 7, 2 8, 2 9, 2 6 and 27, the driver output OUT is fixed to the potential of V 5. Therefore, in Fig.
  • the driving method of the present invention is to use a TAB structure in which the driving semiconductor integrated surface is bonded to a flexible tape or a C ⁇ G (Chip On Glass) structure, so that the driving surface is formed on both sides of the liquid crystal cell. Connected to and easy to store.
  • the COG structure is the most advantageous in that the wiring between the driving surface and the electrodes and the connection resistance can be minimized.
  • the driving method of the present invention has an effect of preventing the phenomenon shown in FIG. 2 even when applied to only the scanning electrodes. That is, since the drive voltage amplitude of the scan electrode is 5 to 10 times larger than the amplitude of the signal electrode, the charge / discharge delay time to the surface element easily affects the surface quality. This method is particularly effective for a single liquid crystal cell having a narrow electrode pitch.
  • the signal electrode lowers the electrode resistance by increasing the thickness of the transparent electrode film and attaching a low-resistance dissimilar metal to the transparent electrode, and the scanning electrode becomes equivalently lower in resistance using the method of the present invention. It is possible to develop applications for economical commercialization.
  • the simple matrix type LCD among the dredged crystal display devices has been described above.However, since the method of the present invention is to improve the image quality deterioration caused by the resistance of the pixel electrode, only the ITO and the Nesa film are used. Active type LCD with TFT (Thin Film Transistor) and MIM (Metal-Metal-Metal) used for wiring materials, PDP (Plasma Display Panel) and ELD (Electric Display Panel), which require large current flow. It can be widely applied to flat displays up to the trolley display.
  • the transparent electrode resistance becomes equivalent. It has the following effects.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Control Of El Displays (AREA)

Abstract

A flat display unit having a plurality of display pixels provided at intersecting points of scanning electrodes and signal electrodes that are arranged in the form of a matrix. Among the scanning electrodes and the signal electrodes, at least the scanning electrodes are driven by separate drive circuits from the terminals on both sides of the electrodes. The invention further provides a method of driving the flat display unit.

Description

明 細 害 - 平板表示装置及びその駆動方法 技 術 分 野  Brightness-Flat panel display and method of driving the same
本発明はマ ト リクス状に配置された走査電極と信号電極の交点に設けられ た複数の表示面素を有する平板表示装置及びその駆動方法に係わり、 特に液 晶表示装置の画質改善に有効な駆動方法に Kする。  The present invention relates to a flat panel display device having a plurality of display surface elements provided at intersections of scanning electrodes and signal electrodes arranged in a matrix and a driving method thereof, and is particularly effective for improving image quality of a liquid crystal display device. K to drive method.
1 0 背 景 技 術 1 0 Background technology
従来の平板表示装置は、 特開昭 5 3 - 3 8 9 3 5号、 特開昭 5 8 - 5 2 6 8 6号に示される様に駆動面路を透明電極の片端に接続し、 表示パネルを駆 動するものであった。  A conventional flat panel display device has a driving surface connected to one end of a transparent electrode as shown in JP-A-53-38935 and JP-A-58-52686, and displays. It was driving the panel.
しかし、 前述の従来技術では、 ドッ トマ ト リ クス液晶パネルが大容量化す , 5 るにつれて、 透明電極の幅が狭くなる一方、 县さは長くなる方向にあるので、 駆動面路出力端から電極先端までの電極抵抗 Rとキャパシタ容量 Cが大き く なり、 画質を低下させる大きな要因となっていた。 すなわち 6 4 0 x 4 0 0 ドッ ト、 1ノ 2 0 0デューティの液晶パネルでは、 およそ R = 1 0〜 6 0 K Ω 1 C = 8 0 0〜 2 0 0 0 p Fである。 このため駆動波形が変化してから安 However, in the above-described conventional technology, as the capacity of the dot matrix liquid crystal panel increases, the width of the transparent electrode becomes narrower and the length thereof becomes longer as the dot matrix liquid crystal panel becomes larger. The electrode resistance R and the capacitor capacitance C up to the tip increased, which was a major factor in lowering image quality. That is, in a liquid crystal panel having a dot of 640 × 400 and a duty of 200 × 100, R is approximately 10 to 60 KΩ 1 C = 800 to 200 pF. For this reason, it is safe after the drive waveform changes.
Z 0 定するまでの各画素の遅延時間は、 数 sから数 1 0 sに達し、 液晶の一 走査時間 6 0〜 8 0 sに対して無視できない水準にあった。 これが各画素 に加わる実効駆動電圧を電圧平均化法で与えられる理想値からずらし、 第 2 図に示すような非点灯領域の濃淡ムラを発生させ、 表示内容によつては点灯 画素と非点灯画素の識別が困難になるほど画質を低下させていた。 第 2図でThe delay time of each pixel until Z 0 was determined reached several s to several tens of s, which was not negligible for a liquid crystal scanning time of 60 to 80 s. This shifts the effective drive voltage applied to each pixel from the ideal value given by the voltage averaging method, causing shading in the non-lighting area as shown in Fig. 2, and depending on the display content, the lighting pixel and the non-lighting pixel The image quality deteriorates as it becomes difficult to identify the image. In Figure 2
25 は、 横線を 1 ライ ンおきに交互に点灯したとき、 非点灯領域 1 1 , 1 2の濃 淡に差が出る一例を示したものである。 1 1の上方に示したように交互点灯 を模に县くすると 1 1のように淡い表示となり、 1 2の上方に示したように 交互点灯領域を横に短くすると 1 2のように獲い表示となる例である。 この ような濃淡の差は主に走査電極の抵抗が高い場合に顕在化しやすい現象であ る。 これに対し、 透明電極抵抗を下げるために電極薄膜の厚みを增すと配向 不良や生産上のスループッ ト の低下によるパネルコ ス ト高を誘発し、 これに も限界があつた。 2 5 indicates that when the horizontal lines are alternately lit every other line, the dark areas 1 1 and 1 2 This is an example of a slight difference. 1 When the alternate lighting is imitated as shown above 1, the display becomes pale as shown in 1 1, and when the alternate lighting area is shortened horizontally as shown above 1 2, it is captured as 1 2 This is an example of display. Such a difference in shading is a phenomenon that is likely to become apparent mainly when the resistance of the scanning electrode is high. On the other hand, increasing the thickness of the electrode thin film to reduce the resistance of the transparent electrode induces panel costs due to poor alignment and reduced production throughput, which also had limitations.
そこで本癸明はこのような問題点を解決するもので、 その目的とするとこ ろは、 液晶パネルの電極を雨端から駆動することにより、 蘧淡ムラの少ない 高画質な液晶表示装置を提供することにある。  The purpose of this invention is to solve such problems. The purpose is to drive the electrodes of the liquid crystal panel from the rain end to provide a high-quality liquid crystal display device with little unevenness in lightness. Is to do.
¾ 明 の 開 示 ¾ Disclosure of light
本発明の平板表示装 S及びその駆動方法は、 走査電極と信号電極とがマ ト In the flat panel display device S of the present invention and its driving method, the scanning electrode and the signal electrode are mated.
Vクス状に配置され、 それらの電極の交点に表示面素が設けられた表示装置 において、 前記走查電極と信号電極のうち少なく とも走査電極は、 電極の雨 端から駆動面路で駆動されるように構成する。 In a display device arranged in a V-shape and provided with a display surface element at an intersection of these electrodes, at least a scanning electrode of the scanning electrode and the signal electrode is driven by a driving surface from a rain end of the electrode. It is configured so that:
本発明の上記の方法によれば、 透明電極の抵抗が等価的に ½になること、 駆動回路の出力抵抗が等価的に になること、 またある画素の電圧変動の影 響を電極雨端から分担するので、 その電極につながる全面素に電圧変動の影 響が伝播しにく くなることにより、 片側駆動より大幅に画 ¾が向上する。 図面の簡単な説明  According to the above method of the present invention, the resistance of the transparent electrode becomes equivalently ½, the output resistance of the drive circuit becomes equivalent, and the influence of the voltage fluctuation of a certain pixel is measured from the electrode rain end. Since the load is shared, the effects of voltage fluctuations are less likely to propagate to the entire element connected to the electrode, and the image is greatly improved over single-sided drive. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本発明の駆動方法の一実施例を示す図。  FIG. 1 is a diagram showing one embodiment of a driving method according to the present invention.
第 2図は、 従来の L C Dにおける濃淡ムラを説明する図。  FIG. 2 is a diagram illustrating shading unevenness in conventional LCD.
第 3図は、 L C Dの等価面路図。 第 4図は、 ショー ト電流防止面路を有する液晶駆動回路の一例を示す図。Fig. 3 is an equivalent area map of LCD. FIG. 4 is a diagram showing an example of a liquid crystal drive circuit having a short current prevention surface.
2 1 Dタイ プフ リ ップフコ ップ 2 1 D type flip flip
2 3 a , 2 3 b レベルシフタ  2 3 a, 2 3 b level shifter
2 6 , 2 7 , 2 8 , 2 9 , 4 0 , 4 1… ト ラ ンスフ ァゲー ト 発明を実施するための最良の形態  26, 27, 28, 29, 40, 41 ... Transformation Best mode for carrying out the invention
第 1図は、 本発明の一実施例における液晶駆動方法を示す図であって、 信 号電極と走査電極の対向部分でマ ト リクス状に絵素が形成されるようにした 液晶パネル 1 の透明電極 （ I TOの薄膜等） の両端から対になった信号側駆 FIG. 1 is a view showing a liquid crystal driving method according to an embodiment of the present invention, in which a liquid crystal panel 1 in which picture elements are formed in a matrix at opposing portions of signal electrodes and scanning electrodes. A pair of signal-side drives from both ends of a transparent electrode (ITO thin film, etc.)
, 0 動面路と走査側駆動面路により同一波形で駆動するものである。 信号側駆動 回路は、 表示データ XDをシフ トク ロ ッ ク X S C Lにより動作するシフ ト レ ジスタ 2により直並列変換し、 ラ ッチ 3により信号 L Pに同期化させ、 レべ ' ルシフタ 4を介して ドライバ 5により電圧平均化法による 4値の電圧からな る液晶駆動波形に変換するものである。 一方走査側駆動回路は、 スター トパ, 0 are driven with the same waveform by the moving surface path and the scanning-side driving surface path. The signal side drive circuit converts the display data XD into serial / parallel by the shift register 2 operated by the shift clock XSCL, synchronizes it to the signal LP by the latch 3, and outputs the signal through the level shifter 4. This is converted by the driver 5 into a liquid crystal drive waveform consisting of four values of voltage by the voltage averaging method. On the other hand, the scanning drive circuit is
15 ルス YDを受けてシフ トク ロ ッ クにより動作するシス ト レジスタ 6の出力を レベルシフタ 7を介して、 ドライバ 8により 4値の電圧からなる液晶駆動波 形に変換する構成である。 In this configuration, the output of the shift register 6 that operates by the shift clock in response to the 15- Ys YD is converted to a liquid crystal driving waveform composed of four values by the driver 8 via the level shifter 7.
この液晶表示装置に電源を印加したとき、 面路が不安定状態となつて透明 電極を介して接続された 2つの駆動面路の出力電圧が異なる場合が発生する zo が、 このときの液晶駆動電圧は 2 0〜4 0 Vあるので、 1出力当り数 1 0 0 β Α〜数 m Αの電流が流れるこ とになり、 この大電流が駆動回路や液晶パネ ルに悪影響を与える。 そこで本発明の液晶表示装置に使用される駆動面路の ドライバには、 禁止信号 I N Hにより電源印加時に駆動面路の状態が同一に 定まるまでの所定期間に、 出力を同一にする面路を備え、 電源印加時の ドラ When power is applied to this liquid crystal display device, the plane becomes unstable and the output voltage of the two driving planes connected via the transparent electrode may be different. Since the voltage is in the range of 20 to 40 V, a current of several 100 β 当 り to several m 出力 flows per output, and this large current adversely affects the driving circuit and the liquid crystal panel. Therefore, the driver of the driving surface used in the liquid crystal display device of the present invention is provided with a surface for making the output the same during a predetermined period until the state of the driving surface is fixed when the power is applied by the inhibition signal INH. , When power is applied
Z5 ィバ出力のショー トを防止する。 第 3図は、 ドッ トマ ト リ クス液晶表示装置の等価面路を示したものである。 図では、 5 X 3マ ト リ クス * バネルを走査電極のみ雨側駆動した場合を示し ている。 図中 ®と ©の画素は、 本癸明と従来方法による駆動面路から最も遠 い位置.にあるものをそれぞれ示したものである。 従来方法による ©は左側かPrevents Z5 output shorting. FIG. 3 shows the equivalent surface area of a dot matrix liquid crystal display device. The figure shows the case where the 5X3 matrix * panel is driven only on the rain side on the scanning electrode. The pixels indicated by ® and 中 in the figure indicate the pixels located at the farthest position from the driving surface according to the present method and the conventional method, respectively. According to the conventional method © is on the left
5 ら片側駆動した場合を示す。 以下にこのときの駆動面路と ®， ®点間の抵抗 値を示すと、 . Fig. 5 shows the case where one side is driven. The resistance between the drive surface and points ® and ® at this time is shown below.
@： ( 3 r c + R c ) ½ Ω  @: (3 r c + R c) ½ Ω
®： 5 r c + Rc Ω ®: 5 rc + R c Ω
ここで r c , r s は、 画素間の電極抵抗、 Where r c and r s are the electrode resistance between pixels,
t o Rc , Rs は、 駆動回路の出力抵抗 to Rc, R s is the output resistance of the drive circuit
である。 Rc は 1 ΚΩ前後であって、 面素数が增えて r c の数が数百以上に なった場合はほぼ無視できる数値である。 従って、 画素数が増えるほど ® : ©の抵抗比は 1 ： 4に近づく。 一方、 電極に付いているキャパシタ Cは変わ らないので、 本発明の駆動方法を使えば、 従来の駆動方法において透明電極 15 抵抗を にしたのと等価な画質が得られることを意味している。 逆に従来と 同一画質ならば、 2倍の大きさの液晶セルを実現することができることを意 味し、 液晶表示装置の高解像度化を実現できる。 It is. R c is around 1ΚΩ, and it is almost negligible when the number of surface prims increases and the number of r c exceeds several hundreds. Therefore, as the number of pixels increases, the resistance ratio of ®: © approaches 1: 4. On the other hand, since the capacitor C attached to the electrode does not change, the use of the driving method of the present invention means that an image quality equivalent to that of the conventional driving method in which the resistance of the transparent electrode 15 is reduced can be obtained. . Conversely, if the image quality is the same as before, it means that a liquid crystal cell twice as large can be realized, and a higher resolution of the liquid crystal display device can be realized.
第 4図は、 走査側駆動駆動 11路のー実施例を示したものである。 破線枠 4 2で囲まれた回路は、 駆動回路 1ビッ ト分を示すもので、 これを複数縦続接 zo 続して使用される。 また破線枠 4 3で示される部分は、 ロジッ ク部に対して 高電圧部になる面路を示したものである。 図において Dタイプ ' フリ ップフ コ ップ 2 1は、 シフ トク ロ ッ ク S C Kにより動作するシフ ト レジスタを構成 するものである。 シフ トクロ ック S C Kには、 第 1図に示される信号 L Pが 入力される。 従って出力 Dn÷I はシフ トク ロ ック S CKに応じて次段のフリ 25 ップフ口 ップの Dn に入力される。 またシフ ト レジスタ初段を構成するフ リ ッ プフ ロ ッ プの Qn— , には、 スタ ー トパルス Y Dが入力される。 フ リ ッ プフ ロップ 2 1 の出力 Qn は、 信号 I N Hにより強制的に ドライバ出力◦ U Tを 同電位にするための N 0 Rゲー ト 2 iを介して、 レベルシフタ 2 3 aの入力 I , 丁に伝える。 レベルシフタ の出力〇， は、 選択電位を出力する相補型 5 ト ラ ンジスタの ト ラ ンスフ ァゲー ト 2 6 , 2 7のゲー ト に接続される と と も に、 非選択電位を交流化させるための NORゲ一ト 3 2、 NANDゲー ト 3 1の一方の入力に接続される。 ゲー ト 3 1 , 3 2の他方の入力は、 フレーム 信号 F Rと信号 I NHを NORゲー ト 3 6で合成した信号が、 レベルシフタ 2 3 b、 イ ンバータ 3 8を介して入力される。 ゲー ト 3 1 , 3 2の出力は、 ,ο それぞれ Pチャ ンネル ト ラ ンジスタ の ト ラ ンスフ ァゲー ト 2 8 , Nチャ ンネ ル ト ラ ンジスタの ト ラ ンスフ ァゲ一ト 2 9のゲー 卜 に接続され、 非選択レべ ル V, , V4 の出力制御を行う。 ' 一方選択電位 （V。 ， V5 ) は、 レベルシフタ 2 3 bの岀カ〇から与えら れる F R信号をゲー ト入力とする Pチヤ ンネルトラ ンジスタの トランスファ 1 s ゲー ト 4 0 , Nチャ ンネル ト ラ ンジスタの ト ラ ンスフ ァゲー ト 4 1 によりマ ルチプレク スされた後、 相補型ト ラ ンスフ ァゲ一ト 2 6 , 2 7のソース電極 に与えられる。 ト ラ ンスフ ァゲー ト 2 6, 2 7は、 レベルシフタ 2 3 aの出 力〇， ϋ"をゲー ト入力とし、 シフ ト レジスタ 2 1の C の出力が のと きだけ導通し、 選択レベルを出力 0 UTに伝える。 ところで信号 Ι ΝΗに ζο " Η " が入力されるとレベルシフタ 2 3 bの入力 I は " H " になり、 ト ラ ン スファゲー ト 2 6 , 2 7のソ一ス電位は、 強制的に V5 電位となる。 一方前 述したように信号 I NHが " H" のとき、 トラ ンスファゲー ト 2 6 , 2 7 , 2 8 , 2 9のうち導通しているゲー トは、 2 6 , 2 7であるので、 ドライバ 出力 O UTは、 V5 電位に固定される。 したがって第 1図において表示装置 5 特に駆動面路がパヮーオ ンのときに I N H信号を " H " にしさえすれば、 両 側の ドライバ 8の出力が同電位となるので、 透明電極を介してドライバ出力 が互いにショー トし、 ドライバ藺に大電流が流れることを防止できる。 ちな みに同電位レベルは、 Vs の他に V。 ， V！ , V4 やハイイ ンピーダンスに して良いことはいうまでもない。 また信号側駆動面路のショ一ト防止面路も 走査側駆動面路と同様の面路で実現することができる。 FIG. 4 shows an embodiment of eleven scanning-side drive paths. The circuit enclosed by a broken line frame 42 indicates one bit of the drive circuit, and is used by connecting a plurality of cascades. The portion indicated by a broken-line frame 43 indicates a surface that becomes a high-voltage portion with respect to the logic portion. In the figure, a D-type flip-flop 21 constitutes a shift register operated by a shift clock SCK. The signal LP shown in FIG. 1 is input to the shift clock SCK. Accordingly, the output D n ÷ I is input in accordance with the shift Tok lock S CK to D n of the next stage flip 25 Ppufu opening-up. In addition, the fly that constitutes the first stage of the shift register The start pulse YD is input to Q n —, of the flip-flop. The output Q n of the full re Tsu Pufu drop 2 1 forces the driver output ◦ UT by signal INH through N 0 R gate 2 i for the same potential, the level shifter 2 3 a of the input I, Ding Tell The outputs 〇 and の of the level shifter are connected to the gates of the complementary gates 26 and 27 of the complementary 5-transistor that outputs the selected potential, and are used to convert the non-selected potential to AC. Connected to one input of NOR gate 32 and NAND gate 31. To the other inputs of the gates 31 and 32, a signal obtained by combining the frame signal FR and the signal INH by the NOR gate 36 is input via the level shifter 23b and the inverter 38. The outputs of gates 3 1 and 3 2 are respectively applied to the gates of transistor P 28 of the P channel transistor and transistor 29 of the N channel transistor. connected, unselected level V,, the output control of the V 4 performed. 'On the other hand, the selection potentials (V., V 5 ) are the transfer 1 s gate 40, N channel of the P channel transistor which uses the FR signal given from the level shifter 23 b as the gate input. After being multiplexed by the transistor's transistor 41, it is supplied to the source electrodes of the complementary transistors 26 and 27. Transistors 26 and 27 use the outputs 〇 and ϋ "of level shifter 23a as gate inputs, conduct only when the output of C of shift register 21 is, and output the selected level. 0 When the signal に が is input with ζο “Η”, the input I of the level shifter 23 b becomes “H”, and the source potential of the transfer gates 26 and 27 becomes forcing the V 5 potential. on the other hand, if before the signal I NH as mentioned "H", the gate that is conducting of the tiger Nsufage DOO 2 6, 2 7, 2 8, 2 9, 2 6 and 27, the driver output OUT is fixed to the potential of V 5. Therefore, in Fig. 1, if the INH signal is set to "H" when the display device 5, especially the driving surface is power-on, , Both Since the output of the driver 8 on the side is at the same potential, the driver outputs are shorted to each other via the transparent electrode, thereby preventing a large current from flowing through the driver rush. Senna the same potential level in the body is, V. In addition to the V s , V! , It is needless to say that may be the V 4 and high impedance. In addition, the short-circuit prevention surface of the signal-side driving surface can be realized by the same surface as the scanning-side driving surface.
ところで本癸明の駆動方法は、 駆動用半導体集積面路をフレキシブルテー プにボンディ ングした T A B構造や C〇G 〔C h i p O n G l a s s ) 構造を用いれば、 駆動面路を液晶セルの両側に接続し、 収納しやすい。 中で も COG構造は、 駆動面路と電極間の配線、 接続抵抗を最小にできる点で最 も有利である。 さらに本発明の駆動方法は、 走査電極のみに適用しても第 2 図の現象を防止する効果がある。 すなわち走査電極の駆動電圧振幅は、 信号 電極の振幅より 5〜 1 0倍大きいので、 面素への充放電遅延時間が面質に影 ' 響を与えやすいからである。 この方法は電極ピッチが狭くなるカラ一液晶セ ルに対して特に有効である。  By the way, the driving method of the present invention is to use a TAB structure in which the driving semiconductor integrated surface is bonded to a flexible tape or a C〇G (Chip On Glass) structure, so that the driving surface is formed on both sides of the liquid crystal cell. Connected to and easy to store. Among them, the COG structure is the most advantageous in that the wiring between the driving surface and the electrodes and the connection resistance can be minimized. Further, the driving method of the present invention has an effect of preventing the phenomenon shown in FIG. 2 even when applied to only the scanning electrodes. That is, since the drive voltage amplitude of the scan electrode is 5 to 10 times larger than the amplitude of the signal electrode, the charge / discharge delay time to the surface element easily affects the surface quality. This method is particularly effective for a single liquid crystal cell having a narrow electrode pitch.
また信号電極は、 透明電極膜の膜厚を厚くするなり、 低抵抗の異金属を透 明電極に付けるなり して電極抵抗を下げ、 走査電極は本発明の方法を用いて 等価的に低抵抗化を図り、 経済的に画黉商上を図る応用展開が可能である。 以上浚晶表示装置のうち単純マト リクス型の L CDについて説明してきた が、 本発明の方法は、 画素電極の抵抗に起因する画質低下を改善するもので あるから、 I TOやネサ膜以外を配線材料に使う TFT (薄膜ト ラ ンジスタ） や M I M (金属一絶緣物—金属） などの構成を有するアクティブタイプの L C Dや電流を多く流す必要のある P D P (プラ ズマディ スプレイパネル） や E L D (エ レク ト ロ ノレ ミ ネ ッ セ ンヌディ スプレイ ） までのフ ラ ッ トディ スプ レイ に広く応用できるものである。  Also, the signal electrode lowers the electrode resistance by increasing the thickness of the transparent electrode film and attaching a low-resistance dissimilar metal to the transparent electrode, and the scanning electrode becomes equivalently lower in resistance using the method of the present invention. It is possible to develop applications for economical commercialization. The simple matrix type LCD among the dredged crystal display devices has been described above.However, since the method of the present invention is to improve the image quality deterioration caused by the resistance of the pixel electrode, only the ITO and the Nesa film are used. Active type LCD with TFT (Thin Film Transistor) and MIM (Metal-Metal-Metal) used for wiring materials, PDP (Plasma Display Panel) and ELD (Electric Display Panel), which require large current flow. It can be widely applied to flat displays up to the trolley display.
以上述べたように本発明によれば、 透明電極抵抗が等価的に になるのて . 以下のような効果を有する。 As described above, according to the present invention, the transparent electrode resistance becomes equivalent. It has the following effects.
(a)パッ シブタィプの液晶セルでは、 液晶に加わる電圧が電圧平均化法による 理想値に近づく ので、 中小容量で従来から行われてきた 2 フ レーム交流駆 動方法でも濃淡ムラが少なく、 コ ン ト ラス トの高い表示が得られる。  (a) In a passive liquid crystal cell, the voltage applied to the liquid crystal approaches the ideal value obtained by the voltage averaging method. A display with high trust can be obtained.
5 (b)フアイ ンピッチ電極パネルを画質を落とさずに大画面化しやすい。  5 (b) It is easy to enlarge the fine pitch electrode panel without deteriorating the image quality.
(c)駆動 E路の出力抵抗をむやみに小さ くする必要がないので、 従来より多ピ ンでしかも低コス トで駆動回路を集積面路化しやすい。  (c) Driving The output resistance of the E path does not need to be made excessively small, so that the driving circuit can be easily integrated into a circuit at a lower cost and with more pins.
(d)透明電極 （ I T O ) の厚みを薄くでき るので低コ ス 卜 のパネルができ る。  (d) Since the thickness of the transparent electrode (ITO) can be reduced, a low-cost panel can be obtained.
1 0 Ten
1 5 1 5
Z 0 Z 0

Claims

請 求 の 範 囲 The scope of the claims
1 . マ ト リ クス状に配置された走査電極と信号電極の交点に設けられた複数 の表示面素を有する平板表示装置において、 前記走査電極を一方の端子か ら駆動する第 1の駆動面路及び他方の端子から駆動する第 2の駆動面路を 5 備えたことを特徴とする平板表示装置。  1. In a flat panel display device having a plurality of display surface elements provided at intersections of scanning electrodes and signal electrodes arranged in a matrix, a first driving surface for driving the scanning electrodes from one terminal 5. A flat panel display device comprising: a drive path and a second drive path driven from the other terminal.
2 . 前記信号電極を一方の端子から駆動する第 3の駆動面路及び他方の端子 から駆動する第 4の駆動回路を備えたことを特徴とする請求項 1記載の平 ®ι表示装 。  2. The flat display device according to claim 1, further comprising a third drive surface for driving the signal electrode from one terminal and a fourth drive circuit for driving the signal electrode from the other terminal.
3 . 前記第 1及び第 2の駆動回路は同一の制御信号により同一の動作制御が 1 0 なされるこ とを特徴とする請求項 1記載の平板表示装置。 3. The first and second driving circuits are flat panel display of claim 1, wherein that you same operation control is performed 1 0 by the same control signal.
4 . 前記第 1及び第 2の駆動面路は同一の第 1の制御信号により同一の動作 制御がなされ、 前記第 3及び第 4の駆動面路は同一の第 2の制御信号によ り同一の動作制御がなされることを特徴とする請求項 2記載の平板表示装 置。  4. The same operation control is performed on the first and second drive planes by the same first control signal, and the third and fourth drive planes are the same by the same second control signal. 3. The flat panel display device according to claim 2, wherein the operation control is performed.
i s 5 . 前記第 1及び第 2の駆動面路は前記制御信号のうちの電源投入を示す信 号を受けて、 強制的に同一レベルの出力を前記走査電極の雨側の端子に出 力する手段を傭えることを特徵とする請求項 3記載の平板表示装置。 is 5. The first and second drive planes receive the signal indicating that the power is turned on among the control signals, and forcibly output the same level output to the rain-side terminal of the scan electrode. 4. The flat panel display device according to claim 3, wherein a means is used.
6 . 前記第 1及び第 2の駆動面路は前記第 1の制御信号のうちの電源投入を 示す信号を受けて、 強制的に同一の第 1 レベルを前記走査電極の雨側の端 6. The first and second drive planes receive the signal indicating the power-on of the first control signal, and forcibly change the same first level to the rain-side end of the scan electrode.
2 0 子に出力する手段を備え、 前記第 3及び第 4の駆動面路は前記第 2の制御 信号のうちの電源投入を示す信号を受けて、 強制的に同一の第 2 レベルを 前記信号電極の雨側の端子に出力する手段を備えることを特徵とする請求 項 4記載の平板表示装置。 20 means for outputting the second control signal, the third and fourth drive surfaces receive the signal indicating the power-on of the second control signal, and forcibly display the same second level as the signal. 5. The flat panel display according to claim 4, further comprising means for outputting to a terminal on the rain side of the electrode.
7 . 前記第 1の駆動面路は、 前記走査電極の一方側の端子に接続される第 1 2 5 の出力端子と、 前記制御信号を受けて該第 1の出力端子に所定レベルの電 圧を出力する第 1 の ト ラ ンジスタとを備え、 前記第 2 の駆動面路は、 前記 走査電極の他方側の端子に接続される第 2の出力端子と、 前記制御信号を 受けて該第 2 の出力端子に前記所定レベルの電圧を出力する第 2 の ト ラ ン ジスタとを備えることを特徴とする請求項 5記載の平板表示装置。 7. The first drive faces path, one side of the first 2 5 output terminal connected to the terminal, electric predetermined level to the first output terminal receiving said control signal of said scanning electrodes A first transistor for outputting a voltage, wherein the second driving surface path has a second output terminal connected to a terminal on the other side of the scanning electrode; 6. The flat panel display device according to claim 5, further comprising a second transistor that outputs the voltage of the predetermined level to a second output terminal.
8 . 前記第 1の駆動面路は、 前記走査電極の一方側の端子に接続される第 1 の出力端子と、 前記第 1 の制御信号を受けて該第 1 の出力端子に第 1 の所 定レベルの電圧を出力する第 1 の ト ラ ンジスタ とを備え、 前記第 2 の駆動 面路は、 前記走査電極の他方側の端子に接続さる第 2の出力端子と、 前記 第 1 の制御信号を受けて該第 2 の出力端子に前記第 1 の所定レベルの電圧 を出力する第 2の ト ラ ンジスタとを備え、 前記第 3の駆動回路は、 前記信 号電極の一方側の端子に接続される第 3の出力端子と、 前記第 2の制御信 号を受けて該第 3の出力端子に第 2の所定レベルの電圧を出力する第 3の ' ト ラ ンジスタ とを備え、 前記第 4の駆動面路は、 前記信号電極の他方側の 端子に接続される第 4の出力端子と、 前記第 2の制御信号を受けて該第 4 の出力端子に前記第 2 の所定レベルの電圧を出力する第 4 の ト ラ ンジスタ とを備えることを特徴とする請求項 6記載の平板表示装置。  8. The first driving surface includes a first output terminal connected to one terminal of the scan electrode, and a first output terminal receiving the first control signal. A first transistor that outputs a constant level voltage, wherein the second drive surface is a second output terminal connected to the other terminal of the scan electrode, and the first control signal And a second transistor that receives the second output terminal and outputs the voltage of the first predetermined level to the second output terminal, wherein the third drive circuit is connected to a terminal on one side of the signal electrode. A third output terminal receiving the second control signal, and outputting a third predetermined voltage to the third output terminal. The driving surface of the first electrode receives the second control signal and a fourth output terminal connected to the other terminal of the signal electrode. The flat panel display of claim 6, characterized in that it comprises a fourth preparative La Njisuta for outputting said second predetermined level of voltage to the output terminal of the fourth.
9 . 前記平板表示装置は液晶表示装置であることを特徴とする請求項 7又は 8記載の平板表示装置。  9. The flat panel display according to claim 7, wherein the flat panel display is a liquid crystal display.
10. 前記走査電極及び前記信号電極は透明電極よりなることを特徵とする請 求項 9記載の平板表示装置。  10. The flat panel display according to claim 9, wherein the scanning electrode and the signal electrode are formed of transparent electrodes.
11. 前記平板表示装置はドッ トマ ト リ クス型の液晶表示装置であるこ とを特 徵とする請求項 10記載の平板表示装置。  11. The flat panel display according to claim 10, wherein the flat panel display is a dot matrix type liquid crystal display.
12. マ ト リクス状に配置された走査電極と i 号電極の交点に複数の表示画素 を設けてなる平板表示装置の駆動方法において、 前記走査電極を該電極の 雨側端子から別々の走査側駆動面路からの同一レベルの出力で駆動するこ とを特徴とする平板表示装置の駆動方法。 12. In a driving method of a flat panel display device having a plurality of display pixels provided at intersections of a scanning electrode and an i-th electrode arranged in a matrix, the scanning electrode is separated from a rain-side terminal of the electrode by a different scanning side. Drive with the same level output from the drive surface. And a driving method of the flat panel display device.
13. 前記信号電極を該電極の雨側端子から別々の信号側駆動面路により同一 レベルの出力で駆動することを特徵とする請求項 1 2記載の平板表示装置 の駆動方法。  13. The driving method of a flat panel display according to claim 12, wherein the signal electrode is driven from a rain-side terminal of the electrode by a different signal-side driving surface at an output of the same level.
14. 前記平板表示装置の電源投入時から所定期間は、 前記別々の走查側駆動 面路の駆動出力を強制的に同一レベルとし、 前記走査電極の雨側端子を同 一レベルとすることを特徵とする請求項 12記載の平板表示装置の駆動方法。 14. For a predetermined period from when the power of the flat panel display device is turned on, the drive outputs of the separate driving side driving surfaces are forcibly set to the same level, and the rain side terminals of the scanning electrodes are set to the same level. 13. The driving method of a flat panel display device according to claim 12, wherein
15. 前記平板表示装置の電源投入時から所定期間は、 前記別々の走査側駆動 回路の駆動出力を強制的に同一レベルと して前記走査電極の雨側端子を同 一の第 1 レベルとし、 前記別々の信号側駆動面路の駆動出力を強制的に同 一レベルとして前記信号電極の雨側端子を同一の第 レベルとすることを 特徵とする請求項 13記載の平扳表示装置の ¾動方法。 ' 15. For a predetermined period from when the power of the flat panel display device is turned on, the drive outputs of the separate scan-side drive circuits are forcibly set to the same level, and the rain-side terminals of the scan electrodes are set to the same first level; 14. The flat display device according to claim 13, wherein the drive outputs of the different signal-side drive surfaces are forcibly set to the same level, and the rain-side terminals of the signal electrodes are set to the same first level. Method. '
PCT/JP1988/001126 1987-11-10 1988-11-09 Flat display unit and a method of driving the same WO1989004533A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP88909834A EP0344323B1 (en) 1987-11-10 1988-11-09 Flat liquid crystal display unit and method of driving the same
KR1019890701273A KR930005371B1 (en) 1987-11-10 1988-11-09 Flat display unit and a method of driving the same
DE3853945T DE3853945T2 (en) 1987-11-10 1988-11-09 LIQUID CRYSTAL FLAT DISPLAY UNIT AND CONTROL METHOD.
US08/026,234 US6091392A (en) 1987-11-10 1993-03-02 Passive matrix LCD with drive circuits at both ends of the scan electrode applying equal amplitude voltage waveforms simultaneously to each end
US09/516,264 US6232949B1 (en) 1987-11-10 2000-02-29 Passive matrix LCD with drive circuits at both ends of the scan electrode applying equal amplitude voltage waveforms simultaneously to each end

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62/284025 1987-11-10
JP28402587 1987-11-10
JP63/271299 1988-10-27
JP63271299A JP2625976B2 (en) 1987-11-10 1988-10-27 Driving method of flat panel display

Publications (1)

Publication Number Publication Date
WO1989004533A1 true WO1989004533A1 (en) 1989-05-18

Family

ID=26549638

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1988/001126 WO1989004533A1 (en) 1987-11-10 1988-11-09 Flat display unit and a method of driving the same

Country Status (5)

Country Link
EP (1) EP0344323B1 (en)
JP (1) JP2625976B2 (en)
KR (1) KR930005371B1 (en)
DE (1) DE3853945T2 (en)
WO (1) WO1989004533A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241687B (en) * 2000-05-09 2010-06-09 夏普公司 Image display device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0161918B1 (en) * 1995-07-04 1999-03-20 구자홍 Data driver of liquid crystal device
JP2792511B2 (en) * 1996-09-26 1998-09-03 日本電気株式会社 Display driver
TW439000B (en) 1997-04-28 2001-06-07 Matsushita Electric Ind Co Ltd Liquid crystal display device and its driving method
KR100462379B1 (en) * 1997-12-22 2005-06-07 비오이 하이디스 테크놀로지 주식회사 LCD
US6504520B1 (en) 1998-03-19 2003-01-07 Denso Corporation Electroluminescent display device having equalized luminance
JP2002202759A (en) * 2000-12-27 2002-07-19 Fujitsu Ltd Liquid crystal display device
JP4551712B2 (en) * 2004-08-06 2010-09-29 東芝モバイルディスプレイ株式会社 Gate line drive circuit
KR101166819B1 (en) 2005-06-30 2012-07-19 엘지디스플레이 주식회사 A shift register
JP2008020675A (en) 2006-07-13 2008-01-31 Mitsubishi Electric Corp Image display apparatus
JP5637664B2 (en) * 2009-03-24 2014-12-10 株式会社ジャパンディスプレイ Liquid crystal display device and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387250A (en) * 1977-01-11 1978-08-01 Toshiba Corp Matrix type liquid crystal display panel
JPS56162794A (en) * 1980-05-19 1981-12-14 Tokyo Shibaura Electric Co Liquid crystal display unit
JPS57100467A (en) * 1980-12-15 1982-06-22 Suwa Seikosha Kk Ic substrate for active matrix display body
JPS6249398A (en) * 1985-08-29 1987-03-04 キヤノン株式会社 Matrix display panel

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2081018B (en) * 1980-07-31 1985-06-26 Suwa Seikosha Kk Active matrix assembly for display device
JPS61236593A (en) * 1985-04-12 1986-10-21 松下電器産業株式会社 Display apparatus and method
JPS6242193A (en) * 1985-08-20 1987-02-24 富士通株式会社 Driver for flat panel
FR2590392B1 (en) * 1985-09-04 1994-07-01 Canon Kk FERROELECTRIC LIQUID CRYSTAL DEVICE
JPH0628425B2 (en) * 1986-05-20 1994-04-13 三洋電機株式会社 Image display device drive circuit
NL8602328A (en) * 1986-09-15 1988-04-05 Philips Nv DISPLAY DEVICE.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387250A (en) * 1977-01-11 1978-08-01 Toshiba Corp Matrix type liquid crystal display panel
JPS56162794A (en) * 1980-05-19 1981-12-14 Tokyo Shibaura Electric Co Liquid crystal display unit
JPS57100467A (en) * 1980-12-15 1982-06-22 Suwa Seikosha Kk Ic substrate for active matrix display body
JPS6249398A (en) * 1985-08-29 1987-03-04 キヤノン株式会社 Matrix display panel

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0344323A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241687B (en) * 2000-05-09 2010-06-09 夏普公司 Image display device

Also Published As

Publication number Publication date
DE3853945T2 (en) 1995-12-21
KR930005371B1 (en) 1993-06-19
KR890702175A (en) 1989-12-23
DE3853945D1 (en) 1995-07-13
JPH0288A (en) 1990-01-05
EP0344323B1 (en) 1995-06-07
EP0344323A1 (en) 1989-12-06
JP2625976B2 (en) 1997-07-02
EP0344323A4 (en) 1991-01-30

Similar Documents

Publication Publication Date Title
US20210056925A1 (en) Gate driving circuit and display apparatus having the same
US7522145B2 (en) Liquid crystal display apparatus
KR101032945B1 (en) Shift register and display device including shift register
US7259738B2 (en) Liquid crystal display device
US7649971B2 (en) Shift register
US7304632B2 (en) Liquid-crystal display driving circuit and method
EP0875879A1 (en) Liquid crystal display device and method for driving the same with driving of both ends of display electrodes
TW530291B (en) Liquid crystal display and method of driving same
US20020149323A1 (en) Method for driving an electro-optical device, driving circuit for driving an electro-optical device, electro-optical device, and electronic apparatus
JPH09265279A (en) Driving circuit for thin film transistor type liquid crystal display device
JP3525018B2 (en) Active matrix type liquid crystal display
US6091392A (en) Passive matrix LCD with drive circuits at both ends of the scan electrode applying equal amplitude voltage waveforms simultaneously to each end
KR101297241B1 (en) Driving device of Liquid crystal display device
WO1989004533A1 (en) Flat display unit and a method of driving the same
KR100933447B1 (en) Gate driving method and apparatus of liquid crystal display panel
JPS6352121A (en) Electrooptic device
JP3728954B2 (en) Electro-optical device and electronic apparatus
US6788281B2 (en) Circuit panel and flat-panel display device
EP0224388A2 (en) Active matrix liquid crystal display device
JP2000235173A (en) Method for driving electro-optic device, driving circuit for electro-optic device, electro-optic device, and electronic apparatus
EP1239444A1 (en) Liquid crystal display device and method for driving the same
KR100516048B1 (en) Gradation voltage generating circuit and liquid crystal display using the same to reduce cross talk
JPH07140439A (en) Display device
CN110850654B (en) Liquid crystal display panel
KR20010110159A (en) Circuit board and flat panel display device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): DE FR IT

WWE Wipo information: entry into national phase

Ref document number: 1988909834

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1988909834

Country of ref document: EP

WWG Wipo information: grant in national office

Ref document number: 1988909834

Country of ref document: EP