EP0344323A1

EP0344323A1 - Flat liquid crystal display unit and method of driving the same

Info

Publication number: EP0344323A1
Application number: EP88909834A
Authority: EP
Inventors: Yoichi Imamura
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 1987-11-10
Filing date: 1988-11-09
Publication date: 1989-12-06
Anticipated expiration: 2008-11-09
Also published as: DE3853945T2; WO1989004533A1; KR930005371B1; KR890702175A; DE3853945D1; JPH0288A; EP0344323B1; JP2625976B2; EP0344323A4

Abstract

A flat display unit having a plurality of display pixels provided at intersecting points of scanning electrodes and signal electrodes that are arranged in the form of a matrix. Among the scanning electrodes and the signal electrodes, at least the scanning electrodes are driven by separate drive circuits from the terminals on both sides of the electrodes. The invention further provides a method of driving the flat display unit.

Abstract

The present invention is directed to a flat display device and the driving method thereof having a plurality of display picture elements which are defined by liquid crystal cell portions formed between the scanning and the signal electrodes arranged in the form of a matrix wherein at least scanning electrodes of said scanning and signasl electrodes are driven from both terminals of the electrodes by individual driving circuits.

Description

Technical Field

The present invention relates to a flat display device having a plurality of display picture elements which are defined by liquid crystal cell portions formed between the scanning and the signal electrodes arranged in the form of a matrix and the method of driving the flat display device. In particular, the present invention relates to a driving method which is effective for the improvement of the picture quality in the liquid crystal display device.

Prior Arts

In a prior art flat display device, as shown in Japanese Patent Laid-Open No. 38935/78 and Japanese Patent Laid-Open No. 52686/83, a driving circuit is connected to one end of transparent electrodes to drive a display panel.
However, in the above-mentioned prior arts, as the large capacity of the dot matrix type liquid crystal panel is required, the width of the transparent electrodes is got to narrower and the length of the transparent electrodes is got to longer, so that the electrode resistance R and the capacitance C are got to larger from the output terminal of the driving circuit to the end of the electrodes, which results in decreasing the quality of the picture. Namely, when the liquid crystal panel has 640 x 400 dots and is driven by 1/200 duty, R = 10∼60 KΩ, and C = 800 ∼2000 pF. Therefore, the time of the respective picture elements from the change of the driving waveform until the stabilization of the waveform is several or several tens of µs as delay time. This degree of the delay time can not be negleced relative to one scanning time of 60∼80 µs. Due to the delay time, the effective driving voltage applied to respective picture elements are displaced from the predetermined value obtained by the voltage standard method. As a result, unevenness of color contrast is generated, as shown in Fig. 2. The quality of the picture is reduced so much that it may be difficult to distinguish the non-selected and selected regions. Fig. 2 shows one embodiment of the prior art wherein unevenness of color contrast is generated between the non-selected regions 11 and 12 when every other horizontal lines are got to ON alternatively. As shown in the upper side of the portion 11, when every other horizontal lines of ON state are long, the display is too light. Otherwise, as shown in the upper side of the portion 12, when every other horizontal lines of ON are short, the display is too dark. The color contrast is likely to be actualized more when the resistance of the scanning electrodes is high. On the other hand, when the thickness of the transparent electrodes is increased in order to reduce the resistance of the transparent electrodes, the inferior alignment or cost-up of the panel due to the reduction of the throughput in the manufacturing. Therefore, there is a limit in the thickness of the tranparent electrodes.
Thereupon, to eliminate the above problems, the object of the present invention is to drive the electrodes of the liquid crystal panel from both terminals thereof, thereby to provide a liquid crystal display device having a high quality of pictures and having a little unevenness of color contrast.

Disclosre of the Present Invention

The flat display device and the method of driving the same according to the present invention has the construction that scanning and signal electrodes are arranged in the form of a matrix, display picture elements are formed at the crossing points therebetween, and at least scanning electrodes of the scanning and signal electrodes are driven from both terminals of the electrodes by a driving circuit.
According to the above method of the present invention, the resistance of the transparent electrodes become equivalently one quarter, the output resistance of the driving circuit become equivalently one half and the affect of the voltage variation of the picture elements is divided from the both terminals of the electrodes, therefore the whole picture elements connected to the electrodes are not likely to be affected by the varied voltage, so that the quality of picture is improved more than that of the drive from the one terminal of the electrodes.

Brief Description of Drawings

Fig. 1 is a view of one embodiment according to a driving method of the present invention.
Fig. 2 is an explanatory view for explaining the unevenness of color contrast in the prior LCD.
Fig. 3 is an equivalent circuit diagram of LCD.
Fig. 4 is a view of one embodiment of a driving circuit having a short preventing circuit
21 - - - D type flip flop
23a, 23b - - - level shifter
26, 27, 28, 29, 40, 41 - - - transfer gate

Best Modes Of Carrying Out the Invention

Fig. 1 is a view showing a driving method according to one embodiment of the present invention. The picture elements are formed on the crossing portions between the scanning and the signal electrodes arranged in the form of a matrix. The liquid crystal display device is driven by pairs of segment and scanning side driving circuits of the transparent electrode (such as ITO), the amplitudes of the voltages applied to the both ends of the scanning and signal side driving circuits being equal, respectively. According to the signal driving circuits, as a shift clock XSCL is input to a shift registor 2, the display data XD is switched in parallel/in series, is synchronized with a signal LP by a latch 3, and is converted through a level shifter 4 to a liquid crystal driving waveform including the 4 voltage level of the voltage standard method by a driver 5. Otherwise, according to the scanning driving circuits, the shift registor 6 receives the start pulse YD and is operated by a shift clock, and the output of the shift registor 6 is converted through a level shifter 7 to a liquid cyrstal driving waveform including the 4 voltage level by a driver 8.
When the power is applied to the liquid cyrstal display device, the circuits become under unstable condition, and the outoput voltages of the two driving circuits which are connected to each other through a transparent electrode are different from each other. Since the liquid crystal driving voltage is 20 - 40 V in this case, the current of several houndred µA - several mA is applied per one output, so that the current gives a bad affect to the driving circuit and the liquid crystal panel. Thereupon, the driver of the driving circuit used in the liquid crystal display device of the present invention is provided with a circuit for controling the outoput for the predetermined time until the condition of the driving circuit is stabilized by a prohibit signal INH at the time of power-on, in order to prevent the driver output from being shortened at the time of power-on.
Fig. 3 is an equivalent circuit according to a dot matrix liquid crystal display device of the present invention. In Fig. 3, 5 x 3 matrix panel is driven from the both terminals of the scanning electrodes. In Fig. 3, the picture elements Ⓐ and Ⓑ are elements most far from the terminals of the present invention and the prior arts. Ⓑ of the prior art is single-sided driven from left side. The following is resistance values between the driving circuit and the portions A and B:
Ⓐ : (3rC + RC) x 1/2 Ω
Ⓑ : 5rC + RC Ω
Herein, r_Cand r_S are electric resistance between picture elements, and R_C and R_S are output resistances of the driving circuit. R_C is more or less than 1 kΩ and when the picture elements are increased and the amount of rC is got to several hundreds or more, the value of R_C can be neglected substantially. Therefore, the more the amount of the pictures are increased, the more the resistance ratio Ⓐ : Ⓑ approaches 1 : 4 . On the other hand, since the capacitor C coupled to the electrodes is not changed, this means that the picture quality obtained according to the driving method of the present invention is the same as that of the prior driving method wherein the resistance of the transparent electrodes is one quarter. Otherwise, if the picture quality of the present invention is the same as that of the prior art, this means that a liquid crystal cell having twice size can be realized and the high resolution of the liquid crystal display device can be realized.
Fig. 4 shows one embodiment of the scanning driving circuit. In Fig. 4, the circuits which are surrounded by a dotted line 42 shows the driving circuits for one bit and are used as a plural vertical connections. The portion surrounded by the dotted line 43 shows circuits of high voltage portions relative to logic portion. In Fig. 4, the shift register which is operated by a shift clock SCK comprises D type flip flop 21. A signal LP shown in Fig. 1 is input to the shift clock SCK. Therefore, the output D_n+1 is input to the the flip flop Dn of the second step according to the shift clock SCK. Further, a start pulse YD is input to the flip flop Qn-1 which is a shift register of the first step. The output Qn of the flip flop 21 is transmitted to the inputs I and I of the level shifter 23a through NOR gate 24 which acts for forcibly changing the driver output OUT to the equivalent electric level by the signal INH. The output O and O of the level shifter is connected to gates the transfer gates 26 and 27 of the co-compensative transistor as well as being connected to either input of the NOR gate 32 and NAND gate 31, the NOR gate 32 and NAND gate 31 acting for changing the non-selected potential to the A.C. The signal which is obtained by combining the frame signal FR with the signal INH by the NOR gate 36 is input to the other sides of the gates 31 and 32 through the level shifter 23b and the invertor 38. The output of the gates 31 and 32 are connected to the gates of the transfer gate 28 of a P channel transistor and the transfer gate 29 of a N channel transistor, respectively to control the output of the non-selected levels V₁ and V₄
On the other hand, the selected potentials (V₀, V₅ ) are multiplexed by the transfer gate 40 of the P channel transistor and the transfer gate 41 of the N channel transistor in each of which a FR signal given from the output O of the level shifter 23b acts as a gate input, and then are supplied to the source electrodes of the co-compensative transfer gates 26 and 27. In the transfer gates 26 and 27, the outputs O, O of the level shifter 23a works as a gate input. When the output of Q_n of the shift register 21 is "H" only, the transfer gates 26 and 27 are conductive and the selecting level is transmitted to the output OUT. Otherwise, as mentioned above, when the signal INH is "H", in the transfer gates 26, 27, 28 and 29, the gates 26 and 27 are conductive, thus the driver output OUT is kept in the level V5. Therefore, when in Fig. 1, the display device, and in particular, the driving circuit is ON, if only INH signal is got to "H", the outputs of the both drivers 8 have the equivalent level, so that the outputs of the drivers are shortened to each other through the transparent electrodes, thereby making it possible to prevent the large current from flowing between the drivers. As a matter of course, the level of the equivalent potential may be not only V₅ but also V₀ , V₁, V₄ or high impedance. Further, it is possible to use the circuit used in a scanning side driving circuit for the short preventing circuit of the signal side driving circuit.
On the other hand, if the driving method of the present invention has TAB construction wherein a semiconductor IC for driving is bonded to the flexible tape or COG (Chip On Glass) construction, the driving circuits are connected to the both terminals of the liquid crystal cell are stored easily. In particular, COG constrauction is superior in that the wires between the driving circuit and electrodes, and connecting resistance are got to minimum. Further, even if the driving method of the present invention is only applied to the scanning electrodes, such a construction is effective in preventing the phenomenon shown in Fig. 2. Namely, since the amplitude of the driving voltage of the scanning electodes is about 5 to 10 times larger than that of the signal electrodes, the delay time of the charge/discharge time is likely to give the affect to the picture quality. This method is most available for the color liquid crystal cell which has the narrow electrode pitches.
Further, the electrode resistances of the signal electrodes are reduced by getting the transparent electrode films thicker or coupling the different metal of the low resistance to the transparent electrodes and the electrode resistances of the scanning electrodes are reduced equivalently. The picture quality can be improved by such reductions economically.
A simple matrix type LCD in the liquid crystal display devices is explained above. The deterioration of the picture quality which may be generated in dependance with the resistances of the picture electrodes can be improved by the method of the present invention. Therefore, the method of the present invention is widely applicable for active type LCD having TFT (thin film of transistor) or MIM (metal-insulator-metal), or for flat display till PDP (plasuma display panel) wherein much current is flown or ELD (electro luminescence display).
As mentioned above, according to the present invention, the transparent electrode resistances are got to one quarter equivalently, therefore it has the following advantages:

(a) Since in a passive type liquid crystal cell, the voltage applied to the liquid crystal approaches a predetermined value which is obtained by the voltage standarizing method, even if the display device has a middle or small capacitance and is driven by the 2 frame A.C. driving method, it is possible to obtain a high contrast display.
(b) A large scale panel display having fine pitch electrodes can be obtained without deterioration of the picture quality.
(c) Since it is not necessary to reduce the output resistance of the driving circuit excessively, it is possible to obtain IC having more pins and a lower cost than those of the prior art.
(d) Since the thickness of the tansparent electrode (ITO) is got to thinner, it is possible to obtain panels which are low in cost.

Claims

1. A flat display device having a plurality of display picture elements which are defined by liquid crystal cell portions formed between the scanning and the signal electrodes arranged in the form of a matrix, comprising first driving circuits which are driven from one terminal of said scanning electrodes and second driving circuits which are driven from another terminal of said scanning electrodes.

2. A flat display device claimed in claim 1, further comprising third driving circuits which are driven from one terminal of said signal electrodes and fourth driving circuits which are driven from another terminal of said signal electrodes.

3. A flat display device claimed in claim 1, wherein said first and second driving circuits are controlled in the same way by the same control signals.

4. A flat display device claimed in claim 2 wherein said first and second driving circuits are controlled in the same way by the same first controlling signals, and said third and fourth driving circuits are controlled in the same way by the same second colntrolling signals.

5. A flat display device claimed in claim 3, further comprising means which receives a signal representative of the power-on in said control signals, and forcibly supplies the output equivalent to said signal to both terminals of said scanning electrodes.

6. A flat display device claimed in claim 4, wherein said first and second driving circuits comprise means which receives a signal representative of the power-on in said first control signals and forcibly outputs the first voltage of equivalent level to said signal to both terminals of said scanning electrodes, and said third and fourth driving circuits comprise means which receives a signal representative of the power-on in said second control signals and fircibly outputs second voltage of equivalent level to said signal to both terminals of said scanning electrodes.

7. A flat display device claimed in claim 5, wherein said first driving circuit comprises first output terminals connected to one side terminals of said scanning electrodes and first transistor which outputs a predetermined level voltage to said first output terminal in response to said control signal, and said second driving circuit comprises second output terminals connected to another side terminals of said scanning electrodes and second transistor which outputs a predetermined level voltage to said second output terminal in response to said control signal.

8. A flat display device claimed in claim 6, wherein said first driving circuit comprises first output terminals connected to one side terminals of said scanning electrodes and a first transistor which outputs a predetermined level voltage to said first output terminal, said second driving cirucit comprises second output terminals connected to another side terminals of said scanning electrodes and second transistor which outputs a predetermined level voltage to said second output terminals, said third driving circuit comprises third output terminals connected to one side terminals of said scanning electrodes and a third transistor which outputs a predetermined level voltage to said third output terminal, and said fourth driving circuit comprises fourth output terminals connected to another side terminals of said scanning electrodes and a fourth transistor which outputs a predetermined level voltage to said fhourth output terminals.

9. A flat display device claimed in claim 7 or 8, wherein said plain display device comprises a liquid crystal display device.

10. A flat display device claimed in claim 9, wherein said scanning electrode and said signal electrodes comprise transparent power sources.

11. A flat display device claimed in claim 10, wherein said plain display device comprises a dot matrix type liquid crystal display device.

12. A flat display device having a plurality of display picture elements which are defined by liquid crystal cell portions formed between the scanning and the signal electrodes arranged in the form of a matrix, wherein said scanning electrodes are driven from both terminals thereof in accordance with the equivalent level output from separate scanning driving circuits.

13. A flat display device claimed in claim 12, wherein said signal electrodes are driven from both terminals thereof in accordance with the equivalent level output from separate scanning driving circuits.

14. A flat display device claimed in claim 12, wherein said separate driving outputs of the scanning driving circuit are forcibly got to the equivalent level and the both terminals of said scanning electrodes are got to the equivalent level for a predetermined period from the power-on of said flat display device.

15. A flat display device claimed in claim 13, wherein said separate driving outputs of the scanning driving circuit are forcibly got to the same level to get the both terminals of said scanning electrodes to the same first level and said separate driving outputs of the signal driving circuit are forcibly got to the same level to get the both terminals of said signal electrodes to the equivalent second level.