WO1983001709A1 - Plane transistor structure - Google Patents

Plane transistor structure Download PDF

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Publication number
WO1983001709A1
WO1983001709A1 PCT/DE1982/000174 DE8200174W WO8301709A1 WO 1983001709 A1 WO1983001709 A1 WO 1983001709A1 DE 8200174 W DE8200174 W DE 8200174W WO 8301709 A1 WO8301709 A1 WO 8301709A1
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WO
WIPO (PCT)
Prior art keywords
zone
area
potential
base
ring
Prior art date
Application number
PCT/DE1982/000174
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German (de)
French (fr)
Inventor
Bosch Gmbh Robert
Original Assignee
Michel, Hartmut
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Michel, Hartmut filed Critical Michel, Hartmut
Publication of WO1983001709A1 publication Critical patent/WO1983001709A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Definitions

  • the invention is based on a planar transistor structure according to the preamble of the main claim.
  • the transistor structures are already known. However, they have the disadvantage that external electric fields, such as those caused by polarization of masking lacquers when operated at high voltage and temperature, can lead to degradation of the blocking characteristics.
  • planar transistor structure according to the invention with the characterizing features of the main claim has the advantage over the fact that the space charge zone that forms during operation around the base zone is limited within the second annular zone and is shielded below the metal layer serving as the cover electrode from external electrical fields.
  • FIG. 1 shows a schematic partial section through the planar transistor structure according to the invention
  • FIG. 2 shows a non-schematic top view of the arrangement according to FIG. 1
  • FIG. 3 shows a top view of one of the Z paths designed as an emitter-base paths according to the invention.
  • 10 denotes a semiconductor wafer with n conductivity.
  • the semiconductor plate 10 has a collector connection C on its underside.
  • a p-conductive base zone 11 is diffused into the semiconductor plate 10 from above.
  • the base zone 11 carries a metallization, not specified, which leads to a base connection B.
  • An emitter zone which is not shown in FIG. 1 and has n + conductivity, is diffused into the base zone 11 from the same main surface of the semiconductor die 10 in the usual way.
  • a passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form contact windows.
  • a first annular zone 14 with p-conductivity is diffused around the base zone 11 into the upper side of the semiconductor die 10.
  • a second annular zone 15 with n + conductivity which serves as a stop ring, is further diffused into the upper side of the semiconductor die 10.
  • a metal layer D serving as a cover electrode is applied, which surrounds the base zone 11 in a ring shape, overlaps the edge of the base zone 11 which occurs at the top of the semiconductor die, extends into the region above the second annular zone 15 and with which first annular zone 1 4 is contacted in the region of the contact window 16.
  • the potential of the first annular zone 1 4 and thus the potential of the cover electrode D is selected according to the invention so that it lies between the potential of the base zone 11 and the potential of the semiconductor wafer 10 forming the collector zone.
  • FIG. 2 which shows a scale top view of the arrangement schematically drawn in FIG. 1, the three Z sections at 17, 18 and 19, indicated only schematically in FIG. 1, can be seen in the top view.
  • the passivation layer 13 is omitted from the drawing or assumed to be transparent so that the Z sections 17, 18, 19 and zones 11, 14 and 15 with their borders on the semiconductor surface become visible.
  • the cover electrode D extends in FIG. 2 over the entire strip-shaped area between the two dashed lines d1 and d2 with the exception of a recess A, which is also surrounded by dashed lines.
  • the recess A is necessary to accommodate the contact windows of the Z sections 17, 18 19 and the metallization bridges between these sections and their connection points.
  • the triangular contact window 16 shown in plan view in FIG. 2 serves to contact the top electrode D with the first annular zone 14.
  • each Z segment consists of a p-type zone 20 diffused into the n-type collector base material 10 and of an n + type zone 21 diffused into this zone.
  • Each of the two zones 20, 21 has a contact window (not shown in FIG. 3) and a metallization accommodated therein.
  • This metallization is indicated in FIG. 2 by dots, while the metallization bridges between the individual Z sections 17, 18, 19 are indicated in FIG. 2 by solid lines.
  • the dashed line drawn in the upper part of the recess A between two contact windows soll, on the other hand, is intended to indicate that further Z sections can also be accommodated in this space.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The structure comprises a collector area in a semiconductor chip (10) with a conductivity n?- and a base area (11) diffused on the main surface of the chip (10) and having a p-type conductivity. It comprises a transmitter area diffused in the base area (11) of n?+ type conductivity and a passivation layer (13). This layer covers the portion of the main surface of the chip (10) which is not used as a contact window. A first ring-shaped area (14) is diffused around the base area (11) in the main surface of the ship. It has a p-type conductivity. A second area of n?+ conductivity is diffused around the ring-shaped area (14) in the main surface of the chip (10). It acts as a stop ring (15). On the passivation layer (13), there is deposited a metal layer (D) which works as a cover electrode, surrounds the base area (11) by forming a ring, overlaps the edge of the base area (11), extends up to above the second annular area (15) and comes in contact in the first area (14) with said area (14). The potential of the first ring area (14) and therefore the potential of the cover electrode (D) is thus fixed so as to be comprised between the potential of the base area (11) and the potential of the semicondutor ship (10) forming the collector area.

Description

Planare Transistorstruktur Planar transistor structure
Stand der TechnikState of the art
Die Erfindung geht aus von einer planaren Transistorstruktur nach der Gattung des Hauptanspruchs. Der artige Transistor Struktur en sind bereits bekannt. Sie haben aber den Nachteil, daß von außen einwirkende elektrische Felder, wie sie beispielsweise durch Polarisation von Abdecklacken bei Betrieb mit hoher Spannung und Temperatur entstehen, zur Degradation von Sperrkennlinien führen können.The invention is based on a planar transistor structure according to the preamble of the main claim. The transistor structures are already known. However, they have the disadvantage that external electric fields, such as those caused by polarization of masking lacquers when operated at high voltage and temperature, can lead to degradation of the blocking characteristics.
Vorteile der ErfindungAdvantages of the invention
Die erfindungsgemäße planare Transistorstruktur mit den kennzeichnenden Merkmalen des Hauptanspruchs hat dem gegenüber den Vorteil, daß die sich im Betrieb um die Basiszone herum ausbildende Raumladungszone innerhalb der zweiten ringförmigen Zone begrenzt wird und unterhalb der als Deckelektrode dienenden Metallschicht von äußeren elektrischen Feldern abgeschirmt wird. ZeichnungThe planar transistor structure according to the invention with the characterizing features of the main claim has the advantage over the fact that the space charge zone that forms during operation around the base zone is limited within the second annular zone and is shielded below the metal layer serving as the cover electrode from external electrical fields. drawing
Ein Ausführungsbeispiel der erfindungsgemäßen planaren Transistorstruktur ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen: Figur 1 einen schematisierten Teilschnitt durch die planare TransistorStruktur gemäß der Erfindung, Figur 2 eine nicht schematisierte Draufsicht auf die Anordnung gemäß Figur 1 und Figur 3 eine Draufsicht auf eine der als Emitter-Basis-Strecken ausgebildeten Z Strecken gemäß der Erfindung.An embodiment of the planar transistor structure according to the invention is shown in the drawing and explained in more detail in the following description. FIG. 1 shows a schematic partial section through the planar transistor structure according to the invention, FIG. 2 shows a non-schematic top view of the arrangement according to FIG. 1, and FIG. 3 shows a top view of one of the Z paths designed as an emitter-base paths according to the invention.
Beschreibung des AusführungsbeispielsDescription of the embodiment
In Figur 1 ist mit 10 ein Halbleit erplättchen mit n Leitfähigkeit bezeichnet. Das Halbleiterplättchen 10 trägt an seiner Unterseite einen Kollektoranschluß C. In das Halbleiterplättchen 10 ist von oben her eine p-leitfähige Basiszone 11 eindiffundiert. Die Basiszone 11 trägt eine nicht näher bezeichnete Metallisierung, die zu einem Basisanschluß B führt. In die Basiszone 11 ist von derselben Hauptoberfläche des Halbleiterplättchens 10 aus in üblicher Weise eine Emitterzone eindiffundiert, die in Figur 1 nicht dargestellt ist und n+-Leitfähigkeit hat. über die Oberseite des Halbleiterplättchens 10 erstreckt sich eine Passivierungsschicht 13, die jedoch an verschiedenen Stellen zur Bildung von Kontaktfenstern unterbrochen ist.In FIG. 1, 10 denotes a semiconductor wafer with n conductivity. The semiconductor plate 10 has a collector connection C on its underside. A p-conductive base zone 11 is diffused into the semiconductor plate 10 from above. The base zone 11 carries a metallization, not specified, which leads to a base connection B. An emitter zone, which is not shown in FIG. 1 and has n + conductivity, is diffused into the base zone 11 from the same main surface of the semiconductor die 10 in the usual way. A passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form contact windows.
Erfindungsgemäß ist um die Basiszone 11 herum in die Oberseite des Halbleiterplättchens 10 eine erste ringförmige Zone 1 4 mit p-Leitfähigkeit eindiffundiert. Um diese erste ringförmige Zone 14 herum ist in die Oberseite des Halbleiterplättchens 10 erfindungsgemäß ferner eine zweite, als Stoppring dienende ringförmige Zone 15 mit n+-Leitfähigkeit eindiffundiert. Auf die Passivierungsschicht 13 ist gemäß einem weiteren Merkmal der Erfindung eine als Deckelektrode dienende Metallschicht D aufgebracht, die die Basiszone 11 ringförmig umgibt, den an die Oberseite des Halbleiterplättchens tretenden Rand der Basiszone 11 überlappt, sich bis in den Bereich oberhalb der zweiten ringförmigen Zone 15 erstreckt und mit der ersten ringförmigen Zone 1 4 im Bereich des Kontaktfensters 16 kontaktiert ist. Das Potential der ersten ringförmigen Zone 1 4 und damit das Potential der Deckelektrode D ist erfindungsgemäß so gewählt, daß es zwischen dem Potential der Basiszone 11 und dem Potential des die Kollektorzone bildenden Halbleiterplättchens 10 liegt.According to the invention, a first annular zone 14 with p-conductivity is diffused around the base zone 11 into the upper side of the semiconductor die 10. Around this first annular zone 14, a second annular zone 15 with n + conductivity, which serves as a stop ring, is further diffused into the upper side of the semiconductor die 10. On the passivation layer 13 According to a further feature of the invention, a metal layer D serving as a cover electrode is applied, which surrounds the base zone 11 in a ring shape, overlaps the edge of the base zone 11 which occurs at the top of the semiconductor die, extends into the region above the second annular zone 15 and with which first annular zone 1 4 is contacted in the region of the contact window 16. The potential of the first annular zone 1 4 and thus the potential of the cover electrode D is selected according to the invention so that it lies between the potential of the base zone 11 and the potential of the semiconductor wafer 10 forming the collector zone.
Dies wird mittels einer Kette von als Emitter-Basis Strecken ausgebildeten Z-Strecken 17, 18, 19 er reicht; die in Figur 1 symbolisch als hintereinander geschaltete Z-Dioden dargestellt sind. Das Potential der ersten ringförmigen Zone 14 kann dabei einen Festwert darstellen. Es kann aber auch durch Abgleich beim Vormessen oder über die Metallisierungsmaske eingestellt werden. Die Basis-Kollektor-Sperrspannung ergibt sich als Summe der Spannungen aller Z-Strecken und des Verarmungsdurchbruchs der Deckelektrode D gegenüber der zweiten ringförmigen Zone 15. Spannungen bis etwa 4 50 V sind auf diese Art mit dem Standardprozess zu erreichen.This is achieved by means of a chain of Z-sections 17, 18, 19 designed as an emitter-based section; which are shown symbolically in FIG. 1 as Z diodes connected in series. The potential of the first annular zone 14 can represent a fixed value. However, it can also be adjusted by comparing it during the preliminary measurement or using the metallization mask. The basic collector reverse voltage results from the sum of the voltages of all Z sections and the depletion breakdown of the cover electrode D compared to the second annular zone 15. Voltages of up to about 4 50 V can be achieved in this way with the standard process.
In Figur 2, die eine maßstabsgetreue Draufsicht auf die in Fig. 1 schemtisch gezeichnete Anordnung darstellt, sind die drei in Figur 1 nur schematisch angedeuteten Z-Strecken bei 17, 18 und 19 in der Draufsicht erkennbar. Die Passivierungsschicht 13 ist dabei in der Zeichnung weggelassen bzw. als durchsichtig angenommen, damit die Z-Strecken 17, 18, 19 und die Zonen 11, 14 und 15 mit ihren Be randungen an der Halbleiteroberfläche sichtbar werden. Die Deckelektrode D erstreckt sich in Figur 2 über den gesamten streifenförmigen Bereich zwischen den beiden gestrichelt gezeichneten Begrenzungslinien d1 und d2 mit Ausnahme einer Aussparung A, die ebenfalls mit gestrichelten Linien umrandet ist. Die Aussparung A ist notwendig, um die Kontaktfenster der Z-Strecken 17, 18 19 und die Metallisierungsbrücken zwischen diesen Strecken und ihren Anschlußstellen unterzubringen. Zur Kontaktierung der Deckelektrode D mit der ersten ringförmigen Zone 14 dient das in Figur 2 in der Draufsicht dargestellte dreieckige Kontaktfenster 16.In FIG. 2, which shows a scale top view of the arrangement schematically drawn in FIG. 1, the three Z sections at 17, 18 and 19, indicated only schematically in FIG. 1, can be seen in the top view. The passivation layer 13 is omitted from the drawing or assumed to be transparent so that the Z sections 17, 18, 19 and zones 11, 14 and 15 with their borders on the semiconductor surface become visible. The cover electrode D extends in FIG. 2 over the entire strip-shaped area between the two dashed lines d1 and d2 with the exception of a recess A, which is also surrounded by dashed lines. The recess A is necessary to accommodate the contact windows of the Z sections 17, 18 19 and the metallization bridges between these sections and their connection points. The triangular contact window 16 shown in plan view in FIG. 2 serves to contact the top electrode D with the first annular zone 14.
In Figur 3 ist eine der Z-Strecken 17, 18, 19 in der Draufsicht einzeln herausgezeichnet. Die Passivierungsschicht 13 ist dabei wie in Fig. 2 weggelassen, so daß der Aufbau der Z-Strecke sichtbar wird. Man erkennt aus Figur 3, daß jede Z-Strecke aus einer in das n--leitende Kollektorgrundmaterial 10 eindiffundierten p-leitenden Zone 20 und aus einer in diese Zone eindiffundierten n+-leitenden Zone 21 besteht. Jede der beiden Zonen 20, 21 hat ein in Figur 3 nicht dargestelltes Kontaktfenster und eine darin untergebrachte Metallisierung. Diese Metallisierung ist in Figur 2 jeweils durch Punkte angedeutet, während die zwischen den einzelnen Z-Strecken 17, 18, 19 liegenden Metallisierungsbrücken in Figur 2 durch ausgezogene Linien angedeutet sind. Der im oberen Teil der Aussparung A zwischen zwei Kontaktfensterή gezeichnete gestrichelte Linienzug soll dagegen andeuten, daß in diesem Zwischenraum auch noch weitere Z-Strecken untergebracht sein können. In Figure 3, one of the Z sections 17, 18, 19 is individually drawn out in plan view. The passivation layer 13 is omitted as in FIG. 2, so that the structure of the Z path is visible. It can be seen from FIG. 3 that each Z segment consists of a p-type zone 20 diffused into the n-type collector base material 10 and of an n + type zone 21 diffused into this zone. Each of the two zones 20, 21 has a contact window (not shown in FIG. 3) and a metallization accommodated therein. This metallization is indicated in FIG. 2 by dots, while the metallization bridges between the individual Z sections 17, 18, 19 are indicated in FIG. 2 by solid lines. The dashed line drawn in the upper part of the recess A between two contact windows soll, on the other hand, is intended to indicate that further Z sections can also be accommodated in this space.

Claims

Ansprüche Expectations
1. Planare TransistorStruktur mit einem die Kollektorzone bildenden Halbleiterplättchen (10) mit n--Leit- fähigkeit, einer in eine Hauptoberfläche des Halbleiterplättchens (10) eindiffundierten Basiszone (11) mit p-Leitfähigkeit, einer in die Basiszone (11) eindiffundierten Emitterzone mit n+-Leitfähigkeit und mit einer Passivierungsschicht (13), die diejenigen Teile der Hauptoberfläche des Halbleiterplättchens (10) bedeckt, die nicht als Kontaktfenster dienen, dadurch gekennzeichnet, daß um die Basiszone (11) herum in die Hauptoberfläche des Halbleiterplättchens (10) eine erste ringförmige Zone (14) mit p-Leitfähigkeit eindiffundiert ist, daß um die erste ringförmige Zone (14) herum in die Hauptoberfläche des Halbleiterplättchens (10) eine zweite, als Stoppring dienende ringförmige Zone (15) mit n+-Leitfähigkeit eindiffundiert ist und daß auf die Passivierungsschicht (13) eine als Deckelektrode dienende Metallschicht (D) aufgebracht ist, die die Basiszone (11 ) ringförmig umgibt, den an die HalbleiterOberfläche tretenden Rand der Basiszone (11) überlappt; sich bis in den. Bereich oberhalb der zweiten ringförmigen Zone (15) erstreckt und im Bereich der ersten ringförmigen Zone (14) mit dieser Zone (14) kontaktiert ist, wobei das Potential der ersten ringförmigen Zone ( 1 4 ). und damit das Potential der Deckelektrode (D) so gewählt ist, daß es zwischen dem Potential der Basiszone (11) und dem Potential des die Kollektorzone bildenden Halbleiterplättchens (10) liegt.1. A planar transistor structure with a semiconductor wafer (10) with n-conductivity forming the collector zone, a base zone (11) with p-conductivity diffused into a main surface of the semiconductor wafer (10) and an emitter zone diffused into the base zone (11) n + conductivity and with a passivation layer (13) which covers those parts of the main surface of the semiconductor die (10) which do not serve as a contact window, characterized in that around the base zone (11) around the main surface of the semiconductor die (10) first ring-shaped zone (14) with p-conductivity is diffused in that around the first ring-shaped zone (14) around the main surface of the semiconductor die (10) a second ring-shaped ring (15) serving as a stop ring is diffused with n + conductivity and that a metal layer (D) serving as a cover electrode is applied to the passivation layer (13) and covers the base zone (11) surrounds in an annular manner, overlaps the edge of the base zone (11) which approaches the semiconductor surface; yourself in the. Extends above the second annular zone (15) and is in contact with this zone (14) in the region of the first annular zone (14), the potential of the first annular zone (1 4). and thus the potential of the cover electrode (D) is selected such that it lies between the potential of the base zone (11) and the potential of the semiconductor wafer (10) forming the collector zone.
2. TransistorStruktur nach Anspruch 1, dadurch gekennzeichnet, daß das Potential der ersten ringförmigen Zone (14) mittels einer Kette von als Emitter-Basis-Strecken (21, 20) ausgebildeten Z-Strecken (17, 18, 19) gegenüber dem Potential der Basiszone (11) einstellbar ist. 2. Transistor structure according to claim 1, characterized in that the potential of the first annular zone (14) by means of a chain of Z-sections (17, 18, 19) designed as an emitter-base sections (21, 20) with respect to the potential of the Base zone (11) is adjustable.
PCT/DE1982/000174 1981-10-28 1982-09-03 Plane transistor structure WO1983001709A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3142616.6811028 1981-10-28
DE19813142616 DE3142616A1 (en) 1981-10-28 1981-10-28 "PLANAR TRANSISTOR STRUCTURE"

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WO1983001709A1 true WO1983001709A1 (en) 1983-05-11

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IT (1) IT1153589B (en)
WO (1) WO1983001709A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098834B1 (en) * 1982-01-20 1987-01-07 Robert Bosch Gmbh Planar semiconductor device
WO1992000606A1 (en) * 1990-06-28 1992-01-09 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
WO1994016462A1 (en) * 1993-01-07 1994-07-21 Harris Corporation Spiral edge passivation structure for semiconductor devices
US5479046A (en) * 1990-06-28 1995-12-26 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
EP0703627A1 (en) * 1994-09-20 1996-03-27 Hitachi, Ltd. Semiconductor device with field plate and power converter using same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710204A (en) * 1967-05-20 1973-01-09 Telefunken Patent A semiconductor device having a screen electrode of intrinsic semiconductor material
US3763406A (en) * 1969-03-25 1973-10-02 Philips Corp Guard junction for semiconductor devices
US3836998A (en) * 1969-01-16 1974-09-17 Signetics Corp High voltage bipolar semiconductor device and integrated circuit using the same and method
FR2282723A1 (en) * 1974-08-19 1976-03-19 Sony Corp SEMICONDUCTOR COMPONENT WITH A JUNCTION COVERED WITH A PASSIVATION LAYER
US4009483A (en) * 1974-04-04 1977-02-22 Motorola, Inc. Implementation of surface sensitive semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710204A (en) * 1967-05-20 1973-01-09 Telefunken Patent A semiconductor device having a screen electrode of intrinsic semiconductor material
US3836998A (en) * 1969-01-16 1974-09-17 Signetics Corp High voltage bipolar semiconductor device and integrated circuit using the same and method
US3763406A (en) * 1969-03-25 1973-10-02 Philips Corp Guard junction for semiconductor devices
US4009483A (en) * 1974-04-04 1977-02-22 Motorola, Inc. Implementation of surface sensitive semiconductor devices
FR2282723A1 (en) * 1974-08-19 1976-03-19 Sony Corp SEMICONDUCTOR COMPONENT WITH A JUNCTION COVERED WITH A PASSIVATION LAYER

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098834B1 (en) * 1982-01-20 1987-01-07 Robert Bosch Gmbh Planar semiconductor device
WO1992000606A1 (en) * 1990-06-28 1992-01-09 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
US5479046A (en) * 1990-06-28 1995-12-26 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
WO1994016462A1 (en) * 1993-01-07 1994-07-21 Harris Corporation Spiral edge passivation structure for semiconductor devices
US5382825A (en) * 1993-01-07 1995-01-17 Harris Corporation Spiral edge passivation structure for semiconductor devices
EP0703627A1 (en) * 1994-09-20 1996-03-27 Hitachi, Ltd. Semiconductor device with field plate and power converter using same

Also Published As

Publication number Publication date
EP0092550A1 (en) 1983-11-02
IT8223923A0 (en) 1982-10-26
DE3142616A1 (en) 1983-05-05
IT1153589B (en) 1987-01-14

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