DE3142616A1 - "PLANAR TRANSISTOR STRUCTURE" - Google Patents

"PLANAR TRANSISTOR STRUCTURE"

Info

Publication number
DE3142616A1
DE3142616A1 DE19813142616 DE3142616A DE3142616A1 DE 3142616 A1 DE3142616 A1 DE 3142616A1 DE 19813142616 DE19813142616 DE 19813142616 DE 3142616 A DE3142616 A DE 3142616A DE 3142616 A1 DE3142616 A1 DE 3142616A1
Authority
DE
Germany
Prior art keywords
zone
area
base
potential
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19813142616
Other languages
German (de)
Inventor
Hartmut Dipl.-Ing. 7410 Reutlingen Michel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE19813142616 priority Critical patent/DE3142616A1/en
Priority to PCT/DE1982/000174 priority patent/WO1983001709A1/en
Priority to EP82902668A priority patent/EP0092550A1/en
Priority to IT23923/82A priority patent/IT1153589B/en
Publication of DE3142616A1 publication Critical patent/DE3142616A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The structure comprises a collector area in a semiconductor chip (10) with a conductivity n<-> and a base area (11) diffused on the main surface of the chip (10) and having a p-type conductivity. It comprises a transmitter area diffused in the base area (11) of n<+> type conductivity and a passivation layer (13). This layer covers the portion of the main surface of the chip (10) which is not used as a contact window. A first ring-shaped area (14) is diffused around the base area (11) in the main surface of the ship. It has a p-type conductivity. A second area of n<+> conductivity is diffused around the ring-shaped area (14) in the main surface of the chip (10). It acts as a stop ring (15). On the passivation layer (13), there is deposited a metal layer (D) which works as a cover electrode, surrounds the base area (11) by forming a ring, overlaps the edge of the base area (11), extends up to above the second annular area (15) and comes in contact in the first area (14) with said area (14). The potential of the first ring area (14) and therefore the potential of the cover electrode (D) is thus fixed so as to be comprised between the potential of the base area (11) and the potential of the semicondutor ship (10) forming the collector area.

Description

Planare TransistorstrukturPlanar transistor structure

Stand der Technik Die Erfindung geht aus von einer planaren Transistorstruktur nach der Gattung des Hauptanspruchs. Derartige Transistorstrukturen sind bereits bekannt. Sie haben aber den Nachteil, daß von außen einwirkende elektrische Felder, wie sie beispielsweise durch Polarisation von Abdecklacken bei Betrieb mit hoher Spannung und Temperatur entstehen, zur Degradation von Sperrkennlinien führen können.PRIOR ART The invention is based on a planar transistor structure according to the genre of the main claim. Such transistor structures already exist known. But they have the disadvantage that external electric fields, such as, for example, by polarization of masking lacquers when operating at high Voltage and temperature arise that can lead to the degradation of blocking characteristics.

Vorteile der Erfindung Die erfindungsgemäße planare Transistorstruktur mit den kennzeichnenden Merkmalen des Hauptanspruchs hat dem gegenüber den Vorteil, daß die sich im Betrieb um die Basiszone herum ausbildende Raumladungszone innerhalb der zweiten ringförmigen Zone begrenzt wird und unterhalb der als Deckelektrode dienenden Metallschicht von äußeren elektrischen Feldern abgeschirmt wird.Advantages of the Invention The planar transistor structure according to the invention with the characterizing features of the main claim has the advantage over that the space charge zone that forms around the base zone during operation is within the second annular zone is limited and below that as a cover electrode serving metal layer is shielded from external electrical fields.

Zeichnung Ein Ausführungsbeispiel der erfindungsgemäßen planaren Transistorstruktur ist in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen: Figur 1 einen schematisierten Teilschnitt durch die planare Transistorstruktur gemäß der Erfindung, Figur 2 eine nicht schematisierte Draufsicht auf die Anordnung gemäß Figur 1 und Figur 3 eine Draufsicht auf eine der als Emitter-Basis-Strecken ausgebildeten Z-Strecken gemäß der Erfindung.DRAWING An embodiment of the planar transistor structure according to the invention is shown in the drawing and explained in more detail in the following description. The figures show: FIG. 1 a schematic partial section through the planar transistor structure according to the invention, FIG. 2 shows a not schematized plan view of the arrangement according to FIG. 1 and FIG. 3, a plan view of one of the emitter-base lines trained Z-segments according to the invention.

Beschreibung des Ausführungsbeispiels In Figur 1 ist mit 10 ein Halbleiterplättchen mit n -Leitfähigkeit bezeichnet. Das Halbleiterplättchen 10 trägt an seiner Unterseite einen Kollektoranschluß C.DESCRIPTION OF THE EXEMPLARY EMBODIMENT In FIG. 1, 10 is a semiconductor wafer denoted by n -conductivity. The semiconductor wafer 10 carries on its underside a collector connection C.

In das Halbleiterplättchen 10 ist von oben her eine p-leitfähige Basiszone 11 eindiffundiert. Die Basiszone 11 trägt eine nicht näher bezeichnete Metallisierung, die zu einem Basisanschluß B führt. In die Basiszone 11 ist von derselben Hauptoberfläche des Halbleiterplättchens 10 aus in üblicher Weise eine Emitterzone eindiffundiert, die in Figur 1 nicht dargestellt ist und n -Leitfähigkeit hat. Über die Oberseite des Halbleiterplättchens 10 erstreckt sich eine Passivierungsschicht 13, die jedoch an verschiedenen Stellen zur Bildung von Kontaktfenstern unterbrochen ist.A p-conductive base zone is located in the semiconductor wafer 10 from above 11 diffused. The base zone 11 has an unspecified metallization, which leads to a base connection B. In the base zone 11 is from the same main surface of the semiconductor wafer 10 diffused from an emitter zone in the usual way, which is not shown in Figure 1 and has n conductivity. Over the top of the semiconductor chip 10 extends a passivation layer 13, which, however is interrupted at various points to form contact windows.

Erfindungsgemäß ist um die Basiszone 11 herum in die Oberseite des Halbleiterplättchens 10 eine erste ringförmige Zone 14 mit p-Leitfähigkeit eindiffundiert. Um diese erste ringförmige Zone 14 herum ist in die Oberseite des Halbleiterplättchens 10 erfindungsgemäß ferner eine zweite, als Stoppring dienende ringförmige Zone 15 mit n -Leitfähigkeit eindiffundiert. Auf die Passivierungsschicht 13 ist gemäß einem weiteren Merkmal der Erfindung eine als Deckelektrode dienende Metallschicht D auBgebracht, die die Basiszone 11 ringförmig umgibt, den an die. Oberseite des Halbleiterplättchens tretenden Rand der Basiszone 11 überlappt, sich bis in den Bereich oberhalb der zweiten ringförmigen Zone 15 erstreckt und mit der ersten ringförmigen Zone 14 im Bereich des Kontaktfensters 16 kontaktiert ist. Das Potential der ersten ringförmigen Zone 14 und damit das Potential der Deckelektrode D ist erfindungsgemäß so gewählt, daß es zwischen dem Potential der Basiszone 11 und dem Potential des die Kollektorzone bildenden Halbleiterplättchens 10 liegt.According to the invention is around the base zone 11 in the top of the Semiconductor wafer 10 a first annular zone 14 diffused with p-conductivity. Around this first annular zone 14 is in the top of the semiconductor die 10 furthermore, according to the invention, a second annular zone 15 serving as a stop ring diffused with n conductivity. On the passivation layer 13 is According to a further feature of the invention, a metal layer serving as a cover electrode D applied, which annularly surrounds the base zone 11, which is attached to the. Top of the Semiconductor wafer stepping edge of the base zone 11 overlaps, into the Area extending above the second annular zone 15 and with the first annular Zone 14 is contacted in the area of the contact window 16. The potential of the first annular zone 14 and thus the potential of the cover electrode D is according to the invention chosen so that it is between the potential of the base zone 11 and the potential of the the semiconductor wafer 10 forming the collector zone is located.

Dies wird mittels einer Kette von als Emitter-Basis-Strecken ausgebildeten Z-Strecken 173 189 19 erreicht, die in Figur 1 symbolisch als hintereinandergeschaltete Z-Dioden dargestellt sind. Das Potential der ersten ringförmigen Zone 14 kann dabei einen Festwert darstellen. Es kann aber auch durch Abgleich beim Vormessen oder über die Metallisierungsmaske eingestellt werden. Die Basis-Kollektor-Sperrspannung ergibt sich als Summe der Spannungen aller Z-Strecken und des Verarmungsdurchbruchs der Deckelektrode D gegenüber der zweiten ringförmigen Zone 15. Spannungen bis etwa 450 V sind auf diese Art mit dem Standardprozess zu erreichen.This is done by means of a chain of emitter-base lines Z-stretches 173 189 19 reached, which are symbolically shown in FIG. 1 as being connected in series Zener diodes are shown. The potential of the first annular zone 14 can thereby represent a fixed value. But it can also be done by comparing the pre-measuring or can be set via the metallization mask. The base-collector reverse voltage results from the sum of the voltages of all Z-segments and the depletion breakthrough of the top electrode D compared to the second annular zone 15. Tensions up to about 450 V can be achieved in this way with the standard process.

In Figur 2, die eine maßstabsgetreue Draufsicht auf die in Fig. 1 scheStisch gezeichnete Anordnung darstellt, sind die drei in Figur 1 nur schematisch angedeuteten Z-Strecken bei 17, 18 und 19 in der Draufsicht erkennbar. Die Passivierungsschicht 13 ist dabei in der Zeichnung weggelassen bzw. als durchsichtig angenommen, damit die Z-Strecken 17, 18, 19 und die Zonen 11, 14 und 15 mit ihren Berandungen an der Halbleiteroberfläche sichtbar werden. Die Deckelektrode D erstreckt sich in Figur 2 über den gesamten streifenförmigen Bereich zwischen den beiden gestrichelt gezeichneten Begrenzungslinien dl und d2 mit Ausnahme einer Aussparung A, die ebenfalls mit gestrichelten Linien umrandet ist. Die Aussparung A ist notwendig, um die Kontaktfenster der Z-Strecken 17, 18 19 und die-.Metallisierungsbrücken zwischen diesen Strecken und ihren Anschlußstellen unterzubringen. Zur Kontaktierung der Deckelektrode D mit der ersten ringförmigen Zone 14 dient das in Figur 2 in der Draufsicht dargestellte dreieckige Kontaktfenster 16.In FIG. 2, which is a true-to-scale plan view of the one in FIG represents schematically drawn arrangement, the three in Figure 1 are only schematically indicated Z-sections at 17, 18 and 19 in the plan view. The passivation layer 13 is omitted in the drawing or assumed to be transparent so the Z-segments 17, 18, 19 and zones 11, 14 and 15 with their Boundaries on the semiconductor surface become visible. The cover electrode D extends in Figure 2 over the entire strip-shaped area between the two dashed lines drawn boundary lines dl and d2 with the exception of a recess A, which is also is outlined with dashed lines. The recess A is necessary for the contact window the Z-stretches 17, 18 19 and the metallization bridges between these stretches and to accommodate their connection points. For contacting the cover electrode D with the first annular zone 14 is used that shown in FIG. 2 in plan view triangular contact windows 16.

In Figur 3 ist eine der Z-Strecken 17, 18, 19 in der Draufsicht einzeln herausgezeichnet. Die Passivierungsschicht 13 ist dabei wie in Fig. 2 weggelassen, so daß der Aufbau der Z-Strecke sichtbar wird. Man erkennt aus Figur 3, daß jede Z-Strecke aus einer in das n -leitende Kollektorgrundmaterial 10 eindiffundierten p-leitenden Zone 20 und aus einer in diese Zone eindiffundierten n -leitenden Zone 21 besteht. Jede der beiden Zonen 20, 21 hat ein in Figur 3 nicht dargestelltes Kontaktfenster und eine darin untergebrachte Metallisierung. Diese Metallisierung ist in Figur 2 jeweils durch Punkte angedeutet, während die zwischen den einzelnen Z-Strecken 17, 18, 19 liegenden Metallisierungsbrücken in Figur 2 durch ausgezogene Linien angedeutet sind. Der im oberen Teil der Aussparung A zwischen zwei Kontaktfenstern gezeichnete gestrichelte Linienzug soll dagegen andeuten, daß in diesem Zwischenraum auch noch weitere Z-Strecken untergebracht sein können.In Figure 3, one of the Z-segments 17, 18, 19 is individual in plan view drawn out. The passivation layer 13 is omitted here, as in FIG. 2, so that the structure of the Z-segment becomes visible. It can be seen from Figure 3 that each Z-segment made of a diffused into the n -conductive collector base material 10 p-conductive zone 20 and from an n -conductive zone diffused into this zone 21 exists. Each of the two zones 20, 21 has one that is not shown in FIG Contact window and a metallization accommodated therein. This metallization is indicated in Figure 2 by dots, while between the individual Z-segments 17, 18, 19 lying metallization bridges in Figure 2 through solid lines Lines are indicated. The one in the upper part of the recess A between two contact windows drawn dashed line is intended to indicate that in this space further Z-sections can also be accommodated.

Claims (2)

Ansprüche C Planare Transistorstruktur mit einem die Kollektorzone bildenden Halbleiterplättchen (10) mit n -Leitfähigkeit, einer in eine Hauptoberfläche des Halbleiterplättchens (10) eindiffundierten Basiszone (11) mit p-Leitfähigkeit, einer in die Basiszone (11) ein-+ diffundierten Emitterzone mit n -Leitfähigkeit und mit einer Passivierungsschicht (13), die diejenigen Teile der Hauptoberfläche des Halbleiterplättchens (10) bedeckt, die nicht als Kontaktfenster dienen, dadurch gekennzeichnet, daß um die Basiszone (11) herum in die Hauptoberfläche des Halbleiterplättchens (10) eine erste ringförmige Zone (14) mit p-Leitfähigkeit eindiffundiert ist, daß um die erste ringförmige Zone (14) herum in die Hauptoberfläche des Halbleiterplättchens (10) eine zweite, als Stoppring dienende ringförmige Zone (15) mit n -Leitfähigkeit eindiffundiert ist und daß auf die Passivierungsschicht (13) eine als Deckelektrode dienende Metallschicht (D) aufgebracht ist, die die Basiszone (11) ringförmig umgibt, den an die Halbleiteroberfläche tretenden Rand der Basiszone (11) überlappt, sich bis in den Bereich oberhalb der zweiten ringförmigen Zone (ins) erstreckt und im Bereich der ersten ringförmigen Zone (14) mit dieser Zone (14) kontaktiert ist, wobei das Potential der ersten ringförmigen Zone (14) und damit das Potential der Deckelektrode (D) so gewählt ist, daß es zwischen dem Potential der Basiszone (11) und dem Potential des die Kollektorzone bildenden Halbleiterplättchens (10) liegt.Claims C planar transistor structure with one the collector zone forming semiconductor wafer (10) with n -conductivity, one in a main surface the semiconductor wafer (10) diffused base zone (11) with p-conductivity, an emitter zone with n -conductivity diffused into the base zone (11) and with a passivation layer (13) covering those parts of the main surface of the semiconductor wafer (10), which do not serve as a contact window, thereby characterized in that around the base region (11) in the major surface of the semiconductor die (10) a first annular zone (14) with p-conductivity is diffused in that around the first annular zone (14) into the major surface of the semiconductor die (10) a second annular zone (15) serving as a stop ring and having n -conductivity has diffused in and that on the passivation layer (13) one as a cover electrode serving metal layer (D) is applied, which annularly surrounds the base zone (11), overlaps the edge of the base zone (11) approaching the semiconductor surface extends into the area above the second annular zone (ins) and in The area of the first annular zone (14) is in contact with this zone (14), whereby the potential of the first annular zone (14) and thus the potential of the cover electrode (D) is chosen so that it is between the potential of the base zone (11) and the potential of the semiconductor wafer (10) forming the collector zone. 2. Transistorstruktur nach Anspruch 1, dadurch gekennzeichnet, daß das Potential der ersten ringförmigen Zone (14) mittels einer Kette von als Emitter-Basis-Strecken (21, 20) ausgebildeten Z-Strecken (17, 18, 19) gegenüber dem Potential der Basiszone (11) einstellbar ist.2. Transistor structure according to claim 1, characterized in that the potential of the first annular zone (14) by means of a chain of emitter-base paths (21, 20) formed Z-segments (17, 18, 19) with respect to the potential of the base zone (11) is adjustable.
DE19813142616 1981-10-28 1981-10-28 "PLANAR TRANSISTOR STRUCTURE" Withdrawn DE3142616A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19813142616 DE3142616A1 (en) 1981-10-28 1981-10-28 "PLANAR TRANSISTOR STRUCTURE"
PCT/DE1982/000174 WO1983001709A1 (en) 1981-10-28 1982-09-03 Plane transistor structure
EP82902668A EP0092550A1 (en) 1981-10-28 1982-09-03 Plane transistor structure
IT23923/82A IT1153589B (en) 1981-10-28 1982-10-26 PLANAR TRANSISTORIZED STRUCTURE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813142616 DE3142616A1 (en) 1981-10-28 1981-10-28 "PLANAR TRANSISTOR STRUCTURE"

Publications (1)

Publication Number Publication Date
DE3142616A1 true DE3142616A1 (en) 1983-05-05

Family

ID=6144948

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813142616 Withdrawn DE3142616A1 (en) 1981-10-28 1981-10-28 "PLANAR TRANSISTOR STRUCTURE"

Country Status (4)

Country Link
EP (1) EP0092550A1 (en)
DE (1) DE3142616A1 (en)
IT (1) IT1153589B (en)
WO (1) WO1983001709A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3201545A1 (en) * 1982-01-20 1983-07-28 Robert Bosch Gmbh, 7000 Stuttgart PLANAR SEMICONDUCTOR ARRANGEMENT
DE4020519A1 (en) * 1990-06-28 1992-01-02 Bosch Gmbh Robert Monolithic integrated semiconductor with higher breakdown voltage
US5479046A (en) * 1990-06-28 1995-12-26 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
US5382825A (en) * 1993-01-07 1995-01-17 Harris Corporation Spiral edge passivation structure for semiconductor devices
JP3111827B2 (en) * 1994-09-20 2000-11-27 株式会社日立製作所 Semiconductor device and power conversion device using the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710204A (en) * 1967-05-20 1973-01-09 Telefunken Patent A semiconductor device having a screen electrode of intrinsic semiconductor material
US3836998A (en) * 1969-01-16 1974-09-17 Signetics Corp High voltage bipolar semiconductor device and integrated circuit using the same and method
NL6904619A (en) * 1969-03-25 1970-09-29
US4009483A (en) * 1974-04-04 1977-02-22 Motorola, Inc. Implementation of surface sensitive semiconductor devices
JPS573225B2 (en) * 1974-08-19 1982-01-20

Also Published As

Publication number Publication date
IT1153589B (en) 1987-01-14
IT8223923A0 (en) 1982-10-26
EP0092550A1 (en) 1983-11-02
WO1983001709A1 (en) 1983-05-11

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