USRE41684E1 - Set of integrated capacitor arrangements, especially integrated grid capacitors - Google Patents

Set of integrated capacitor arrangements, especially integrated grid capacitors Download PDF

Info

Publication number
USRE41684E1
USRE41684E1 US12/175,170 US17517003A USRE41684E US RE41684 E1 USRE41684 E1 US RE41684E1 US 17517003 A US17517003 A US 17517003A US RE41684 E USRE41684 E US RE41684E
Authority
US
United States
Prior art keywords
capacitor
correction
capacitors
connection
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US12/175,170
Other languages
English (en)
Inventor
Armin Fischer
Franz Ungar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of USRE41684E1 publication Critical patent/USRE41684E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only

Definitions

  • the invention relates to an integrated capacitor arrangement containing at least one circuitry-effective main capacitor.
  • Layer application methods and layer patterning methods are used as fabrication techniques for integrated arrangements.
  • a capacitor contains two electrodes opposite one another between which a dielectric is arranged.
  • Examples of integrated capacitors are:
  • circuitry-effective capacitors serve as:
  • the intention is to specify a set of grid capacitors.
  • the set according to the invention contains at least two integrated capacitor arrangements, which have been produced in accordance with identical geometrical designs or layouts and which each contain a circuitry-effective main capacitor and at least one correction capacitor.
  • One capacitor arrangement contains an electrically conductive connection between the correction capacitor and the main capacitor, the connection having been produced after the production of the main capacitor of this capacitor arrangement.
  • the other capacitor arrangement contains an electrically insulating interruption between the same correction capacitor and the main capacitor, the interruption having been produced in accordance with the geometrical designs.
  • connection is produced in a simple manner by local heating, so that components in proximity to the connection are protected from an increased thermal loading.
  • permanent links can be produced by local heating in a simple manner. Compared with the production of interruption by local heating, links can be implemented by local heating at lower temperatures. The thermal loading is thus low, particularly during the production of a multiplicity of links on a semiconductor wafer.
  • the local heating is carried out for example with the aid of a laser beam.
  • This correction possibility allows integrated capacitor arrangements with predetermined capacitance values to be produced in a simple manner.
  • the connection contains two interconnect sections which are spaced apart from one another and between which only a dielectric is arranged.
  • the materials of the interconnect sections and of the dielectric are chosen such that material warpages of the interconnect which penetrate through the dielectric arise during the heating.
  • the dielectric contains doping atoms which change the conductivity of the dielectric during the heating. Activation of the doping atoms is an expression that is also used in this context.
  • an antifuse there are also other possibilities for producing the connection, which is also referred to as an antifuse.
  • the circuit arrangements contain at least one further correction capacitor, which is disconnected from the main capacitor or has been connected to the main capacitor.
  • a further interruption for disconnecting the further correction capacitor is produced by local heating.
  • the local heating can be carried out, for example, with the aid of a laser beam or with the aid of a current surge through an interconnect constriction.
  • dielectrics of the capacitors are formed by a dielectric between metallization layers in which connection sections of connections to integrated semiconductor components of the integrated capacitor arrangement are situated. It is possible to use a different dielectric in the region of the capacitor than in the remaining region between the metallization layers, e.g. a dielectric having a higher dielectric constant. Examples of such capacitors are stacked capacitors or grid capacitors. In other words, the electrodes of a capacitor lie in more than two metallization layers. In the case of such capacitors, in one configuration, not only electrodes in the topmost metallization layer but also electrodes in lower metallization layers are disconnected in terms of circuitry or added in terms of circuitry during the correction.
  • the linking elements and interruptions for the lower electrodes are situated either in the lower metallization layer, so that it is necessary, for example, to provide cutouts of corresponding depth for a laser beam, or in an upper metallization layer, to which connections from the lower metallization layer lead.
  • dielectrics of the capacitors have a thickness which is significantly less than the thickness of the dielectric between metallization layers.
  • capacitors are MIM capacitors.
  • at least one electrode of the capacitor lies outside a metallization layer.
  • the capacitance of a correction capacitor amounts to less than 1 ⁇ 3, less than 1/10, less than 1/100 or less than 1/1000 of the capacitance of a main capacitor. This measure means that fine trimming is possible.
  • the capacitance values of two capacitor arrangements of the same integrated circuit arrangement can be coordinated with one another very precisely. This is absolutely necessary for some applications.
  • the invention additionally relates to a set of grid capacitors with correction transverse electrodes. Individual transverse electrodes of the grid capacitors also afford a possibility for correction of the capacitance during the production. The abovementioned technical effects therefore apply particularly to the grid capacitors.
  • FIG. 1 shows a plan view of an MIM capacitor arrangement
  • FIG. 2 shows a plan view of a grid capacitor arrangement
  • FIG. 3 shows a transverse electrode of a grid capacitor with two interruption possibilities
  • FIG. 4 shows a transverse electrode of a grid capacitor with a continuous interruption possibility
  • FIG. 5 shows method steps for correcting the capacitance of an integrated capacitor.
  • FIG. 1 shows a plan view of an MIM capacitor arrangement 10 , which contains a main capacitor 12 connected to an electronic circuit and a plurality of disconnectable capacitors situated to the right of the main capacitor 12 , of which only one disconnectable capacitor 14 is illustrated.
  • the dielectric is not illustrated in FIG. 1 for reasons of improved clarity.
  • a plurality of connectable capacitors are situated to the left of the main capacitor 12 , of which one connectable capacitor 16 is illustrated in FIG. 1 .
  • the capacitors 12 to 16 are constructed identically except for their longitudinal dimensions.
  • the capacitors 12 , 14 and 16 respectively contain a bottom electrode 18 , 20 and 22 near the substrate and an electrode 24 , 26 and 28 remote from the substrate.
  • the bottom electrodes 18 , 20 and 22 are longer than the respectively associated electrode 24 , 26 and 28 remote from the substrate and project beyond the electrode 24 , 26 and 28 remote from the substrate in the longitudinal direction on both sides, so that terminal regions for vertically running contacts 30 are produced at the bottom electrodes 18 , 20 and 22 near the substrate.
  • the main capacitor 12 and the disconnectable capacitors 14 are electrically connected in parallel by interconnects 32 between the bottom electrodes 18 , 20 and by interconnects 34 between the electrodes 24 , 26 remove from the substrate. As seen geometrically, however, the disconnectable capacitors 14 are arranged in a row one behind the other.
  • the interconnects 32 and 34 are situated in an upper metallization layer.
  • the connectable capacitors 16 can be electrically connected in parallel with the main capacitor 12 with the aid of interconnects 52 between the bottom electrodes 18 , 22 and interconnects 54 between the electrodes 24 , 28 remote from the substrate. Geometrically, however, the connectable capacitors 16 are arranged in a row. The interconnects 52 and 54 are also situated in an upper metallization layer.
  • Cutouts 56 and 58 lead through an insulating material (not illustrated) as far as linking regions 60 and 62 of the interconnects 52 and 54 , respectively.
  • the linking regions 60 , 62 form so-called antifuses, i.e. a connection possibility which forms a permanent electrically conductive connection between the sections of the interconnect 52 and an interconnect 54 , respectively, upon the impingement of a laser beam.
  • the main capacitor 12 has a length La in the longitudinal direction of the capacitor arrangement 10 , said length being greater than lengths Lb of the disconnectable capacitors 14 and lengths Lc of the connectable capacitors 16 .
  • a capacitance C( 0 ) of the main capacitor 12 is also greater than a capacitance Cm(I) of the capacitor 14 .
  • 1 is a natural number for designating the last disconnectable capacitor 14 .
  • the disconnectable capacitors not illustrated have capacitances Cm( 1 ) to Cm(I ⁇ 1 ) which are equal to the capacitance Cm(I) in the exemplary embodiment explained.
  • the capacitance C( 0 ) of the main capacitor 12 is likewise greater than the capacitance Cp( 1 ) of the connectable capacitor 16 .
  • the connectable capacitors not illustrated in FIG. 1 have capacitances Cp( 2 ) to Cp(N), which are equal to the capacitance Cp( 1 ) or Cm(I). In this case, N is a natural number for designating the last connectable capacitor.
  • the capacitances Cm( 1 ) to Cm(I) of the capacitor arrangement 10 are different from one another.
  • the capacitances Cp( 1 ) to Cp(N) of the capacitor arrangement 10 can also be made different from one another.
  • FIG. 2 shows a plan view of a grid capacitor arrangement 110 , which contains a main capacitor 112 connected to a circuit and a plurality of disconnectable capacitors, one capacitor 114 of which is illustrated in FIG. 2 . Furthermore, the grid capacitor arrangement 110 contains a plurality of connectable capacitors, one capacitor 116 of which is illustrated in FIG. 2 . Only the upper electrode of the main capacitor 112 and of the capacitor 114 and of the capacitor 116 is respectively illustrated in FIG. 2 . In the underlying metallization layers there are further electrodes having the same profile as the upper electrodes. In a first exemplary embodiment, the electrodes of a capacitor 112 , 114 and 116 which are situated in the different metallization layers are connected among one another in each case by at least one vertical content. Interconnects between capacitors 112 , 114 and 116 are situated only in the upper metallization layer.
  • the main capacitor 112 contains two comb-shaped electrodes whose tines mesh with one another.
  • a meandering interspace is thus formed between the transverse electrodes 120 to 126 and 130 to 136 , said interspace being filled by a dielectric.
  • the length of the meander of the main capacitor 112 shall again be La.
  • the disconnectable capacitors and the connectable capacitors are constructed like the main capacitor 112 , but contain shorter longitudinal electrodes 140 , 142 , 144 and 146 , respectively from each of which, by way of example, only two transverse electrodes 150 to 160 branch.
  • a region 162 Situated between the longitudinal electrode 118 and the longitudinal electrode 142 of the capacitor 114 is a region 162 , to which a cutout 164 leads from the surface of the integrated circuit.
  • a region 166 Situated between the longitudinal electrode 128 and the longitudinal electrode 140 of the capacitor 114 is a region 166 , to which a further cutout 168 leads.
  • the cutouts 164 and 168 it is possible, with the aid of a laser beam, to produce an interruption between the longitudinal electrodes 118 and 142 and the longitudinal electrodes 128 and 140 in the region 162 and 166 , respectively.
  • all the disconnectable capacitors 114 can be disconnected from the main capacitor 112 .
  • Situated between the further disconnectable capacitors are further regions 170 and 172 , to which cutouts 174 and 176 lead, so that disconnection can also be effected at other locations.
  • a linking region 180 is situated between the longitudinal electrode 118 and the longitudinal electrode 146 of the correction capacitor 116 .
  • a linking region 182 is situated between the longitudinal electrode 128 and the longitudinal electrode 144 of the capacitor 116 .
  • a cutout 184 and 186 leads to the linking region 140 and to the linking region 182 , respectively.
  • the linking regions 180 and 182 can be locally heated with the aid of a laser beam.
  • a connection is produced between the longitudinal electrode 118 and the longitudinal electrode 146 , and between the longitudinal electrode 128 and the longitudinal electrode 144 .
  • Electrically conductive connections to further connectable capacitors 116 can be produced with the aid of further linking regions 190 , 192 to which cutouts 194 and 196 , respectively, lead.
  • the meander of the main capacitor 112 has a length La, which is greater than a length Lb of a meander of the disconnectable capacitor 114 and a length Lc of a meander of the connectable capacitor 116 .
  • a capacitance (C0) of the main capacitor 112 is greater than a capacitance Cm(I) of the disconnectable capacitor 114 .
  • Further capacitances Cm( 1 ) to Cm(I ⁇ 1) of further disconnectable capacitors are equal to the capacitance Cm(I).
  • a capacitance Cp( 1 ) of the connectable capacitor 116 is equal to the capacitance Cm( 1 ).
  • Capacitances Cp( 2 ) to Cp(N) of the further disconnectable capacitors 116 are equal to the capacitance Cp( 1 ).
  • connection or interruption possibilities which are arranged offset with respect to connection or interruption possibilities situated above or below the latter.
  • linking regions or regions for interruptions are arranged in an upper metallization layer even though they also relate to electrodes in lower metallization layers.
  • the capacitances Cm( 1 ) to Cm(I) or Cp( 1 ) to Cp(N) of the capacitor arrangement 110 may have capacitances that differ from one another.
  • FIG. 3 shows a transverse electrode 200 of a grid capacitor.
  • the transverse electrode 200 has a region 202 over approximately one third of its length and a region 204 over approximately two thirds of its length.
  • a cutout 206 leads to the region 202 .
  • a cutout 208 leads to the region 204 .
  • an interruption is produced in the region 202 or an interruption is produced in the region 204 . If the interruption is produced in the region 202 , then only approximately one third of the transverse electrode 200 is circuitry-effective. By contrast, if an interruption is produced in the region 204 , then approximately two thirds of the transverse electrode 200 are circuitry-effective.
  • the length of the transverse electrode 200 is 10 micrometers, for example.
  • the width is 0.5 micrometer, for example, so that a process of severing using a laser beam is possible without any difficulty.
  • FIG. 4 shows a transverse electrode 220 , to which a cutout 222 leads.
  • the cutout 222 extends approximately over the entire length of the transverse electrode 220 .
  • the interruption points can be placed continuously along the longitudinal axis of the transverse electrode 220 .
  • linking regions are used instead of, or in combination with, the regions serving for interruption.
  • the interruption regions and/or the linking regions are arranged either on one transverse electrode of a grid capacitor or on a plurality of transverse electrodes of the grid capacitor.
  • FIG. 5 shows method steps for correcting the capacitance of an integrated capacitor arrangement, e.g. according to FIG. 1 , 2 , 3 or 4 .
  • the variation of the capacitance of the integrated circuit arrangement around a desired capacitance is determined, for example empirically or on the basis of simulation runs, see method step 300 .
  • Correction possibilities are provided depending on the capacitance variations, see method step 302 .
  • the correction possibilities are, for example, disconnectable capacitors, connectable capacitors, disconnectable capacitor regions and/or connectable capacitor regions.
  • the correction possibilities are prescribed in method step 302 taking account of the expected capacitance variation such that, with regard to the overall production, the fewest possible interruptions and links have to be produced by heating using the laser beam.
  • the actual correction method begins in a method step 304 , which is followed by the processing of a wafer, see method step 306 .
  • transistors are produced in a semiconductor material of the wafer.
  • metallization layers are applied, capacitors also being produced.
  • a measurement is used to detect the actual capacitance of an integrated capacitor arrangement, i.e. in particular the capacitance of the main capacitor 12 , 112 together with the capacitances of the disconnectable capacitors 14 , 114 .
  • a subsequent method step 310 the actual capacitance is compared with the desired capacitance. If the actual capacitance is less than or greater than the desired capacitance, in particular less than or greater than a predetermined tolerance range, then method step 310 is directly followed by a method step 312 .
  • method step 312 a check is made to determine whether the actual capacitance is greater than the desired capacitance. If this is the case, then method step 312 is followed by a method step 314 , in which interruptions are produced in the integrated capacitor arrangement with the aid of a laser beam, disconnectable capacitors 14 , 114 being disconnected from the main capacitor 12 , 112 . The capacitance of the capacitor arrangement decreases. A disconnection of an electrode section from a transverse electrode is also carried out as an alternative.
  • method step 312 is directly followed by a method step 316 .
  • method step 316 linking regions are heated with the aid of a laser beam.
  • connectable capacitors 16 , 116 are supplementarily connected to the main capacitor 12 , 112 or to a main region.
  • the capacitance of the capacitor arrangement thus increases in the direction of the desired capacitance.
  • a connection of electrode sections of a transverse electrode is also carried out as an alternative.
  • Method step 318 follows directly afterward. Method step 318 is also executed after method step 314 or method step 316 . The wafer is processed further in method step 318 . In this case, inter alia, a passivation layer is applied, which closes off the cutouts for the laser beam.
  • the circuits arranged on the wafer are singulated and encapsulated in housings.
  • the method is ended in a method step 322 .
  • the correction is carried out after the singulation of the circuits.
  • current surges are used to heat the interruption regions or the linking regions.
  • the interrogations in method steps 310 and 312 can also be formulated differently.
  • the index i in the summation over the capacitances Cm must take account of all the disconnected capacitors, where I 1 designates the last disconnected capacitor.
  • the index in the summation over the capacitances Cp must take account of all the connected capacitances, where N 1 designates the last connected capacitor. Furthermore, it must be taken into consideration that either capacitors are connected or disconnected.
  • C ⁇ 0 ⁇ r ⁇ Ae ⁇ /De ⁇ .
  • ⁇ 0, ⁇ r represent the corresponding dielectric constants
  • Aeff represents the effective electrode area
  • Deff represents the effective distance between electrodes.
  • the effective electrode area corresponds, in the case of:
  • the effective distance between electrodes corresponds, in the case of:
  • the MIM capacitors to the thickness of the dielectric, which differs from the dielectric between the metallization layers,
  • the grid capacitors to the thickness of the intrametal dielectric, i.e. the so-called spacing.
  • the fluctuations in the capacitances may have the following process-dictated causes:
  • MIM capacitors fluctuations in the thickness of the MIM dielectric, e.g. due to inhomogeneous deposition rates over the wafer, or different roughness of the lower electrode.
  • Sandwich capacitors fluctuations in the thickness of the intermetal dielectric, e.g. thickness fluctuations due to polishing inhomogeneities or fluctuations in the etching depth over the wafer.
  • Grid capacitors fluctuations in the distance between electrodes due to variation of the thickness of the intrametal dielectric caused e.g. by lithography fluctuations, RIE patterning (Reactive Ion Etching) with the use of aluminum or by trench etching with the use of copper. Further causes are fluctuations in the electrode area due to variation of the interconnect thickness or due to CMP fluctuations (Chemical Mechanical Polishing), so-called dishing, non-right-angled trench profile with the use of copper or due to inhomogeneous deposition rates.
  • CMP fluctuations Chemical Mechanical Polishing
  • a 0 is the electrode basic area that can no longer be corrected
  • M is a natural number
  • Ai is the disconnectable or connectable discrete area elements.
  • the minus sign applies to the disconnectable area elements.
  • the plus sign applies to the connectable area elements.
  • M denotes a natural number
  • Li denotes the disconnectable or connectable discrete interconnect segments.
  • the minus sign applies to the disconnectable interconnect segments.
  • the plus sign applies to the connectable interconnect segments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)
US12/175,170 2002-07-08 2003-06-12 Set of integrated capacitor arrangements, especially integrated grid capacitors Expired - Lifetime USRE41684E1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10230697 2002-07-08
DE10230697 2002-07-08
PCT/DE2003/001956 WO2004006334A2 (de) 2002-07-08 2003-06-12 Satz integrierter kondensatoranordnungen, insbesondere integrierter gitterkondensatoren

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/520,742 Reissue US7079375B2 (en) 2002-07-08 2003-06-12 Set of integrated capacitor arrangements, especially integrated grid capacitors

Publications (1)

Publication Number Publication Date
USRE41684E1 true USRE41684E1 (en) 2010-09-14

Family

ID=30009837

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/175,170 Expired - Lifetime USRE41684E1 (en) 2002-07-08 2003-06-12 Set of integrated capacitor arrangements, especially integrated grid capacitors
US10/520,742 Ceased US7079375B2 (en) 2002-07-08 2003-06-12 Set of integrated capacitor arrangements, especially integrated grid capacitors

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/520,742 Ceased US7079375B2 (en) 2002-07-08 2003-06-12 Set of integrated capacitor arrangements, especially integrated grid capacitors

Country Status (7)

Country Link
US (2) USRE41684E1 (ja)
EP (2) EP1520299B1 (ja)
JP (1) JP4409428B2 (ja)
CN (1) CN100413074C (ja)
DE (2) DE50311201D1 (ja)
TW (1) TWI226125B (ja)
WO (1) WO2004006334A2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090179301A1 (en) * 2008-01-16 2009-07-16 Hynix Semiconductor Inc. Fuse having cutting regions and fuse set structure having the same
US11257750B2 (en) 2020-02-06 2022-02-22 International Business Machines Corporation E-fuse co-processed with MIM capacitor

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070235880A1 (en) * 2006-03-30 2007-10-11 Chin-Sheng Yang Semiconductor device and method of fabricating the same
US20090014832A1 (en) * 2007-07-09 2009-01-15 Peter Baumgartner Semiconductor Device with Reduced Capacitance Tolerance Value
JP2016162925A (ja) * 2015-03-03 2016-09-05 力晶科技股▲ふん▼有限公司 Ｍｏｍキャパシタ回路及び半導体装置
FR3053156B1 (fr) * 2016-06-28 2018-11-16 Stmicroelectronics (Rousset) Sas Composant a faible dispersion dans une puce electronique
US11145591B2 (en) * 2019-11-18 2021-10-12 International Business Machines Corporation Integrated circuit (IC) device integral capacitor and anti-fuse

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766308A (en) 1972-05-25 1973-10-16 Microsystems Int Ltd Joining conductive elements on microelectronic devices
US4152714A (en) * 1978-01-16 1979-05-01 Honeywell Inc. Semiconductor apparatus
US4190854A (en) * 1978-02-15 1980-02-26 National Semiconductor Corporation Trim structure for integrated capacitors
DE3124740A1 (de) * 1980-08-14 1982-04-08 VEB Elektronik Gera, DDR 6500 Gera Verfahren zum abgleichen der kapazitaet elektrischer kondensatoren
JPS60121757A (ja) * 1983-12-06 1985-06-29 Nec Corp 半導体集積回路装置
JPS62155536A (ja) 1985-12-27 1987-07-10 Casio Comput Co Ltd トリミング機能付半導体集積回路
JPH097887A (ja) 1995-06-16 1997-01-10 Chichibu Onoda Cement Corp コンデンサ
US5659182A (en) 1994-03-18 1997-08-19 Massachusetts Institute Of Technology Three-terminal fuse
DE19652325C1 (de) * 1996-12-16 1998-05-07 Siemens Ag Integrierte Halbleiterschaltung mit Kapazitäts-Redundanz
JPH10303061A (ja) * 1997-04-25 1998-11-13 Matsushita Electric Ind Co Ltd 加熱導電性絶縁材料およびその加熱方法
JP2000323664A (ja) 1999-05-13 2000-11-24 Nec Corp 半導体装置
US6198619B1 (en) 1998-04-24 2001-03-06 Mitsubishi Denki Kabushiki Kaisha Capacitor network
EP1111694A2 (de) 1999-12-21 2001-06-27 Philips Corporate Intellectual Property GmbH Bauteil mit Dünnschichtschaltkreis mit trimmbaren Kondensator
JP2001308280A (ja) * 2000-03-14 2001-11-02 Internatl Business Mach Corp <Ibm> 精密回路素子の構造及びその形成方法
WO2001093283A1 (en) * 2000-06-02 2001-12-06 Koninklijke Philips Electronics N.V. Passive component
JP2003323664A (ja) * 2002-05-01 2003-11-14 Nec Soft Ltd カード決済システム
US20040151024A1 (en) * 2003-02-05 2004-08-05 Peter Fricke Memory array
US6858916B2 (en) * 2002-04-18 2005-02-22 Nec Electronics Corporation Semiconductor memory device with series-connected antifuse-components

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198609B1 (en) 1998-11-09 2001-03-06 Read-Rite Corporation CPP Magnetoresistive device with reduced edge effect and method for making same

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766308A (en) 1972-05-25 1973-10-16 Microsystems Int Ltd Joining conductive elements on microelectronic devices
US4152714A (en) * 1978-01-16 1979-05-01 Honeywell Inc. Semiconductor apparatus
US4190854A (en) * 1978-02-15 1980-02-26 National Semiconductor Corporation Trim structure for integrated capacitors
DE3124740A1 (de) * 1980-08-14 1982-04-08 VEB Elektronik Gera, DDR 6500 Gera Verfahren zum abgleichen der kapazitaet elektrischer kondensatoren
JPS60121757A (ja) * 1983-12-06 1985-06-29 Nec Corp 半導体集積回路装置
JPS62155536A (ja) 1985-12-27 1987-07-10 Casio Comput Co Ltd トリミング機能付半導体集積回路
US5659182A (en) 1994-03-18 1997-08-19 Massachusetts Institute Of Technology Three-terminal fuse
JPH097887A (ja) 1995-06-16 1997-01-10 Chichibu Onoda Cement Corp コンデンサ
DE19652325C1 (de) * 1996-12-16 1998-05-07 Siemens Ag Integrierte Halbleiterschaltung mit Kapazitäts-Redundanz
JPH10303061A (ja) * 1997-04-25 1998-11-13 Matsushita Electric Ind Co Ltd 加熱導電性絶縁材料およびその加熱方法
US6198619B1 (en) 1998-04-24 2001-03-06 Mitsubishi Denki Kabushiki Kaisha Capacitor network
JP2000323664A (ja) 1999-05-13 2000-11-24 Nec Corp 半導体装置
US6417557B1 (en) 1999-05-13 2002-07-09 Nec Corporation Semiconductor device having a capacitance adjustment section
EP1111694A2 (de) 1999-12-21 2001-06-27 Philips Corporate Intellectual Property GmbH Bauteil mit Dünnschichtschaltkreis mit trimmbaren Kondensator
JP2001308280A (ja) * 2000-03-14 2001-11-02 Internatl Business Mach Corp <Ibm> 精密回路素子の構造及びその形成方法
WO2001093283A1 (en) * 2000-06-02 2001-12-06 Koninklijke Philips Electronics N.V. Passive component
US6858916B2 (en) * 2002-04-18 2005-02-22 Nec Electronics Corporation Semiconductor memory device with series-connected antifuse-components
JP2003323664A (ja) * 2002-05-01 2003-11-14 Nec Soft Ltd カード決済システム
US20040151024A1 (en) * 2003-02-05 2004-08-05 Peter Fricke Memory array

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
European search report and opinion for related Application No. EP 05 10 669, mailed Apr. 4, 2007.
International Search Report from PCT patent application No. PCT/DE03/01956. *
Japanese Patent Office communication for related Application No. 2004-518391, mailed Feb. 19, 2007.
Preliminary Examnation Report from PCT patent application No. PCT/DE03/01956. *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090179301A1 (en) * 2008-01-16 2009-07-16 Hynix Semiconductor Inc. Fuse having cutting regions and fuse set structure having the same
US11257750B2 (en) 2020-02-06 2022-02-22 International Business Machines Corporation E-fuse co-processed with MIM capacitor

Also Published As

Publication number Publication date
US7079375B2 (en) 2006-07-18
US20060097580A1 (en) 2006-05-11
EP1587145A2 (de) 2005-10-19
EP1520299B1 (de) 2006-10-25
DE50311201D1 (de) 2009-04-02
EP1587145A3 (de) 2007-05-16
CN1666343A (zh) 2005-09-07
EP1520299A2 (de) 2005-04-06
WO2004006334A2 (de) 2004-01-15
JP4409428B2 (ja) 2010-02-03
WO2004006334A3 (de) 2004-04-08
TW200401431A (en) 2004-01-16
TWI226125B (en) 2005-01-01
CN100413074C (zh) 2008-08-20
JP2005538533A (ja) 2005-12-15
DE50305508D1 (de) 2006-12-07
EP1587145B1 (de) 2009-02-18

Similar Documents

Publication Publication Date Title
US9647057B2 (en) Capacitor 3D-cell and 3D-capacitor structure
US8790989B2 (en) Modularized three-dimensional capacitor array
EP1351304B1 (en) Integrated circuit capacitors
US7288804B2 (en) Electrically programmable π-shaped fuse structures and methods of fabrication thereof
US6437385B1 (en) Integrated circuit capacitor
US8455979B2 (en) Three dimensional integrated deep trench decoupling capacitors
US9583557B2 (en) Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime
US20220122910A1 (en) Low-dispersion component in an electronic chip
USRE41684E1 (en) Set of integrated capacitor arrangements, especially integrated grid capacitors
US6680520B2 (en) Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses
US7784009B2 (en) Electrically programmable π-shaped fuse structures and design process therefore
US6815264B2 (en) Antifuses
CN105575945A (zh) 一种mom电容及其制作方法
US4315239A (en) Process for producing a calibrated resistance element and integrated circuitry incorporating same
US11830870B2 (en) ESD protection device and manufacturing method thereof
US11664466B2 (en) Semiconductor device, power module and method for manufacturing the semiconductor device
US20220115321A1 (en) Fuse structure and formation method
US20230299158A1 (en) Electrostatic discharge protection device
TW202341406A (zh) 靜電放電保護結構
CN104103623A (zh) 电熔丝结构及其形成方法
CN114446898A (zh) 半导体装置

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553)

Year of fee payment: 12