US8836301B2 - Power supply unit - Google Patents

Power supply unit Download PDF

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US8836301B2
US8836301B2 US13/459,916 US201213459916A US8836301B2 US 8836301 B2 US8836301 B2 US 8836301B2 US 201213459916 A US201213459916 A US 201213459916A US 8836301 B2 US8836301 B2 US 8836301B2
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power supply
sub
switching element
voltage
output terminal
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US20120326681A1 (en
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Ken Shono
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Transphorm Japan Inc
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Transphorm Japan Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel

Definitions

  • the present invention relates to a power supply unit.
  • a power supply unit generates a desired potential of output voltage by boosting or dropping the power supply voltage.
  • the power supply unit is therefore a voltage converter which converts the power supply voltage supplied from the outside into desired voltage.
  • a switching element coupled to the power supply voltage performs the ON/OFF switching operation according to the potential of the output voltage, and generates output voltage having a desired potential for an output terminal by intermittently outputting current to the output terminal.
  • An inductor is disposed between the switching element and the output terminal, and current smoothed by the inductor is output to the output terminal.
  • a load circuit is coupled to the output terminal, and voltage having a desired potential is output to the load circuit. The potential of the output voltage fluctuates according to the power consumption of the load circuit, and the voltage converter performs the switching operation so as to minimize the fluctuation (ripple).
  • a switching element is disposed between inductor coupled to the power supply voltage and a reference potential, such as a ground, and current is intermittently supplied to the inductor by the ON/OFF switching operation of the switching element, the current is output to the output terminal by electromagnetic energy stored in the inductor, and output voltage having a desired potential, which has been boosted to be higher than the power supply voltage, is generated for the output terminal.
  • a load circuit is coupled to the output terminal, and voltage having a desired potential is supplied to the load circuit. The potential of the output voltage fluctuates according to the power consumption of the load circuit, and the voltage converter performs the switching operation so as to minimize the fluctuation.
  • the voltage converter has an inductor for smoothing the output current, as mentioned above, and a capacitor for smoothing the output voltage is coupled to the output terminal.
  • a standard voltage converter is a DC-DC converter which converts a DC voltage into another DC voltage.
  • the inductor and the capacitor are large and expensive, and are normally externally coupled to a power supply chip integrating a switching element and a control circuit for controlling the switching element.
  • the inductance of the inductor and the capacitance of the capacitor must be large, and for this reason the external dimensions of the conductor and the capacitor are large.
  • the inductance of the inductor and the capacitance of the capacitor may be decreased by increasing the switching frequency.
  • a power MOSFET which operates at high-speed, is necessary for the switching element, and the chip size of such a power MOSFET is large.
  • a multiphase type voltage converter where a voltage converter is constituted by a plurality (N) of sub-voltage converters, and these sub-voltage converters perform the switching operation in N phase.
  • the frequency of each sub-voltage converter may be decreased, and the requirements for the power MOSFET, the inductor and the capacitor may be relaxed. In other words, the size of the power MOSFET may be decreased by decreasing the frequency.
  • the voltage converter has a plurality (N) of sub-voltage converters, the overall inductance is set to a demanded value even if the inductance of the inductor of each sub-voltage converter is decreased to 1/N.
  • the following non-patent documents all disclose a multiphase type voltage converter.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-260992
  • Non-Patent Document 1 “A DLL Based Multiphase Hysteretic DC-DC Converter”, P. Li, ISQED, 2007, pp. 98
  • Non-Patent Document 2 “A Hysteretic Control Method for Multiphase Voltage Regulator”, K. Lee, IEEE Power Electronics, vol. 24, No. 12, (2009), pp. 2726
  • Non-Patent Document 3 “A Multiphase DC/DC Converter with Hysteretic Voltage Control and Current Sharing”, W. Gu, APEC, 2002, pp. 670
  • Non-Patent Document 4 “A 480-MHz Multi-Phase Interleaved Buck DC-DC Converter with Hysteretic Control”, G. Schrom, IEEE 35 th Power Electronics Specialist Conf., (2004), pp. 4702
  • Non-Patent Document 5 Multiphase Voltage-Mode Hysteretic Controlled VRM with DSP Control and Novel Current Sharing”, J. A. Abu-Qahouq, APEC, 2002, pp. 663
  • Non-Patent Document 6 “New Digital Control Architecture Eliminating the Need for High Resolution DPWM”, J. Li, PESC, 2007, pp. 814
  • the multiphase type voltage converter however, must control the switching of the plurality of sub-voltage converters in N phases, and perform complicated pulse width modulation (PWM) and pulse frequency modulation (PFM), hence the control circuit for controlling the switching becomes complicated and large in terms of circuit scale.
  • PWM pulse width modulation
  • PFM pulse frequency modulation
  • a large scale control circuit of each sub-voltage converter causes the overall circuit scale to increase.
  • a power supply unit includes: a first sub-power supply module, comprising a first inductor, a first switching element which switches current supplied from an input power supply to the first inductor, a first drive control circuit which drives the first switching element, and a first sub-output terminal to which current is output from the first inductor; a second sub-power supply module, comprising a second inductor, a second switching element which switches current supplied from an input power supply to the second inductor, a second drive control circuit which drives the second switching element, and a second sub-output terminal to which current is output from the second inductor; and a common output terminal to which the first sub-output terminal and the second sub-output terminal are coupled, wherein an ON operation of the first switching element is controlled depending on whether or not an output voltage of the common output terminal is lower than a first voltage, and an ON operation of the second switching element is controlled depending on whether or not the output voltage is lower than a second voltage, which is different from the first voltage.
  • FIG. 1 is a block diagram depicting a power supply unit according to a first embodiment.
  • FIG. 2 is a circuit diagram of a sub-power supply module of the step-down type power supply unit in FIG. 1 .
  • FIG. 3 illustrates a variant form of the sub-power supply module in FIG. 2 .
  • FIG. 4 is a diagram depicting the waveforms of 0th step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 5 is a diagram depicting the waveforms of 1st step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 6 is a diagram depicting the waveforms of 2nd step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 7 is a diagram depicting the waveforms of 3rd step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 8 is a diagram depicting the waveforms of 4th step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 9 is a diagram depicting the waveforms of 5th step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 10 is a diagram depicting the waveforms of 6th step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 11 is a diagram depicting the waveforms of 7th step sub-power supply module of a power supply unit, which has an eight-step sub-power supply module.
  • FIG. 12 is a diagram depicting the waveforms of a feedback voltage Vfb with respect to seven reference voltages, Vref_ 0 to Vref_n ⁇ 1, of the power supply unit.
  • FIG. 13 depicts the ripple current which flows into the output terminal in the example of the eight-step sub-power supply module.
  • FIG. 14 is a waveform diagram of the connection nodes Lx of the eight-step sub-power supply module and the output voltages Vout when the load of the load circuit is at the intermediate level.
  • FIG. 15 is a waveform diagram of the connection nodes Lx of the eight-step sub-power supply module and the output voltages Vout when the load of the load circuit is heavy.
  • FIG. 16 is a waveform diagram when the difference of the reference voltage Vref in each step is not equal.
  • FIG. 17 is a diagram depicting a variant form of FIG. 1 .
  • FIG. 18 is a block diagram depicting a step-up type power supply unit according to a second embodiment.
  • FIG. 19 is a circuit diagram of a sub-power supply module of the step-up type power supply unit in FIG. 18 .
  • FIG. 20 is a circuit diagram of a sub-power supply module of a step-down type power supply unit circuit according to the third embodiment.
  • FIG. 21 is a plan view and cross-sectional views of an integrated circuit device having the power supply unit circuit in FIG. 20 .
  • FIG. 22 is a circuit diagram of a sub-power supply module of a step-up type power supply unit circuit according to the third embodiment.
  • FIG. 1 is a block diagram depicting a power supply unit according to a first embodiment.
  • the first embodiment is an example of a step-down type power supply unit.
  • sub-output terminals 0 _ 0 to 0 _n ⁇ 1, of n number of sub-power supply modulating in the 0th step to the (n ⁇ 1)th step are coupled, and generates a desired output voltage to a common output terminal Vout.
  • Each sub-power supply module has an output inductor Lout, a module circuit M_ 0 to M_n ⁇ 1 having a switching element coupled to an input power supply (not illustrated), and a drive circuit AND_ 0 to AND_n ⁇ 1 for driving the switching element.
  • this drive circuit has an AND gate, and a pulse signal from a pulse generation circuit PG_ 0 to PG_n ⁇ 1 and a comparison signal from a comparator CMP_ 0 to CMP_n ⁇ 1 are input to this AND gate.
  • the pulse generation circuit PG_ 0 to PG_n ⁇ 1 generates pulse signals of which phases are preferably shifted from each other. In the case of the example in FIG. 1 , there are n number of sub-power supply modules, and the pulse signals generated by the pulse generation circuits have N phases, and as mentioned later, these pulses may overlap with each other.
  • a smoothing capacitor Cout is coupled to the common output terminal Vout, and a load circuit RL which supplies the generated power is also coupled.
  • the comparator CMP_ 0 to CMP_n ⁇ 1 which corresponds to each sub-power supply module compares feedback voltage Vfb, which is generated by dividing the output voltage of the common output terminal Vout by resistors R 1 and R 2 between the common output terminal Vout and the ground voltage VSS, and reference voltages Vref_ 0 to Vref_n ⁇ 1 that are different from each other, and outputs the comparison result to the drive circuit AND_ 0 to AND_n ⁇ 1 respectively as a comparison result signal. If the feedback voltage Vfb is lower than the reference voltage, the comparison result signal becomes H level, and if the pulse signal generated by the pulse generation circuit is H level, the drive circuit controls the switching element in the modulate circuit M_ 0 to M_n ⁇ 1 to the ON state respectively. Current according to the duration of the ON state is output to the output terminal O_ 0 to O_n ⁇ 1 of each sub-power supply modulate respectively.
  • the comparator, the pulse generation circuit and the drive circuit constitute a drive control circuit for controlling the driving of the switching element.
  • FIG. 2 is a circuit diagram of a sub-power supply module of the step-down type power supply unit in FIG. 1 .
  • the sub-power supply module in the (n ⁇ 1)th step has a module circuit M_n ⁇ 1 including an inductor Lout, a switching element M 1 constituted by an N-channel MOS (NMOS) transistor disposed between the power supply Vcc 2 and the inductor Lout, and a Schottky Barrier Diode SBD disposed between the ground Vss and the inductor Lout.
  • the switching element M 1 and the inductor Lout are coupled via a connection node Lx_n ⁇ 1.
  • the sub-power supply module in the (n ⁇ 1)th step also has an AND gate (drive circuit) for supplying a drive pulse to the gate of the switching element Mi, a comparator CMP_n ⁇ 1 and the pulse generation circuit PG_n ⁇ 1.
  • the AND gate, the comparator CMP_n ⁇ 1, and the pulse generation circuit PG_n ⁇ 1 constitute a drive control circuit CNT_n ⁇ 1 for driving the switching element M 1 .
  • the comparator CMP_n ⁇ 1 compares the feedback voltage Vfb generated from the output voltage Vout and the (n ⁇ 1)th reference voltage Vref_n ⁇ 1, and sets the output C_out to H level if the feedback voltage Vfb is lower than the reference voltage Vref_n ⁇ 1, and sets the output C_out to L level if the feedback voltage Vfb is higher than the reference voltage Vref_n ⁇ 1.
  • the pulse generation circuit PG_n ⁇ 1 outputs a pulse signal P_n ⁇ 1 having the (n ⁇ 1)th phase, out of the pulse signals having the 0 th phase to the (n ⁇ 1)th phase generated by the n number of sub-power supply modules.
  • the AND gate passes the comparison result signal C_n ⁇ 1 of the comparator CMP_n ⁇ 1, and supplies the drive pulse D_n ⁇ 1 to the gate of the switching element M 1 to turn the switching element M 1 ON/OFF.
  • the switching element M 1 When the pulse signal P_n ⁇ 1 is in the H level period, the switching element M 1 turns ON, supplies current from the power supply Vcc 2 to the inductor Lout, and stores the electromagnetic energy in the inductor Lout if the potential of the output voltage of the common output terminal Vout is lower than the potential corresponding to the reference voltage Vref_n ⁇ 1. If the potential of the output voltage of the common output terminal Vout is higher than the potential corresponding to the reference voltage Vref_n ⁇ 1 when the pulse signal P_n ⁇ 1 is in the H level period, on the other hand, the switching element M 1 turns OFF.
  • the switching element M 1 turns OFF, current flows from the ground Vss to the inductor Lout and the output terminal O_n ⁇ 1 via the Schottky Barrier Diode SBD.
  • the inductor Lout smoothes current that is intermittently supplied from the power supply Vcc 2 by the ON/OFF operation of the switching element M 1 , and outputs the smoothed current to the output terminal O_n ⁇ 1.
  • the switching element M 1 is not ON/OFF-controlled, but remains OFF.
  • the sub-power supply module in the (n ⁇ 2)th step has a configuration similar to the (n ⁇ 1)th step.
  • the pulse generation circuit PG_n ⁇ 2 generates a pulse signal P_n ⁇ 2, which is 1/n cycle-phase-shifted from the pulse signal P_n ⁇ 1 generated by the pulse generation circuit in the (n ⁇ 1)th step.
  • the duty ratio of the pulse signal is the same.
  • the switching element M 1 turns ON/OFF by the comparison result signal C_n ⁇ 2, which becomes H level if the feedback voltage Vfb is lower than the reference voltage Vref_n ⁇ 2, and becomes L level if the feedback voltage Vfb is higher than the reference voltage Vref_n ⁇ 2.
  • the switching element module M 1 of the sub-power supply module in the (n ⁇ 2)th step is controlled to be ON or OFF based on the potential of the output voltage Vout which is lower than the sub-power supply module in the (n ⁇ 1)th step, whereas the switching element M 1 of the sub-power supply module in the (n ⁇ 1)th step is controlled to be ON or OFF based on the potential of the output voltage Vout, which is higher than the sub-power supply module in the (n ⁇ 2)th step.
  • both switching elements M 1 in the (n ⁇ 2)th step and the (n ⁇ 1)th step turn ON, and if the feedback voltage Vfb is Vref_n ⁇ 2 ⁇ Vfb ⁇ Vref_n ⁇ 1, then only the switching element M 1 in the (n ⁇ 1)th step turns ON, and if the feedback voltage Vfb is higher than the reference voltage Vref_n ⁇ 1 (Vref_n ⁇ 1 ⁇ Vfb), then the switching element M 1 in the (n ⁇ 1)th step as well as the switching element M 1 in the (n ⁇ 2)th step turn OFF.
  • the sub-power supply modules in the (n ⁇ 3)th step to the 0 th step also have a similar configuration as the sub-power supply modules in the (n ⁇ 1)th step and the (n ⁇ 2)th step.
  • the power supply unit of this embodiment has n steps of sub-power supply modules, and the switching element M 1 of the sub-power supply module in each step turns ON or OFF when the pulse signal generated by the respective pulse generation circuit is in the H level period, depending on whether the feedback voltage Vfb is lower or not than the respective reference voltage Vref. Since the switching element M 1 turns ON or OFF by a pulse signal based on the comparison result of the comparator CMP, the output voltage Vout pulsates vertically from the reference voltage group Vref_ 0 to Vref_n ⁇ 1.
  • the state where the switching elements M 1 are ON in all of the n steps of the sub-power supply modules changes such that the switching elements M 1 are sequentially turned OFF from the 0 th step side, and the number of switching elements M 1 which are ON decreases.
  • the state where the switching elements M 1 are OFF in all the n steps of the sub-power supply modules changes such that the switching elements M 1 are sequentially turned ON from the (n ⁇ 1)th step side, and the number of switching elements M 1 which are ON increases. Since the potential of the output voltage Vout at which the switching element M 1 turns ON is different in each step, the ON period is different, and the ON duty thereof is also different depending on the step.
  • the switching element of the sub-power supply module in each step turns ON or OFF based on a different reference voltage Vref, therefore the pulsation of the output voltage Vout is small and the ripple thereof is also small, compared with the case of the switching elements of all the sub-power supply modules turning ON or OFF based on the same reference voltage Vref.
  • the switching elements M 1 in all the sub-power supply modules turn ON or OFF at the same time, hence the total amount of current which is supplied to the inductor Lout is high, and the ripple of the output voltage Vout becomes very high.
  • the output voltage Vout is stepped up by turning many switching elements M 1 ON and supplying current to the inductors
  • FIG. 3 illustrates a variant form of the sub-power supply module in FIG. 2 .
  • each of the module circuits M_n ⁇ 1 and M_n ⁇ 2 has a first switching element M 1 and a second switching element M 2 .
  • the second switching element M 2 is disposed instead of the Schottky Barrier Diode SBD in FIG. 2 .
  • These switching elements M 1 and M 2 are both NMOS transistors, hence the output signal of the AND gate is directly supplied as a drive pulse to the first switching element Ml, and to the second switching element M 2 via the inverter INV.
  • the rest of the configuration is the same as FIG. 2 .
  • the first switching element M 1 may be constituted by a PMOS transistor and the second switching element M 2 may be constituted by an NMOS transistor. In this case, the same drive pulse is supplied to both of these transistors.
  • the step-down type power supply unit in FIG. 1 has n number of sub-power supply modules, therefore the inductance of the inductor Lout of each sub-power supply module is 1/n compared with the case of using a single power supply module.
  • the inductance of the inductor Lout of each sub-power supply module is smaller, 1/n, and the size of the inductor Lout is also smaller, 1/n, accordingly.
  • the inductor becomes smaller, the inductor operates at a higher frequency.
  • the threshold frequency becomes higher as the inductance becomes smaller.
  • the frequency at each sub-power supply module also becomes lower, hence the size of the power MOSFET constituting the switching element M 1 may be decreased accordingly. If the size is decreased, the gate-source capacity decreases, and operation at a higher frequency becomes possible.
  • the overall size may be decreased even if the number of elements increases, compared with a single power supply module. Furthermore if inductance is small, the response speed with respect to the output voltage may be increased.
  • the drive control circuit for controlling the switching element M 1 is comprised of the pulse generation circuit PG, the comparator CMP and the AND gate, and is not so complicated as a conventional PWM control circuit, therefore the overall circuit scale does not become large, even if the multi-power supply module configuration is used.
  • the plurality of sub-power supply modules illustrated in FIG. 1 , FIG. 2 and FIG. 3 are formed within a single semiconductor chip.
  • the inductance of the inductor Lout of each sub-power supply module is small, hence it is preferable that the plurality of the sub-power supply modules, including these inductors, are formed on a single semiconductor chip.
  • the inductor Lout of each sub-power supply module may be coupled as an external component, and the sub-power supply modules, other than the inductors Lout, may be formed on a single semiconductor chip.
  • the capacitance of the smoothing capacitor Cout coupled to the common output terminal Vout may be decreased since the ripple of the output voltage is smaller. Therefore the smoothing capacitor Cout may be formed on a same semiconductor chip of the plurality of sub-power supply modules, or may be coupled as an external component.
  • FIG. 4 to FIG. 11 are diagrams depicting the waveforms of each sub-power supply module of a power supply unit, which has an eight-step sub-power supply module. Operation waveforms from power ON at time 0 ⁇ s until operation becomes relatively stable are depicted.
  • FIG. 12 is a diagram depicting the waveforms of a feedback voltage Vfb with respect to seven reference voltages, Vref_ 0 to Vref_n ⁇ 1, of the power supply unit.
  • the waveforms in FIG. 12 are the waveforms from time 14 ⁇ s to 32 ⁇ s in FIG. 4 to FIG. 11 .
  • the feedback voltage Vfb is pulsated vertically up and down from the reference voltage group.
  • each drive pulse D_ 0 to D_n ⁇ 1 to be supplied to the gate of the switching element M 1 is generated corresponding to the comparison result signal C of the comparator CMP.
  • the switching element M 1 turns ON when each drive pulse D_ 0 to D_n ⁇ 1 is in the H level, and turns OFF when each drive pulse D_ 0 to D_n ⁇ 1 is in the L level, and corresponding to the ON or OFF operation, the potential of each connection node Lx_ 0 to Lx_n ⁇ 1 between the switching element M 1 and the inductor Lout moves vertically between the power supply voltage Vcc 2 and the negative voltage.
  • the feedback voltage Vfb pulsates vertically, as depicted in the enlarged diagram in FIG. 12 .
  • the pulse generation circuit PG_ 0 sets the pulse P_ 0 to H level first. Therefore the drive pulse D_ 0 of the output of the AND gate becomes H level, the switching element M 1 turns ON, and the connection node Lx_ 0 becomes H level.
  • the comparison result signal C_ 0 of the comparator CMP_ 0 becomes L level
  • the drive pulse D_ 0 also becomes L level
  • the switching element M 1 turns OFF.
  • the connection node Lx_ 0 drops from the ground Vss by the amount of the forward voltage of the Schottky Barrier Diode SBD.
  • the drive pulse D_ 0 When the pulse P_ 0 becomes L level, the drive pulse D_ 0 becomes L level, but in the subsequent period where the pulse P_ 0 is in H level, the feedback voltage Vfb does not become lower than the reference voltage Vref_ 0 because of the rise of the output voltage Vout, and the drive pulse D_ 0 is not generated. In other words, after the switching element M 1 turns ON at the first drive pulse D_ 0 , the sub-power supply module in the 0 th step does not perform the ON/OFF operation.
  • the vertical vibration of the connection node Lx_ 0 is depicted in FIG. 4 .
  • the drive pulse D_ 1 becomes H level, and the switching element M 1 turns ON when the pulse P_ 1 is in the first H level period after the start of the operation at time 0 , and thereafter the drive pulse D_ 1 is not generated.
  • the drive pulse D_ 2 is not generated at all.
  • the sub-power supply module in the second step does not perform the ON/OFF operation at all.
  • the drive pulse D_ 3 is generated only once when the pulse P_ 3 is in the second and later H level periods respectively.
  • the switching element M 1 when the pulse P_ 3 is in the H level period, the switching element M 1 is turned ON once, and supplies current to the output terminal Vout, thereby the output voltage Vout rises every time, the feedback voltage Vfb exceeds the reference voltage Vref_ 3 , and the comparison result signal C_ 3 of the comparator CMP_ 3 does not becomes H level.
  • the drive pulse D_ 4 in the H level is generated twice, three times, twice and twice when the pulse P_ 3 is in the second and later H level periods respectively.
  • the reference voltage Vref_ 4 is higher than the reference voltage Vref_ 3 of the sub-power supply module in the third step, therefore the drive pulse D_ 4 is generated a higher number of times, turns the switching element M 1 ON, and supplies more current to the output terminal O_ 4 .
  • the drive pulse D_ 5 is generated twice, five times, five times and five times when the pulse P_ 3 is in the first and later H level periods respectively.
  • the switching element M 1 turns ON a higher number of times than the sub-power supply module in the fourth step, and more current is supplied to the output terminal O_ 5 .
  • the drive pulse D_ 6 is generated three times, five times, five times and five times when the pulse P_ 3 is in the first and later H level periods respectively.
  • the pulse width of each drive pulse D_ 6 is wider than that of the sub-power supply module in the fifth step.
  • the switching element M 1 turns ON a higher number of times and is on for a longer duration than the sub-power supply module in the fifth step, so that more current is supplied to the output terminal O_ 6 .
  • the drive pulse D_ 7 is generated four times, five times, five times and five times when the pulse P_ 3 is in the first and later H level periods respectively.
  • the pulse width of each drive pulse D_ 7 is higher than that of the sub-power supply module in the sixth step.
  • the switching element M 1 turns ON the highest number of times, and is ON for a longest duration in the seven sub-power supply modules, so that most current is supplied to the output terminal O_ 7 .
  • the feedback voltage Vfb repeats ascending and descending from the reference voltage group Vref_ 0 to Vref_ 7 . Therefore as described in FIG. 4 to FIG. 11 , the number of times, when the drive pulse D_ 0 to D_ 7 is generated in each sub-power supply module is lower and the H level pulse width is shorter as the reference voltage Vref becomes lower, and the number of times when the drive pulse D_ 0 to D_ 7 is generated in each sub-power supply module is higher, and the H level pulse width is wider as the reference voltage Vref becomes higher.
  • the ratio of the ON period of the switching element M 1 (ON duty ratio) is changed by changing the reference voltage Vref depending on the sub-power supply module.
  • FIG. 13 depicts the ripple current which flows into the output terminal in the example of the eight-step sub-power supply module.
  • IL_sub indicates the output current in each sub-power supply module. Since the ON operation of the switching element M 1 of each sub-power supply module is different, the output current of each sub-power supply module is different from each other.
  • the inductance of the inductor Lout is high, such as 160 ⁇ He. Therefore the cycle of ripple of the output current is long.
  • the fluctuation width of each output current is approximately the same as that of a single power supply module, but the inductance of the inductor Lout of each sub-power supply module is 1 ⁇ 8 that of the single power supply module, which is 20 ⁇ He, so the cycle of the ripple of the output current becomes short.
  • the ON/OFF operation periods are shifted by the eight-phase pulses P_ 0 to P_ 7 . Therefore the fluctuation width of the output voltage Vout would be smaller than that of the single power supply module.
  • FIG. 14 is a waveform diagram of the connection nodes Lx of the eight-step sub-power supply module and the output voltages Vout when the load of the load circuit is at the intermediate level. This is an example where load is heavier than the examples in FIG. 4 to FIG. 11 .
  • Vertical fluctuation of the connection node Lx indicates that the switching element M 1 is performing the ON/OFF operation.
  • the connection nodes Lx_ 1 to Lx_ 7 vertically fluctuate in the sub-power supply modules in the first step to seventh step, but the connection node Lx_ 0 of the sub-power supply module in the 0 th step does not fluctuate.
  • FIG. 15 is a waveform diagram of the connection nodes Lx of the eight-step sub-power supply module and the output voltages Vout when the load of the load circuit is heavy. This is an example where load is heavier than the example in FIG. 14 .
  • the connection nodes Lx_ 0 to Lx_ 7 of all the sub-power supply modules vertically fluctuate, and the sub-power supply modules perform ON/OFF operation evenly.
  • the n phases of the pulses P_ 0 to P_n ⁇ 1 in the n steps of the sub-power supply modules need not be shifted accurately by a 1/n cycle respectively.
  • the n number of sub-power supply modules may be divided into k number of groups, and the phase of each group may be shifted by 1/k respectively.
  • the difference of each voltage value need not be precisely the same, but it is sufficient if the difference is approximately the same.
  • FIG. 16 is a waveform diagram when the difference of the reference voltage Vref in each step is not equal. This is an example where the load of the load circuit is heavy, like FIG. 15 . However the vertically fluctuating timing of the connection node Lx is not even, as in the case of FIG. 15 since the eight reference voltage Vrf values are not equally spaced. In this case as well, a similar effect would be obtained since the timings are shifted appropriately.
  • the gate width of the switching transistor M 1 is wider and the current drive capability is higher as the reference voltage Vref of the sub-power supply module is higher, and the gate width of the switching transistor M 1 is narrower and the current drive capability is lower as the reference voltage Vref of the sub-power supply module is lower.
  • the frequency of the switching operation is higher and time thereof is longer as the reference voltage Vref of the sub-power supply module is higher, therefore the current supply capability of this module is increased so as to suppress fluctuation of the output voltage Vout, whereas the output voltage is boosted and the switching operation is stopped even more as the reference voltage Vref of the sub-power supply module is lower, therefore the current supply capability of this module is decreased so as to adjust the output voltage Vout at higher resolution.
  • FIG. 17 is a diagram depicting a variant form of FIG. 1 .
  • each reference voltage Vref_ 0 to Vref_n ⁇ 1 to be input to the comparator CMP_ 0 to CMP_n ⁇ 1 of each sub-power supply module is generated by the resistors dividing the output voltage between the voltage Vref_n ⁇ 1 and the ground Vss.
  • the reference voltage Vref to be input to the comparator CMP_ 0 to CMP_n ⁇ 1 of each sub-power supply module is common, and the feedback voltage Vfb is divided by the resistors.
  • the feedback voltage to be input to the comparator CMP_ 0 to CMP_n ⁇ 1 of each sub-power supply module is Vfb_ 0 to Vfb_n ⁇ 1 in order from the lower voltage side.
  • the ON time is longer as the switching element M 1 becomes closer to the sub-power supply module in the 0 th step, and is shorter as the switching element M 1 becomes close to the sub-power supply module in the (n ⁇ 1)th step, if the output voltage Vout is increasing in both FIG. 1 and FIG. 17 however, the potential of the output voltage Vout, at which each switching element M 1 turns ON or OFF, is different in each of the plurality of the sub-power supply modules respectively.
  • FIG. 18 is a block diagram depicting a step-up type power supply unit according to a second embodiment.
  • the step-up type power supply unit like the step-down type power supply unit, generates an output voltage for a common output terminal Vout by n steps of the sub-power supply modules.
  • Each sub-power supply module has a module circuit M_ 0 to M_n ⁇ 1 having an inductor (not illustrated), a pulse generation circuit PG_ 0 to PG_n ⁇ 1, a comparator CMP_ 0 to CMP_n ⁇ 1, and an AND gate AND_ 0 to AND_n ⁇ 1 which outputs AND of the outputs of the pulse generation circuit and the comparator as a drive pulse.
  • the comparator CMP_ 0 to CMP_n ⁇ 1 compares a common feedback voltage Vfb and mutually different reference voltages Vref_ 0 to Vref_n ⁇ 1 respectively, and outputs the comparison result signals.
  • the sub-output terminals 0 _ 0 to 0 _n ⁇ 1 of n number of sub-power supply modules are coupled to the common output terminal Vout, and a smoothing capacitor Cout is disposed at the common output terminal Vout, and a load circuit RL is coupled to the common output terminal Vout.
  • FIG. 19 is a circuit diagram of a sub-power supply module of the step-up type power supply unit in FIG. 18 .
  • the sub-power supply module in the (n ⁇ 1)th step has a module circuit M_n ⁇ 1 which includes an inductor L coupled to the power supply voltage Vcc 2 , a switching element M 1 constituted by an N-channel MOS (NMOS) transistor disposed between the inductor L and the ground Vss, and a Schottky Barrier Diode SBD disposed between the connection node Lx_n ⁇ 1 of the inductor L and the switching element M 1 and a sub-output terminal 0 _n ⁇ 1.
  • NMOS N-channel MOS
  • the sub-power supply module in the (n ⁇ 1)th step also has an AND gate for supplying a drive pulse to the gate of the switching element M 1 , a comparator CMP_n ⁇ 1, and a pulse generation circuit PG_n ⁇ 1.
  • the AND gate, the comparator CMP_n ⁇ 1 and the pulse generation circuit PG_n ⁇ 1 constitute a drive control circuit CNT_n ⁇ 1 for driving the switching element M 1 .
  • the drive control circuit CNT_n ⁇ 1 has a same configuration as the drive control circuit of the step-down type power supply circuit of the first embodiment, and operates in the same manner.
  • the switching element M 1 When the pulse signal P_n ⁇ 1 is in the H level period, the switching element M 1 turns ON, supplies current from the power supply Vcc 2 to the inductor L, and stores the electromagnetic energy in the inductor L if the potential of the output voltage of the common output terminal Vout is lower than the potential corresponding to the reference voltage Vref_n ⁇ 1. If the potential of the output voltage of the common output terminal Vout is higher than the potential corresponding to the reference voltage Vref_n ⁇ 1 when the pulse signal P_n ⁇ 1 is in the H level period, on the other hand, the switching element M 1 turns OFF.
  • the switching element M 1 turns OFF, current of the inductor L is output to the sub-output terminal O_n ⁇ 1 via the Schottky Barrier Diode SBD by the electromagnetic energy stored in the inductor L.
  • the switching element Mi repeats turning ON and OFF intermittently, but the current supplied to the output terminal is smoothed by the inductor L.
  • the sub-power supply module in the (n ⁇ 2)th step has a configuration similar to the (n ⁇ 1)th step.
  • the pulse generation circuit PG_n ⁇ 2 generates a pulse signal, of which phase is shifted by a 1/n cycle from that of the (n ⁇ 1)th pulse generation circuit.
  • the duty ratios of the pulse signals are the same.
  • the switching element M 1 turns ON or OFF by the comparison result signal C_n ⁇ 2, which becomes H level if the feedback voltage Vfb is lower than the reference voltage Vref_n ⁇ 2, and becomes L level if the feedback voltage Vfb is higher than the reference voltage Vref_n ⁇ 2.
  • the switching element M 1 of the sub-power supply module in the (n ⁇ 2)th step is controlled to be ON or OFF based on the potential of the output voltage Vout, which is lower than the sub-power supply module in the (n ⁇ 1)th step, whereas the switching element M 1 of the sub-power supply module in the (n ⁇ 1)th step is controlled to be ON or OFF based on the potential of the output voltage Vout which is higher than the sub-power supply module in the (n ⁇ 2)th step.
  • the sub-power supply modules in the (n ⁇ 3)th step to the 0 th step also have a similar configuration as the sub-power supply modules in the (n ⁇ 1)th step and the (n ⁇ 2)th step.
  • the n steps of the sub-power supply modules perform the ON/OFF switching operation based on a different potential of the output voltage Vout. Since the potential of the output voltage Vout at which the switching element M 1 turns ON is different in each step, the period when the switching element M 1 turns ON is different in each step, and the ON duty ratio thereof is also different depending on the step. Therefore comparing with the case of the switching elements of all the sub-power supply modules which turn ON or OFF based on the same reference voltage Vref, the pulsation of the output voltage Vout is small, and the ripple becomes low.
  • the comparators CMP of the n number of sub-power supply modules may compare the same reference potential Vref and a different feedback voltage Vfb_ 0 to Vfb_n ⁇ 1 respectively.
  • the ON duty ratio of each switching element of the n number of sub-power supply modules is longer as the switching element is closer to the 0 th step, and is shorter as the switching element is closer to the (n ⁇ 1)th step.
  • n number of sub-power supply modules are coupled to the common output terminal Vout, and the ON/OFF operation of the switching element M 1 in each sub-power supply module is switched based on a different potential of the output voltage Vout, whereby the ON duty ratio of each switching element M 1 is different from other switching elements.
  • the inductor Lout or L is disposed, and the smoothing capacitor Cout is disposed at the common output terminal Vout.
  • the circuit configuration of the sub-power supply module is simple, therefore a higher number of sub-power supply modules may be installed, and increasing the number of sub-power supply modules may decrease the inductance of the inductor Lout or L, and since the current amount from each sub-power supply module is low, capacitance of the smoothing capacitor Cout may also be decreased.
  • the number of sub-power supply modules is increased to 1000, 10,000, 100,000 or 1,000,000, for example, and the inductor and capacitor are replaced with a parasitic inductance and parasitic capacitance of wirings in the integrated circuit device.
  • the parasitic inductor and parasitic capacitor of the wirings in the semiconductor circuit device are used, instead of disposing an inductor element and a capacitor element independently.
  • FIG. 20 is a circuit diagram of a sub-power supply module of a step-down type power supply unit circuit according to the third embodiment. Differences from the circuit in FIG. 2 are that the inductor Lout is not disposed between the connection node Lx_n ⁇ 1 or Lx_n ⁇ 2 and the output terminal Vout, and the smoothing capacitor Cout is not disposed at the output terminal Vout.
  • the parasitic inductor Lp generated in the wiring between the connection node Lx_n ⁇ 1 or Lx_n ⁇ 2 and the output terminal Vout is used as the smoothing coil.
  • the parasitic capacitor Cp generated at the output terminal Vout is used as the smoothing capacitor.
  • FIG. 21 is a plan view and cross-sectional views of an integrated circuit device having the power supply unit circuit in FIG. 20 .
  • the plan view is illustrated at the left side of FIG. 21
  • the cross-sectional views sectioned at positions A, B and C in the plan view are illustrated at the right side.
  • an AND gate, a switching transistor Ml, a parasitic inductor Lp, a common output terminal Vout, and a parasitic capacitor Cp disposed at the common output terminal Vout are illustrated for six sub-power supply modules.
  • each AND gate is coupled to a gate electrode of the switching transistor M 1 via a gate electrode wiring, and the parasitic inductor Lp, having inductance that is sufficient for a thin wiring between a connection node Lx of the switching transistor M 1 and a Schottky barrier diode and the output terminal Vout, is formed.
  • the parasitic inductor Lp As the wiring width becomes narrower, the inductance of the parasitic inductor Lp increases.
  • the gate electrode of the switching transistor M 1 is located under the wiring of the power supply Vcc 2 .
  • the wiring of the ground GND (Vss) is illustrated, and the gate electrode of the switching transistor M 1 is located there under.
  • a thin wiring having the parasitic inductance Lp is illustrated respectively.
  • FIG. 22 is a circuit diagram of a sub-power supply module of a step-up type power supply unit circuit according to the third embodiment. Differences from the circuit in FIG. 19 are that the inductor L is not disposed between the input power supply Vcc 2 and the connection node Lx_n ⁇ 1 or Lx_n ⁇ 2, and the smoothing capacitor Cout is not disposed in the output terminal Vout.
  • the parasitic inductor Lp which is generated in the wiring between the input power supply Vcc 2 and the connection node Lx_n ⁇ 1 or Lx_n ⁇ 2, is used as a smoothing coil. In the same manner, the parasitic capacitor Cp, generated at the output terminal Vout, is used as the smoothing capacitor.
  • each parasitic inductor Lp is formed in the thin wiring between the input power supply Vcc 2 and the connection node Lx_n ⁇ 1 or Lx_n ⁇ 2, and the parasitic capacitor Cp is formed in the wide conductor layer of the common output terminal Vout.
  • the number of sub-power supply modules is increased using a drive control circuit of each sub-power supply module having a simple circuit configuration, and an area of the sub-power supply modules on the integrated circuit is decreased. Accordingly the inductor Lout or L of each sub-power supply module is decreased accordingly to the size of the parasitic inductor, and the smoothing capacitor Cout is decreased approximately to the size of the parasitic capacitor. As a result, several thousand to several million sub-power supply modules may be integrated.

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