US8258043B2 - Manufacturing method of thin film semiconductor substrate - Google Patents

Manufacturing method of thin film semiconductor substrate Download PDF

Info

Publication number
US8258043B2
US8258043B2 US13/225,039 US201113225039A US8258043B2 US 8258043 B2 US8258043 B2 US 8258043B2 US 201113225039 A US201113225039 A US 201113225039A US 8258043 B2 US8258043 B2 US 8258043B2
Authority
US
United States
Prior art keywords
semiconductor substrate
thin film
semiconductor
manufacturing
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US13/225,039
Other languages
English (en)
Other versions
US20120077331A1 (en
Inventor
Toshiyuki Sameshima
Yutaka Inouchi
Takeshi Matsumoto
Yuko Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Ion Equipment Co Ltd
Tokyo University of Agriculture and Technology NUC
Original Assignee
Nissin Ion Equipment Co Ltd
Tokyo University of Agriculture and Technology NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Ion Equipment Co Ltd, Tokyo University of Agriculture and Technology NUC filed Critical Nissin Ion Equipment Co Ltd
Assigned to NISSIN ION EQUIPMENT CO., LTD., NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY reassignment NISSIN ION EQUIPMENT CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJIMOTO, YUKO, INOUCHI, YUTAKA, MATSUMOTO, TAKESHI, SAMESHIMA, TOSHIYUKI
Publication of US20120077331A1 publication Critical patent/US20120077331A1/en
Application granted granted Critical
Publication of US8258043B2 publication Critical patent/US8258043B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane

Definitions

  • the present invention relates to a manufacturing method of thin film semiconductor substrates.
  • the present invention specifically relates to a manufacturing method of a thin film semiconductor substrate including an ion implantation and cleaving process.
  • a thin film semiconductor substrate typically represented by an SOI (silicon on insulator) substrate has a single crystal semiconductor thin film, for example, of a single crystal silicon, on an insulating substrate.
  • SOI silicon on insulator
  • a semiconductor device manufactured using such a thin film semiconductor substrate has sufficient insulation for semiconductor elements along its depth direction. Accordingly, such substrates are appreciated as being useful in manufacturing semiconductor devices requiring high integration and high functionality.
  • the ion implantation and cleaving process is known as a method for manufacturing thin film semiconductor substrates.
  • ions of a light mass element, such as hydrogen are implanted at a specified depth into a wafer made of a single crystal silicon for an activation layer.
  • an insulating substrate is laminated on an ion implantation side of the wafer for the activation layer.
  • bubbles are generated in the ions introduced into the wafer for the activation layer by causing a change of volume in minute cavities by a heat treatment at a temperature in a range of 400° C. to 700° C.
  • a bubble layer is formed at the specified depth in the wafer for the activation layer.
  • the wafer for the activation layer is cleaved along the bubble layer, which functions as a cleaving surface, thereby obtaining a thin film semiconductor substrate that includes a semiconductor thin film (single crystal silicon thin film) made of the thin wafer for the activation layer on the side of the insulating substrate (refer to Japanese Patent Application Laid-Open No. 2009-158943, specifically the paragraphs 0039 to 0041).
  • the thin film has a uniform thickness and the cleaving surface has high flatness. Therefore, the semiconductor elements are formed on the thin film substrate after subjecting the surface (the cleaving surface) of the semiconductor thin film to flattening by polishing.
  • An increase in the unevenness of the cleaving surface increases the polishing work for flattening the cleaving surface and causes a longer TAT (turn around time) and decreases the yield.
  • the present invention aims to provide a thin film semiconductor substrate manufacturing method that enables forming of the bubble layer with minute bubbles, and as the effect, improves the TAT and the yield.
  • a manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate.
  • the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 microseconds ( ⁇ s) to 100 milliseconds (ms).
  • the heating of the semiconductor substrate is performed by using, for example, a light beam h ⁇ .
  • the semiconductor substrate is heated at the temperature in the temperature range of approximately 1000° C. to 1200° C. for an extremely short time, such as approximately 10 ⁇ s to 100 ms. Therefore, extremely minute bubbles are formed by ion vaporization at the forming, merging of these bubbles is suppressed, and a bubble layer consisting of extremely minute bubbles can be formed. Accordingly, the surface (cleaving surface) of the semiconductor thin film obtained by cleaving at the bubble layer, which is formed of extremely minute bubbles, has little roughness. As a result, polishing work to flatten the surface of the semiconductor thin film can be reduced.
  • FIG. 1 shows cross sectional diagrams for explaining a manufacturing method according to a first embodiment.
  • FIG. 2 shows another cross sectional diagram for explaining the manufacturing method according to the first embodiment.
  • FIG. 3 shows cross sectional diagrams for explaining salient features of a manufacturing method according to a second embodiment.
  • FIG. 4 shows an optical reflectivity spectrum of a hydrogen molecular ion implantation surface of a semiconductor substrate.
  • FIG. 5 shows a depth profile of a crystallization degree of a semiconductor substrate obtained from a numerical analysis of the optical reflectivity spectrum shown in FIG. 4 .
  • FIG. 6 shows an optical reflectivity spectrum of a hydrogen molecular implantation surface of a semiconductor substrate after the semiconductor substrate is irradiated with a light beam.
  • FIG. 7 shows a depth profile of a crystallization degree of a semiconductor substrate obtained from a numerical analysis of the optical reflectivity spectrum shown in FIG. 6 .
  • FIG. 1 shows cross sectional diagrams for explaining a manufacturing method of a thin film semiconductor substrate according to a first embodiment of the present invention. The manufacturing method according to the first embodiment is explained below with reference to FIG. 1 .
  • a semiconductor substrate 1 that is to be converted into a wafer for an activation layer is prepared.
  • This semiconductor substrate 1 is assumed to be a substrate made of a single crystal silicon or some other semiconductor material having a single crystal property.
  • a single crystal silicon substrate is used as an example.
  • an oxide film 3 is laminated on the semiconductor substrate 1 .
  • the oxide film 3 is used as a protective film at an ion implantation process that is performed later.
  • the oxide film 3 is assumed to be a thermal oxide film formed, for example, by a heat treatment.
  • the oxide film 3 can be formed only when necessary, i.e., the oxide film 3 may not be formed when the protective film is not necessary at the ion implantation process.
  • the ion implantation process is performed to form an ion implantation layer 5 at a specified depth in the semiconductor substrate 1 by implanting ions from a top surface of the semiconductor substrate 1 .
  • a depth d at which the ion implantation layer 5 is formed corresponds to a thickness of the semiconductor thin film required for the thin film semiconductor substrate manufactured at this stage.
  • the depth d can be adjusted by controlling the implantation energy depending on the type of the ions used.
  • Hydrogen ions, hydrogen molecular ions, or some other ions of light mass element can be used in the ion implantation process.
  • Helium ions can also be used as the light mass element ions.
  • the light mass element ions are preferable in that the light mass element ions do not cause serious damage to the semiconductor substrate at the ion implantation process.
  • a dosing density is set to 3 ⁇ 10 16 particles/cm 2 .
  • the semiconductor substrate 1 is subjected to a heat treatment at a temperature lower than the temperature at which the ions constituting the ion implantation layer 5 vaporize.
  • the heat treatment With the heat treatment, the ions implanted into the semiconductor substrate 1 are reduced to nearly a maximum implantation density, and the thickness of the ion implantation layer 5 in the depth direction, i.e., the distribution of an ion zone is reduced.
  • the heat treatment is performed at a temperature that is lower than approximately 400° C., for example, approximately 300° C.
  • the heat treatment can be performed only when necessary, that is, the heat treatment may not be performed when the ion distribution at the ion implantation process is narrow and accordingly the adjustment of the ion distribution is not required.
  • a bubble layer forming process shown in FIG. 1C characterizing the present invention is performed.
  • bubbles A are generated by vaporizing the ions implanted into the semiconductor substrate 1 through heating of the semiconductor substrate 1 by irradiating a light beam h ⁇ as an energy beam over the whole surface of the semiconductor substrate 1 .
  • the bubbles A are formed and distributed at a depth d′ from a top surface of the ion implantation layer 5 . That is, a bubble layer 7 is formed by the bubbles A distributed at the specified depth d′ ( ⁇ d).
  • a light absorption layer can be provided on the semiconductor substrate 1 and the semiconductor substrate 1 can be heated via this light absorption layer instead of directly heating the semiconductor substrate 1 .
  • the semiconductor substrate 1 When the semiconductor substrate 1 is heated via the light absorption layer, the semiconductor substrate 1 can be heated to a desired temperature in a shorter time.
  • Metals for example, molybdenum (Mo), or tantalum (Ta), or tungsten (W), besides carbon, can be listed as a material of the light absorption layer.
  • the light beam h ⁇ is assumed to have a wavelength that can be absorbed by the semiconductor substrate 1 .
  • a laser beam such as a semiconductor laser or a solid state laser that is not restricted by oscillating devices can be used.
  • the laser beam need not be of a single wavelength, but can include a plurality of wavelengths including the light of the wavelength range mentioned above.
  • the semiconductor substrate 1 is made of a single crystal silicon, a light beam of wavelength approximately 300 nm to 1000 nm like in an infrared semiconductor laser can be used.
  • Heating of the semiconductor substrate 1 by irradiating the light beam h ⁇ is performed by scanning the light beam h ⁇ on the oxide film 3 formed on the surface of the semiconductor substrate 1 closer to the bubble layer 7 .
  • the light beam h ⁇ is irradiated on the whole surface of the semiconductor substrate 1 .
  • the number of required scans can be reduced, and the process can be made faster.
  • the irradiation of the light beam h ⁇ is performed while adjusting an intensity and an irradiation duration (scanning speed) of the light beam h ⁇ so that the semiconductor substrate 1 is heated up to a temperature at which the ions introduced in the semiconductor substrate 1 are vaporized.
  • the light beam h ⁇ is irradiated such that the semiconductor substrate 1 is heated up to a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ⁇ s to 100 ms.
  • Such a high temperature heating for a short time can be realized by irradiation of the light beam h ⁇ , and cannot be realized by heating with a lamp or heating in a furnace.
  • the light beam h ⁇ is assumed to be irradiated on the surface of the semiconductor substrate 1 that is closer to the bubble layer 7 .
  • a light beam of a wavelength that can penetrate the semiconductor substrate 1 it is possible to irradiate the surface of the semiconductor substrate 1 that is opposite to the surface shown in FIG. 1C , for example, upon which the light beam impinges.
  • an insulating substrate 11 is laminated on the semiconductor substrate 1 .
  • the insulating substrate 11 is laminated on that surface of the oxide film 3 that is closer to the bubble layer 7 of the semiconductor substrate 1 .
  • the purpose of the insulating substrate 11 is to secure insulation at the surface for bonding to the semiconductor substrate 1 . Therefore, a substrate formed by laminating a semiconductor substrate, such as a single crystal silicon with oxide films, a glass substrate, a plastic substrate, or a metal substrate laminated with insulating film can be used as the insulating substrate 11 .
  • the cleaving process includes cleaving the semiconductor substrate 1 along the bubble layer 7 as a cleaving surface 15 .
  • a semiconductor thin film 1 a is formed on the side of the insulating substrate 11 due to cleaving of the semiconductor substrate 1 .
  • the semiconductor substrate 1 can be cleaved along the bubble layer 7 through heating or physically impacting the semiconductor substrate 1 .
  • the heating it is preferable that the heating be completed in a short time. If the heating is performed for a long time, a stress may be generated due to a difference in thermal expansion coefficients of the insulating substrate 11 and the semiconductor thin film 1 a leading to generation of cracks in the semiconductor thin film 1 a.
  • a thin film semiconductor substrate 13 with the semiconductor thin film 1 a formed on the insulating substrate 11 is obtained by the above-mentioned process.
  • a surface of the semiconductor thin film 1 a of the thin film semiconductor substrate 13 obtained in this manner assumes a form that depends on the shape of the inner surfaces of the bubbles A of the bubble layer 7 .
  • a flattening process is performed to flatten the surface (the cleaving surface 15 ) of the semiconductor thin film 1 a .
  • the surface (the cleaving surface 15 ) of the semiconductor thin film 1 a can be flattened by applying CMP (chemical mechanical polishing). Meanwhile, if required, a thickness of the semiconductor thin film 1 a can be reduced to a desired thickness in the flattening process.
  • the recrystallization process includes heating the thin film semiconductor substrate 13 .
  • the heating can be performed by irradiating the surface of the semiconductor thin film 1 a with a laser or light of a lamp, or heating the thin film semiconductor substrate 13 in a furnace. It is preferable that the heating be completed in a short time. If the heating is performed for a long time, a stress may be generated due to a difference in thermal expansion coefficients of the insulating substrate 11 and the semiconductor thin film 1 a leading to generation of cracks in the semiconductor thin film 1 a.
  • element separation areas are formed on the semiconductor thin film 1 a and the semiconductor elements are formed on activation areas that are separated due to the presence of the element separation areas.
  • the element separation areas are formed even in the depth direction of the semiconductor thin film 1 a . As a result, separation among the semiconductor elements formed on each of the activation areas can be secured.
  • the semiconductor substrate 1 is heated by using the light beam h ⁇ during the bubble layer forming process explained with reference to FIG. 1C . Accordingly, the ions can be vaporized to form the bubbles A by heating of the semiconductor substrate 1 in a short time and at a high temperature, and the bubbles A can be prevented from merging and forming bubbles of larger diameter. Consequently, the bubble layer 7 containing very minute bubbles A can be formed. As a result, the surface (the cleaving surface 15 ) of the semiconductor thin film 1 a obtained by cleaving along the bubble layer 7 , which contains extremely minute bubbles A, can be finished as a surface with little roughness that depends on the shape of the inner surface of the extremely minute bubbles A.
  • the bubbles A will not merge after the bubbles A are formed near a point of maximum implantation density of the ion implantation layer 5 during an initial stage of the bubble layer forming process. Accordingly, the bubble layer 7 containing minute bubbles A can be formed at a uniform depth even at a deeper position in the semiconductor substrate 1 .
  • the semiconductor thin film 1 a obtained by cleaving the semiconductor substrate 1 at the bubble layer 7 has a certain thickness, its surface (i.e., the cleaving surface 15 ) will have little roughness that depends on the shape of the inner surface of the extremely minute bubbles A.
  • the polishing work at the flattening process to flatten the surface (i.e., the cleaving surface 15 ) of the semiconductor thin film 1 a can be reduced, and as a result, the TAT can be shortened and the yield can be improved. The same effect can be achieved even if the semiconductor thin film 1 a has a certain higher thickness.
  • the semiconductor substrate 1 is heated up to a high temperature in an extremely short time.
  • the crystal structure of the semiconductor substrate 1 that had degraded in the ion implantation process can be recovered to a certain degree. Accordingly, sufficient recrystallization becomes feasible by a process with a suppressed thermal hysteresis at the recrystallization process of the semiconductor thin film 1 a .
  • FIG. 3 shows cross sectional diagrams for explaining salient features of the manufacturing method according to a second embodiment of the present invention.
  • the manufacturing method according to the second embodiment differs from the manufacturing method according to the first embodiment in the point that the bubble layer forming process by irradiating the light beam h ⁇ and the process of laminating the insulating substrate 11 are performed in a reverse order. The rest of the processes are substantially similar.
  • the processes similar to the first embodiment explained with reference to FIG. 1A and FIG. 1B are performed first. That is, the oxide film 3 is formed on the surface of the semiconductor substrate 1 and the ion implantation layer 5 is formed next and further the width of the ion implantation layer 5 in the depth direction is narrowed by a heat process as required.
  • the insulating substrate 11 is laminated on the semiconductor substrate 1 .
  • the insulating substrate 11 is laminated on the surface of the oxide film 3 located close to the ion implantation layer 5 of the semiconductor substrate 1 .
  • the insulating substrate 11 is assumed to be made of a material with sufficiently high transparency for the light beam to be used at the next process.
  • the insulating substrate 11 is made of a light transparent material and it functions to secure insulation at a bonding surface with the semiconductor substrate 1 .
  • a glass substrate or a plastic substrate can be used as the insulating substrate 11 .
  • the bubble layer forming process shown in FIG. 3B that is the salient feature of the present invention is performed.
  • the semiconductor substrate 1 is heated by irradiating the light beam h ⁇ as the energy beam on the whole surface of the semiconductor substrate 1 , the bubbles A are generated by vaporizing the ions implanted into the semiconductor substrate 1 , and the bubble layer 7 is formed by distributing the bubbles A at the depth d′ ( ⁇ d).
  • the salient feature of the second embodiment is that the semiconductor substrate 1 is irradiated with the light beam h ⁇ from the side of the insulating substrate 11 through the very insulating substrate 11 itself.
  • the irradiation of the semiconductor substrate 1 with the light beam h ⁇ is similar to that explained in connection with the first embodiment.
  • the cleavage process similar to that explained with reference to FIG. 1E in connection with the first embodiment is performed. That is, the semiconductor substrate 1 is cleaved along the bubble layer 7 as the cleaving surface 15 . Thus, the semiconductor substrate 1 is cleaved along the bubble layer 7 , and the thin film semiconductor substrate 13 formed by the semiconductor thin film 1 a on the insulating substrate 11 is obtained.
  • the thin film semiconductor substrate 13 obtained through the processes explained above includes the semiconductor thin film 1 a which has a surface (i.e., the cleaving surface 15 ) of the form same as the inner surfaces of the bubbles A in the bubble layer 7 similar to that in the first embodiment. Accordingly, as explained in FIG. 2 in connection with the first embodiment, the flattening process for flattening the surface (the cleaving surface 15 ) of the semiconductor thin film 1 a in the thin film semiconductor substrate 13 is performed by polishing, for example, with the CMP. In the flattening process, if required, the thickness of the semiconductor thin film 1 a is reduced to a desired thickness. Next, the recrystallization process is performed to recover the crystal structure of the semiconductor thin film 1 a that had degraded in the ion implantation process. The recrystallization process includes heating.
  • the element separation areas are formed on the semiconductor thin film 1 a and the semiconductor elements are formed on the activation areas that are separated due to the presence of the element separation areas.
  • the element separation areas are formed even in the depth direction of the semiconductor thin film 1 a . As a result, separation among the semiconductor elements formed on each of the activation area can be secured.
  • the heating of the semiconductor substrate 1 with the light beam h ⁇ is performed at the bubble layer forming process explained with reference to in FIG. 3B also in the manufacturing method according to the second embodiment.
  • the bubble layer 7 containing the extremely minute bubbles A can be formed and the roughness of the cleaving surface 15 obtained by cleaving the semiconductor substrate 1 can be reduced.
  • the polishing work at the flattening process for flattening the surface (the cleaving surface 15 ) of the semiconductor thin film 1 a can be reduced.
  • improvement of the TAT and the yield of the manufacturing of the semiconductor devices using the thin film semiconductor substrate 13 can be achieved.
  • the crystal structure of the semiconductor substrate 1 that had degraded in the ion implantation process can be recovered to a certain degree at the bubble forming process, generation of cracks in the semiconductor thin film 1 a can be prevented by reducing the thermal hysteresis at the recrystallization process of the semiconductor thin film 1 a.
  • the heating of the semiconductor substrate 1 is performed by using the light beam h ⁇ specifically in the bubble layer forming process shown in FIG. 3B , the stress caused due to the difference in the thermal expansion coefficients of the semiconductor substrate 1 and the insulating substrate 11 can be suppressed and the damage of the semiconductor substrate 1 and the insulating substrate 11 can be prevented. Accordingly, the process of forming the bubble layer 7 that includes heating of the semiconductor substrate 1 can be performed after laminating the insulating substrate 11 .
  • the method of heating the semiconductor substrate at the bubble layer forming process by using the light beam h ⁇ is employed.
  • the bubble layer forming process it is important to form the bubbles of a diameter as small as possible.
  • heating of the semiconductor substrate by scanning with the light beam h ⁇ for a short time at the bubble layer forming process is effective.
  • other methods of heating can also be adopted as long as they allow heating of the semiconductor substrate in a very short time up to a temperature in the temperature range of approximately 1000° C. to 1200° C.
  • the semiconductor substrate 1 can be heated up to a temperature in the temperature range of 1000° C. to 1200° C. for a duration in the range of 10 ⁇ s to 100 ms.
  • a carbon heating body heated up to approximately 1200° C. or higher is arranged adjacent to the surface of the semiconductor substrate 1 , without bringing it in contact with the semiconductor substrate 1 , and moved at a high speed, thereby heating the semiconductor substrate 1 .
  • the carbon heating body can be heated by irradiating it with light energy (refer to the Japanese Patent Application Laid-open No. 2007-115926).
  • the carbon heating body can be arranged near the ion implantation layer of the semiconductor substrate 1 and moved at a high speed.
  • Electrodes are formed on the semiconductor substrate 1 and an electric current is passed through the electrodes to generate Joule's heat (refer to Applied Physics A73, pp. 419-423).
  • the electrodes can be formed on the semiconductor substrate 1 through a chrome film and the electric current can be passed through these electrodes.
  • the semiconductor substrate 1 is irradiated with a thermal plasma beam as the energy beam to heat the semiconductor substrate (refer to Japanese Journal of Applied Physics, Vol. 45, No. 5B (2006), pp. 4313-4320).
  • the ion implantation surface of the semiconductor substrate 1 can be scanned with the thermal plasma beam.
  • the semiconductor substrate 1 is heated by irradiating with an electron beam as the energy beam.
  • the ion implantation surface of the semiconductor substrate 1 can be scanned with the electron beam.
  • the oxide film 3 of thickness approximately 100 nm was formed by the heat process on the surface of the semiconductor substrate 1 made of single crystal silicon.
  • the ion implantation layer 5 was formed at the specified depth in the semiconductor substrate 1 by implanting hydrogen molecular ions into the semiconductor substrate 1 from a side of the oxide film 3 with an implantation energy of 60 keV and the dosing density of 3 ⁇ 10 16 particles/cm 2 .
  • an optical reflectivity spectrum of the hydrogen molecular ion implantation surface on the semiconductor substrate 1 was measured to check transition of the crystal structure of the semiconductor substrate 1 in the ion implantation process.
  • the oxide film 3 was removed to expose the single crystal silicon surface of the semiconductor substrate 1 , and the optical reflectivity spectrum was measured on this exposed surface.
  • the result of the measurement is shown in FIG. 4 as an experimental value.
  • a moderate vibration waveform could be observed at a visible or near infrared range of wavelength 450 nm or longer in the measured optical reflectivity spectrum.
  • a depth profile of a crystallization rate was calculated as shown in FIG. 5 based on a numerical analysis of the experimental value of the optical reflectivity spectrum shown in FIG. 4 .
  • the calculation of the depth profile of the crystallization rate from the optical reflectivity spectrum was performed as follows.
  • the optical reflectivity spectrum was calculated using a computer assuming that the semiconductor substrate 1 for which the optical reflectivity spectrum was measured has a multilayered structure. A crystallization rate and a film thickness of each layer of the multilayer structure are shifted and the optical reflectivity spectrum was calculated by using the Fresnel's coefficient method considering a light interference effect. The crystallization rate and the film thickness of each layer were input such that this calculated value matches the measured optical reflectivity spectrum (up to here, refer to Japanese Patent Application Laid-open No. 2008-124083). Incidentally, the optical reflectivity spectrum calculated in this way is shown in FIG. 4 with a broken line as a calculated value.
  • the semiconductor substrate 1 was heated for 1 ms at a temperature of 1050° C. by irradiating an infrared semiconductor laser of wavelength 940 nm as the light beam h ⁇ and the bubble layer 7 was formed.
  • the optical reflectivity spectrum on the hydrogen molecular ion implantation surface of the semiconductor substrate 1 was measured in the same way as explained with reference to FIG. 4 to check transition of the crystal structure of the semiconductor substrate 1 due to the irradiation of the light beam h ⁇ .
  • the result is shown in FIG. 6 as an experimental value.
  • the optical reflectivity spectrum shown in FIG. 6 differs drastically from the optical reflectivity spectrum shown in FIG. 4 . That is, an oscillation waveform of the visible or near infrared range of wavelength 450 nm or shorter is conspicuously enhanced in the optical reflectivity spectrum shown in FIG. 6 .
  • the experimental value of the optical reflectivity spectrum shown in FIG. 6 was numerically analyzed and a depth profile of crystallization rates was calculated.
  • the calculated depth profile is shown in FIG. 7 .
  • the optical reflectivity spectrum calculated in this way is shown with a broken line in FIG. 6 as a calculated value.
  • the crystallization rate in the region from the surface up to a depth of 270 mm has improved, and the crystal structure is recovered due to heating of the semiconductor substrate 1 by irradiating with the light beam.
  • Formation of a thin space of a width 4 nm and a deflection coefficient of approximately 1, i.e., a cavity at the depth of 270 nm was also observed. This cavity indicates that minute bubbles were formed in a high density at an edge of hydrogen molecular ion implantation.
  • the diameters of the bubbles were measured and found to be approximately 4 nm.
  • the diameter of the bubbles was approximately 10 nm. Accordingly, it was confirmed that the diameter of the bubbles can be scaled down to approximately 2 ⁇ 5 by using the method according to the embodiments.
  • the roughness of the cleaving surface cleaved along the bubble layer can be reduced since the bubbles forming the bubble layer can be scaled down.
  • the polishing work to flatten the surface of the semiconductor thin film can be reduced.
  • the TAT and the yield can be improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)
US13/225,039 2010-09-24 2011-09-02 Manufacturing method of thin film semiconductor substrate Expired - Fee Related US8258043B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-214417 2010-09-24
JP2010214417A JP5688709B2 (ja) 2010-09-24 2010-09-24 薄膜半導体基板の製造方法

Publications (2)

Publication Number Publication Date
US20120077331A1 US20120077331A1 (en) 2012-03-29
US8258043B2 true US8258043B2 (en) 2012-09-04

Family

ID=45871076

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/225,039 Expired - Fee Related US8258043B2 (en) 2010-09-24 2011-09-02 Manufacturing method of thin film semiconductor substrate

Country Status (2)

Country Link
US (1) US8258043B2 (ja)
JP (1) JP5688709B2 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6757953B2 (ja) * 2016-08-09 2020-09-23 学校法人 名古屋電気学園 表面加工方法、構造体の製造方法
SG11202009989YA (en) * 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
US11694897B2 (en) * 2021-06-16 2023-07-04 Applied Materials, Inc. Backside wafer dopant activation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140210A (en) * 1997-09-26 2000-10-31 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated thereby
WO2001048825A1 (fr) 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Procédé de production de tranche collée
JP2002305292A (ja) 2001-04-06 2002-10-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハおよびその製造方法
JP2008294268A (ja) 2007-05-25 2008-12-04 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2009158943A (ja) 2007-12-03 2009-07-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US20110097873A1 (en) * 2008-06-20 2011-04-28 Tien-Hsi Lee Method for producing thin film

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134672A (ja) * 2002-10-11 2004-04-30 Sony Corp 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置
US6911376B2 (en) * 2003-10-01 2005-06-28 Wafermasters Selective heating using flash anneal
JP5110772B2 (ja) * 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP5496608B2 (ja) * 2008-11-12 2014-05-21 信越化学工業株式会社 Ｓｏｉ基板の作製方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140210A (en) * 1997-09-26 2000-10-31 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated thereby
WO2001048825A1 (fr) 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Procédé de production de tranche collée
JP2002305292A (ja) 2001-04-06 2002-10-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハおよびその製造方法
JP2008294268A (ja) 2007-05-25 2008-12-04 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
JP2009158943A (ja) 2007-12-03 2009-07-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US20110097873A1 (en) * 2008-06-20 2011-04-28 Tien-Hsi Lee Method for producing thin film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Hydrogen-induced silicon wafer splitting. Fuqian Yang, J. Appl. Phys. 94, 1454 (2003). accepted May 6, 2003). *

Also Published As

Publication number Publication date
JP2012069817A (ja) 2012-04-05
US20120077331A1 (en) 2012-03-29
JP5688709B2 (ja) 2015-03-25

Similar Documents

Publication Publication Date Title
JP4222644B2 (ja) 特に電子構成品を含む半導体材料薄膜の製法
CN105899325B (zh) 借助于激光处理和温度诱导的应力的组合的晶片制造法
KR101558192B1 (ko) 반도체 기판의 제작 방법 및 반도체 장치의 제작 방법
US7479442B2 (en) Method of manufacturing single crystal Si film
JP4730581B2 (ja) 貼り合わせウェーハの製造方法
WO2011081146A1 (ja) 応力を低減したｓｏｓ基板
JP2013033953A (ja) 半導体層の欠陥を修復する方法
US8058148B2 (en) Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
KR20090018848A (ko) 방사 어닐링을 이용하여 제조되는 반도체-온-인슐레이터 구조
US8258043B2 (en) Manufacturing method of thin film semiconductor substrate
US11508613B2 (en) Method of healing an implanted layer comprising a heat treatment prior to recrystallisation by laser annealing
US8003491B2 (en) Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
US11195711B2 (en) Healing method before transfer of a semiconducting layer
JP2012038932A (ja) 半導体ウェーハの薄厚化方法および貼り合せウェーハの製造方法
TWI430338B (zh) 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置
US6952269B2 (en) Apparatus and method for adiabatically heating a semiconductor surface
JP2012507870A5 (ja)
JP6757953B2 (ja) 表面加工方法、構造体の製造方法
TW200818321A (en) Semiconductor on insulator structure made using radiation annealing
JP2000294467A (ja) 表面に識別パターンを有する多層基板の製造方法および管理方法
JP4468643B2 (ja) 切断方法
EP4150656A1 (en) Ion implantation device comprising energy filter and additional heating element

Legal Events

Date Code Title Description
AS Assignment

Owner name: NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY O

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAMESHIMA, TOSHIYUKI;INOUCHI, YUTAKA;MATSUMOTO, TAKESHI;AND OTHERS;SIGNING DATES FROM 20110721 TO 20110725;REEL/FRAME:026861/0289

Owner name: NISSIN ION EQUIPMENT CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SAMESHIMA, TOSHIYUKI;INOUCHI, YUTAKA;MATSUMOTO, TAKESHI;AND OTHERS;SIGNING DATES FROM 20110721 TO 20110725;REEL/FRAME:026861/0289

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20200904