US7229566B2 - Position detecting method and apparatus - Google Patents

Position detecting method and apparatus Download PDF

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US7229566B2
US7229566B2 US10/664,998 US66499803A US7229566B2 US 7229566 B2 US7229566 B2 US 7229566B2 US 66499803 A US66499803 A US 66499803A US 7229566 B2 US7229566 B2 US 7229566B2
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mark
position detection
line
alignment
information
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US20040058540A1 (en
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Takahiro Matsumoto
Hideki Ina
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7092—Signal processing

Definitions

  • This invention relates to position detecting method and apparatus effective in aligning a wafer or reticle in a semiconductor exposure apparatus, by way of example.
  • a projection-type exposure apparatus utilized in the manufacture of various devices, e.g., semiconductor chips such as IC and LSI chips, display elements such as liquid crystal panels, detecting elements such as magnetic heads, and image sensors such as CCDs
  • an increase in the fineness and density of the circuits used in these devices has been accompanied by the need to project a circuit pattern on the surface of a reticle onto the surface of a wafer, to thereby expose the wafer to the pattern, at a higher resolution.
  • the projection resolution of a circuit pattern depends upon the NA (numerical aperture) of the projection optical system and the wavelength of the exposing light
  • a method of enlarging the NA of the projection optical system or a method of shortening the wavelength of the exposing light has been adopted as a method of raising resolution.
  • a shift from g rays to i rays and from i rays to an excimer laser is in progress in regard to the exposing light source.
  • Exposure systems based upon excimer lasers having lasing wavelengths of 248 nm and 193 nm have already been put into practical use.
  • Exposure systems of even shorter lasing wavelengths namely a VUV exposure system that utilizes exposing light having a wavelength of 157 nm and an EUV exposure system that utilizes exposing light having a wavelength of 13 nm, are being studied as candidates for next-generation exposure systems.
  • CMP Chemical Mechanical Polishing
  • P-HEMT Pulseudomorphic High Electron Mobility Transistor
  • M-HEMT Metalmorphe-HEMT
  • HBT Heterojunction Bipolar Transistor
  • the required precision is 1 ⁇ 3 of the circuit line width.
  • the required precision in current 180-nm designs is 60 nm, or 1 ⁇ 3 of 180.
  • Alignment in an exposure apparatus is carried out by exposing a wafer to the circuit pattern on a reticle and alignment marks simultaneously to transfer the circuit pattern and alignment marks, detecting the position of the alignment marks optically when the wafer is exposed to the circuit pattern of the next reticle, and positioning the wafer with respect to the reticle.
  • Methods of detecting an alignment mark include a method of capturing the image of the alignment mark upon enlarging the image by a microscope, and then detecting the position of the mark image, and a method of using a diffraction grating as an alignment mark, detecting the phase of an interference signal that interferes with the diffracted light, and detecting the position of the diffraction grating.
  • the state of the art in the semiconductor industry is such that raising overlay accuracy for aligning the design pattern of the next step and the circuit pattern already on the wafer is essential for the purpose of improving the performance of semiconductor devices and the yield of manufacture insofar as an exposure apparatus is used.
  • the structure of circuit patterns has been improved but a frequently occurring problem is the occurrence of a variation in the shape of the alignment marks between wafers or between shots and an attendant decline in alignment precision.
  • FIG. 18 is a diagram illustrating alignment marks that have been acquired in a semiconductor manufacturing process.
  • a resist pattern 105 is formed through exposure and development steps.
  • a method of detecting alignment-mark position along the Y direction in FIG. 18 will be described as an example. Specifically, an average value Ym 1 of a position intermediate the positions of the alignment marks 101 and 103 and a deviation in the position of a cent r point Ym 2 of a resist mark 105 are detected.
  • the alignment-mark image processing range is as illustrated.
  • Position information regarding the marks 101 and 103 is calculated after this area is integrated along the non-detection direction (the X direction).
  • a process error for example, may occur after parameters have been decided. In such case it may be necessary to alter the parameters of the exposure apparatus to follow up a modification in the manufacturing process in response to the process error. Altering the parameters takes a great deal of time.
  • an object of the present invention is to provide a position detection method and apparatus capable of performing high-precision detection without detracting from the precision of alignment-mark detection even in a case where alignment marks formed on a wafer are flawed to some extent.
  • the foregoing object is attained by providing a position detection method for detecting the position of an object upon receiving light from a plurality of position detection marks on the object, comprising: an image information acquisition step of obtaining image information of the position detection marks from the light that has been received; a conversion step of converting the image information to a light-intensity signal for each line of a plurality of lines partitioned in a direction substantially orthogonal to a direction in which the position detection marks are detected; a determination step of determining whether the light-intensity signal of each line is valid or not; and a position information calculation step of calculating position information of the position detection marks from light-intensity signals of valid lines.
  • a position detection apparatus for detecting the position of an object upon receiving light from a plurality of position detection marks on the object, comprising: an image information acquisition unit for obtaining image information of the position detection marks from the light that has been received; a conversion unit for converting the image information to a light-intensity signal for each line of a plurality of lines partitioned in a direction substantially orthogonal to a direction in which the position detection marks are detected; a determination unit for determining whether the light-intensity signal of each line is valid or not; and a position information calculation unit for calculating position information of the position detection marks from a valid light-intensity signal of a line.
  • the above-described position detection method and apparatus calculate information representing an error of a position detection mark, which corresponds to the position information, with respect to a reference position.
  • An exposure apparatus has a stage device driven in order to position the object based upon error information calculated by the above-described position detection apparatus, the stage device positioning a substrate or a reticle or both as the object.
  • a method of manufacturing a semiconductor device comprises the steps of placing a group of manufacturing equipment for various processes, inclusive of the above-described exposure apparatus, in a plant for manufacturing semiconductor devices; and manufacturing a semiconductor device by a plurality of processes using this group of manufacturing equipment.
  • a semiconductor manufacturing plant comprises: a group of manufacturing equipment for various processes, inclusive of the above-described exposure apparatus; a local-area network for interconnecting the group of manufacturing equipment; and a gateway for making it possible to access, from the local-area network, an external network outside the plant; whereby information relating to at least one of the pieces of manufacturing equipment can be communicated by data communication.
  • a method of maintaining an exposure apparatus according to the present invention namely a method of maintained the above-described exposure apparatus that has been installed in a semiconductor manufacturing plant, comprises the steps of: providing a maintenance database, which is connected to an external network of the semiconductor manufacturing plant, by a vendor or user of the exposure apparatus; allowing access to the maintenance database from within the semiconductor manufacturing plant via the external network; and transmitting maintenance information, which is stored in the maintenance database, to the side of the semiconductor manufacturing plant via the external network.
  • the exposure apparatus includes a display, a network interface and a computer for running network software, wherein maintenance information relating to the exposure apparatus is capable of being communicated via a computer network.
  • the present invention is such that even if a position detection mark has a defect, mark position can be detected highly precisely without being affected by the defect in execution of global alignment.
  • the present invention in a case where the present invention is applied to alignment of a wafer or reticle in a semiconductor exposure apparatus, susceptibility to the influence of mark defects ascribable to the semiconductor process is reduced, alignment precision can be improved and it is possible to raise yield in a process for manufacturing semiconductor devices.
  • the productivity of semiconductor-device manufacture can be improved because it is possible to shorten the time needed to set semiconductor-process conditions necessary to stabilize alignment-mark shape.
  • detection error ascribable to a defect in an overlay verification mark ascribable to a semiconductor process can be reduced and whether an article is acceptable or not can be discriminated with better accuracy.
  • overlay accuracy can be improved by causing the detected value to be reflected as an offset in an exposure apparatus.
  • FIG. 1 is a schematic view illustrating a semiconductor exposure apparatus according to an embodiment of the present invention
  • FIG. 2 is a schematic view illustrating an alignment detecting optical system according to this embodiment
  • FIG. 3 is a diagram illustrating alignment marks according to this embodiment
  • FIG. 4 is a diagram illustrating alignment marks according to this embodiment
  • FIG. 5 is a diagram illustrating a two-dimensional image of alignment marks
  • FIG. 6 is a diagram illustrating the structure of an image sensor
  • FIG. 7 is a diagram schematically illustrating an example of signal waveforms in a case where an alignment mark has a defect
  • FIG. 8 is a diagram illustrating templates used in detecting alignment-mark position according to a first embodiment of the present invention.
  • FIG. 9 is a diagram illustrating alignment-mark pitch and frequency distribution thereof obtained from the example of the signal waveforms of FIG. 7 ;
  • FIG. 10 is a diagram illustrating an example of placement of an image sensor
  • FIG. 11 is a flowchart illustrating processing for detecting alignment-mark position according to the first embodiment
  • FIG. 12 is a diagram useful in describing global alignment
  • FIG. 13 is a diagram illustrating a linear coordinate transformation and residual error
  • FIG. 14 is a diagram illustrating, in the form of a histogram, a variation 3 ⁇ x(n) in residual error Ri(n) of each line;
  • FIG. 15 is a schematic view illustrating an alignment-mark detecting optical system used in a method of detecting position of an overlay verification mark according to a third embodiment
  • FIG. 16 is a diagram illustrating overlay verification marks according to the third embodiment.
  • FIG. 17 is a diagram exemplifying a two-dimensional image, in which the overlay verification marks of FIG. 16 have been captured by an image sensor, and an intensity distribution of a line signal of every line;
  • FIG. 18 is a diagram illustrating alignment marks acquired in a semiconductor manufacturing process
  • FIG. 19 is a conceptual view showing a semiconductor device production system, which includes the exposure apparatus of this embodiment, as seen from a certain angle;
  • FIG. 20 is a conceptual view showing the semiconductor device production system, which includes the exposure apparatus of this embodiment, as seen from another angle;
  • FIG. 21 shows a specific example of a user interface in the semiconductor device production system that includes the exposure apparatus of this embodiment
  • FIG. 22 is a flowchart useful in describing the flow of a device manufacturing process that uses the exposure apparatus according to this embodiment.
  • FIG. 23 is a diagram useful in describing a wafer process that uses the exposure apparatus according to this embodiment.
  • FIG. 1 is a schematic view illustrating a semiconductor exposure apparatus according to this embodiment of the present invention.
  • a semiconductor exposure apparatus (referred to also as an exposure apparatus below) 1 comprises a projection optical system 11 for demagnifying and projecting a reticle 10 on which a predetermined circuit pattern has been formed; a wafer chuck 13 for holding a wafer 12 on which a base pattern and an alignment mark have been formed by a preceding step; a wafer stage 14 for positioning the wafer 12 at a predetermined position (alignment position); and an alignment detecting optical system (alignment scope) 15 for detecting the position of the alignment mark that has been formed on the wafer 12 .
  • a projection optical system 11 for demagnifying and projecting a reticle 10 on which a predetermined circuit pattern has been formed
  • a wafer chuck 13 for holding a wafer 12 on which a base pattern and an alignment mark have been formed by a preceding step
  • a wafer stage 14 for positioning the wafer 12 at a predetermined position (alignment position)
  • an alignment detecting optical system (alignment scope) 15 for detecting
  • FIG. 2 is a schematic view illustrating the main structural components of the alignment detecting optical system 15 .
  • illuminating light from a light source 18 is reflected by a beam splitter 19 , impinges upon a lens 20 and illuminates an alignment mark 30 on the wafer 12 from the lens 20 .
  • Diffracted light from the alignment mark 30 passes through the lens 20 , beam splitter 19 and a lens 21 and is split by a beam splitter 22 , and the split beams are received by respective ones of image sensors 23 , 24 .
  • the alignment mark 30 is enlarged at an image-forming magnification on the order of 100 ⁇ by the lenses 20 and 21 and the enlarged image is formed on the image sensors 23 , 24 .
  • the image sensors 23 and 24 are used to detect a shift in the position of the alignment mark 30 along the X and Y directions, respectively, and are placed at an angle of approximately 90° with respect to the optic axis.
  • the image sensors 23 , 24 send a signal processor 16 an image pick-up signal obtained by optoelectronically converting the optical image of the alignment mark 30 .
  • the signal processor 16 calculates position information representing the alignment mark 30 .
  • a central processing unit 17 positions the wafer stage 14 so as to correct positional deviation of the wafer based upon the position information calculated by the signal processor 16 .
  • a mark having a shape of the kind shown in FIG. 3 or FIG. 4 is used as the alignment mark 30 .
  • four rectangular marks each having a length of 4 ⁇ m in the X direction, which is the mark detection direction, and a length 20 ⁇ m in the Y direction, which is substantially orthogonal to the mark detection direction, are arrayed at intervals of 20 ⁇ m in the X direction.
  • the cross section of the mark is made concave by etching. In actuality, the mark is coated with a resist, though this is not illustrated.
  • each mark has a shape obtained by forming an edge portion having a line width of 0.6 ⁇ m on the exterior of the marks shown in FIG. 3 .
  • the image information representing the alignment mark thus sensed is processed by the signal processor 16 in the manner described below.
  • FIG. 5 is a diagram illustrating a two-dimensional image of alignment marks
  • FIG. 6 is a diagram illustrating the structure of an image sensor.
  • the image sensors 23 , 24 in this embodiment are CCD cameras each having 512 pixels in the horizontal (X) direction and 60 pixels in the vertical (Y) direction for capturing two-dimensional image information of the alignment mark 30 .
  • Pixel pitch is 24 ⁇ m in both the H (horizontal) and V (vertical) directions. In order to facilitate the description, the number of pixels is
  • the image sensor shown in FIG. 6 includes photodiodes 31 , a vertical transfer CCD 32 , a horizontal transfer CCD 33 and an output circuit 34 .
  • Reference numerals 35 , 36 and 37 denote an A/D converter, a memory and a CPU, respectively.
  • Electric charge resulting from a photo electric conversion by the photodiodes 31 is transferred vertically by the vertical transfer CCD 32 , and such charge is transferred to the horizontal transfer CCD 33 in succession.
  • the charge is transferred horizontally and is output as a sensed-image signal via the output circuit 34 .
  • a sensed-image signal on a line-by-line basis is converted to a digital signal by the A/D converter 35 , after which the digital signal is stored in the memory 36 .
  • the CPU 37 controls CCD drive circuits (not shown) for the vertical and horizontal directions and manages signals in such a manner that the sensed-image signal of each line will correspond to the line number of that line.
  • line signals are acquired, as shown in FIG. 7 , as a light-intensity distribution of each line (in the direction of detection). This serves as two-dimensional image information captured by the image sensor 23 .
  • a template matching method is used to calculate alignment-mark position information according to this embodiment.
  • Template matching calculates the correlation between a sensed-image signal, which represents image information indicated at S in FIG. 8 , and a template (indicated at T in FIG. 8 ) retained beforehand on the apparatus side. Position information exhibiting the highest correlation is detected as the center position of the alignment mark. By obtaining the position of a centroid pixel of an area of several pixels to the left and right of a peak pixel in a function of correlation values illustrated at E in FIG. 8 , a resolution of 1/10 to 1/50 pixel can be achieved.
  • Equation (1) An arithmetic equation used in template matching is represented by Equation (1) below.
  • FIG. 8 illustrates processing relating to image information concerning a single alignment mark among the four alignment marks.
  • the template there has been proposed a method of utilizing the symmetry of the sensed-image signal waveform to fold the left-half portion indicated at S in FIG. 8 with respect to the direction of detection, performing a correlation operation and detecting the alignment-mark position information (e.g., see the specification of Japanese Patent Application Laid-Open No. 8-94315).
  • the calculation of alignment-mark position information is not limited to the template-matching method of this embodiment.
  • each item of position information is detected from each line signal sensed by the image sensor by means of the template matching method.
  • position information X 1 (n), X 2 (n), X 3 (n), X 4 (n) of the alignment marks of each of the lines is found by the template matching method (the units are pixels), where n represents the line number. Thereafter, the average position of the alignment marks is found from Equation (2) below.
  • Xa ( n ) [ X 1( n )+ X 2( n )+ X 3( n )+ X 4( n )]/4 (2)
  • M represents the image forming magnification of the alignment detecting optical system 15 and Px the pixel pitch in the direction in which the alignment marks are detected by the image sensor 23 .
  • FIG. 7 is a diagram schematically illustrating an example of a signal waveform in a case where an alignment mark at the left end of Line No. 3 has a defect.
  • the signal waveform of Line No. 3 has a shape different from those of the other signal waveforms.
  • the pitch (spacing) between neighboring ones of the four alignment marks is used as a criterion.
  • the pitches P 1 ( n ), P 2 ( n ), P 3 ( n ) of the marks are averaged to find Pa(n), an average value Paa of Pa(n) obtained from each line signal is calculated, only line signals for which the deviations from the average value Paa fall within a predetermined range are used, and other line signals are not used.
  • FIG. 9 illustrates alignment-mark pitch and frequency distribution thereof obtained from the line signals of FIG. 7 .
  • line signals outside a standard deviation ⁇ are excluded, as unnecessary lines, from position-deviation detection processing.
  • this embodiment is such that the pixel pitch of the image sensor is made 24 ⁇ m, and a sensor having a very small number of pixels, namely 512 ⁇ 60 pixels, is used as the image sensor.
  • the image sensor is mounted in a particular way. Specifically, as shown in FIG. 10 , the axis along the X′ direction of the image sensor is set at an angle of rotation of ⁇ with respect to the detection direction X of the alignment mark.
  • the rotation angle ⁇ is set to an angle of 20 mrad, which is equivalent to one pixel along the X′ direction, at both ends (equivalent to 50 pixels) of the mark along the non-detection direction (Y direction).
  • a position-shift offset value S(n) is set for every line in dependence upon the rotation angle ⁇ .
  • Each pixel of an image sensor generally has a dark component and there is a variation in the efficiency of the photo electric conversion. It is desirable, therefore, to sense the image of an alignment mark having an ideal, defect-free shape, such as a resist pattern, and acquire the difference between pixels as a correction value beforehand. At such time it is possible to also simultaneously acquire the offset value S(n) of every line that accompanies a difference in angle of rotation between the image sensor and alignment mark.
  • a method of detecting the position of an alignment mark along the X direction has been described above.
  • a similar operation can be performed using the image sensor 24 with regard to detection of the position of an alignment mark along the Y direction (an X-direction alignment mark that has been rotated through 90°).
  • a C-MOS-type sensor can also be used as the image sensor.
  • the alignment mark 30 to be detected on the wafer 12 is positioned below the alignment scope 15 at step S 60 .
  • positional deviation of the wafer 12 is corrected for in advance as by prealignment in such a manner that the alignment mark 30 will fall within the effective visual field of the alignment scope 15 .
  • a two-dimensional image of the alignment mark 30 is acquired by the alignment scope 15 at step S 61 .
  • the two-dimensional image acquired at step S 61 is converted to a light-intensity signal line by line at step S 62 .
  • a selection as to whether each line signal is valid or unnecessary is made at step S 63 .
  • the amount of positional deviation of the alignment mark 30 is calculated using only valid line signals at step S 64 .
  • the signal relating to the defective portion is eliminated effectively and the position of the alignment mark can be detected highly accurately without being influenced by the defect.
  • AGA Global alignment
  • FIG. 12 illustrates the manner in which an array of shots on a wafer has deviated with respect to the xy coordinate system of the wafer stage in the above-described exposure apparatus 1 .
  • the deviation in the position of the wafer can be described by six parameters, namely shift Sx in the x direction, shift Sy in the y direction, inclination ⁇ x with respect to the x axis, inclination ⁇ y with respect to the y axis, magnification Bx along the x direction and magnification By along the y direction.
  • the magnifications Bx By represent expansion and contraction of the wafer with the direction in which the wafer stage of the exposure apparatus is fed serving as a reference. This expansion and contraction of the wafer is caused by film formation and etching in the semiconductor process.
  • FIG. 13 illustrates the manner in which the linear coordinate transformation of Equation (8) is performed.
  • An alignment mark on a wafer is located at the position indicated by W in FIG. 13 . This is a deviation of Ai from the position of point M, which is the designed position. If the coordinate transformation D′i is carried out, the positional deviation (residual error) of the alignment mark on the wafer is calculated using Equation (9) b low.
  • Ri ( Di+Ai ) ⁇ D′i (9)
  • the method of least squares is applied so as to minimize the residual error Ri of each sample shot, and AGA parameters (Sx, Sy, ⁇ x, ⁇ y, Bx, By) that will minimize the mean sum of the squares of the residual error Ri are calculated.
  • the AGA parameters (Sx, Sy, ⁇ x, ⁇ y, Bx, By) are found by substituting the position information (xi,yi) of the alignment mark of each sample shot and the alignment-mark designed position (Xi,Yi) into Equations (10) and (11) cited above, positioning of each shot is performed upon correcting for positional deviation based upon these AGA parameters, and the pattern on the reticle is transferred to the wafer by exposure.
  • This embodiment is applied to alignment in a semiconductor exposure apparatus in a manner similar to that of the first embodiment.
  • the method of selecting valid and unnecessary lines after acquisition of the two-dimensional image differs from that of the first embodiment.
  • the pitch of alignment marks is utilized in the method of detecting valid lines.
  • the residual error Ri of AGA calculated from the AGA parameters is utilized.
  • the structures of the exposure apparatus, alignment-mark detecting optical system and alignment mark are the same as those of the first embodiment and need not be described again.
  • a two-dimensional image of the alignment mark 30 on the wafer 12 is acquired for all sample shots of AGA.
  • the alignment-mark position information X 1 ( n ), X 2 ( n ), X 3 ( n ), X 4 ( n ) of each line is found by the template matching method (the units are pixels).
  • alignment-mark position information Xai(n) along the X direction is calculated from each line signal of every shot in accordance with Equation (2), where the subscript i represents the shot number.
  • Alignment-mark position information Yai(n) along the Y direction is calculated in similar fashion.
  • a variation 3 ⁇ x(n) in the residual error Ri(n) is calculated for every line.
  • FIG. 14 is a diagram illustrating, in the form of a histogram, a variation 3 ⁇ x(n) in residual error Ri(n) of each line.
  • a line signal indicative of an abnormality such as a defect in an alignment mark
  • the result obtained will be as if the array of shots has shifted from a straight line and, hence, a large residual error is obtained. Only line signals for which the residual error is less than a predetermined threshold value are deemed to be valid, and line signals for which the residual error exceeds the threshold value are judged to be unnecessary line signals.
  • the amount of positional deviation of each shot is found from Equation (5) using only the results of signal processing applied to valid line signals, the final AGA parameters (Sx, Sy, ⁇ x, ⁇ y, Bx, By) are found from the positional deviation and Equations (10), (11), positioning of each shot is performed upon correcting for positional deviation based upon these AGA parameters, and the pattern on the reticle is transferred to the wafer by exposure.
  • the above-mentioned threshold value is made a value that is twice the positioning reproducibility precision of the wafer stage in this exposure apparatus.
  • first and second embodiments may be viewed from a different standpoint. Specifically, in the first embodiment, unnecessary line signals are discriminated using only alignment marks within one shot, whereas in the second embodiment, use is made of line signals of alignment marks in a number of shots on a wafer. Conversely, in the first embodiment, it is required that a plurality of patterns of identical shape be arrayed at a specific pitch as the alignment marks. In the second embodiment, however, a single rectangular pattern suffices and a unique advantage is that the area occupied by alignment marks in a shot is reduced.
  • the exposure apparatus 1 illustrated in the first and second embodiments is exemplified as one having a demagnifying projection optical system.
  • the exposure apparatus is not limited to such an arrangement.
  • the present invention is applicable to an X-ray exposure apparatus in which X rays serve as the exposing light source and a pattern on a mask is projected at a ratio of 1:1, and to an electron-beam exposure apparatus in which a plurality of shots are written on a wafer by an electron beam.
  • a third embodiment will now be described with regard to a method of detecting the position of an overlay verification mark.
  • This method is for verifying the accuracy (overlay accuracy) of the position of a circuit pattern in a succeeding step relative to the position of an already existing pattern on a wafer.
  • FIG. 15 is a schematic view illustrating the main components of an alignment-mark detecting optical system used in a method of detecting position of an overlay verification mark according to the third embodiment. Components identical with those of the first embodiment are designated by like reference characters.
  • the alignment detecting optical system of the third embodiment is used in an apparatus for verifying the accuracy (overlay accuracy) of the position of a circuit pattern in a succeeding step relative to the position of an already existing pattern on a wafer. Illuminating light from the light source 18 is reflected by the beam splitter 19 , impinges upon the lens 20 and illuminates an overlay verification mark 50 on the wafer 12 from the lens 20 . Diffracted light from the overlay verification mark 50 passes through the lens 20 , beam splitter 19 and lens 21 and is split by the beam splitter 22 , and the split beams are received by respective ones of the image sensors 23 , 24 .
  • the overlay verification mark 50 is enlarged at an image-forming magnification on the order of 100 ⁇ by the lenses 20 and 21 and the enlarged image is formed on the image sensors 23 , 24 .
  • the image sensors 23 and 24 are used to detect a shift in the position of the overlay verification mark 50 along the X and Y directions, respectively, and are placed at an angle of approximately 90° with respect to the optic axis.
  • the wafer 12 is held on a wafer chuck 51 , and the wafer chuck 51 is so adapted that the wafer 12 can be positioned relative to the alignment detecting optical system 15 by an XY stage 52 .
  • Marks 50 a , 50 b shown in FIG. 16 are used as the overlay verification mark 50 .
  • two rectangular marks each having a length of 1 ⁇ m in the X direction, which is the mark detection direction, and a length 15 ⁇ m in the Y direction, which is substantially orthogonal to the mark detection direction, are arrayed at a spacing of 20 ⁇ m in the X direction as a base mark 50 a indicating a layer position of a step preceding a semiconductor manufacturing step.
  • two rectangular marks each having a length of 1 ⁇ m in the X direction and a length 7 ⁇ m in the Y direction are arrayed at a pitch of 10 ⁇ m inwardly of the base marks 50 a as a mark 50 b indicating the present layer position after positioning has been performed with respect to the mark 50 a of the preceding step.
  • the base mark 50 a is an etching mark that has been fabricated by a semiconductor process
  • the mark 50 b indicating the present layer position is a resist pattern.
  • a deviation in the position of the present layer with respect to the layer of the preceding step is found by detecting amount of shift (dx,dy) in the center position of the two rectangular marks with respect to the center of the two rectangular marks 50 a.
  • FIG. 17 exemplifies a two-dimensional image, in which the overlay verification marks of FIG. 16 have been captured by the image sensor 23 , and an intensity distribution of a line signal of every line.
  • Position information [X 1 ( n ), X 2 ( n ), X 3 ( n ), X 4 ( n ) from the left, where n represents the line number] is detected with regard to line signals 50 a ′ of the base marks 50 a by a template T 1 and with regard to line signals 50 b ′ of the resist patterns 50 b by a template T 2 .
  • an average value P 1 a of P 1 ( n ) and an average value P 2 a of P 2 ( n ) acquired from each line signal are calculated, use is made only of line signals for which the deviation from the average value falls within a predetermined range, and the line signals of other lines are deemed unnecessary, as in the first embodiment.
  • positional deviation along the Y direction can be detected by eliminating unnecessary lines using a two-dimensional image that has been detected by the image sensor 24 whose optic axis has been rotated by approximately 90° with respect to the optic axis of the image sensor 23 .
  • the correction parameters (Sx, Sy, ⁇ x, ⁇ y, Bx, By) thus found become global alignment error of the exposure apparatus that exposes this wafer, and the residual error Ri corresponds to a value that is twice the positioning reproducibility precision of the wafer stage of the exposure apparatus. Furthermore, in a case where a mark has a defect, this can be judged by the fact that the residual error Ri exceeds the value that is twice the positioning reproducibility precision of the wafer stage.
  • the residual error Ri is calculated with regard to each line of the image sensor, a value that is twice the positioning reproducibility precision of the wafer stage in a exposure apparatus that performs exposure evaluation is adopted as a threshold value, line signals for which this value is exceeded are judged to be unnecessary, and the average value of amount of positional deviation calculated with regard to the remaining valid line signals may be adopted as the result of detection.
  • This system utilizes a computer network outside the semiconductor manufacturing plant to provide troubleshooting and regular maintenance of manufacturing equipment installed at the manufacturing plant and to furnish maintenance service such as the provision of software.
  • FIG. 19 illustrates the overall system as seen from a certain angle.
  • the system includes the business office 101 of the vendor (equipment supplier) that provides the equipment for manufacturing semiconductor devices.
  • Semiconductor manufacturing equipment for various processes used in a semiconductor manufacturing plant is assumed to be the manufacturing equipment. Examples of the equipment are pre-treatment equipment (lithographic equipment such as exposure equipment, resist treatment equipment and etching equipment, heat treatment equipment, thin-film equipment and flattening equipment, etc.) and post-treatment equipment (assembly equipment and inspection equipment, etc.).
  • the business office 101 includes a host management system 108 for providing a manufacturing-equipment maintenance database, a plurality of control terminal computers 110 , and a local-area network (LAN) 109 for connecting these components into an intranet.
  • the host management system 108 has a gateway for connecting the LAN 109 to the Internet 105 , which is a network external to the business office 101 , and a security function for limiting access from the outside.
  • Numerals 102 to 104 denote manufacturing plants of semiconductor makers which are the users of the manufacturing equipment.
  • the manufacturing plants 102 to 104 may be plants belonging to makers that differ from one another or plants belonging to the same maker (e.g., pre-treatment plants and post-treatment plants, etc.).
  • Each of the plants 102 to 104 is provided with a plurality of pieces of manufacturing equipment 106 , a local-area network (LAN) 111 which connects these pieces of equipment to construct an intranet, and a host management system 107 serving as a monitoring unit for monitoring the status of operation of each piece of manufacturing equipment 106 .
  • LAN local-area network
  • the host management system 107 provided at each of the plants 102 to 104 has a gateway for connecting the LAN 111 in each plant to the Internet 105 serving as the external network of the plants.
  • the LAN of each plant it is possible for the LAN of each plant to access the host management system 108 on the side of the vendor 101 via the Internet 105 .
  • users allowed to access the host management system 108 are limited. More specifically, status information (e.g., the condition of manufacturing equipment that has malfunctioned), which indicates the status of operation of each piece of manufacturing equipment 106 , can be reported from the plant side to the vendor side.
  • information in response to such notification can be acquired from the vendor side.
  • a communication protocol (TCP/IP), which is used generally over the Internet, is employed for data communication between the plants 102 ⁇ 104 and the vendor 101 and for data communication over the LAN 111 within each plant.
  • TCP/IP communication protocol
  • the host management system is not limited to that provided by a vendor, for an arrangement may be adopted in which the user constructs a database, places it on an external network and allows the database to be accessed from a number of plants that belong to the user.
  • FIG. 20 is a conceptual view illustrating the overall system of this embodiment as seen from an angle different from that depicted in FIG. 19 .
  • a plurality of user plants each having manufacturing equipment are connected by an external network to the management system of the vendor that provided the manufacturing equipment, and information concerning the production management of each plant and information concerning at least one piece of manufacturing equipment is communicated by data communication via the external network.
  • a plant having manufacturing equipment provided by a plurality of vendors is connected by an outside network to management systems of respective ones of the vendors of these plurality of pieces of manufacturing equipment, and maintenance information for each piece of manufacturing equipment is communicated by data communication.
  • the system includes a manufacturing plant 201 of the user of manufacturing equipment (the maker of semiconductor devices).
  • the manufacturing line of this plant includes manufacturing equipment for implementing a variety of processes. Examples of such equipment are exposure equipment 202 , resist treatment equipment 203 and thin-film treatment equipment 204 . Though only one manufacturing plant 201 is shown in FIG. 20 , in actuality a plurality of these plants are networked in the same manner.
  • the pieces of equipment in the plant are interconnected by a LAN 206 to construct an intranet and the operation of the manufacturing line is managed by a host management system 205 .
  • the business offices of vendors such as an exposure equipment maker 210 , resist treatment equipment maker 220 and thin-film treatment equipment maker 230 have host management systems 211 , 221 , 231 , respectively, for remote maintenance of the equipment they have supplied. These have maintenance databases and gateways to the outside network, as described earlier.
  • the host management system 205 for managing each piece of equipment in the manufacturing plant of the user is connected to the management systems 211 , 221 , 231 of the vendors of these pieces of equipment by the Internet or leased-line network serving as an external network 200 . If any of the series of equipment in the manufacturing line malfunctions, the line ceases operating. However, this can be dealt with rapidly by receiving remote maintenance from the vendor of the faulty equipment via the Internet 200 , thereby making it possible to minimize line downtime.
  • Each piece of manufacturing equipment installed in the semiconductor manufacturing plant has a display, a network interface and a computer for executing network-access software and equipment operating software stored in a storage device.
  • the storage device can be an internal memory or hard disk or a network file server.
  • the software for network access includes a special-purpose or general-purpose Web browser and presents a user interface, which has a screen of the kind shown by way of example in FIG. 21 , on the display. The operator managing the manufacturing equipment at each plant enters information at the input items on the screen while observing the screen.
  • the information includes model 401 of the manufacturing equipment, its serial number 402 , subject matter 403 of the problem, its date of occurrence 404 , degree of urgency 405 , the particular condition 406 , countermeasure method 407 and progress report 408 .
  • the entered information is transmitted to the maintenance database via the Internet.
  • the resulting appropriate maintenance information is sent back from the maintenance database and is presented on the display screen.
  • the user interface provided by the Web browser implements hyperlink functions 410 , 411 , 412 as illustrated and enables the operator to access more detailed information for each item, to extract the latest version of software, which is used for the manufacturing equipment, from a software library provided by the vender, and to acquire an operating guide (help information) for reference by the plant operator.
  • the maintenance information provided by the maintenance database also includes information relating to the present invention described above, and the above-mentioned software library also provides the latest software for implementing the present invention.
  • FIG. 22 illustrates the overall flow of a process for manufacturing a semiconductor device.
  • the circuit for the device is designed at step S 1 (circuit design).
  • a mask on which the designed circuit pattern has been formed is fabricated at step S 2 (mask fabrication).
  • a wafer is manufactured using a material such as silicon or glass at step S 3 (wafer manufacture).
  • the actual circuit is formed on the wafer by lithography, using the mask and wafer that have been prepared, at step S 4 (wafer process), which is also referred to as “pre-treatment”.
  • a semiconductor chip is obtained, using the wafer fabricated at step S 4 , at step S 5 (assembly), which is also referred to as “post-treatment”.
  • This step includes steps such as assembly (dicing and bonding) and packaging (chip encapsulation).
  • the semiconductor device fabricated at step S 5 is subjected to inspections such as an operation verification test and durability test at step S 6 (inspection).
  • the semiconductor device is completed through these steps and then is shipped (step S 7 ).
  • the pre- and post-treatments are performed at separate special-purpose plants. Maintenance is carried out on a per-plant basis by the above-described remote maintenance system. Further, information for production management and equipment maintenance is communicated by data communication between the pre- and post-treatment plants via the Internet or leased-line network.
  • FIG. 23 is a flowchart illustrating the detailed flow of the wafer process mentioned above.
  • the surface of the wafer is oxidized at step S 11 (oxidation).
  • An insulating film is formed on the wafer surface at step S 12 (CVD), electrodes are formed on the wafer by vapor deposition at step S 13 (electrode formation), and ions are implanted in the wafer at step S 14 (ion implantation).
  • the wafer is coated with a photoresist at step S 15 (resist treatment), the wafer is exposed to the circuit pattern of the mask to print the pattern onto the wafer by the above-described exposure apparatus at step S 16 (exposure), and the exposed wafer is developed at step S 17 (development).
  • Portions other than the developed photoresist are etched away at step S 18 (etching), and unnecessary resist left after etching is performed is removed at step S 19 (resist removal).
  • Multiple circuit patterns are formed on the wafer by implementing these steps repeatedly. Since the manufacturing equipment used at each step is maintained by the remote maintenance system described above, malfunctions can be prevented and quick recovery is possible if a malfunction should happen to occur. As a result, the productivity of semiconductor device manufacture can be improved over the prior art.

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
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  • Length Measuring Devices By Optical Means (AREA)
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