US6734058B2 - Method for fabricating a semiconductor device - Google Patents

Method for fabricating a semiconductor device Download PDF

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Publication number
US6734058B2
US6734058B2 US10/329,587 US32958702A US6734058B2 US 6734058 B2 US6734058 B2 US 6734058B2 US 32958702 A US32958702 A US 32958702A US 6734058 B2 US6734058 B2 US 6734058B2
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Prior art keywords
forming
layer
contact hole
semiconductor device
fabricating
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US10/329,587
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English (en)
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US20030124804A1 (en
Inventor
Cheol Soo Park
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Cavium International
Marvell Asia Pte Ltd
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Dongbu Electronics Co Ltd
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Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARK, CHEOL SOO
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Assigned to DONGBUANAM SEMICONDUCTOR INC. reassignment DONGBUANAM SEMICONDUCTOR INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU ELECTRONICS CO., LTD.
Assigned to INPHI CORPORATION reassignment INPHI CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU HITEK, CO., LTD.
Assigned to INPHI CORPORATION reassignment INPHI CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: DONGBU HITEK, CO., LTD.
Assigned to MARVELL TECHNOLOGY CAYMAN I reassignment MARVELL TECHNOLOGY CAYMAN I ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INPHI CORPORATION
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Assigned to MARVELL ASIA PTE LTD. reassignment MARVELL ASIA PTE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAVIUM INTERNATIONAL
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation

Definitions

  • the present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device having a cylinder type transistor.
  • an MOS transistor generally belongs to a category of insulated gate field effect transistors (FET) and uses electrons induced on the surface of a silicon substrate opposing a metal (typically polysilicon) gate material in the structure of an MOS (metal oxide semiconductor) capacitor as electrical currents.
  • FET insulated gate field effect transistors
  • MOS metal oxide semiconductor
  • the MOS transistor is essentially a majority carrier device, and it has a good characteristic as regards its high frequency activation and has advantages in that driving is easy and the circuit design can be simplified due to the electrical insulation of a gate by an insulating layer such as a gate oxide layer.
  • a gate oxide layer 3 is formed on a semiconductor device wherein a field oxide layer has been formed, and a gate electrode 4 is formed on a desired part of the gate oxide layer 3 .
  • low concentration impurities are implanted into the semiconductor substrate by using the gate electrode 4 as an ion implantation mask, thereby forming a low concentration impurity region 5 .
  • a spacer is formed so that an insulating layer remains at both sides of the gate electrode 4 , by a blanket etching process.
  • a source/drain region is formed by implanting high concentration impurity into the exposed substrate with using the gate electrode 4 and the spacer 6 as ion implantation masks thereby accomplishing the transistor.
  • an object of the present invention is to provide a method for fabricating a highly integrated semiconductor device wherein a vertical cylinder type transistor has been formed inside of an epitaxial silicon layer of a cylinder type.
  • a method for fabricating a semiconductor device comprising the steps of: forming an insulating layer and a nitride layer sequentially on a semiconductor substrate; selectively removing the insulating layer and the nitride layer, resulting in the formation of a first contact hole; forming a silicon layer in the first contact hole after the removal of a part of the insulating layer at the side walls of the first contact hole; forming a trench through selective removal of the silicon layer; forming a source region in the semiconductor substrate and a drain region on an upper part of the trench, after the removal of the nitride layer; forming a gate oxide layer and gates sequentially at the side walls of the trench; forming a planarization layer on the resultant structure to fill the trench; forming a second contact hole that exposes the gate, the drain region, and the source region through selective patterning the resultant structure; and forming plugs in the exposed second contact hole.
  • FIG. 1 is a cross-sectional view for illustrating a method for fabricating a semiconductor device in accordance with a conventional art
  • FIGS. 2 a to 2 e are cross-sectional views for illustrating each step of a method for fabricating a semiconductor device in accordance with the present invention
  • FIG. 3 is a planar view showing the method for fabricating a semiconductor device in accordance with the present invention.
  • FIGS. 2 a to 2 e are cross-sectional views for illustrating each step of a method for fabricating a semiconductor device in accordance with the present invention
  • FIG. 3 is a planar view showing the fabricating method for fabricating a semiconductor device in accordance with the present invention.
  • an insulating layer 20 made of oxide layer is thermally grown to a thickness D of some thousands of A on a semiconductor substrate 10 made of semiconductor material such as silicon (Si) by a wet oxidation process.
  • a nitride layer 30 is deposited on the thermally grown insulating layer 20 and a mask pattern is formed on the nitride layer 30 , then the nitride layer 30 and the insulating layer 20 are selectively removed through a dry etch process using the mask pattern.
  • a first contact hole 45 is formed on the semiconductor substrate 10 , and the insulating layer 20 is controlled to remain in the first contact hole 45 to a thickness d of some tens to some hundreds of ⁇ during the dry etching process. This is because if the surface of the semiconductor substrate 10 has been exposed during the dry etching process, the exposed surface functions as a defect source.
  • a part of the insulating layer 20 remained in the first contact hole 45 is removed through a wet etching process, and simultaneously a part of the insulating layer 20 positioned below the nitride layer 30 is removed.
  • an epitaxial layer 50 e.g. an epitaxial silicon layer, is formed to entirely fill the inside of the first contact hole 45 by doping impurities at an in-situ.
  • the epitaxial silicon layer 50 is removed selectively by employing the nitride layer 30 as a hard mask and using a high etch selection rate of dry etching for the nitride layer with respect to the epitaxial silicon layer.
  • the epitaxial silicon layer 50 below the nitride layer 30 is left and the exposed epitaxial silicon layer 50 that was not protected by the nitride layer 30 is etched, thereby forming a trench 47 .
  • the surface of the semiconductor substrate 10 inside of the first contact hole 45 is etched to a desired depth, e.g., some hundreds of ⁇ during the etching process.
  • the nitride layer 30 that has been used as the hard mask is removed with a hot phosphoric etchant, and an ion implanting process is performed to the surface of the semiconductor substrate 10 in order to form a source/drain region.
  • a source region 60 a is formed below the surface of the semiconductor substrate 10 in the trench 47 , and simultaneously a drain region 60 b is formed on the epitaxial silicon layer 50 .
  • a gate oxide layer 70 is formed to a thickness of some tens of ⁇ after the formation of a sacrificial oxide layer in the trench 47 and selective removal of the sacrificial oxide layer, and then gates 80 made of metal having a good electrical conductivity are formed vertically to oppose the epitaxial silicon layer 50 while interposing the gate oxide layer 70 in the trench 47 .
  • a thermal oxide layer has been grown at the source region 60 a and the drain region 60 b of more than 5 times than at the gate oxide layer 70 due to doping over about 10 15 , and although a sacrificial oxidation is performed, the oxide layer has been grown in the vicinity of the source region 60 a and the drain region 60 b to a thickness of some hundreds of ⁇ .
  • a threshold voltage Vt
  • a PSG phospho-silicate glass
  • a BSG boro-silicate glass
  • the threshold voltage may be controlled by means of the annealing temperature or the length of annealing time.
  • the PSG or the BSG is easily removed with little thermal oxide loss during the process of pre-cleaning of the gate oxide layer, because PSG and BSG have a wet etch selection rate being several tens of that of the thermal oxide layer.
  • an insulating layer is deposited thickly to fill the trench 47 , and a chemical-mechanical polishing (CMP) process is performed, resulting in the formation of a planarization layer 90 .
  • CMP chemical-mechanical polishing
  • a second contact hole is formed by selective removal of the planarization layer 90 , and a plurality of plugs 100 a , 100 b , 100 c are formed to fill the second contact hole.
  • a gate plug 100 a interconnecting the gate 80 , a source plug 100 b interconnecting the source region 60 a , and a drain plug 100 c interconnecting the drain region 60 b are formed.
  • the semiconductor device is accomplished by performing the predetermined following processes.
  • gate lines connected by the gate plug 100 a are configured to form a rectangle extended vertically
  • drain lines connected by the drain plug 100 b are configured to form a rectangle extending horizontally in a semiconductor device fabricated by the process of the present invention described above.
  • the gate 80 is constructed to include the planarization layer 90 and configured to be surrounded by the epitaxial layer 50 defining an active region and a field layer, and a plurality of patterns configured in a rectangular form are formed on the semiconductor substrate 10 .
  • a highly integrated semiconductor device can be produced through forming a cylindrical epitaxial silicon layer on the substrate and arranging a vertical cylinder type transistor at inside of the epitaxial silicon layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US10/329,587 2001-12-29 2002-12-26 Method for fabricating a semiconductor device Expired - Lifetime US6734058B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2001-88235 2001-12-29
KR10-2001-0088235A KR100406578B1 (ko) 2001-12-29 2001-12-29 반도체 소자의 제조방법

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US20030124804A1 US20030124804A1 (en) 2003-07-03
US6734058B2 true US6734058B2 (en) 2004-05-11

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Country Status (4)

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US (1) US6734058B2 (ko)
JP (1) JP2003289142A (ko)
KR (1) KR100406578B1 (ko)
DE (1) DE10261404B4 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070215940A1 (en) * 2006-03-16 2007-09-20 Spansion Llc Vertical semiconductor device
US20090085102A1 (en) * 2007-09-27 2009-04-02 Elpida Memory, Inc. Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8193612B2 (en) 2004-02-12 2012-06-05 International Rectifier Corporation Complimentary nitride transistors vertical and common drain
JP4393260B2 (ja) * 2004-04-20 2010-01-06 株式会社東芝 エッチング液管理方法
KR100541515B1 (ko) 2004-07-22 2006-01-11 삼성전자주식회사 수직 채널 패턴을 갖는 반도체 장치 및 이를 제조하는 방법
KR100673105B1 (ko) * 2005-03-31 2007-01-22 주식회사 하이닉스반도체 반도체 소자의 수직형 트랜지스터 및 그의 형성 방법
JP4746600B2 (ja) 2007-11-01 2011-08-10 シャープ株式会社 縦型ｍｏｓｆｅｔの製造方法
KR100971411B1 (ko) * 2008-05-21 2010-07-21 주식회사 하이닉스반도체 반도체 장치의 수직 채널 트랜지스터 형성 방법
CN105448989B (zh) * 2014-08-26 2018-12-25 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
WO2017085788A1 (ja) * 2015-11-17 2017-05-26 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置及び半導体装置の製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291438A (en) * 1992-03-23 1994-03-01 Motorola, Inc. Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell
US5382816A (en) 1992-07-03 1995-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having vertical transistor with tubular double-gate
US5547889A (en) 1994-03-28 1996-08-20 Samsung Electronics Co. Ltd. Method of forming a semiconductor device having vertical conduction transistors and cylindrical cell gates
US5872037A (en) * 1995-06-20 1999-02-16 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing a vertical mosfet including a back gate electrode
US6075265A (en) * 1997-06-27 2000-06-13 Siemens Aktiengesellschaft DRAM cell arrangement and method for its fabrication
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03187272A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ及びその製造方法
DE4300806C1 (de) * 1993-01-14 1993-12-23 Siemens Ag Verfahren zur Herstellung von vertikalen MOS-Transistoren
JP3371708B2 (ja) * 1996-08-22 2003-01-27 ソニー株式会社 縦型電界効果トランジスタの製造方法
KR100390920B1 (ko) * 2001-10-15 2003-07-12 주식회사 하이닉스반도체 다중채널을 갖는 수직 구조 트랜지스터 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291438A (en) * 1992-03-23 1994-03-01 Motorola, Inc. Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell
US5382816A (en) 1992-07-03 1995-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having vertical transistor with tubular double-gate
US5547889A (en) 1994-03-28 1996-08-20 Samsung Electronics Co. Ltd. Method of forming a semiconductor device having vertical conduction transistors and cylindrical cell gates
US5872037A (en) * 1995-06-20 1999-02-16 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing a vertical mosfet including a back gate electrode
US6075265A (en) * 1997-06-27 2000-06-13 Siemens Aktiengesellschaft DRAM cell arrangement and method for its fabrication
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070215940A1 (en) * 2006-03-16 2007-09-20 Spansion Llc Vertical semiconductor device
US7859026B2 (en) * 2006-03-16 2010-12-28 Spansion Llc Vertical semiconductor device
US20090085102A1 (en) * 2007-09-27 2009-04-02 Elpida Memory, Inc. Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system
US8735970B2 (en) * 2007-09-27 2014-05-27 Yoshihiro Takaishi Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system

Also Published As

Publication number Publication date
DE10261404A1 (de) 2003-07-10
KR100406578B1 (ko) 2003-11-20
JP2003289142A (ja) 2003-10-10
US20030124804A1 (en) 2003-07-03
DE10261404B4 (de) 2010-10-14
KR20030059375A (ko) 2003-07-10

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