US3858197A - Device for controlling display output by micro-program - Google Patents
Device for controlling display output by micro-program Download PDFInfo
- Publication number
- US3858197A US3858197A US00303013A US30301372A US3858197A US 3858197 A US3858197 A US 3858197A US 00303013 A US00303013 A US 00303013A US 30301372 A US30301372 A US 30301372A US 3858197 A US3858197 A US 3858197A
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- United States
- Prior art keywords
- digit
- numeric
- information
- input terminals
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
Definitions
- the present invention relates to a device for controlling, by the micro-program stored in a read-only memory, the display outputs, which are stored in a register, to be displayed by a display unit of a desk top calculator, or the like.
- the recent large scale integrated circuits make it possible to design desk top calculators very compact in size and light in weight.
- the large scale integrated circuits consisting of, for example, MOS transistors are used in the memory, arithmetic unit, arithmetic operation convtrol unit, output control unit and the like in such desk top calculators.
- the control unit generally occupies the largest space, whereas the memory occupies the smallest space, because the former generally comprises a plurality of gates and a'plurality of flip-flops, whereas the latter comprises only a shift register or matrix, which is best adapted to be manufactured as a large scale integrated circuit.
- the present invention is directed to incorporating a display output control unit for deriving the numeric information stored in an indicating register and a digit information signal generating unit in a control unit, thereby making full use of the advantages of the large scale integrated circuits.
- the present invention further intends to provide a device for controlling the numeric information output stored in an indicating register by the micro-program stored in a read-only memory.
- a display unit of the type comprising a plurality of gaseous-discharge lamps, or the like, which are arrayed and turned on to dynamically display the numeric information.
- the digit pulses having a predetermined pulse width, must be applied to the display unit so that there must be provided a first counter for counting the clock pulses generated by a clock pulse generator, a second counter for counting one for every four output signals from the first counter and a digitpulse generator.
- a first counter for counting the clock pulses generated by a clock pulse generator
- a second counter for counting one for every four output signals from the first counter
- a digitpulse generator As a result the number of component parts is considerably increased, and the period of the digit pulse is limited to that of the clock pulse, because the digit pulse generator is generally actuated in response to the clock pulses.
- the clock pulses also determine the speed of the arithmetic operations so that the period of the clock pulses must be shortened in order to increase the speed of operation.
- the period of the clock pulses is shortened, the period of the digit pulses is also shortened so that digit pulses, having a sufficient pulse width to dynamically turn on the indicating lamps or the like, cannot be obtained. That is, when the operation speed is increased. the ON time of the indicating lamp becomes shorter so that a display, with a desired brightness, cannot be attained because of the delay in discharge, or the like. Therefore, unless a specially designed digit pulse generator and an indicating lamp driving circuit for turning on the indicating lamp with a desired brightness are provided,
- a circuit for supressing the insignificant zeros or digits, as well as a circuit for displaying a decimal point may be designed, compact in size and simple in construction.
- FIG. 1 is a fundamental block diagram of one preferred embodiment of the present invention
- FIG. 2 is a detailed circuit diagram of the device shown in FIG. 1;
- FIG. 3 is a flow chart of the commands stored in a read-only memory
- FIG. 4 is a circuit diagram of one example of a readonly memory; and 7 FIG. 5 shows the waveforms of the command signals derived from the read-only memory.
- FIG. 1 there is illustrated in block diagram from a preferred embodiment of the present invention, that includes a read-only memory 11 in wlii cliis stored output control commands and digit information in the form of micro-commands.
- micro-commands is used to refer to those simple and fundamental commands, the combinations of which constitute the micro-commands such as ADD, DIVIDE, PRINT, etc.
- the readonly memory 11 may comprise a diode matrix.
- the digit information from the read-only memory 11 is temporarily stored in a digit information buffer memory 12.
- a display unit 13 comprises an array of indicating .lamps in the instant embodiment, but any other suitable indicating device such as photo-diodes or liquid crystal may be used. Alternatively, a printer may be used instead of the display unit 13 when the content stored in the read-only memory 11 is appropriately changed.
- the numeric information to be displayed which is stored in an indicating register 15, is temporarily stored in a numeric information, buffer memory 14 so as to be applied to cathode segments in the display unit 13.
- a digit having a decimal point is detected in the numeric information stored in the indicating register 15 and is temporarily stored in a decimal point buffer memory 16.
- the decimal point information is compared by a coindidence circuit'l7 with the digit information from the digit information buffer memory 12 so that when they coincide with each other the decimal point may be displayed by the display unit 13.
- the various arithmetic operations carried by an arithmetic unit 18 are controlled by the information derived from the read-only memory 11.
- the numeric information entered by a keyboard (not shown) of a desk top calculator, or the result of the arithmetic operations is transferred from the arithmetic unit 18 and stored in the indicating register 15, in which the numeric information is shifted to right in the ordinary manner, that is, from the most significant digit to the least significant digit.
- the numeric information in the indicating register is derived digit by digit from the most significant digit.
- the numeric information in the indicating register 15 is transferred from the most significant digit into the numeric information buffer memory 14. The above method is very effective for suppressing the zero.
- the prior art control circuit used for this method is generally large in size and complex in construction.
- the numeric information stored in the indicating register 15 is detected from the most significant digit by the read-only memory so that the circuit may be made extremely compact in size.
- the numeric information in the indicating register 15 is transferred digit by digit from the most significant digit into the numeric information buffer memory l4 in response to the timing signals from the rend-only memory 11. For example, when the numeric information in the n-th digit is transferred into the numeric information buffer 14, it is decoded to energizes, selectively, predetermined numeral pattern segments out of the cathode segments in the display unit 13. Thereafter, the nth digit information is transferred into the digit information buffer 12 from the read-only memory 11 so that the anode of the n-th digit in the display unit 13 is energized.
- the ON time of the indicating lamp in the n-th digit may be freely adjusted depending upon the content in the read-only memory 11. For example, the ON time may be twoor three-digit time interval or oneword time interval during which the numeric informa tion in the indicating register makes one circulation.
- the numeric information in the (n l th digit is transferred from the indicating register 15 into the numeric information buffer 14 so that the predetermained numeral pattern segments in the display unit 13 are energized.
- the digit information from the read-only memory 11 is transferred into the digit information buffer memory 12 so that the anode in the (n l th digit may be energized.
- the indicating lamp in the (n 1) th digit is turned on.
- the indicating lamps in all digit positions are turned on sequentially, and thereafter they are turned on again from the one in the most significant digit so that the numeric information stored in the indicating register 15 may be dynamically indicated.
- the decimal point information stored in the indicating register 15 is transferred into the decimal point information buffer memory 16 in response to the control signal from the read-only memory 11, and then transferred into the coindidence circuit 17.
- the coincidence circuit 17 gives the coincidence signal to the display unit 13, thereby causing the latter to display the decimal point at the predetermined digit.
- the digit information buffer memory 12 comprises a group of AND gates 12 and a group of flip-flops 12
- the dis play unit 13 comprises an anode driver 13AD, a display unit part (1) 13A, a cathode driver 13K and a display unit part (2) 13K.
- the binary coded 4-bit decimal digit information is applied to the anode driver 13A, which, in turn, gives the output signals equal in number to the digits to be displayed by the display unit part (1) 13A.
- the anode driver 13A when the display unit 13 has 16 digits, the anode driver 13A generates 16 output signals to be applied sequentially to the 16 anodes in the display unit part (1) 13A.
- the anode driver 13A generally comprises a decoder and an amplifier.
- the display unit part (1) 13A comprises a plurality of anodes equal in number to the digits to be displayed in the display unit.
- a very flexible output control system may be provided because the pulse application time interval may be changed appropriately only by changing the content in the read-only memory 11.
- the optimum pulse application time may be selected depending upon the indicating means used in the display unit 13 such as photo-diodes or liquid crystal for example.
- the output control system in accordance with the present invention is advantageous because the digit information may be selectively applied for every three or four digits in order to ensure that all of the indicating lamps in the display unit 13 may be turned on.
- the cathode driver 13K In response to the binary-coded four-bit decimal digit information, the cathode driver 13K selectively energizes the predetermined cathode segments. For example, when the cathode segments are those of a-seven-bar format or pattern, the cathode driver 13K generally comprises a binary-decimal decoder and a decimal-septimal encoder.
- the decimal point information buffer memory 16 comprises a group of AND gates 16 and a group of flip-flops 16 which store the decimal point information supplied from the indicating register.
- the numeric information buffer memory 14 generally comprises two groups of AND gates 14 and 14 and two groups of flip-flops 14 and l4 'which store, temporarily, the numeric information from the indicating register 15.
- the coincidence circuit 17 generally comprises a group of AND gates 17, and NOR gates 17, which puts out a signal when, and only when, the information stored in the flip-flop group 12 in the digit information buffer memory l2 coincideswith the decimal point information stored in the flip-flop group 16 in the decimal point information buffer memory 16.
- the output signal is applied to the decimal point segment driver in the cathode driver IBK in the display unit 13 and to the set ter minal of a zero-suppression flip-flop 20.
- To the set terminal of the flipflop 20 is also applied the binarycoded four-bit decimal digit information from the flipflop group 14 in the numeric information buffer memory 14 through a numeric detection OR gate 21 and an OR gate 19.
- the numeric information to be displayed is stored in the indicating register 15.
- the numeric information, in the most significant digit is applied to the AND gate group 14, in response to the command signal @(See FIG. 5) from the read-only memory 11 so that the AND gates are opened and the numeric information, in the most significant digit, is stored in the flipflop group 14 in the form of the binary-coded four-bit decimal digit.
- the OR gate 21 does not put out a signal so that the flipflop 20 will not be set.
- the output signals of the flipflops 14 are applied to one set of input terminals of the AND gates 14;, so that when the control signal@(See FIG.
- the AND gates 12 are opened so that the digit information is stored in the flipflops 12
- the output signals of the flip-flops 12 are applied to the anode driver l3A decoded and applied to the anode group in the display unit part (2) 13A, thereby selecting and energizing the most significant digit.
- the output signal of the flip-flop 20 is applied to one set of input terminals of the AND gates 22 whereas the output signals from the cathode driver 13K are applied to the other set of input terminals respectively so that the numeric information may be displayed only when the flip-flop 20 gives the set output signal, whereas the numeric information may not be displayed when the flipflop 20 gives the reset output signal.
- the most significant digit is zero so that the flip-flop 20 is not set. Thus the zero suppression may be effected.
- the numeric information is detected digit by digit until the decimal digit other than zero is detected. Once the decimal digit other than zero is detected and displayed, all of the following decimal digits are displayed. Thus, the suppression of zeros can be made, only by one flip-flop.
- the decimal point information is transferred from the indicating register 15 through the AND gates 16, and stored in the flip-flops 16
- the output signals of the flip-flops 16 are applied to one set of input terminals of the AND gates 17, in the coincidence circuit 17, and when, and only when, the output signals coincide with those applied from the digit information buffer memory 12 in response to the command signalfrom the readonly memory 11, the NOR gate 17 gives the output signal.
- the decimal point information may be applied to the coincidence circuit 17 from any suitable means such as a counter instead of the indicating register l5.
- the output signal from the NOR gate 17 is applied to the decimal point segment selection circuit in the cathode driver 13K,, to select and energize the decimal point segment of the cathode segments in the display unit part (2) 13K.
- the output signal of the NOR gate 17 is also applied to the flip-flop 20, causing it to set so that the AND gates 22 are opened in order to display the decimal point even when the decimal digit in the digit in which the decimal point is displayed is zero.
- FIG. 3 is a flow chart of the micro-commands stored in the read-only memory 11. It is assumed that the micro-commands derive decimal point information from indicating register" be stored in one address in the read-only memory 11. Then, in the next address, is stored the micro-command derive n-th numeric information from indicating register.” Various microcommands, as shown in FIG. 3, are stored in the readonly memory 11 and used to carry out various operations step by step, automatically, unless there is no branch or jump command.
- the command and control portions are stored in one address in the read-only memory 11.
- the micro-command 1001 stored in the control portion means transfer the content in the data portion into the register 12
- the control signa hown in FIG. 5 is generated to open the AND gates 12, so that the digit information 1100 in the data portion is transferred to and stored in the register 12
- the content in the register 12 is decoded by the anode driver 13A,; so that the anode in the l2-th digit is selected and energized.
- the read-only memory 11 comprises core memories, or the like.
- a display control device for a numeric display unit comprising:
- a shift register having input and output terminals for storing a binary coded numeric information from the input terminals
- the numeric display unit (13) having a plurality of digit segments and a plurality of numeric segments in each of said digit segments for displaying the information stored in said shift register;
- a digit segment drive circuit (l3A connected to said digit segments of said numeric display unit for selectively energizing said digit segments, said digit segment drive circuit including a first decoder for decoding a plurality of binary codes entered and for selecting one of said digit segments;
- numeric segment drive circuit (131( for selectively energizing said plurality of numeric segments associated with each of said digit segments, said numeric segment drive circuit including a second decoder for decoding a plurality of binary codes entered and for selecting some or all of said numeric segments;
- a digit information buffer circuit (12,) having output terminals connected to the input terminals of said digit segment drive circuit;
- numeric information buffer circuit (14 having output tenninals connected to the input terminals of said numeric segment drive circuit;
- an arithmetic unit having output terminals for executing an arithmetic operation and for delivering the operational result to said shift register;
- a readonly memory (11) composed of a semiconductor large scale integration circuit having at least a data portion including digit position information stored and a control portion including gate control signal stored therein;
- said numeric display unit means for controlling said numeric display unit so that said plurality of digit segments are sequentially energized in accordance with the sequence of the digit information stored in said read-only memory and said numeric segments are selectively energized to display the numeric information stored in said shift register in accordance with the gate control signal included in said read-only memory, thereby to display plural digits of numerics on a time division basis.
- decimal point buffer circuit (16 for storing a decimal point position information to indicate a decimal point on said numeric display unit
- a third group of AND gates (16,) having output terminals connected to the input terminals of said decimal point buffer circuit and two sets of input terminals one set of which is connected to said shift register and the other set of input terminals is connected to said read-only memory to receive the gate control signal therefrom;
- a coincidence circuit (17) to which is applied the decimal point position information from said decimal point buffer circuit and the digit information from said digit information buffer circuit, thereby to display the decimal point on said numeric display unit on a time division basis.
- a display control device as defined in claim 1 the
- numeric information intermediate buffer circuit (14 connected between said numeric information buffer circuit (14 and the output terminals of said shift register;
- a fourth group of AND gates (14 having output terminals connected to the input terminals of said numeric information intermediate buffer circuit and two sets of input terminals one set of which is applied with the numeric information from said shift register and the other set of input terminals is applied with the gate control signal from said readonly memory;
- a fifth group of AND gates (22) having one set of input terminals to which is applied a set output from said flip-flop and the other set of input terminals to which are applied outputs from said numeric segment drive circuit (13K thereby to generate at the output of said fifth group of AND gates a signal for suppressing an insignificant zero or zeros to be displaced in higher significant digit or digits thtn the significant digit.
- a display control device as defined in claim 3, wherein said second OR gate (19) has a further input terminal to which is applied the output from said coincidence circuit (17) to set said flip-flop, thereby to display a zero in a digit associated with the decimal point. 1:
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Digital Computer Display Output (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP46089560A JPS4854825A (de) | 1971-11-10 | 1971-11-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
US3858197A true US3858197A (en) | 1974-12-31 |
Family
ID=13974192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US00303013A Expired - Lifetime US3858197A (en) | 1971-11-10 | 1972-11-02 | Device for controlling display output by micro-program |
Country Status (3)
Country | Link |
---|---|
US (1) | US3858197A (de) |
JP (1) | JPS4854825A (de) |
DE (1) | DE2255252C3 (de) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953719A (en) * | 1974-11-26 | 1976-04-27 | Texas Instruments Incorporated | Latched decoder for digit outputs to an electronic digital calculator display |
US3991306A (en) * | 1974-11-19 | 1976-11-09 | Texas Instruments, Inc. | Electronic calculator or digital processor chip with separately controllable digit and segment outputs |
US3991305A (en) * | 1974-11-19 | 1976-11-09 | Caudel Edward R | Electronic calculator or digital processor chip with multiple code combinations of display and keyboard scan outputs |
US20110248984A1 (en) * | 2010-04-12 | 2011-10-13 | Dialog Semiconductor Gmbh | User programmable graphics in non-volatile memory for EPD driver IC |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3880836A (en) * | 1972-05-18 | 1975-04-29 | Goodrich Co B F | Thiocarbamylsulfenamides |
JPS5634887B2 (de) * | 1973-09-28 | 1981-08-13 | ||
JPS5147327A (ja) * | 1974-10-21 | 1976-04-22 | Sharp Kk | Keisankitonohyojisochi |
DE2656304C3 (de) | 1976-12-11 | 1980-02-14 | Dr. Johannes Heidenhain Gmbh, 8225 Traunreut | Elektronische Schaltung |
DE2660292C3 (de) * | 1976-12-11 | 1987-05-07 | Dr. Johannes Heidenhain Gmbh, 8225 Traunreut | Schaltung zur Auswertung des Ausgangssignals eines digitalen Meßsystems |
JPS53129683A (en) * | 1977-04-19 | 1978-11-11 | Casio Comput Co Ltd | Display control system |
JPS553347U (de) * | 1979-02-21 | 1980-01-10 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3396377A (en) * | 1964-06-29 | 1968-08-06 | Gen Electric | Display data processor |
-
1971
- 1971-11-10 JP JP46089560A patent/JPS4854825A/ja active Pending
-
1972
- 1972-11-02 US US00303013A patent/US3858197A/en not_active Expired - Lifetime
- 1972-11-10 DE DE2255252A patent/DE2255252C3/de not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3396377A (en) * | 1964-06-29 | 1968-08-06 | Gen Electric | Display data processor |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3991306A (en) * | 1974-11-19 | 1976-11-09 | Texas Instruments, Inc. | Electronic calculator or digital processor chip with separately controllable digit and segment outputs |
US3991305A (en) * | 1974-11-19 | 1976-11-09 | Caudel Edward R | Electronic calculator or digital processor chip with multiple code combinations of display and keyboard scan outputs |
US3953719A (en) * | 1974-11-26 | 1976-04-27 | Texas Instruments Incorporated | Latched decoder for digit outputs to an electronic digital calculator display |
US20110248984A1 (en) * | 2010-04-12 | 2011-10-13 | Dialog Semiconductor Gmbh | User programmable graphics in non-volatile memory for EPD driver IC |
US8581804B2 (en) * | 2010-04-12 | 2013-11-12 | Dialog Semiconductor Gmbh. | User programmable graphics in non-volatile memory for EPD driver IC |
Also Published As
Publication number | Publication date |
---|---|
DE2255252C3 (de) | 1979-12-20 |
DE2255252B2 (de) | 1976-04-29 |
JPS4854825A (de) | 1973-08-01 |
DE2255252A1 (de) | 1973-05-17 |
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