US3806800A - Method and apparatus for determining the location of electrically conductive members on a structure - Google Patents

Method and apparatus for determining the location of electrically conductive members on a structure Download PDF

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Publication number
US3806800A
US3806800A US00318155A US31815572A US3806800A US 3806800 A US3806800 A US 3806800A US 00318155 A US00318155 A US 00318155A US 31815572 A US31815572 A US 31815572A US 3806800 A US3806800 A US 3806800A
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United States
Prior art keywords
probes
electrically conductive
conductive members
pads
electrical
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US00318155A
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English (en)
Inventor
R Bove
E Hubacher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US00318155A priority Critical patent/US3806800A/en
Priority to CA186,121A priority patent/CA1003045A/en
Priority to FR7342433A priority patent/FR2211658B1/fr
Priority to JP48129829A priority patent/JPS5122345B2/ja
Priority to GB5540273A priority patent/GB1431226A/en
Priority to DE2360801A priority patent/DE2360801C2/de
Application granted granted Critical
Publication of US3806800A publication Critical patent/US3806800A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07392—Multiple probes manipulating each probe element or tip individually

Definitions

  • ABSTRACT The electrically conductive pads on a semiconductor chip or the engineering change pads on a multilayered substrate are located electronically relative to probes, which are in a predetermined orthogonal orientation, so that the particular probe or probes in engagement with each of the pads is determined. Then, the electrical characteristics of any electrical unit connected to each of the pads is ascertained through selectively controlling the electrical power supplied through the probes to the pads in a controlled manner.
  • each mechanical contactor so that its probes are arranged for use with a chip of a particular design and having its pads at specific locations. if the size of the chip is changed, the location of any pad on the chip is changed, or the size of any pad is changed, for example, a new arrangement of the probes of the mechanical contactor has been required. Thus, any change in the relationship of the pads on a chip has required a new contactor, which is a probe tool, to be designed.
  • each probe of the contactor has been designed for engagement with a pad at a specific location on a chip of a specific size.
  • the universal electronic contactor of the present invention satisfactorily overcomes the foregoing problems by providing an arrangement of the probes wherein alignment of each of the pads on the chip with a specific probe or probes is not required. Additionally, the contactor of the present invention is capable of having its probes engage the pads on the chip irrespective of the arrangement of the pads on the chip as long as the spacing between the pads relative to the size of each of the probes is such that no probe can contact two of the pads simultaneously.
  • the contactor of the present invention satisfactorily solves the foregoing problems through utilizing a plurality of probes arranged in a predetermined orientation, which is preferably with the probes disposed in an orthogonal grid in which the probes are arranged in rows and columns.
  • the location of a first of the pads can be electronically determined.
  • the contactor of the present invention can readily determine the location of all of the pads on the chip. With this programmed information, the computer can supply signals to regulate the supply of power from a tester to various pads in a specific sequence to permit the testing of the integrated circuits connected to the pads on a semiconductor chip.
  • the contactor of the present invention enables Kelvin testing to be achieved.
  • the Kelvin technique insures more accurate electrical measurements independent of the probe contact resistance.
  • the contactor of the present invention has AC probing capability because of the relatively short length of each of the probes.
  • the contactor of the present invention has both AC and DC testing capability.
  • a multilayered ceramic substrate has a plurality of engineering change pads on at least one of its surfaces with the metal layers, which are insulated from each other by the ceramic, providing electrical interconnections between the various engineering change pads.
  • each chip site area has a plurality of engineering change pads equal to the number of pads on a semiconductor chip. Thus, for example, if each chip has one hundred pads, then each chip site area would have one hundred engineering change pads.
  • the contactor of the present invention satisfactorily solves this problem through having the matrix of the probes encompass the entire one hundred chip site areas. As a result, the engineering'change pads are contacted only once during testing so as to reduce the possibility of product damage in comparison with that of the previously available mechanical contactors.
  • the contactor of the present invention overcomes these problems since there is no requirement of any stepping or indexing equipment or any alignment system. Furthermore, the time for testing is significantly reduced due to the elimination of the stepping or indexing and alignment.
  • the specific locations between the engineering change pads on a multilayered ceramic substrate do not have to meet as stringent location manufacturing requirements as has been previously required with the prior mechanical contactors.
  • the contactor of the present invention it is only necessary that the engineering change pads be located relative to each other so that the distance therebetween is greater than the diameter of the probes so that a single probe cannot simultaneously contact two of the engineering change pads.
  • the contactor of the present invention is capable of having two of the probes engage each of the engineering change pads.
  • Kelvin testing can be easily employed with a multilayered ceramic substrate when the contactor of the present invention is employed.
  • An object of this invention is to provide an apparatus for locating separated electrically conductive members on a support structure relative to predetermined oriented probes with which the members are engaged.
  • Another object of this invention is to provide a method for determining the positions of separated electrically conductive members on a structure relative to probes arranged in a predetermined orientation.
  • FIG. 1 is a schematic view showing the apparatus of the present invention for locating and testing pads on a semiconductor chip.
  • FIG. 2 is an enlarged schematic view showing engagement of a pair of the probes with one of the pads on the semiconductor chip.
  • FIG. 3 is a schematic view showing the relationship of the probes to engineering change pads on a multilayered ceramic substrate.
  • FIG. 4 is a schematic view showing the relationship of the probes to pads on a semiconductor chip.
  • FIG. 1 there is shown a semiconductor chip 10 having a plurality of electrically conductive pads 11 extending from its electrically insulating surface 12.'Each of the pads 11 may be connected to an integrated circuit (not shown) or a plurality of integrated circuits on the chip 10 with the circuits being disposed beneath the electrically insulating surface 12.
  • the apparatus of the present invention includes a plurality of probes 14 extending upwardly through an electrically insulating member 15, which may be formed of a plastic, for example.
  • the probes 14 are arranged in an orthogonal grid in which the probes 14 are disposed in a plurality of rows and a plurality of columns.
  • each of the probes 14 is capable of sliding within the insulating member 15 when engaged by one of the pads 1 1. Accordingly, each of the probes l4 slidably extends through an opening 16 (see FIG. 2) in the member 15.
  • Each of the probes 14 includes a wire 17 extending therefrom and connected by electronic switches 18 to each of a plurality of wires 19.
  • the electronic switches 18 can be silicon controlled rectifiers or transistors, for example.
  • Each of the wires 19 is connected to a pin 20 of a tester 21.
  • the tester 21 is capable of supplying electrical power of different values to each of the pins 20, which function as a power supply output.
  • tester 21 is sold by Fairchild Systems Technology, Inc., Sunnyvale, Calif. as model No. 5,000.
  • the tester can have up to one bundred of the pins 20 so that there would be one hundred of the wires 19 extending therefrom.
  • each of the wires 17 would have of the electronic switches 18 connected thereto so that each of the wires 17 could be connected to each of the wires 19 when desired.
  • a computer 22 is connected to the tester 21 and to a matrix decoder 23, which is connected to each of the electronic switches 18 by a separate wire 23'. Accordingly, the computer 22 can supply signals to the matrix decoder 23 to activate one or more of the electronic switches 18 at any time.
  • One" suitable example of the computer 22 is an IBM 1800 computer with the matrix decoder 23 being one of the matrix decoders in the IBM 1800 computer.
  • the chip 10 When the chip 10 is to have the functionality of its integrated circuits tested, the chip 10 is lowered by suitable means such as a vacuum pencil 24 on which it is supported, for example, into engagement with the probes 14. With the probes 14 arranged in an orthogonal grid and using the apparatus of the present invention, the chip 10 can be lowered onto any portion of the grid of the probes 14 as long as all of the pads 11 are on or within the grid of the probes 14. As shown in FIG. 4, for example, each of the pads 11 is engaged by at least two of the probes 14. The contact of two of the probes 14 with one of the pads 11 is shown in FIG. 2.
  • the computer 22 which is programmed for the location of the pads 11 on the chip 10 being tested, supplies signals to the matrix decoder 23 to connect all of the probes 14 in a row 25 of the grid, for example, to one of the pins 20 and all of the probes 14 in a row 26, which is adjacent the row 25, to another of the pins 20 of the tester 21. Accordingly, by then supplying power through the rows 25 and 26, it can be readily determined if one of the pads 11 is in engagement with the two rows if the tester 21 supplies either a constant voltage or current to the two rows 25 and 26 of the grid of the probes 14.
  • the computer 22 disconnects the electronic switches 18 from the wires 17 connected to the probes 14 in the row 25. Then, the row 26 and a row 27, which is adjacent the row 26, are connected to the two output pins 20 of the tester 21 to which the rows and 25 were connected. The constant voltage is again supplied. With the constant voltage supplied, a short will cause a higher current as previously mentioned.
  • the testing of adjacent rows in the orthogonal grid of the probes 14 continues until there is a short between two of the adjacent rows.
  • the computer 22 then connects the two left-most probes 14 in one of the two rows having the pad 1 1 produce a short circuit thereacross.
  • Each two of the adjacent probes 14 are connected to the two output pins 20 through the electronic switches 18, which are controlled from the computer 22 through the matrix decoder 23, until there is a short between two of the adjacent probes 14 in one of the rows.
  • the location of the pad 11 at one of the corners of the chip 111 is ascertained.
  • each of the other pads 11 on the chip 111 may be readily located through the computer 22 connecting various of the electronic switches 18 to the tester 21. If the pads 11 are not properly spaced relative to other of the pads 11, the computer 22 will determine this.
  • the computer 22 connects the probes 14 through the electronic switches 18 to the particular pins 20 of the tester 21 so that the desired testing of the integrated circuits occurs.
  • the grid of the probes 14 With the probes 14 so small and closely spaced in relation to the diameter of the pads 11, it is possible that two of the probes 14 will contact one of the pads 11 when the pads 11 are placed in contact with the probes 14. While it is desirable to have two of the probes 14 contact each of the pads 11 on the chip 10, it should be understood that this is not necessary for the apparatus to function satisfactorily. It is only necessary that a sufficient number of the pads 11 be contacted by two of the probes 14 to insure that orientation of the chip 10 is obtained.
  • the probes 14 have been shown in FIGS. 1 and 2 as making contact with the pads 11 on the chip 10, it should be understood that the probes 14 could engage an engineering change pad 28 (see FIG. 3) on a multilayered ceramic substrate. Because of the size of the pads 28 relative to the size and spacing of the probes 14, at least two of the probes 14 will always contact each of the pads 28 as shown in FIG. 3. Accordingly, the Kelvin technique can be employed for testing each of the engineering change pads 28 on a multilayered ceramic substrate.
  • the distance between the pads 11 on the chip 141 or the engineering change pads 28 (see FIG. 3) on the multilayered ceramic substrate it is necessary that the distance between adjacent pads be greater than the diameter of the probes 14. If a non-circular probe were employed, there still must be sufficient spacing between adjacent pads to prevent any shorting therebetween.
  • the computer 22 can determine if one of the pads 11 is missing from the chip 10. If this condition exists, no testing will occur since the chip 10 is defective. Similarly, if one of the pads 11 fails to contact the probes 14 because of lack of sufficient height in comparison with the other of the pads 11 whereby the pad 11 would not be capable of making the connection to a substrate on which the chip 10 is to be supported, then the computer 22 also can recognize this, if the probe structure of the aforesaid Bove application is employed, and prevent testing of the chip 10 since it is defective.
  • the present invention has shown and described the probes 14 as being arranged in an orthogonal grid in which the probes 14 are disposed in rows and columns, it should be understood that any other predetermined orientation of the probes 14 may be employed. It is only necessary that the probes 14 have a predetermined orientation.
  • the use of the term electrical characteristic includes both testing of the functionality of the integrated circuits of a semiconductor chip, for example, and the testing of the electrical interconnections between engineering change pads on a multilayered ceramic substrate to ascertain whether the interconnections are open (functional) or shorted (nonfunctional).
  • the use of the term electrical unit in the claims includes an integrated circuit or circuits orthe interconnection between a pair of engineering change pads on a multilayered ceramic substrate.
  • An advantage of this invention is that the same contactor or probe tool may be employed for various chip designs. Another advantage of this invention is that no alignment is required between the probes and the pads on a chip or a multilayered ceramic substrate. Still another advantage of this invention is that all engineering change pads on a multilayered ceramic substrate are contacted only once during testing of the interconnections. A further advantage of this invention is that it eliminates the requirement for any stepping equipment or alignment system for testing the interconnections between the engineering change pads on a multilayered ceramic substrate. Yet another advantage of this invention is that testing is faster and at a lower cost than the previously available equipment. A still further advantage of this invention is that broader tolerances in the relationship of the engineering change pads on a multilayered ceramic substrate may be employed.
  • a universal electronic aligned contactor including: probe means adapted to directly engage each of a plurality of separated electrically conductive members arranged in a predetermined relation on a structure and randomly located relative to said probe means;
  • the contactor according to claim 2 including means to selectively control the connection of said power supply means to said probes to determine the electrical characteristic of any electrical unit connected to each of the electrically conductive members after completion of the location of the electrically conductive members relative to said probes.
  • said determining means includes means to ascertain that the electrically conductive members are located on the structure in the desired arrangement.
  • a method for locating the position of each of a plurality of separated electrically conductive members arranged in a predetermined relation on a structure and randomly located relative to probes arranged in a predetermined orientation uncorrelated to the predetermined relation of the electrically conductive members with each of the probes having a size so that no probe can engage more than one of the electrically conductive members including:
  • the predetermined orientation of the probes is an orthogonal grid of the probes arranged in rows and columns and determining the location of the first of the electrically conductive members by initially supplying power to each pair of adjacent rows of the probes until a short is found and then supplying power to each adjacent pair of the probes in each of the pairs of rows having the short until a short is found between an adjacent pair of the probes.
  • the method according to claim 9 including testing electrical units connected to the electrically conductive members after locating the electrically conductive members relative to the probes by selectively supplying electrical power in a controlled arrangement to the probes to test any electrical unit connected to each of the electrically conductive members.

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  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Engineering & Computer Science (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Tests Of Electronic Circuits (AREA)
US00318155A 1972-12-26 1972-12-26 Method and apparatus for determining the location of electrically conductive members on a structure Expired - Lifetime US3806800A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US00318155A US3806800A (en) 1972-12-26 1972-12-26 Method and apparatus for determining the location of electrically conductive members on a structure
CA186,121A CA1003045A (en) 1972-12-26 1973-11-19 Method and apparatus for determining the location of electrically conductive members on a structure
FR7342433A FR2211658B1 (de) 1972-12-26 1973-11-20
JP48129829A JPS5122345B2 (de) 1972-12-26 1973-11-20
GB5540273A GB1431226A (en) 1972-12-26 1973-11-29 Testing electronic components connector for deformable tubes
DE2360801A DE2360801C2 (de) 1972-12-26 1973-12-06 Schaltungsprüfeinrichtung für integrierte Schaltkreise auf Schichtschaltungsträgern

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US00318155A US3806800A (en) 1972-12-26 1972-12-26 Method and apparatus for determining the location of electrically conductive members on a structure

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US (1) US3806800A (de)
JP (1) JPS5122345B2 (de)
CA (1) CA1003045A (de)
DE (1) DE2360801C2 (de)
FR (1) FR2211658B1 (de)
GB (1) GB1431226A (de)

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DE2557621A1 (de) * 1974-12-30 1976-07-08 Ibm Elektrisches pruefsystem
US4019129A (en) * 1975-06-02 1977-04-19 Bell Telephone Laboratories, Incorporated Metallic plating testing apparatus
US4038501A (en) * 1975-07-10 1977-07-26 Volk Victor F Apparatus and method for automatically connecting to the individual conductors of a multiconductor cable
US4099119A (en) * 1977-02-03 1978-07-04 Honeywell Inc. Probe apparatus for in place testing of electrical circuit boards
US4214201A (en) * 1978-02-24 1980-07-22 Teradyne, Inc. Integrated circuit testing probe
US4218745A (en) * 1978-09-11 1980-08-19 Lockheed Corporation Microcomputer assisted electrical harness fabrication and testing system
US4443756A (en) * 1980-11-25 1984-04-17 Lightbody James D Apparatus and method for testing circuit boards
US4463310A (en) * 1980-07-11 1984-07-31 Rca Corporation Apparatus for detecting the presence of components on a printed circuit board
US4565966A (en) * 1983-03-07 1986-01-21 Kollmorgen Technologies Corporation Method and apparatus for testing of electrical interconnection networks
US4587481A (en) * 1982-09-22 1986-05-06 Siemens Aktiengesellschaft Arrangement for testing micro interconnections and a method for operating the same
US4633175A (en) * 1984-11-23 1986-12-30 Avx Corporation Testing method and apparatus for electronic components
US4897598A (en) * 1987-03-31 1990-01-30 Siemens Aktiengesellschaft Apparatus for electrical function testing of wiring matrices, particularly of printed circuit boards
US4949035A (en) * 1989-01-06 1990-08-14 Digital Equipment Corporation Connector alignment verification and monitoring system
US5235740A (en) * 1991-03-22 1993-08-17 International Business Machines Corporation Press with pin detection for interference connectors
EP0639777A1 (de) * 1993-08-21 1995-02-22 Hewlett-Packard Company Prüfen von elektrischen Komponenten unter Verwendung einer Sonde
US5420520A (en) * 1993-06-11 1995-05-30 International Business Machines Corporation Method and apparatus for testing of integrated circuit chips
US5543724A (en) * 1994-10-03 1996-08-06 Motorola, Inc. Method and apparatus for locating conductive features and testing semiconductor devices
WO1997038324A1 (en) * 1996-04-09 1997-10-16 Phase Metrics Testing of multiple magnetic recording heads
US5861743A (en) * 1995-12-21 1999-01-19 Genrad, Inc. Hybrid scanner for use in an improved MDA tester
US6255827B1 (en) 1999-04-30 2001-07-03 International Business Machines Corporation Search routine for 2-point electrical tester
US6297653B1 (en) * 1999-06-28 2001-10-02 Micron Technology, Inc. Interconnect and carrier with resistivity measuring contacts for testing semiconductor components
US6303993B1 (en) * 1997-12-18 2001-10-16 Micron Technology, Inc. Method and apparatus for testing bumped die
US20040022042A1 (en) * 1999-07-28 2004-02-05 Sammy Mok Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
US20040075455A1 (en) * 2002-07-15 2004-04-22 Sammy Mok Mosaic decal probe
US20050051353A1 (en) * 1999-05-27 2005-03-10 Chong Fu Chiung Massively parallel interface for electronic circuit
US20050068054A1 (en) * 2000-05-23 2005-03-31 Sammy Mok Standardized layout patterns and routing structures for integrated circuit wafer probe card assemblies
US20050242826A1 (en) * 2003-10-09 2005-11-03 Parker Kenneth P Methods for testing continuity of electrical paths through connectors of circuit assemblies
US20060186906A1 (en) * 2000-05-23 2006-08-24 Bottoms W R High density interconnect system for IC packages and interconnect assemblies
US20070098895A1 (en) * 2001-08-24 2007-05-03 Smith Donald L Method and Apparatus for Producing Uniform, Isotropic Stresses in a Sputtered Film
US20070245553A1 (en) * 1999-05-27 2007-10-25 Chong Fu C Fine pitch microfabricated spring contact structure & method
US7349223B2 (en) 2000-05-23 2008-03-25 Nanonexus, Inc. Enhanced compliant probe card systems having improved planarity
US20080090429A1 (en) * 2000-06-20 2008-04-17 Sammy Mok Systems for testing and packaging integrated circuits
US7382142B2 (en) 2000-05-23 2008-06-03 Nanonexus, Inc. High density interconnect system having rapid fabrication cycle
US7952373B2 (en) 2000-05-23 2011-05-31 Verigy (Singapore) Pte. Ltd. Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
US20150091390A1 (en) * 2013-10-01 2015-04-02 Sierra Wireless, Inc. Method and Apparatus for Electrical Keying of an Integrated Circuit Package Having Rotationally Symmetric Footprint
US11219134B2 (en) * 2019-01-28 2022-01-04 Hefei Boe Vision-Electronic Technology Co., Ltd. Device and method for detecting missing element on circuit board

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JPS51145158U (de) * 1975-05-16 1976-11-22
US4052793A (en) * 1976-10-04 1977-10-11 International Business Machines Corporation Method of obtaining proper probe alignment in a multiple contact environment
JPS55164376A (en) * 1979-06-11 1980-12-22 Nippon Telegr & Teleph Corp <Ntt> Integrated circuit testing unit
DE2938567C2 (de) * 1979-09-24 1982-04-29 Siemens AG, 1000 Berlin und 8000 München Gehäuse für hochintegrierte Schaltkreise
DE3223664A1 (de) * 1982-06-24 1983-12-29 Siemens AG, 1000 Berlin und 8000 München Messanordnung fuer duenne schichten und duennschichtbauelemente auf scheibenfoermigen substraten
JPS62106170U (de) * 1985-12-23 1987-07-07
JPH05166903A (ja) * 1991-12-12 1993-07-02 Mitsubishi Electric Corp 半導体検査装置

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Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2557621A1 (de) * 1974-12-30 1976-07-08 Ibm Elektrisches pruefsystem
US4019129A (en) * 1975-06-02 1977-04-19 Bell Telephone Laboratories, Incorporated Metallic plating testing apparatus
US4038501A (en) * 1975-07-10 1977-07-26 Volk Victor F Apparatus and method for automatically connecting to the individual conductors of a multiconductor cable
US4099119A (en) * 1977-02-03 1978-07-04 Honeywell Inc. Probe apparatus for in place testing of electrical circuit boards
US4214201A (en) * 1978-02-24 1980-07-22 Teradyne, Inc. Integrated circuit testing probe
US4218745A (en) * 1978-09-11 1980-08-19 Lockheed Corporation Microcomputer assisted electrical harness fabrication and testing system
US4463310A (en) * 1980-07-11 1984-07-31 Rca Corporation Apparatus for detecting the presence of components on a printed circuit board
US4443756A (en) * 1980-11-25 1984-04-17 Lightbody James D Apparatus and method for testing circuit boards
US4587481A (en) * 1982-09-22 1986-05-06 Siemens Aktiengesellschaft Arrangement for testing micro interconnections and a method for operating the same
US4565966A (en) * 1983-03-07 1986-01-21 Kollmorgen Technologies Corporation Method and apparatus for testing of electrical interconnection networks
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Also Published As

Publication number Publication date
DE2360801C2 (de) 1985-08-22
FR2211658B1 (de) 1978-12-01
FR2211658A1 (de) 1974-07-19
DE2360801A1 (de) 1974-06-27
CA1003045A (en) 1977-01-04
JPS4991775A (de) 1974-09-02
JPS5122345B2 (de) 1976-07-09
GB1431226A (en) 1976-04-07

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