US3796991A - Error-correcting device for the transmission of data - Google Patents

Error-correcting device for the transmission of data Download PDF

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Publication number
US3796991A
US3796991A US00270035A US3796991DA US3796991A US 3796991 A US3796991 A US 3796991A US 00270035 A US00270035 A US 00270035A US 3796991D A US3796991D A US 3796991DA US 3796991 A US3796991 A US 3796991A
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Prior art keywords
gate
packing
flip
output
signal
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Expired - Lifetime
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US00270035A
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English (en)
Inventor
C Stenstrom
M Lambourg
R Duprez
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Alcatel CIT SA
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Alcatel CIT SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates

Definitions

  • Pans France An error-correcting device for the transmission of July 10, 1972 data on a telegraph line with modulation by coded pulses (MIC) whose sampling sequence is more rapid than the telegraphic speed (number of bits per secend), which leads to transmitting in the MIC pattern
  • MIC coded pulses
  • the present invention relates to the transmission of data or characteristics on a telegraph line. It is more particularly concerned with and directed to the transmission of data on a telegraph path or line with a modulation by coded pulses (MIC) whose sampling sequence or repetition is more rapid than the telegraphic speed (number of bits per second), which leads to transmitting in the MIC pattern (1) information bits, (2) doubled bits, the so-called padded bits, as well as (3) supplementary bits, called packing indications or signals," which make it possible to recognize whether a given bit is an information bit or a padded bit.
  • MIC modulation by coded pulses
  • the succession of the valences of the packing indications follows a well defined law, and the present invention furnishes the means for producing a correction if this law is not complied with.
  • the application of the present invention is directed toward the transmission of datain an MIC pattern.
  • the transmission of data on a telegraph line is carried out at a telegraphic speed chosen from among the normal telegraphic speeds, for example at one of the following speeds: 1,200 2,400 4,800 9,600 bits/second. 1
  • sampling sequences or repetitions of the MIC patterns in use for the telegraph transmissions are multiples of 500 Hz.
  • V the telegraphic speed
  • the valances 1 are never present with a sequence higher than two, i.e., there are never three or more in a row.
  • the correcting means or device for the packing indication or signal according to the present invention is based on the following principle: There are never two consecutive false packing indications or signals present. It can be shown that with practical values of the parameters this is verified with a probability of approximately 10* On the other hand, one will refrain from proceeding with consecutive corrections whose result would be a propagation of errors. Rather, after a correction has been made, one will wait at least two clock times before making the decision for effecting a possible new correction.
  • FIG. 1 comprises three graphs concerning the interposition of padded bits between certain information bits
  • FIG. 2 indicates the process of correction in different error cases
  • FIG. 3 illustrates a flow diagram of the correcting process according to the present invention
  • FIG. 4 represents a schematic block diagram of the correcting means or device of the present invention.
  • FIG. 5 is a schematic circuit diagram of one embodiment of the correcting means.
  • FIG. 1 comprises three sampling diagrams of a succession of moments at the speed of 4,800 b/s through an MIC section or pattern at 6,000 Hz.
  • the MIC sampling pulses are shown in groups of three. There is packing if two MIC pulses fall within the same moment 3 of the data. In this case, the recall line is marked with an arrow to designate the padded bit.
  • Each diagram contains two lines. On the line at the top, the sampling instants have been indicated; while, on the line at the bottom, the data train is indicated.
  • Diagram (a) represents a case with little distortion.
  • Diagram (b) corresponds to a first case of a distortion limit of the data signal, involving an extension or lengthening by 20 percent of the period within seven periods.
  • the formation of a sequence of three packings will never occur in the succession of packing signals or indications three'successive signals equal to I, nor two successive signals or indications equal to O.
  • T he principle of the error-correcting device is immediately deduced therefrom.
  • the errorcorrecting device detects two sucessive packing signals equal to 0, it sets the second one at l; and, each time the correcting device detects three successive signals equal to 1, it sets the third one at 0.
  • the correcting device waits for the passage of at least two new signals prior to proceeding with a new correction.
  • FIG. 2 shows a succession of packing signals on which nine positions have been specified by way of example, and it has been assumed that one error (valence inversion) is produced on each of thenine positions.
  • the law of the correcting device is to replace by a l a second 0 occurring after a first zero and to replace by a O a third 1 occurring after two ls.
  • the correcting device will either carry out an immediate correction, as seen in cases (I), (2), (4), (6), (8) and (9), or there will be a correction made with a time delay, as seen in cases (3), I
  • the correction relates to an erroneous bit.
  • the correction is set offby an incompatibility caused by a previous error by one step.
  • the correction in the third case is effected with a delay in time and it will be noted that the corrected sequence is not identical with the data sequence, but allows an. error to continue'to exist.
  • the delayed correction resides in the passage of the second IB from the valence 0 to the valence -l. Y It is apparent that, inthe data according to case 3) where the error is not corrected, beyond ab all the bits are displaced; in other words, all the bits are false. In the data according to case (4), there is a disturbance bearing on, or relating to, the bits c d e, which after the correct correspondence is reestablished.
  • FIG. 3 is a flow diagram which indicates the operation of the correcting device.
  • the correcting device is a sequential system whose configuration evolves as a function of the incident packing or padding indications or signals. This system possesses four stages or states which are interconnected by reason of the-following conditions, as can be ascertained from the flow diagram of FIG. 3.
  • FIG. 4 is a schematic diagram of the correcting device of the present invention.
  • the correcting device comprises two subgroups, a member 1 following the operations of the stage of the correcting device, receiving the incident packing indication (IB), and receiving the clock of the packing indications I-IB.
  • IB incident packing indication
  • I-IB clock of the packing indications
  • FIG. 5 is a diagram of one embodiment of a correcting device corresponding to the flow diagram of FIG. 3 and to the schematic block diagram of FIG. 4. It comprises at the input an inverter which receives the clock signals of the packing indications HB and an AND circuit 11 which, receiving the incident signal S and the clock signals FE, furnishes an output E.
  • Two flip-flops 12 and 13 receive on the clock terminal H thereof the signals HB and on the terminals D signals whose origin will be indicated hereinbelow.
  • the flipflops 12 and 13 furnish respective outputs A and A, B and E.
  • An inverter 14 and sevenAND circuits 15, l6, l7, 18, 19, and 21 serve to apply to the terminal D of the flip-flop 12 a signal E AB and to the terminal D of the flip-flop 13 a signal A B E (A E).
  • An A lTD circuit 22 receiving signals HE, (A E) and (E E) furnishes signal IE.
  • the circuits 21 and 22 are part of the subgroup 2 of FIG. 4.
  • the circuit 20 is part, at the same time, of the subgroup 1 and of the subgroup 2. All the other circuits are part of the subgroup l of FIG. 4.
  • a device for correcting the packing indication signals in a transmission of telegraphic data, integrated in an MIC pattern with a sampling frequency higher than the telegraphic speed of the transmission of the data so as to include packing or padded bits comprising input means for receiving the incident MIC signal and clock signals timing the packing indications, and logic means connected to said input means and including four logic states operating sequentially according to the valence of the successive packing indications received for detecting at least two prohibited sequences of packing indication signals and a device for inverting the valence 0-1 of a packing indication signal in response to an output of the second state of said logic means representing detection of one prohibited sequence and for inverting the valence l-O of a packing indication signal in response to an output of the fourth state of said logic means representing detection of the other prohibited sequence.
  • saidlogic means comprises first and second flip-flops each having respective first and second input terminals, whichflip-flops receive respectively on the first input thereof the inverse of said clock signal, and gate means connected to said flipflops for applying to the second inputs thereof respectively two logical signals derived from the output states of said flip-flops, one of which is (E) AB, the other is AE (m) (A E), wherein lB designates the packing indication signal extracted from the incident MIC signal and signals A, A and B, E are the respective outputs of said first and second flip-flops.
  • a device for correcting the packing indication including a first AND gate connected to the A and B outputs of said flip-flops, a second AND gate connected to the E output of the flipflop and the inverse of said packing indication signal IB, and a third AND gate connected to the outputs of said first and second AND gates and said clock signals.
  • a device for correcting the packing indication includes a fourth AND gate connected to the A and B outputs of said flip-flops, a fifth AND gate connected to the output of said fourth AND gate and to the inverse of said packing indication signal 18, a sixth AND gate connected to the A and E outputs of said flip-flops and a seventh AND gate connected to the outputs of said fifth and sixth AND gates and having an output connected to the second input of said second flip-flop.
  • a device for correcting the packing indication according to claim 5 wherein said gate means includes an eighth AND gate connected to the output of said first AND gate and to said packing indication signal IB and an output connected to the second input of said first flip-flop.
  • said input means includes an AND gate having inputs receiving said clock signals and said incident MIC signal; the output of said AND gate being connected to said gate means.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
US00270035A 1971-07-08 1972-07-10 Error-correcting device for the transmission of data Expired - Lifetime US3796991A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7125063A FR2144614B1 (de) 1971-07-08 1971-07-08

Publications (1)

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US3796991A true US3796991A (en) 1974-03-12

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US00270035A Expired - Lifetime US3796991A (en) 1971-07-08 1972-07-10 Error-correcting device for the transmission of data

Country Status (8)

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US (1) US3796991A (de)
BE (1) BE785572A (de)
DE (1) DE2233597C3 (de)
FR (1) FR2144614B1 (de)
GB (1) GB1394561A (de)
IT (1) IT962499B (de)
LU (1) LU65633A1 (de)
NL (1) NL165898C (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004856A1 (de) * 1978-04-18 1979-10-31 Siemens-Albis Aktiengesellschaft Verfahren zur synchronen Uebertragung von Datenströmen unterschiedlicher Bitrate sowie sende- und empfangsseitige Schaltungsanordnung zur Durchführung des Verfahrens

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1379751A (fr) * 1962-10-18 1964-11-27 Western Electric Co Réseau de transmission multiplex à modulation par impulsions codées synchronisé

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004856A1 (de) * 1978-04-18 1979-10-31 Siemens-Albis Aktiengesellschaft Verfahren zur synchronen Uebertragung von Datenströmen unterschiedlicher Bitrate sowie sende- und empfangsseitige Schaltungsanordnung zur Durchführung des Verfahrens

Also Published As

Publication number Publication date
BE785572A (fr) 1972-12-29
GB1394561A (en) 1975-05-21
FR2144614B1 (de) 1974-04-05
NL7209471A (de) 1973-01-10
DE2233597A1 (de) 1973-01-18
LU65633A1 (de) 1973-01-22
IT962499B (it) 1973-12-20
NL165898B (nl) 1980-12-15
NL165898C (nl) 1981-05-15
DE2233597B2 (de) 1980-08-28
FR2144614A1 (de) 1973-02-16
DE2233597C3 (de) 1981-04-30

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