US3796991A

US3796991A - Error-correcting device for the transmission of data

Info

Publication number: US3796991A
Application number: US00270035A
Authority: US
Inventors: C Stenstrom; M Lambourg; R Duprez
Original assignee: Alcatel CIT SA
Current assignee: Alcatel CIT SA
Priority date: 1971-07-08
Filing date: 1972-07-10
Publication date: 1974-03-12
Anticipated expiration: 1991-03-12
Also published as: BE785572A; GB1394561A; FR2144614B1; NL7209471A; DE2233597A1; LU65633A1; IT962499B; NL165898B; NL165898C; DE2233597B2; FR2144614A1; DE2233597C3

Abstract

An error-correcting device for the transmission of data on a telegraph line with modulation by coded pulses (MIC) whose sampling sequence is more rapid than the telegraphic speed (number of bits per second), which leads to transmitting in the MIC pattern information bits, doubling bits, called ''''padded bits,'''' as well as supplementary bits, called ''''packing or padded indications,'''' which make it possible to recognize whether a given bit is an information bit or a padded bit. The succession of the valances of the packing indications follows a well defined law. The invention furnishes the means to carry out a correction if this law is not complied with.

Description

[451 Mar. 12 1974 TRANSMISSION OF DATA Primary Examiner-Malcolm A. Morrison I [75] Inventors: Claude Stenstrom, Villebon; Michel jfj f gi'gfZFfifjggfi g gk z i Lambourg, Meudon-la-Foret; g g Robert Duprez, Briis-sous-Forges, all of France Assignee: Compagnie Industrielle Des 57 ABSTRACT Telecommunications Cit-Alcatel, I

Pans France An error-correcting device for the transmission of July 10, 1972 data on a telegraph line with modulation by coded pulses (MIC) whose sampling sequence is more rapid than the telegraphic speed (number of bits per secend), which leads to transmitting in the MIC pattern Foreign Application Priority Data information bits, doubling bits, called padded bits,

United States Patent [191 Stenstrom et al.

[5 ERROR-CORRECTING DEVICE FOR THE 22 Filed:

[21] Appl. No.: 270,035

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1 2 3 4 5 6 7 8 9 11 1 11 11 11 11 1 11 11 O0 00 00 0O 00 00 0O 00 00 11 1 1 1 11 1 117 1 11 11 11 1 11 11 11 11 1 01 O 0 00 O0 0 00 0& 0 00 11 11 1 11 11 11 0O 11 11 11 11 11 1 1 01 11 11 1 O0 00 AUG 00 11 00 O0 00 00 11 11 10 1 1 11 11 11 1 00 0 0 1 00 00 0O 00 00 0 11 01 1 11 1 1 1 1 11 0 00 00 00 00 00 AUG 00 00 11 11 11 1 1 11 11 1 11 11 11 11 11 11 11 11 11 11 PAIENTEUMAR 12 I914 3 796' 991 SHEET 3 of 4 FIGS FIG.4

The present invention relates to the transmission of data or characteristics on a telegraph line. It is more particularly concerned with and directed to the transmission of data on a telegraph path or line with a modulation by coded pulses (MIC) whose sampling sequence or repetition is more rapid than the telegraphic speed (number of bits per second), which leads to transmitting in the MIC pattern (1) information bits, (2) doubled bits, the so-called padded bits, as well as (3) supplementary bits, called packing indications or signals," which make it possible to recognize whether a given bit is an information bit or a padded bit. The succession of the valences of the packing indications follows a well defined law, and the present invention furnishes the means for producing a correction if this law is not complied with. The application of the present invention is directed toward the transmission of datain an MIC pattern.

The transmission of data on a telegraph line is carried out at a telegraphic speed chosen from among the normal telegraphic speeds, for example at one of the following speeds: 1,200 2,400 4,800 9,600 bits/second. 1

The sampling sequences or repetitions of the MIC patterns in use for the telegraph transmissions are multiples of 500 Hz. In order not to lose information in a transmission of data on an MIC frame or pattern, it is evidently necessary to adopt a higher frame or pattern sequence and, in fact, in a fixed ratio to the telegraphic speed V. For the telegraphic speeds V referred to above, this leads to the following sampling sequences:

F V ratio F/V 1500 Hz for I200 b/s 5/4 3000 Hz for 2400 b/S 5/4 6000 Hz for 4800 b/s 5/4 12000 Hz for 9600 b/S 5/4 This speed supplement of the frequency MICF over the telegraphic speed V leads by intermittence to two consecutive samplings of the same bit of information of the data. In this case, the second bit MIC corresponding to the same bit of data is called the packing bit or packed bit.

Under these circumstances it is necessary to feed into the line a supplementary information which renders it possible to recognize whether a bit which has been received is an information bit or a packed or padded bit. This is obtained by systematically interposing at a specific sequence bits that are called packing indications in accordance with the following rule: if the packing indication (IB) received is l, the preceding bit is a padded bit (BB); if the packing indication is 0, the preceding bit is an information bit.

The description will be continued within the framework of a transmission of data at a well defined telegraphic speed, for example 4,800 b/s, but it is understood that the conclusions which will be drawn extend and are applicable to any telegraphic speed with a frequency MIC being adapted accordingly.

It is apparent from the table provided above that there is, in principle, a ratio of 5/4 between the frequency MIC (6,000 Hz) and the telegraphic speed (4,800 b/s). In fact, it is necessary to also provide space for the packing indications. Simple arithmetic ratios lead to the possibility of interposing a packing indication one time out of four. Under these conditions, the frequency MIC passes from 6,000 Hz to 8,000 l-Iz (6,000 X 4/3 The MIC. frequencies associated with the different telegraphic speeds therefore have the following actual values:

2,000 Hz for 1,200 b/s 4,000 Hz for' 2,400 b/S 8,000 Hz for 4,800 b/s 16,000 Hz for 9,600 b/s It is easy to show that under ideal conditions, with the clock of data synchronized with the MIC clock, no distortion, and no error in transmission, the flow of packing indications is periodic (a period 0101 l When synchronization is not assured, and when distortion phenomena appear, this period becomes a pseudo-period," nevertheless the fact remains that the following results will be obtained Within the limits of distortion which will be specified hereinbelow:

1. The valances 0 (no padding) are always isolated; there are never two or more in a row;

2. The valances 1 (padding) are never present with a sequence higher than two, i.e., there are never three or more in a row.

The result thereof is that any violation of one of these requirements stems from an error in transmission, and conversely, any error in transmission causes a violation of one of these requirements.

It is the role of the correcting device, in such a case, to carry out the necessary valance inversion. It will be shown by a detailed analysis of the various possible eventualities that, in certain cases, the false packing indication or signal is corrected immediately, while in other cases the correction is made with a time lag or delay.

The correcting means or device for the packing indication or signal according to the present invention is based on the following principle: There are never two consecutive false packing indications or signals present. It can be shown that with practical values of the parameters this is verified with a probability of approximately 10* On the other hand, one will refrain from proceeding with consecutive corrections whose result would be a propagation of errors. Rather, after a correction has been made, one will wait at least two clock times before making the decision for effecting a possible new correction.

These and other objects, features and advantages of the present invention will be described in greater detail in the following specification, taken in conjunction with the accompanying drawing, wherein:

FIG. 1 comprises three graphs concerning the interposition of padded bits between certain information bits;

FIG. 2 indicates the process of correction in different error cases;

FIG. 3 illustrates a flow diagram of the correcting process according to the present invention;

FIG. 4 represents a schematic block diagram of the correcting means or device of the present invention, and

FIG. 5 is a schematic circuit diagram of one embodiment of the correcting means.

FIG. 1 comprises three sampling diagrams of a succession of moments at the speed of 4,800 b/s through an MIC section or pattern at 6,000 Hz. The MIC sampling pulses are shown in groups of three. There is packing if two MIC pulses fall within the same moment 3 of the data. In this case, the recall line is marked with an arrow to designate the padded bit. Each diagram contains two lines. On the line at the top, the sampling instants have been indicated; while, on the line at the bottom, the data train is indicated.

Diagram (a) represents a case with little distortion. The formation of the pseudo-period mentioned above, i.e., 01011, l0ll,'is apparent in this case.

Diagram (b) corresponds to a first case of a distortion limit of the data signal, involving an extension or lengthening by 20 percent of the period within seven periods. The formation of a sequence of three packings will never occur in the succession of packing signals or indications three'successive signals equal to I, nor two successive signals or indications equal to O.

T he principle of the error-correcting device is immediately deduced therefrom. Each time the errorcorrecting device detects two sucessive packing signals equal to 0, it sets the second one at l; and, each time the correcting device detects three successive signals equal to 1, it sets the third one at 0. Moreover, once a correction has been made, the correcting device waits for the passage of at least two new signals prior to proceeding with a new correction.

FIG. 2 shows a succession of packing signals on which nine positions have been specified by way of example, and it has been assumed that one error (valence inversion) is produced on each of thenine positions. The law of the correcting device is to replace by a l a second 0 occurring after a first zero and to replace by a O a third 1 occurring after two ls.

Under these conditions, the correcting device will either carry out an immediate correction, as seen in cases (I), (2), (4), (6), (8) and (9), or there will be a correction made with a time delay, as seen in cases (3), I

and (7). In the first case, the correction relates to an erroneous bit. In the second case, the correction is set offby an incompatibility caused by a previous error by one step. The correction in the third case is effected with a delay in time and it will be noted that the corrected sequence is not identical with the data sequence, but allows an. error to continue'to exist.

If, in cases (3) a nd ('7), once the correction has been made, one were not to take 'the precaution of waiting through two signal periods before making the decision to effect a possible new correction, one would create a chain of corrections, and this would in fact result in a propagation of errors. Instead of such a prejudicial result for the entire transmission, one allows an incompatibility to continue to exist locally; for example, two

0s in case (3) and three ls in case (7). In the case of the immediate correction, the advantage is obvious; the error iserased, i.e.,.there remains no trace of it.

It will be shown hereinbelow that for a particular example in the case of the delayed correction, even though there remains a trace of the error, the correction is no less indispensable. Let it be assumed that the following signal is emitted (and it will be recalled that BB signifies a padded or packed bit and IB signifies a packing indication or packing signal): a

Signal MIC emitted a b l IBcde IBfg h i Signal MIC received without error a b BB 1 c d e 0 f g h Signal MIC received with error a b' 1 0 c d e 0 f g h Signal MIC received corrected a b l O c d e l f g h 4 dataaccordingto (2) -abcdefgh data according to (3) a b l cdefg data'according to (4) a b l c dfg h The error resides in (3) in the passage of the first IB from the valence l to the valence O. The delayed correction resides in the passage of the second IB from the valence 0 to the valence -l. Y It is apparent that, inthe data according to case 3) where the error is not corrected, beyond ab all the bits are displaced; in other words, all the bits are false. In the data according to case (4), there is a disturbance bearing on, or relating to, the bits c d e, which after the correct correspondence is reestablished.

FIG. 3 is a flow diagram which indicates the operation of the correcting device. The correcting device is a sequential system whose configuration evolves as a function of the incident packing or padding indications or signals. This system possesses four stages or states which are interconnected by reason of the-following conditions, as can be ascertained from the flow diagram of FIG. 3.

One passes from the stage (a) to the'stage (B) if IB 0 One passes from the stage (a) to the stage (3/) if I8 l 1 One passes from the stage (B) to the stage (a) if IB O One passes from the stage (,8) to the stage ('3 if I8 1 One passes from the stage (y) to the stage (B) if 13 0 One passes from the stage (7) to the stage (6) if IB l One passes from the stage (8) to the stage (,8) if IB 0 One passes from the stage (6) to the stage (a) if IB Each time there is a passage to the stage (a), there is a correction of the last incident indication. If the system passes from (E) to (a), the last packing indication passes from 0 to 1; if the system passes from (8) to a the last IB passes from 1 to 0. V

On the other hand, the examination of the flow diagram shows clearly that, after making a correction at stage (a), it is necessary to wait at least two, times before making another correction.

FIG. 4 is a schematic diagram of the correcting device of the present invention. The correcting device comprises two subgroups, a member 1 following the operations of the stage of the correcting device, receiving the incident packing indication (IB), and receiving the clock of the packing indications I-IB. There will re-' A B stage a O stage I? O 1 stage 7 l 0 stage 8 l l Deduced from this table is the following truth table:

Instant N stunt N+l Instant N In Instant N IB A B stage A B stage IB' 0 00 a 01. B 0 l 00 a 10 l 0 OI ,B 00 a l+ l 01 B IO 7 I 0 l0 y 01 B O l 10 'y ll 8 l 0 II a OI p 0 I ll IO 0: I+I- There is a correction 0I in the case marked and a correction l0 in the case marked +4- in accordance with the flow diagram of FIG. 3.

FIG. 5 is a diagram of one embodiment ofa correcting device corresponding to the flow diagram of FIG. 3 and to the schematic block diagram of FIG. 4. It comprises at the input an inverter which receives the clock signals of the packing indications HB and an AND circuit 11 which, receiving the incident signal S and the clock signals FE, furnishes an output E. Two flip-

flops

12 and 13 receive on the clock terminal H thereof the signals HB and on the terminals D signals whose origin will be indicated hereinbelow. The

flipflops

12 and 13 furnish respective outputs A and A, B and E.

An inverter 14 and sevenAND circuits 15, l6, l7, 18, 19, and 21 serve to apply to the terminal D of the flip-flop 12 a signal E AB and to the terminal D of the flip-flop 13 a signal A B E (A E). An A lTD circuit 22 receiving signals HE, (A E) and (E E) furnishes signal IE.

The

circuits

21 and 22 are part of the subgroup 2 of FIG. 4. The circuit 20 is part, at the same time, of the subgroup 1 and of the subgroup 2. All the other circuits are part of the subgroup l of FIG. 4.

While there have been shown and described but specific embodiments of the invention, it will be understood by those skilled in the art that the invention is not limited thereto or thereby.

What is claimed is:

1. A device for correcting the packing indication signals in a transmission of telegraphic data, integrated in an MIC pattern with a sampling frequency higher than the telegraphic speed of the transmission of the data so as to include packing or padded bits, comprising input means for receiving the incident MIC signal and clock signals timing the packing indications, and logic means connected to said input means and including four logic states operating sequentially according to the valence of the successive packing indications received for detecting at least two prohibited sequences of packing indication signals and a device for inverting the valence 0-1 of a packing indication signal in response to an output of the second state of said logic means representing detection of one prohibited sequence and for inverting the valence l-O of a packing indication signal in response to an output of the fourth state of said logic means representing detection of the other prohibited sequence.

2. A device for correcting the packing indication according to claim 1 wherein saidlogic means comprises first and second flip-flops each having respective first and second input terminals, whichflip-flops receive respectively on the first input thereof the inverse of said clock signal, and gate means connected to said flipflops for applying to the second inputs thereof respectively two logical signals derived from the output states of said flip-flops, one of which is (E) AB, the other is AE (m) (A E), wherein lB designates the packing indication signal extracted from the incident MIC signal and signals A, A and B, E are the respective outputs of said first and second flip-flops.

3. A device for correcting the packing indication according to claim 2 wherein said input means includes an AND gate having inputs receiving said clock signals and said incident MIC signal, the output of said AND gate being connected to said gate means.

4. A device for correcting the packing indication according to claim 2 including a first AND gate connected to the A and B outputs of said flip-flops, a second AND gate connected to the E output of the flipflop and the inverse of said packing indication signal IB, and a third AND gate connected to the outputs of said first and second AND gates and said clock signals.

5. A device for correcting the packing indication according to claim 4 wherein said gate means includes a fourth AND gate connected to the A and B outputs of said flip-flops, a fifth AND gate connected to the output of said fourth AND gate and to the inverse of said packing indication signal 18, a sixth AND gate connected to the A and E outputs of said flip-flops and a seventh AND gate connected to the outputs of said fifth and sixth AND gates and having an output connected to the second input of said second flip-flop.

6. A device for correcting the packing indication according to claim 5 wherein said gate means includes an eighth AND gate connected to the output of said first AND gate and to said packing indication signal IB and an output connected to the second input of said first flip-flop.

7. A device for correcting the packing indication according to claim 6 wherein said input means includes an AND gate having inputs receiving said clock signals and said incident MIC signal; the output of said AND gate being connected to said gate means.

Claims

1. A device for correcting the packing indication signals in a transmission of telegraphic data, integrated in an MIC pattern with a sampling frequency higher than the telegraphic speed of the transmission of the data so as to include packing or padded bits, comprising input means for receiving the incident MIC signal and clock signals timing the packing indications, and logic means connected to said input means and including four logic states operating sequentially according to the valence of the successive packing indications received for detecting at least two prohibited sequences of packing indication signals and a device for inverting the valence 0-1 of a packing indication signal in response to an output of the second state of said logic means representing detection of one prohibited sequence and for inverting the valence 1-0 of a packing indication signal in response to an output of the fourth state of said logic means representing detection of the other prohibited sequence.

2. A device for correcting the packing indication according to claim 1 wherein said logic means comprises first and second flip-flops each having respective first and second input terminals, which flip-flops receive respectively on the first input thereof the inverse of said clock signal, and gate means connected to said flip-flops for applying to the second inputs thereof respectively two logical signals derived from the output states of said flip-flops, one of which is (IB) + AB, the other is AB + (IB) (A + B), wherein IB designates the packing indication signal extracted from the incident MIC signal and signals A, A and B, B are the respective outputs of said first and second flip-flops.

4. A device for correcting the packing indication according to claim 2 including a first AND gate connected to the A and B outputs of said flip-flops, a second AND gate connected to the B output of the flip-flop and the inverse of said packing indication signal IB, and a third AND gate connected to the outputs of said first and second AND gates and said clock signals.

5. A device for correcting the packing indication according to claim 4 wherein said gate means includes a fourth AND gate connected to the A and B outputs of said flip-flops, a fifth AND gate connected to the output of said fourth AND gate and to the inverse of said packing indication signal IB, a sixth AND gate connected to the A and B outputs of said flip-flops and a seventh AND gate connected to the outputs of said fifth and sixth AND gates and having an output connected to the second input of said second flip-flop.

7. A device for correcting the packing indication according to claim 6 wherein said input means includes an AND gate having inputs receiving said clock signals and said incident MIC signal, the output of said AND gate being connected to said gate means.