US20210135003A1 - Single-chip containing porous-wafer battery and device and method of making the same - Google Patents

Single-chip containing porous-wafer battery and device and method of making the same Download PDF

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US20210135003A1
US20210135003A1 US17/087,600 US202017087600A US2021135003A1 US 20210135003 A1 US20210135003 A1 US 20210135003A1 US 202017087600 A US202017087600 A US 202017087600A US 2021135003 A1 US2021135003 A1 US 2021135003A1
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chip
wafer
pores
region
silicon substrate
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US17/087,600
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Gerard Christopher D'Couto
Slobodan Petrovic
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XNRGI Inc
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XNRGI Inc
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Assigned to XNRGI, INC. reassignment XNRGI, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: D'COUTO, GERARD CHRISTOPHER
Publication of US20210135003A1 publication Critical patent/US20210135003A1/en
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    • H01M50/204—Racks, modules or packs for multiple batteries or multiple cells
    • H01M50/207—Racks, modules or packs for multiple batteries or multiple cells characterised by their shape
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    • H01M10/4257—Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
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Definitions

  • This invention relates generally to a single-chip and a method of making the same. More particularly, the present invention relates to a single-chip containing a porous-wafer battery and a device.
  • One requirement for current and future batteries is the ability to integrate a chip on or in a battery. For example, integrating a controller with a battery in a chip may reduce an overall size of the controller and the battery. It may eliminate long conductive traces. It also provides better safety for battery cells because of a real time monitoring by a nearby controller.
  • Another requirement is to integrate a battery on a device. For example, the battery can provide power to the device.
  • a chip comprises a porous wafer battery and a device.
  • the chip further comprises a wafer containing the device and at least a portion of the porous wafer battery.
  • the wafer comprises a silicon substrate.
  • the silicon substrate comprises a first region and a second region.
  • the first region comprises a plurality of pores of the porous wafer battery.
  • the second region 345 comprises a trench to accommodate a gate electrode of the device.
  • a method of fabrication a chip comprising the steps of providing a substrate comprising a plurality of doped regions; patterning a mask on a front surface of the substrate; applying an etching process forming the plurality of pores in the first region of the substrate and the trench in the second region of the substrate; and then removing the mask.
  • FIG. 1 is a side view of a chip in examples of the present disclosure.
  • FIG. 2 is a side view of another chip in examples of the present disclosure.
  • FIG. 3 is a front view of still another chip in examples of the present disclosure.
  • FIG. 4 is a cross-sectional plot along AA′ of the chip of FIG. 3 in examples of the present disclosure.
  • FIG. 5 is a cross-sectional plot of yet another chip in examples of the present disclosure.
  • FIG. 6 is a flowchart of a portion of a process to develop a chip in examples of the present disclosure.
  • FIGS. 7A, 7B, 7C, and 7D show a portion of the steps of the process to fabricate the chip in examples of the present disclosure.
  • FIG. 1 is a side view of a chip 100 in examples of the present disclosure.
  • the chip 100 comprises a porous wafer battery 120 and a device 140 .
  • a size of the porous wafer battery 120 is larger than a size of the device 140 .
  • the porous wafer battery 120 is of a circular disk shape having a centerline 121 and the device 140 is of a rectangular prism shape.
  • the porous wafer battery 120 comprises a wafer 130 .
  • the wafer 130 comprises a back-end metal layer 132 and a substrate 134 .
  • the back-end metal layer 132 is attached to the substrate 134 .
  • the substrate 134 comprises a plurality of pores 180 (shown in dashed lines because of the side view).
  • the substrate 134 is made of a silicon material.
  • the porous wafer battery 120 is electrically and mechanically connected to the device 140 .
  • a surface of the device 140 is attached to a surface of the back-end metal layer 132 .
  • a surface of the device 140 is directly attached to a surface of the back-end metal layer 132 .
  • the porous wafer battery 120 is electrically and mechanically connected to the device 140 by a plurality of conductive traces.
  • the porous wafer battery 120 is electrically and mechanically connected to the device 140 by a plurality of connecting vias similar to those in FIG. 1 of U.S. Pat. No. 7,794,510 to Hopper, et al.
  • FIG. 2 is a side view of a chip 200 in examples of the present disclosure.
  • the chip 200 comprises a porous wafer battery 220 and a device 240 .
  • a size of the porous wafer battery 220 is smaller than a size of the device 240 .
  • the porous wafer battery 220 is of a circular disk shape having a centerline 221 and the device 240 is of a rectangular prism shape.
  • the porous wafer battery 220 comprises a wafer 230 .
  • the wafer 230 comprises a back-end metal layer 232 and a substrate 234 .
  • the back-end metal layer 232 is attached to the substrate 234 .
  • the substrate 234 comprises a plurality of pores 280 (shown in dashed lines because of the side view).
  • the porous wafer battery 220 is electrically and mechanically connected to the device 240 .
  • FIG. 3 is a front view of a chip 300 in examples of the present disclosure.
  • FIG. 4 is a cross-sectional plot along AA′ of the chip 300 of FIG. 3 in examples of the present disclosure.
  • the chip 300 comprises a porous wafer battery 320 and a device 340 .
  • the porous wafer battery 320 is electrically and mechanically connected to the device 340 .
  • the device is a gate trench power (MOSFET) of FIGS. 4A and 4B of U.S. Pat. No. 9,887,287 to Lichtenwalner, et al.
  • MOSFET gate trench power
  • the chip 300 further comprises a wafer 305 containing the porous wafer battery 320 and the device 340 .
  • the wafer 305 comprises a silicon substrate 310 .
  • the silicon substrate 310 comprises a first region 335 and a second region 345 .
  • the first region 335 comprises a plurality of pores 380 .
  • the second region 345 comprises a trench 483 to accommodate a gate electrode 484 .
  • the first region 335 of the silicon substrate 310 is directly connected to the second region 345 of the silicon substrate 310 .
  • the plurality of pores 380 are not symmetric with respect to X-axis because of the device 340 at the second region 345 .
  • the plurality of pores 380 are not symmetric with respect to Y-axis because of the device 340 at the second region 345 .
  • the silicon substrate 310 is of a circular disk shape having a centerline 331 .
  • a diameter of the silicon substrate 310 is 4 inches.
  • a diameter of the silicon substrate 310 is 6 inches.
  • a diameter of the silicon substrate 310 is 8 inches.
  • a diameter of the silicon substrate 310 is 12 inches.
  • a diameter of the silicon substrate 310 is 18 inches.
  • the device 340 is of a rectangular prism shape.
  • a top surface 435 of the first region 335 and a top surface 445 of the second region 345 are coplanar. Therefore, a same mask can be used for a same etching process to etch the plurality of pores 380 and the trench 483 .
  • a depth 485 of the plurality of pores 380 is larger than a depth 495 of the trench 483 .
  • a depth 485 of the plurality of pores 380 is the same as a depth 495 of the trench 483 .
  • a depth 485 of the plurality of pores 380 is smaller than a depth 495 of the trench 483 .
  • a conductive layer 430 is on a respective side wall 442 of each of the plurality of pores 380 .
  • a passivation layer 476 is on a front side of the first region 335 of the silicon substrate 310 .
  • the first region 335 of the silicon substrate 310 comprises a plurality of pores 380 and a P+ doped region 123 .
  • the passivation layer 476 comprises a plurality of passivation sections 477 .
  • Each of the plurality of passivation sections 477 is of a letter U shape.
  • a first leg 471 of the letter U shape is directly attached to the conductive layer 430 of a first selected pore 491 of the plurality of pores 380 .
  • a second leg 472 of the letter U shape is directly attached to the conductive layer 430 of a second selected pore 492 of the plurality of pores 380 .
  • a length of the first leg 471 and a length of the second leg 472 is in a range from 20 microns to 50 microns.
  • an adhesion promotion layer 447 is between the conductive layer 430 and the respective side wall 442 of each of the plurality of pores 380 .
  • a respective side wall 442 of each of the plurality of pores 380 is perpendicular to a front surface of the silicon substrate 310 .
  • the porous wafer battery 320 is electrically and mechanically connected to another device 399 (optional, shown in dashed lines), external to the chip, through a plurality of conductive traces 398 (optional, shown in dashed lines).
  • the device 340 comprises a p-well region 451 , a heavily-doped n-type source region 453 , a gate electrode 461 , gate insulating layer 463 , and a p-type deep shielding connection pattern 469 .
  • FIG. 5 is a cross-sectional plot of a chip 500 in examples of the present disclosure.
  • the chip 500 comprises a porous wafer battery 520 and a device 540 .
  • the porous wafer battery 520 comprises a plurality of pores 580 .
  • An inclination angle 538 between a respective side wall 542 of each of the plurality of pores 580 and a respective bottom wall 533 of each of the plurality of pores 580 is in a range from 40 degrees to 50 degrees.
  • the lower limit of the inclination angle 538 is to maintain required pitch of the plurality of pores 332 .
  • the upper limit of the inclination angle 538 is to increase metallization efficiency on side walls 542 of the plurality of pores 580 .
  • the device 540 comprises a p-well region 551 , a heavily-doped n-type source region 553 , a gate electrode 561 , gate insulating layer 563 , and a p-type deep shielding connection pattern 569 .
  • the gate electrode 561 is of a trapezoid shape in the cross-sectional plot.
  • the chip 500 further comprises an additional wafer 590 .
  • the additional wafer 590 comprises an additional silicon substrate 592 and an additional passivation layer 591 on a front side of the additional silicon substrate 592 .
  • the additional silicon substrate 592 comprises an additional plurality of pores 594 .
  • the passivation layer 511 of the wafer 510 directly contacts the additional passivation layer 591 of the additional wafer 590 .
  • the first region 509 of the wafer 510 serves as an anode and the additional wafer 590 serves as a cathode.
  • a size of the additional wafer 590 is smaller than a size of the wafer 510 .
  • FIG. 6 is a flowchart of a portion of a process 600 to develop a chip 300 of FIG. 4 in examples of the present disclosure.
  • the process 600 may start from block 602 .
  • a substrate 700 is provided.
  • the substrate 700 is a silicon wafer.
  • the substrate 700 comprises a plurality of doped regions 702 .
  • Block 602 may be followed by block 604 .
  • Block 604 referring now to FIG. 7B , a mask 722 is patterned on the substrate 700 .
  • Block 604 may be followed by block 606 .
  • Block 606 referring now to FIG. 7C , an etching process is performed.
  • a trench 783 to receive gate electrode and a plurality of pores 780 are formed.
  • Block 606 may be followed by block 608 .
  • the device 240 is fabricated. Then, the porous wafer battery 220 is implanted on the device 240 .
  • the porous wafer battery 120 is fabricated. Then, the device 140 is implanted on the porous wafer battery 120 .
  • the device 340 and the porous wafer battery 220 are made from a same wafer and share a predetermined manufacturing steps.
  • the porous wafer battery 520 is made by a first wafer and a second wafer.
  • the device 540 and a portion of the porous wafer battery 520 are made from the first wafer and share a predetermined manufacturing steps.

Abstract

A chip comprises a porous wafer battery and a device. The chip further comprises a wafer containing the device and at least a portion of the porous wafer battery. The wafer comprises a silicon substrate. The silicon substrate comprises a first region and a second region. The first region comprises a plurality of pores of the porous wafer battery. The second region 345 comprises a trench to accommodate a gate electrode of the device. A method of fabrication a chip comprising the steps of providing a substrate comprising a plurality of doped regions; patterning a mask on a front surface of the substrate; applying an etching process forming the plurality of pores in the first region of the substrate and the trench in the second region of the substrate; and then removing the mask.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This patent application claims benefit of provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 because of a common inventor, Slobodan Petrovic. The disclosures made in the provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 are hereby incorporated by reference. The disclosures made in U.S. Ser. No. 7,794,510 to Hopper, et al. and U.S. Ser. No. 9,887,287 to Lichtenwalner, et al. are also hereby incorporated by reference.
    • FIELD OF THE INVENTION
  • This invention relates generally to a single-chip and a method of making the same. More particularly, the present invention relates to a single-chip containing a porous-wafer battery and a device.
    • BACKGROUND OF THE INVENTION
  • As devices become smaller and more powerful, the demand for batteries having a decreased size, while keeping or increasing capacity and current ability is necessitated. The current state of the art including lithium and other types of batteries are not able to meet the needs for this demand. Current design of lithium batteries only has a limited potential for energy storage because of the cell design and the requirement of packaging.
  • One requirement for current and future batteries is the ability to integrate a chip on or in a battery. For example, integrating a controller with a battery in a chip may reduce an overall size of the controller and the battery. It may eliminate long conductive traces. It also provides better safety for battery cells because of a real time monitoring by a nearby controller. Another requirement is to integrate a battery on a device. For example, the battery can provide power to the device.
    • SUMMARY OF THE INVENTION
  • A chip comprises a porous wafer battery and a device. The chip further comprises a wafer containing the device and at least a portion of the porous wafer battery. The wafer comprises a silicon substrate. The silicon substrate comprises a first region and a second region. The first region comprises a plurality of pores of the porous wafer battery. The second region 345 comprises a trench to accommodate a gate electrode of the device.
  • A method of fabrication a chip comprising the steps of providing a substrate comprising a plurality of doped regions; patterning a mask on a front surface of the substrate; applying an etching process forming the plurality of pores in the first region of the substrate and the trench in the second region of the substrate; and then removing the mask.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a side view of a chip in examples of the present disclosure.
  • FIG. 2 is a side view of another chip in examples of the present disclosure.
  • FIG. 3 is a front view of still another chip in examples of the present disclosure.
  • FIG. 4 is a cross-sectional plot along AA′ of the chip of FIG. 3 in examples of the present disclosure.
  • FIG. 5 is a cross-sectional plot of yet another chip in examples of the present disclosure.
  • FIG. 6 is a flowchart of a portion of a process to develop a chip in examples of the present disclosure.
  • FIGS. 7A, 7B, 7C, and 7D show a portion of the steps of the process to fabricate the chip in examples of the present disclosure.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 is a side view of a chip 100 in examples of the present disclosure. The chip 100 comprises a porous wafer battery 120 and a device 140. A size of the porous wafer battery 120 is larger than a size of the device 140. In examples of the present disclosure, the porous wafer battery 120 is of a circular disk shape having a centerline 121 and the device 140 is of a rectangular prism shape. The porous wafer battery 120 comprises a wafer 130. The wafer 130 comprises a back-end metal layer 132 and a substrate 134. The back-end metal layer 132 is attached to the substrate 134. The substrate 134 comprises a plurality of pores 180 (shown in dashed lines because of the side view). In examples of the present disclosure, the substrate 134 is made of a silicon material. The porous wafer battery 120 is electrically and mechanically connected to the device 140. In one example, a surface of the device 140 is attached to a surface of the back-end metal layer 132. In another example, a surface of the device 140 is directly attached to a surface of the back-end metal layer 132. In still another example, the porous wafer battery 120 is electrically and mechanically connected to the device 140 by a plurality of conductive traces. In yet another example, the porous wafer battery 120 is electrically and mechanically connected to the device 140 by a plurality of connecting vias similar to those in FIG. 1 of U.S. Pat. No. 7,794,510 to Hopper, et al.
  • FIG. 2 is a side view of a chip 200 in examples of the present disclosure. The chip 200 comprises a porous wafer battery 220 and a device 240. A size of the porous wafer battery 220 is smaller than a size of the device 240. In examples of the present disclosure, the porous wafer battery 220 is of a circular disk shape having a centerline 221 and the device 240 is of a rectangular prism shape. The porous wafer battery 220 comprises a wafer 230. The wafer 230 comprises a back-end metal layer 232 and a substrate 234. The back-end metal layer 232 is attached to the substrate 234. The substrate 234 comprises a plurality of pores 280 (shown in dashed lines because of the side view). The porous wafer battery 220 is electrically and mechanically connected to the device 240.
  • FIG. 3 is a front view of a chip 300 in examples of the present disclosure. FIG. 4 is a cross-sectional plot along AA′ of the chip 300 of FIG. 3 in examples of the present disclosure. The chip 300 comprises a porous wafer battery 320 and a device 340. The porous wafer battery 320 is electrically and mechanically connected to the device 340. In examples of the present disclosure, the device is a gate trench power (MOSFET) of FIGS. 4A and 4B of U.S. Pat. No. 9,887,287 to Lichtenwalner, et al.
  • The chip 300 further comprises a wafer 305 containing the porous wafer battery 320 and the device 340. The wafer 305 comprises a silicon substrate 310. The silicon substrate 310 comprises a first region 335 and a second region 345. The first region 335 comprises a plurality of pores 380. The second region 345 comprises a trench 483 to accommodate a gate electrode 484. The first region 335 of the silicon substrate 310 is directly connected to the second region 345 of the silicon substrate 310. The plurality of pores 380 are not symmetric with respect to X-axis because of the device 340 at the second region 345. The plurality of pores 380 are not symmetric with respect to Y-axis because of the device 340 at the second region 345.
  • In examples of the present disclosure, the silicon substrate 310 is of a circular disk shape having a centerline 331. In one example, a diameter of the silicon substrate 310 is 4 inches. In another example, a diameter of the silicon substrate 310 is 6 inches. In still another example, a diameter of the silicon substrate 310 is 8 inches. In yet another example, a diameter of the silicon substrate 310 is 12 inches. In yet still another example, a diameter of the silicon substrate 310 is 18 inches. The device 340 is of a rectangular prism shape.
  • In examples of the present disclosure, a top surface 435 of the first region 335 and a top surface 445 of the second region 345 are coplanar. Therefore, a same mask can be used for a same etching process to etch the plurality of pores 380 and the trench 483.
  • In one example, a depth 485 of the plurality of pores 380 is larger than a depth 495 of the trench 483. In another example, a depth 485 of the plurality of pores 380 is the same as a depth 495 of the trench 483. In still another example, a depth 485 of the plurality of pores 380 is smaller than a depth 495 of the trench 483.
  • In examples of the present disclosure, a conductive layer 430 is on a respective side wall 442 of each of the plurality of pores 380. A passivation layer 476 is on a front side of the first region 335 of the silicon substrate 310. The first region 335 of the silicon substrate 310 comprises a plurality of pores 380 and a P+ doped region 123. The passivation layer 476 comprises a plurality of passivation sections 477. Each of the plurality of passivation sections 477 is of a letter U shape. A first leg 471 of the letter U shape is directly attached to the conductive layer 430 of a first selected pore 491 of the plurality of pores 380. A second leg 472 of the letter U shape is directly attached to the conductive layer 430 of a second selected pore 492 of the plurality of pores 380. A length of the first leg 471 and a length of the second leg 472 is in a range from 20 microns to 50 microns.
  • In examples of the present disclosure, an adhesion promotion layer 447 is between the conductive layer 430 and the respective side wall 442 of each of the plurality of pores 380.
  • In examples of the present disclosure, a respective side wall 442 of each of the plurality of pores 380 is perpendicular to a front surface of the silicon substrate 310.
  • In examples of the present disclosure, the porous wafer battery 320 is electrically and mechanically connected to another device 399 (optional, shown in dashed lines), external to the chip, through a plurality of conductive traces 398 (optional, shown in dashed lines).
  • Similar to FIGS. 4A and 4B of U.S. Pat. No. 9,887,287 to Lichtenwalner, et al., the device 340 comprises a p-well region 451, a heavily-doped n-type source region 453, a gate electrode 461, gate insulating layer 463, and a p-type deep shielding connection pattern 469.
  • FIG. 5 is a cross-sectional plot of a chip 500 in examples of the present disclosure. The chip 500 comprises a porous wafer battery 520 and a device 540. The porous wafer battery 520 comprises a plurality of pores 580. An inclination angle 538 between a respective side wall 542 of each of the plurality of pores 580 and a respective bottom wall 533 of each of the plurality of pores 580 is in a range from 40 degrees to 50 degrees. The lower limit of the inclination angle 538 is to maintain required pitch of the plurality of pores 332. The upper limit of the inclination angle 538 is to increase metallization efficiency on side walls 542 of the plurality of pores 580.
  • Similar to FIG. 5 of U.S. Pat. No. 9,887,287 to Lichtenwalner, et al., the device 540 comprises a p-well region 551, a heavily-doped n-type source region 553, a gate electrode 561, gate insulating layer 563, and a p-type deep shielding connection pattern 569. The gate electrode 561 is of a trapezoid shape in the cross-sectional plot.
  • In examples of the present disclosure, the chip 500 further comprises an additional wafer 590. The additional wafer 590 comprises an additional silicon substrate 592 and an additional passivation layer 591 on a front side of the additional silicon substrate 592. The additional silicon substrate 592 comprises an additional plurality of pores 594. The passivation layer 511 of the wafer 510 directly contacts the additional passivation layer 591 of the additional wafer 590. The first region 509 of the wafer 510 serves as an anode and the additional wafer 590 serves as a cathode. In examples of the present disclosure, a size of the additional wafer 590 is smaller than a size of the wafer 510.
  • FIG. 6 is a flowchart of a portion of a process 600 to develop a chip 300 of FIG. 4 in examples of the present disclosure. The process 600 may start from block 602.
  • In block 602, referring now to FIG. 7A, a substrate700 is provided. In examples of the present disclosure, the substrate 700 is a silicon wafer. The substrate700 comprises a plurality of doped regions 702. Block 602 may be followed by block 604.
  • In block 604, referring now to FIG. 7B, a mask 722 is patterned on the substrate 700. Block 604 may be followed by block 606.
  • In block 606, referring now to FIG. 7C, an etching process is performed. A trench 783 to receive gate electrode and a plurality of pores 780 are formed. Block 606 may be followed by block 608.
  • In block 606, referring now to FIG. 7D, the mask 722 of FIG. 7B is removed. Surfaces 741 are exposed.
  • Similar to FIG. 3A of provisional patent applications 62/930,018, the device 240 is fabricated. Then, the porous wafer battery 220 is implanted on the device 240.
  • Similar to FIG. 3B of provisional patent applications 62/930,018, the porous wafer battery 120 is fabricated. Then, the device 140 is implanted on the porous wafer battery 120.
  • Similar to FIG. 3C of provisional patent applications 62/930,018, the device 340 and the porous wafer battery 220 are made from a same wafer and share a predetermined manufacturing steps.
  • Similar to FIG. 3D of provisional patent applications 62/930,018, the porous wafer battery 520 is made by a first wafer and a second wafer. The device 540 and a portion of the porous wafer battery 520 are made from the first wafer and share a predetermined manufacturing steps.
  • Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the plurality of pores may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.

Claims (16)

1. A chip comprising
a porous wafer battery; and
a device;
wherein the porous wafer battery is electrically and mechanically connected to the device.
2. The chip of claim 1, wherein the porous wafer battery comprises
a wafer comprising
a back-end metal layer; and
a substrate comprising
a plurality of pores;
wherein the back-end metal layer is attached to the substrate; and
wherein a bottom surface of the device is attached to the back-end metal layer of the wafer.
3. The chip of claim 1 further comprising a wafer containing the porous wafer battery and the device.
4. The chip of claim 3, wherein the wafer comprises
a silicon substrate comprising
a first region comprising
a plurality of pores; and
a second region comprising
a trench to accommodate a gate electrode.
5. The chip of claim 4, wherein the first region of the silicon substrate is directly connected to the second region of the silicon substrate.
6. The chip of claim 5, wherein a top surface of the first region and a top surface of the second region are coplanar.
7. The chip of claim 4, wherein a conductive layer is on a respective side wall of each of the plurality of pores; and
a passivation layer is on a front side of the first region of the silicon substrate.
8. The chip of claim 7, wherein an adhesion promotion layer is between the conductive layer and the respective side wall of each of the plurality of pores.
9. The chip of claim 7, wherein the passivation layer comprises a plurality of passivation sections; and
wherein each of the plurality of passivation sections is of a letter U shape;
10. The chip of claim 9, wherein a first leg of the letter U shape is directly attached to the conductive layer of a first selected pore of the plurality of pores; and
wherein a second leg of the letter U shape is directly attached to the conductive layer of a second selected pore of the plurality of pores.
11. The chip of claim 7, wherein a respective side wall of each of the plurality of pores is perpendicular to a front surface of the silicon substrate.
12. The chip of claim 7, wherein an inclination angle between a respective side wall of each of the plurality of pores and a respective bottom wall of each of the plurality of pores is in a range from forty degrees to fifty degrees.
13. The chip of claim 7 further comprising an additional wafer comprising
an additional silicon substrate comprising
an additional plurality of pores; and
an additional passivation layer on a front side of the additional silicon substrate;
wherein the passivation layer of the wafer directly contacts the additional passivation layer of the additional wafer.
14. The chip of claim 13, wherein the first region of the wafer serves as an anode and the additional wafer serves as a cathode.
15. A method of fabrication the chip of claim 4, the method comprising the steps of providing a substrate comprising a plurality of doped regions;
patterning a mask on a front surface of the substrate;
applying an etching process forming the plurality of pores in the first region of the silicon substrate and the trench in the second region of the silicon substrate; and
removing the mask.
16. The chip of claim 1, wherein the porous wafer battery is electrically and mechanically connected to another device external to the chip.
US17/087,600 2019-11-04 2020-11-02 Single-chip containing porous-wafer battery and device and method of making the same Pending US20210135003A1 (en)

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