US20210135311A1 - Battery package containing porous wafer battery - Google Patents
Battery package containing porous wafer battery Download PDFInfo
- Publication number
- US20210135311A1 US20210135311A1 US17/087,604 US202017087604A US2021135311A1 US 20210135311 A1 US20210135311 A1 US 20210135311A1 US 202017087604 A US202017087604 A US 202017087604A US 2021135311 A1 US2021135311 A1 US 2021135311A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- porous
- battery
- housing
- battery package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 235000012431 wafers Nutrition 0.000 claims abstract description 154
- 238000001816 cooling Methods 0.000 claims abstract description 40
- 239000011148 porous material Substances 0.000 claims abstract description 29
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 239000007788 liquid Substances 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000003063 flame retardant Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000002826 coolant Substances 0.000 description 2
- 238000013016 damping Methods 0.000 description 2
- 238000002386 leaching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GUHKMHMGKKRFDT-UHFFFAOYSA-N 1785-64-4 Chemical compound C1CC(=C(F)C=2F)C(F)=C(F)C=2CCC2=C(F)C(F)=C1C(F)=C2F GUHKMHMGKKRFDT-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M50/00—Constructional details or processes of manufacture of the non-active parts of electrochemical cells other than fuel cells, e.g. hybrid cells
- H01M50/20—Mountings; Secondary casings or frames; Racks, modules or packs; Suspension devices; Shock absorbers; Transport or carrying devices; Holders
- H01M50/204—Racks, modules or packs for multiple batteries or multiple cells
- H01M50/207—Racks, modules or packs for multiple batteries or multiple cells characterised by their shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M10/4257—Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M10/0436—Small-sized flat cells or batteries for portable equipment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M10/0477—Construction or manufacture in general with circular plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/05—Accumulators with non-aqueous electrolyte
- H01M10/052—Li-accumulators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/05—Accumulators with non-aqueous electrolyte
- H01M10/058—Construction or manufacture
- H01M10/0585—Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/60—Heating or cooling; Temperature control
- H01M10/61—Types of temperature control
- H01M10/613—Cooling or keeping cold
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/60—Heating or cooling; Temperature control
- H01M10/61—Types of temperature control
- H01M10/615—Heating or keeping warm
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/13—Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/62—Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
- H01M4/624—Electric conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M4/62—Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
- H01M4/628—Inhibitors, e.g. gassing inhibitors, corrosion inhibitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
- H01L2021/60135—Applying energy, e.g. for the soldering or alloying process using convection, e.g. reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M4/00—Electrodes
- H01M4/02—Electrodes composed of, or comprising, active material
- H01M2004/021—Physical characteristics, e.g. porosity, surface area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/04—Construction or manufacture in general
- H01M2010/0495—Nanobatteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- This invention relates generally to a battery package. More particularly, the present invention relates to a battery package containing one or more porous wafer batteries.
- a battery stack contains a plurality of single cell batteries is formed.
- a battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
- each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
- a plurality of wafers may be stacked in a housing.
- the housing can be a solid housing.
- the housing may include tabs, slots or grooves for holding the wafers in place.
- the housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
- Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
- a battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries.
- Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery.
- Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode.
- a first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode.
- the battery package further comprises a plurality of heating wafers and a plurality of cooling wafers.
- a cavity of the housing may be filled with a liquid.
- FIG. 1 shows a side view of a battery package comprising a single porous wafer battery in examples of the present disclosure.
- FIG. 2 shows a side view of a battery package comprising a single porous two-wafer battery in examples of the present disclosure.
- FIG. 3 shows a side view of a battery package comprising a porous wafer battery and a porous two-wafer battery in examples of the present disclosure.
- FIG. 4 shows a side view of a battery package comprising a plurality of slots and a plurality of spacers in examples of the present disclosure.
- FIG. 5 shows a side view of a battery package comprising a plurality of slots in examples of the present disclosure.
- FIG. 6 shows a side view of a battery package comprising a cooling wafer in examples of the present disclosure.
- FIG. 7 shows a side view of a battery package comprising an anode tab and a cathode tab in examples of the present disclosure.
- FIG. 8 shows a top view of a porous wafer and a slot in examples of the present disclosure.
- FIG. 1 shows a side view of a battery package 100 in examples of the present disclosure.
- the battery package 100 comprises a single porous wafer battery 140 and a housing 120 enclosing the single porous wafer battery 140 .
- the housing 120 is shown in transparent.
- the housing 120 comprises a cavity 122 .
- the single porous wafer battery 140 is disposed in the cavity 122 of the housing 120 .
- the single porous wafer battery 140 is of a circular wafer shape.
- the housing 120 is of a cylinder shape.
- the single porous wafer battery 140 and the housing 120 share a same centerline 150 .
- a diameter of the single porous wafer battery 140 is 4 inches. In another example, a diameter of the single porous wafer battery 140 is 6 inches. In still another example, a diameter of the single porous wafer battery 140 is 8 inches. In yet another example, a diameter of the single porous wafer battery 140 is 12 inches. In yet still another example, a diameter of the single porous wafer battery 140 is 18 inches.
- the single porous wafer battery 140 comprises a plurality of pores 142 (shown in dashed lines in a side view plot).
- the battery package 100 does not contain another porous wafer battery.
- Each of the plurality of pores 142 comprises a respective anode 143 and a respective cathode 145 .
- Each of the plurality of pores 142 is parallel to one another.
- a depth of each of the plurality of pores 142 is larger than a half of a thickness of the single porous wafer battery 140 .
- the battery package 100 is communicated with an optional external system 192 (shown in dashed lines because it is optional) by a wired or wireless connection 191 .
- the optional external system 192 may be a mobile device or a power grid in a house.
- the battery package 100 is connected to an optional heating device 194 (shown in dashed lines because it is optional) through a pipe 193 to heat up the battery package 100 in an initial ramping up state to increase efficiency.
- the optional heating device 194 may be a heater or a heat exchanger.
- the battery package 100 is connected to an optional conditional device 196 (shown in dashed lines because it is optional) through a pipe 195 to reduce the temperature of the battery package 100 during operation.
- the optional conditional device 196 may be a radiator, a compressor, or a heat sink.
- the battery package 100 excludes a wafer-level sub-housing 121 (shown in dotted lines because of being excluded) enclosing the single porous wafer battery 140 .
- FIG. 2 shows a side view of a battery package 200 in examples of the present disclosure.
- the battery package 200 comprises a single porous two-wafer battery 230 and a housing 220 .
- the single porous two-wafer battery 230 comprises a first porous wafer 240 serving as an anode and a second porous wafer 250 serving as a cathode.
- the first porous wafer 240 comprises a first plurality of pores 242 .
- the second porous wafer 250 comprises a second plurality of pores 252 .
- the housing 220 is shown in transparent.
- the housing 220 comprises a cavity 222 .
- the single porous two-wafer battery 230 is disposed in the cavity 222 of the housing 220 .
- the first porous wafer 240 is of a circular wafer shape.
- the second porous wafer 250 is of a circular wafer shape.
- the housing 220 is of a cylinder shape. The first porous wafer 240 , the second porous wafer 250 , and the housing 220 share a same centerline 251 .
- the single porous two-wafer battery 230 does not contain another porous wafer battery.
- the cavity 222 of the housing 220 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 200 is under shock or vibration.
- the cavity 222 of the housing 220 is filled with water.
- the cavity 222 of the housing 220 is filled with water containing coolant.
- the cavity 222 of the housing 220 When the cavity 222 of the housing 220 is in a positive pressure environment, it may reduce leaching of exterior ambient substance into the battery package 200 . When the cavity 222 of the housing 220 is in a vacuum state (in one example, less than one torr), it may reduce leaching of substance of the battery package 200 into environment.
- a plurality of inner surfaces of the housing 220 is coated with a layer 271 (shown in dashed line because of being optional) of fire retardant material.
- a plurality of outer surfaces of the housing 220 is coated with a layer 273 (shown in dashed line because of being optional) of fire retardant material.
- the fire retardant material may be made of Parylene-F.
- FIG. 3 shows a side view of a battery package 300 in examples of the present disclosure.
- the battery package 300 comprises a porous wafer battery 310 , a porous two-wafer battery 330 , a first slot 371 , a second slot 373 , a third slot 375 , and a housing 320 .
- the porous wafer battery 310 comprises a plurality of pores 312 (shown in dashed lines in a side view plot). Each of the plurality of pores 312 comprises a respective anode and a respective cathode.
- the porous two-wafer battery 330 comprises a first porous wafer 340 serving as an anode and a second porous wafer 350 serving as a cathode.
- the first porous wafer 340 comprises a first plurality of pores 342 .
- the second porous wafer 350 comprises a second plurality of pores 352 .
- the housing 320 is shown in transparent.
- the housing 320 comprises a cavity 322 .
- the porous wafer battery 310 and the porous two-wafer battery 330 are disposed in the cavity 322 of the housing 320 .
- the porous wafer battery 310 is of a circular wafer shape.
- the first porous wafer 340 is of a circular wafer shape.
- the second porous wafer 350 is of a circular wafer shape.
- the housing 320 is of a cylinder shape.
- Each of the first slot 371 , the second slot 373 , and the third slot 375 is of a circular ring shape or of arc sections of a ring shape.
- the porous wafer battery 310 is inserted in the first slot 371 .
- the first porous wafer 340 is inserted in the second slot 373 .
- the second porous wafer 350 is inserted in the third slot 375 .
- a shortest distance 381 between the porous wafer battery 310 and the porous two-wafer battery 330 is larger than a distance 383 between the first porous wafer 340 and the second porous wafer 350 .
- FIG. 4 shows a side view of a battery package 400 in examples of the present disclosure.
- the battery package 400 comprises a plurality of porous wafer batteries 410 , a plurality of slots 470 , a heating wafer 451 , a cooling wafer 461 , and a housing 420 .
- the housing 420 is shown in transparent.
- the plurality of porous wafer batteries 410 , the heating wafer 451 , and the cooling wafer 461 are inserted into the plurality of slots 470 respectively.
- the heating wafer 451 comprises a heating element 453 .
- the heating element 453 may include resistors, a heater or a heat exchanger.
- the cooling wafer 461 comprising a cooling element 463 .
- the cooling element 463 may include a radiator, a compressor, or a heat sink.
- the housing 420 comprises a cavity 422 .
- the cavity 422 of the housing 420 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 400 is under shock or vibration.
- the cavity 422 of the housing 420 is filled with water.
- the cavity 422 of the housing 420 is filled with water containing coolant.
- the plurality of porous wafer batteries 410 are sealed. The sealing process may use one or more caps similar to those of U.S. Pat. No. 6,969,639 to Cho, et al. except that no dicing process is needed.
- the plurality of porous wafer batteries 410 are submerged in the liquid.
- the battery package 400 further comprises a plurality of spacers 490 (shown in dashed lines because of being optional). Each of the plurality of spacers 490 is between a respective pair of the plurality of slots 470 . Each of the plurality of spacers 490 is of a circular ring shape or of arc sections of a ring shape.
- FIG. 5 shows a side view of a battery package 500 in examples of the present disclosure.
- the battery package 500 comprises a plurality of porous wafer batteries 510 , a plurality of slots 570 , a temperature-adjusting wafer 551 , and a housing 520 .
- the housing 520 is shown in transparent.
- the plurality of porous wafer batteries 510 and the temperature-adjusting wafer 551 are inserted into the plurality of slots 570 respectively.
- the temperature-adjusting wafer 551 comprises a heating element 553 and a cooling element 563 .
- the heating element 553 may include resistors, a heater or a heat exchanger.
- the cooling element 563 may include a radiator, a compressor, or a heat sink.
- the housing 520 further comprises an anode tab 527 and a cathode tab 529 .
- the anode tab 527 and the cathode tab 529 are on a same end of the housing 520 .
- the battery package 500 further comprises a first plurality of conductive members 591 and a second plurality of conductive members 593 (shown in dashed lines because of being an example).
- the first plurality of conductive members 591 connect a respective anode of each of the plurality of porous wafer batteries 510 to the anode tab 527 of the housing 520 .
- a second plurality of conductive members 593 connect a respective cathode of each of the plurality of porous wafer batteries 510 to the cathode tab 529 of the housing 520 .
- the first plurality of conductive members 591 and the second plurality of conductive members 593 may be conductive traces, connectors, or wires.
- the plurality of porous wafer batteries 510 are configured in parallel in the circuit including the first plurality of conductive members 591 and the second plurality of conductive members 593 . Therefore, even the porous wafer battery corresponding to the slot 579 is removed, the battery package 500 is still functioning.
- FIG. 6 shows a side view of a battery package 600 in examples of the present disclosure.
- the battery package 600 comprises a plurality of porous wafer batteries 610 , a plurality of slots 670 , a cooling wafer 661 , and a housing 620 .
- the housing 620 is shown in transparent.
- the housing 420 comprises a cavity 422 .
- the plurality of slots 670 are attached to an inner surface of the housing 620 .
- the plurality of porous wafer batteries 610 are inserted into the plurality of slots 670 respectively.
- the cooling wafer 661 comprises a cooling element 663 .
- the cooling element 663 may include a radiator, a compressor, or a heat sink.
- a majority portion, more than 50%, of the cooling wafer 661 is disposed external to the housing 620 .
- a minority portion, less than 50%, of the cooling wafer is disposed in the cavity 622 of the housing 620 .
- An entirely of the cooling element 663 is disposed external to the housing 620 .
- FIG. 7 shows a side view of a battery package 700 in examples of the present disclosure.
- the battery package 700 comprises a plurality of porous wafer batteries 710 , a plurality of slot 770 , a plurality of cooling wafers 750 , and a housing 720 .
- the housing 720 is shown in transparent.
- the housing 720 comprises a cavity 722 .
- the plurality of porous wafer batteries 710 and the plurality of cooling wafers 750 are inserted into the plurality of slot 770 respectively.
- the plurality of cooling wafers 750 comprises a first cooling wafer 751 and a second cooling wafer 757 .
- the first cooling wafer 751 comprises a first cooling element 753 .
- the second cooling wafer 757 comprises a second cooling element 759 .
- the first cooling element 753 and the second cooling element 759 may include a radiator, a compressor, or a heat sink.
- the housing 720 further comprises an anode tab 727 and a cathode tab 729 .
- the anode tab 727 and the cathode tab 729 are on opposite ends of the housing 720 respectively.
- the battery package 700 further comprises a first plurality of conductive members 791 and a second plurality of conductive members 793 (shown in dashed lines because of being an example).
- the first plurality of conductive members 791 connect a respective anode of each of the plurality of porous wafer batteries 710 to the anode tab 727 of the housing 720 .
- a second plurality of conductive members 793 connect a respective cathode of each of the plurality of porous wafer batteries 710 to the cathode tab 729 of the housing 720 .
- the first plurality of conductive members 791 and the second plurality of conductive members 793 may be conductive traces, connectors, or wires.
- FIG. 8 shows a top view of a porous wafer 810 and a slot 870 in examples of the present disclosure.
- the porous wafer 810 comprises a plurality of pores 820 and a contact region 811 .
- the plurality of pores 820 are symmetric with respect to a center 831 of the porous wafer 810 .
- the plurality of pores 820 are symmetric with X-axis.
- the plurality of pores 820 are symmetric with X-axis.
- the plurality of pores 820 are of rectangular shapes.
- the plurality of pores 820 are of circular shapes.
- the slot 870 comprises a contact region 871 and a groove 872 .
- the contact region 871 of the slot 870 directly contacts the contact region 811 of the porous wafer 810 .
- a radius of the groove 872 is 1% to 3% smaller than a radius of the porous wafer 810 so that the porous wafer 810 is pressed fitted into the slot 870 .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
- Secondary Cells (AREA)
- Battery Mounting, Suspending (AREA)
- Battery Electrode And Active Subsutance (AREA)
Abstract
A battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries. Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery. Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode. A first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode. The battery package further comprises a plurality of heating wafers and a plurality of cooling wafers. A cavity of the housing may be filled with a liquid.
Description
- This patent application claims benefit of provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 because of a common inventor, Slobodan Petrovic. The disclosures made in the provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 are hereby incorporated by reference. The disclosure made in U.S. Pat. No. 6,969,639 to Cho, et al. is also hereby incorporated by reference.
- This invention relates generally to a battery package. More particularly, the present invention relates to a battery package containing one or more porous wafer batteries.
- Applications for vehicles or stationary apparatus require large size batteries. Currently, the industry standard for large size battery is to take standardized or proprietary small scale batteries and package them together to form a large size battery. For example, hundreds or thousands of 18650-type batteries are packaged together to form a large size battery. It is inefficient because each cell requires casing, packaging or housing. Thus, it lowers the energy density of the stack. It also induces problems for cooling, longevity and maintenance, and replacement. Some current players in the industry, Panasonic and Tesla, tried to introduce the 2170-type cell. 2170-type is larger than 18650-type. The large number of individually packaging cells requires packaging with complex heat distribution capability and interconnections between the cells. Other manufacturers also introduced larger cells including cells as large as 20 Ah, in a pouch cell package. It results in packing a large number of pouch cells stacked next to one another or in strings on top of one another. It is still inefficient and faces many challenges due to non-uniform current distribution, sensitivity of welded contact tabs and excessive heat generation issue. Those batteries are also expensive because each 20 Ah cell has a pouch package. In large scale manufacturing, it still does not realize a true cost effective package and application.
- Therefore, there is a need for a high-power density, high current and low cost battery stack facilitating efficiently scaling the size of the battery.
- The present disclosure does not require special packing used in current large-size battery industry. A battery stack contains a plurality of single cell batteries is formed.
- A battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
- In one example, each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
- A plurality of wafers may be stacked in a housing. The housing can be a solid housing. The housing may include tabs, slots or grooves for holding the wafers in place. The housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
- Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
- A battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries. Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery. Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode. A first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode.
- The battery package further comprises a plurality of heating wafers and a plurality of cooling wafers. A cavity of the housing may be filled with a liquid.
-
FIG. 1 shows a side view of a battery package comprising a single porous wafer battery in examples of the present disclosure. -
FIG. 2 shows a side view of a battery package comprising a single porous two-wafer battery in examples of the present disclosure. -
FIG. 3 shows a side view of a battery package comprising a porous wafer battery and a porous two-wafer battery in examples of the present disclosure. -
FIG. 4 shows a side view of a battery package comprising a plurality of slots and a plurality of spacers in examples of the present disclosure. -
FIG. 5 shows a side view of a battery package comprising a plurality of slots in examples of the present disclosure. -
FIG. 6 shows a side view of a battery package comprising a cooling wafer in examples of the present disclosure. -
FIG. 7 shows a side view of a battery package comprising an anode tab and a cathode tab in examples of the present disclosure. -
FIG. 8 shows a top view of a porous wafer and a slot in examples of the present disclosure. -
FIG. 1 shows a side view of abattery package 100 in examples of the present disclosure. Thebattery package 100 comprises a singleporous wafer battery 140 and ahousing 120 enclosing the singleporous wafer battery 140. Thehousing 120 is shown in transparent. Thehousing 120 comprises acavity 122. The singleporous wafer battery 140 is disposed in thecavity 122 of thehousing 120. In examples of the present disclosure, the singleporous wafer battery 140 is of a circular wafer shape. Thehousing 120 is of a cylinder shape. The singleporous wafer battery 140 and thehousing 120 share asame centerline 150. - In one example, a diameter of the single
porous wafer battery 140 is 4 inches. In another example, a diameter of the singleporous wafer battery 140 is 6 inches. In still another example, a diameter of the singleporous wafer battery 140 is 8 inches. In yet another example, a diameter of the singleporous wafer battery 140 is 12 inches. In yet still another example, a diameter of the singleporous wafer battery 140 is 18 inches. - In examples of the present disclosure, the single
porous wafer battery 140 comprises a plurality of pores 142 (shown in dashed lines in a side view plot). Thebattery package 100 does not contain another porous wafer battery. Each of the plurality ofpores 142 comprises arespective anode 143 and arespective cathode 145. Each of the plurality ofpores 142 is parallel to one another. A depth of each of the plurality ofpores 142 is larger than a half of a thickness of the singleporous wafer battery 140. - In examples of the present disclosure, the
battery package 100 is communicated with an optional external system 192 (shown in dashed lines because it is optional) by a wired orwireless connection 191. The optionalexternal system 192 may be a mobile device or a power grid in a house. Thebattery package 100 is connected to an optional heating device 194 (shown in dashed lines because it is optional) through apipe 193 to heat up thebattery package 100 in an initial ramping up state to increase efficiency. Theoptional heating device 194 may be a heater or a heat exchanger. Thebattery package 100 is connected to an optional conditional device 196 (shown in dashed lines because it is optional) through apipe 195 to reduce the temperature of thebattery package 100 during operation. The optionalconditional device 196 may be a radiator, a compressor, or a heat sink. - In examples of the present disclosure, the
battery package 100 excludes a wafer-level sub-housing 121 (shown in dotted lines because of being excluded) enclosing the singleporous wafer battery 140. -
FIG. 2 shows a side view of abattery package 200 in examples of the present disclosure. Thebattery package 200 comprises a single porous two-wafer battery 230 and ahousing 220. The single porous two-wafer battery 230 comprises a firstporous wafer 240 serving as an anode and a secondporous wafer 250 serving as a cathode. The firstporous wafer 240 comprises a first plurality ofpores 242. The secondporous wafer 250 comprises a second plurality ofpores 252. Thehousing 220 is shown in transparent. Thehousing 220 comprises acavity 222. The single porous two-wafer battery 230 is disposed in thecavity 222 of thehousing 220. In examples of the present disclosure, the firstporous wafer 240 is of a circular wafer shape. The secondporous wafer 250 is of a circular wafer shape. Thehousing 220 is of a cylinder shape. The firstporous wafer 240, the secondporous wafer 250, and thehousing 220 share asame centerline 251. - In examples of the present disclosure, the single porous two-
wafer battery 230 does not contain another porous wafer battery. - In examples of the present disclosure, the
cavity 222 of thehousing 220 is filled with liquid or air so as to increase damping and to reduce damage when thebattery package 200 is under shock or vibration. In one example, thecavity 222 of thehousing 220 is filled with water. In another example, thecavity 222 of thehousing 220 is filled with water containing coolant. - When the
cavity 222 of thehousing 220 is in a positive pressure environment, it may reduce leaching of exterior ambient substance into thebattery package 200. When thecavity 222 of thehousing 220 is in a vacuum state (in one example, less than one torr), it may reduce leaching of substance of thebattery package 200 into environment. - In examples of the present disclosure, a plurality of inner surfaces of the
housing 220 is coated with a layer 271 (shown in dashed line because of being optional) of fire retardant material. A plurality of outer surfaces of thehousing 220 is coated with a layer 273 (shown in dashed line because of being optional) of fire retardant material. The fire retardant material may be made of Parylene-F. -
FIG. 3 shows a side view of abattery package 300 in examples of the present disclosure. Thebattery package 300 comprises aporous wafer battery 310, a porous two-wafer battery 330, afirst slot 371, asecond slot 373, athird slot 375, and ahousing 320. Theporous wafer battery 310 comprises a plurality of pores 312 (shown in dashed lines in a side view plot). Each of the plurality ofpores 312 comprises a respective anode and a respective cathode. The porous two-wafer battery 330 comprises a firstporous wafer 340 serving as an anode and a secondporous wafer 350 serving as a cathode. The firstporous wafer 340 comprises a first plurality ofpores 342. The secondporous wafer 350 comprises a second plurality ofpores 352. Thehousing 320 is shown in transparent. Thehousing 320 comprises acavity 322. Theporous wafer battery 310 and the porous two-wafer battery 330 are disposed in thecavity 322 of thehousing 320. In examples of the present disclosure, theporous wafer battery 310 is of a circular wafer shape. The firstporous wafer 340 is of a circular wafer shape. The secondporous wafer 350 is of a circular wafer shape. Thehousing 320 is of a cylinder shape. Each of thefirst slot 371, thesecond slot 373, and thethird slot 375 is of a circular ring shape or of arc sections of a ring shape. - The
porous wafer battery 310 is inserted in thefirst slot 371. The firstporous wafer 340 is inserted in thesecond slot 373. The secondporous wafer 350 is inserted in thethird slot 375. Ashortest distance 381 between theporous wafer battery 310 and the porous two-wafer battery 330 is larger than adistance 383 between the firstporous wafer 340 and the secondporous wafer 350. -
FIG. 4 shows a side view of abattery package 400 in examples of the present disclosure. Thebattery package 400 comprises a plurality ofporous wafer batteries 410, a plurality ofslots 470, aheating wafer 451, a coolingwafer 461, and ahousing 420. Thehousing 420 is shown in transparent. The plurality ofporous wafer batteries 410, theheating wafer 451, and thecooling wafer 461 are inserted into the plurality ofslots 470 respectively. Theheating wafer 451 comprises aheating element 453. Theheating element 453 may include resistors, a heater or a heat exchanger. The coolingwafer 461 comprising acooling element 463. Thecooling element 463 may include a radiator, a compressor, or a heat sink. - The
housing 420 comprises acavity 422. Thecavity 422 of thehousing 420 is filled with liquid or air so as to increase damping and to reduce damage when thebattery package 400 is under shock or vibration. In one example, thecavity 422 of thehousing 420 is filled with water. In another example, thecavity 422 of thehousing 420 is filled with water containing coolant. The plurality ofporous wafer batteries 410 are sealed. The sealing process may use one or more caps similar to those of U.S. Pat. No. 6,969,639 to Cho, et al. except that no dicing process is needed. The plurality ofporous wafer batteries 410 are submerged in the liquid. - In examples of the present disclosure, the
battery package 400 further comprises a plurality of spacers 490 (shown in dashed lines because of being optional). Each of the plurality ofspacers 490 is between a respective pair of the plurality ofslots 470. Each of the plurality ofspacers 490 is of a circular ring shape or of arc sections of a ring shape. -
FIG. 5 shows a side view of abattery package 500 in examples of the present disclosure. Thebattery package 500 comprises a plurality ofporous wafer batteries 510, a plurality ofslots 570, a temperature-adjustingwafer 551, and ahousing 520. Thehousing 520 is shown in transparent. The plurality ofporous wafer batteries 510 and the temperature-adjustingwafer 551 are inserted into the plurality ofslots 570 respectively. The temperature-adjustingwafer 551 comprises aheating element 553 and acooling element 563. Theheating element 553 may include resistors, a heater or a heat exchanger. Thecooling element 563 may include a radiator, a compressor, or a heat sink. - In examples of the present disclosure, the
housing 520 further comprises ananode tab 527 and acathode tab 529. Theanode tab 527 and thecathode tab 529 are on a same end of thehousing 520. Thebattery package 500 further comprises a first plurality ofconductive members 591 and a second plurality of conductive members 593 (shown in dashed lines because of being an example). The first plurality ofconductive members 591 connect a respective anode of each of the plurality ofporous wafer batteries 510 to theanode tab 527 of thehousing 520. A second plurality ofconductive members 593 connect a respective cathode of each of the plurality ofporous wafer batteries 510 to thecathode tab 529 of thehousing 520. The first plurality ofconductive members 591 and the second plurality ofconductive members 593 may be conductive traces, connectors, or wires. - In examples of the present disclosure, the plurality of
porous wafer batteries 510 are configured in parallel in the circuit including the first plurality ofconductive members 591 and the second plurality ofconductive members 593. Therefore, even the porous wafer battery corresponding to theslot 579 is removed, thebattery package 500 is still functioning. -
FIG. 6 shows a side view of abattery package 600 in examples of the present disclosure. Thebattery package 600 comprises a plurality ofporous wafer batteries 610, a plurality ofslots 670, a coolingwafer 661, and ahousing 620. Thehousing 620 is shown in transparent. Thehousing 420 comprises acavity 422. The plurality ofslots 670 are attached to an inner surface of thehousing 620. The plurality ofporous wafer batteries 610 are inserted into the plurality ofslots 670 respectively. The coolingwafer 661 comprises acooling element 663. Thecooling element 663 may include a radiator, a compressor, or a heat sink. A majority portion, more than 50%, of the coolingwafer 661 is disposed external to thehousing 620. A minority portion, less than 50%, of the cooling wafer is disposed in thecavity 622 of thehousing 620. An entirely of thecooling element 663 is disposed external to thehousing 620. -
FIG. 7 shows a side view of abattery package 700 in examples of the present disclosure. Thebattery package 700 comprises a plurality ofporous wafer batteries 710, a plurality ofslot 770, a plurality of coolingwafers 750, and ahousing 720. Thehousing 720 is shown in transparent. Thehousing 720 comprises acavity 722. The plurality ofporous wafer batteries 710 and the plurality of coolingwafers 750 are inserted into the plurality ofslot 770 respectively. The plurality of coolingwafers 750 comprises afirst cooling wafer 751 and asecond cooling wafer 757. Thefirst cooling wafer 751 comprises afirst cooling element 753. Thesecond cooling wafer 757 comprises asecond cooling element 759. Thefirst cooling element 753 and thesecond cooling element 759 may include a radiator, a compressor, or a heat sink. - In examples of the present disclosure, the
housing 720 further comprises ananode tab 727 and acathode tab 729. Theanode tab 727 and thecathode tab 729 are on opposite ends of thehousing 720 respectively. Thebattery package 700 further comprises a first plurality ofconductive members 791 and a second plurality of conductive members 793 (shown in dashed lines because of being an example). The first plurality ofconductive members 791 connect a respective anode of each of the plurality ofporous wafer batteries 710 to theanode tab 727 of thehousing 720. A second plurality ofconductive members 793 connect a respective cathode of each of the plurality ofporous wafer batteries 710 to thecathode tab 729 of thehousing 720. The first plurality ofconductive members 791 and the second plurality ofconductive members 793 may be conductive traces, connectors, or wires. -
FIG. 8 shows a top view of aporous wafer 810 and aslot 870 in examples of the present disclosure. Theporous wafer 810 comprises a plurality ofpores 820 and acontact region 811. The plurality ofpores 820 are symmetric with respect to acenter 831 of theporous wafer 810. The plurality ofpores 820 are symmetric with X-axis. The plurality ofpores 820 are symmetric with X-axis. In one example, the plurality ofpores 820 are of rectangular shapes. In one example, the plurality ofpores 820 are of circular shapes. Theslot 870 comprises acontact region 871 and agroove 872. In examples of the present disclosure, thecontact region 871 of theslot 870 directly contacts thecontact region 811 of theporous wafer 810. In one example, a radius of thegroove 872 is 1% to 3% smaller than a radius of theporous wafer 810 so that theporous wafer 810 is pressed fitted into theslot 870. - Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the plurality of pores may vary. A number of wafers in a battery package may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.
Claims (15)
1. A battery package comprising
one or more porous wafer batteries; and
a housing enclosing the one or more porous wafer batteries.
2. The battery package of claim 1 , wherein the battery package excludes a respective wafer-level sub-housing enclosing each of the one or more porous wafer batteries.
3. The battery package of claim 1 , wherein the one or more porous wafer batteries comprises
a single porous wafer battery comprising
a plurality of pores;
wherein the battery package excludes an additional porous wafer battery; and
wherein each of the plurality of pores comprises
a respective anode; and
a respective cathode.
4. The battery package of claim 1 , wherein the one or more porous wafer batteries comprises
a single porous two-wafer battery comprising
a first porous wafer serving as an anode, the first porous wafer comprising
a first plurality of pores; and
a second porous wafer serving as a cathode, the second porous wafer comprising
a second plurality of pores.
5. The battery package of claim 1 , wherein a plurality of inner surfaces of the housing is coated with a layer of fire retardant material.
6. The battery package of claim 1 further comprising
a heating wafer enclosed by the housing, the heating wafer comprising
a heating element.
7. The battery package of claim 1 , further comprising
a cooling wafer enclosed by the housing, the cooling wafer comprising
a cooling element.
8. The battery package of claim 1 , further comprising
a cooling wafer comprising
a cooling element;
wherein a majority portion of the cooling wafer is disposed external to the housing; and
wherein a minority portion of the cooling wafer is disposed in the housing.
9. The battery package of claim 1 , further comprising
a temperature-adjusting wafer enclosed by the housing, the temperature-adjusting wafer comprising
a heating wafer enclosed by the housing, the heating wafer comprising
a heating element; and
a cooling wafer enclosed by the housing, the cooling wafer comprising
a cooling element.
10. The battery package of claim 1 , wherein an internal volume of the housing is filled with a liquid; and
wherein the one or more porous wafer batteries are sealed; and
wherein the one or more porous wafer batteries are submerged in the liquid.
11. The battery package of claim 1 , wherein the housing comprises one or more slots; and
wherein each porous wafer of the one or more porous wafers is inserted into a respective slot of the one or more slots.
12. The battery package of claim 11 , wherein each slot of the one or more slots comprises a groove; and wherein a contact region of each porous wafer of the one or more porous wafers is inserted into the groove of the respective slot of the one or more slots.
13. The battery package of claim 12 , wherein a spacer is between a selected slot of the one and more slots and an adjacent slot of the one and more slots.
14. The battery package of claim 12 , wherein the housing further comprises
an anode tab; and
a cathode tab; and
wherein the battery package further comprises
a first plurality of conductive members connecting a respective anode of each of the one or more wafer batteries to the anode tab of the housing; and
a second plurality of conductive members connecting a respective cathode of each of the one or more wafer batteries to the cathode tab of the housing.
15. The battery package of claim 1 , wherein the one or more porous wafer batteries comprises
a porous one-wafer battery comprising
a plurality of pores; and
a porous two-wafer battery comprising
a first porous wafer serving as an anode; and
a second porous wafer serving as a cathode;
wherein each of the plurality of pores of the porous one-wafer battery comprises
a respective anode; and
a respective cathode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/087,604 US20210135311A1 (en) | 2019-11-04 | 2020-11-02 | Battery package containing porous wafer battery |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962930019P | 2019-11-04 | 2019-11-04 | |
US201962930021P | 2019-11-04 | 2019-11-04 | |
US201962930018P | 2019-11-04 | 2019-11-04 | |
US201962930016P | 2019-11-04 | 2019-11-04 | |
US201962930020P | 2019-11-04 | 2019-11-04 | |
US17/087,604 US20210135311A1 (en) | 2019-11-04 | 2020-11-02 | Battery package containing porous wafer battery |
Publications (1)
Publication Number | Publication Date |
---|---|
US20210135311A1 true US20210135311A1 (en) | 2021-05-06 |
Family
ID=75686355
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/087,607 Active 2041-02-04 US11342625B2 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating and method of using porous wafer battery |
US17/087,575 Abandoned US20210135231A1 (en) | 2019-11-04 | 2020-11-02 | Porous two-wafer battery |
US17/087,617 Abandoned US20210135271A1 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating porous wafer battery |
US17/087,604 Abandoned US20210135311A1 (en) | 2019-11-04 | 2020-11-02 | Battery package containing porous wafer battery |
US17/087,600 Pending US20210135003A1 (en) | 2019-11-04 | 2020-11-02 | Single-chip containing porous-wafer battery and device and method of making the same |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/087,607 Active 2041-02-04 US11342625B2 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating and method of using porous wafer battery |
US17/087,575 Abandoned US20210135231A1 (en) | 2019-11-04 | 2020-11-02 | Porous two-wafer battery |
US17/087,617 Abandoned US20210135271A1 (en) | 2019-11-04 | 2020-11-02 | Method of fabricating porous wafer battery |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/087,600 Pending US20210135003A1 (en) | 2019-11-04 | 2020-11-02 | Single-chip containing porous-wafer battery and device and method of making the same |
Country Status (1)
Country | Link |
---|---|
US (5) | US11342625B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11342625B2 (en) * | 2019-11-04 | 2022-05-24 | Xnrgi, Inc. | Method of fabricating and method of using porous wafer battery |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090155678A1 (en) * | 2007-08-21 | 2009-06-18 | Less Gregory B | Separator for electrochemical cell and method for its manufacture |
US20100291431A1 (en) * | 2009-05-13 | 2010-11-18 | Front Edge Technology, Inc. | Thin film battery with protective packaging |
US20130244066A1 (en) * | 2010-12-28 | 2013-09-19 | Lg Chem, Ltd. | Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same |
US20140308576A1 (en) * | 2011-11-02 | 2014-10-16 | I-Ten | Method for manufacturing all-solid-state thin-film batteries |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1210872B (en) * | 1982-04-08 | 1989-09-29 | Ates Componenti Elettron | PROCESS FOR THE MANUFACTURE OF COMPLEMENTARY MOS TRANSISTORS IN HIGH DENSITY INTEGRATED CIRCUITS FOR HIGH VOLTAGES. |
US6197450B1 (en) * | 1998-10-22 | 2001-03-06 | Ramot University Authority For Applied Research & Industrial Development Ltd. | Micro electrochemical energy storage cells |
US6432577B1 (en) * | 2000-06-29 | 2002-08-13 | Sandia Corporation | Apparatus and method for fabricating a microbattery |
US20030042587A1 (en) | 2001-08-31 | 2003-03-06 | Tsung-Jen Lee | IC packaging and manufacturing methods |
WO2004036668A2 (en) * | 2002-10-17 | 2004-04-29 | Tel-Aviv University Future Technology Development L.P. | Thin-film cathode for 3-dimensional microbattery and method for preparing such cathode |
CA2432397A1 (en) * | 2003-06-25 | 2004-12-25 | Hydro-Quebec | Procedure for preparing an electrode from porous silicon, the electrode so obtained, and an electrochemical system containing at least one such electrode |
US7295029B2 (en) * | 2005-03-24 | 2007-11-13 | Memsic, Inc. | Chip-scale package for integrated circuits |
US7776679B2 (en) * | 2007-07-20 | 2010-08-17 | Stmicroelectronics Crolles 2 Sas | Method for forming silicon wells of different crystallographic orientations |
CN102203905A (en) | 2008-11-10 | 2011-09-28 | Kelk株式会社 | Apparatus and method for controlling temperature of semiconductor wafer |
US9368429B2 (en) * | 2011-10-25 | 2016-06-14 | Intel Corporation | Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips |
EP2913847B1 (en) * | 2014-02-28 | 2018-04-18 | LFoundry S.r.l. | Method of fabricating a semiconductor device and semiconductor product |
US9876200B2 (en) * | 2015-08-07 | 2018-01-23 | International Business Machines Corporation | All-silicon hermetic package and processing for narrow, low-profile microbatteries |
US10079375B2 (en) * | 2015-12-30 | 2018-09-18 | International Business Machines Corporation | Dual seal microbattery and method of making |
WO2018175423A1 (en) * | 2017-03-20 | 2018-09-27 | Millibatt, Inc. | Battery system and production method |
US10505160B2 (en) * | 2017-06-26 | 2019-12-10 | International Business Machines Corporation | Micro-battery using glass package |
US11233288B2 (en) * | 2018-07-11 | 2022-01-25 | International Business Machines Corporation | Silicon substrate containing integrated porous silicon electrodes for energy storage devices |
US10833301B2 (en) * | 2019-01-02 | 2020-11-10 | International Business Machines Corporation | Through silicon via energy storage devices |
US11342625B2 (en) * | 2019-11-04 | 2022-05-24 | Xnrgi, Inc. | Method of fabricating and method of using porous wafer battery |
-
2020
- 2020-11-02 US US17/087,607 patent/US11342625B2/en active Active
- 2020-11-02 US US17/087,575 patent/US20210135231A1/en not_active Abandoned
- 2020-11-02 US US17/087,617 patent/US20210135271A1/en not_active Abandoned
- 2020-11-02 US US17/087,604 patent/US20210135311A1/en not_active Abandoned
- 2020-11-02 US US17/087,600 patent/US20210135003A1/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090155678A1 (en) * | 2007-08-21 | 2009-06-18 | Less Gregory B | Separator for electrochemical cell and method for its manufacture |
US20100291431A1 (en) * | 2009-05-13 | 2010-11-18 | Front Edge Technology, Inc. | Thin film battery with protective packaging |
US20130244066A1 (en) * | 2010-12-28 | 2013-09-19 | Lg Chem, Ltd. | Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same |
US20140308576A1 (en) * | 2011-11-02 | 2014-10-16 | I-Ten | Method for manufacturing all-solid-state thin-film batteries |
Also Published As
Publication number | Publication date |
---|---|
US11342625B2 (en) | 2022-05-24 |
US20210135003A1 (en) | 2021-05-06 |
US20210135231A1 (en) | 2021-05-06 |
US20210134608A1 (en) | 2021-05-06 |
US20210135271A1 (en) | 2021-05-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20170237112A1 (en) | Porous spacers for electrochemical cells | |
US8795867B2 (en) | Wire mounted battery module on vertical support frame | |
KR100667943B1 (en) | Secondary battery module | |
US20110183176A1 (en) | Battery cell module | |
US20110189522A1 (en) | Battery pack | |
CN103904381B (en) | Internal temperature of battery measurement apparatus | |
JP6437546B2 (en) | Energy storage module comprising a plurality of energy storage assemblies | |
KR20170132514A (en) | Battery module, battery pack comprising the battery module and vehicle comprising the battery pack | |
US11196109B2 (en) | Battery module and battery module stack for a motor vehicle | |
US20210135311A1 (en) | Battery package containing porous wafer battery | |
JP2010212165A (en) | Cell module and manufacturing method therefor | |
KR20170019229A (en) | Battery module, battery pack comprising the battery module and vehicle comprising the battery pack | |
KR20210140775A (en) | Battery module including asymmetric cell electrical connections | |
JP2011150902A (en) | Lithium ion secondary battery | |
US10193196B1 (en) | Internal battery cell cooling with heat pipe | |
US11296385B2 (en) | Battery module and battery pack | |
CN110770965A (en) | Battery module with improved cooling structure | |
JP2013004468A (en) | Battery pack device | |
JP2023514326A (en) | Battery cases, batteries, battery packs, battery modules and vehicles | |
CN111226344B (en) | Battery module and battery pack including the same | |
KR20240023439A (en) | Batteries and Electrical Appliances | |
JP2010272319A (en) | Battery pack | |
CN211507807U (en) | Quick radiating lithium cell structure | |
KR20190074796A (en) | Battery module with improved cooling efficiency | |
CN113823865A (en) | Square battery shell, battery with same, battery pack and automobile |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: XNRGI, INC., WASHINGTON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:D'COUTO, GERARD CHRISTOPHER;REEL/FRAME:054248/0098 Effective date: 20201102 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |