US20210135311A1 - Battery package containing porous wafer battery - Google Patents

Battery package containing porous wafer battery Download PDF

Info

Publication number
US20210135311A1
US20210135311A1 US17/087,604 US202017087604A US2021135311A1 US 20210135311 A1 US20210135311 A1 US 20210135311A1 US 202017087604 A US202017087604 A US 202017087604A US 2021135311 A1 US2021135311 A1 US 2021135311A1
Authority
US
United States
Prior art keywords
wafer
porous
battery
housing
battery package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US17/087,604
Inventor
Gerard Christopher D'Couto
Slobodan Petrovic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XNRGI Inc
Original Assignee
XNRGI Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XNRGI Inc filed Critical XNRGI Inc
Priority to US17/087,604 priority Critical patent/US20210135311A1/en
Assigned to XNRGI, INC. reassignment XNRGI, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: D'COUTO, GERARD CHRISTOPHER
Publication of US20210135311A1 publication Critical patent/US20210135311A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M50/00Constructional details or processes of manufacture of the non-active parts of electrochemical cells other than fuel cells, e.g. hybrid cells
    • H01M50/20Mountings; Secondary casings or frames; Racks, modules or packs; Suspension devices; Shock absorbers; Transport or carrying devices; Holders
    • H01M50/204Racks, modules or packs for multiple batteries or multiple cells
    • H01M50/207Racks, modules or packs for multiple batteries or multiple cells characterised by their shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/42Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M10/4257Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/04Construction or manufacture in general
    • H01M10/0436Small-sized flat cells or batteries for portable equipment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/04Construction or manufacture in general
    • H01M10/0477Construction or manufacture in general with circular plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/05Accumulators with non-aqueous electrolyte
    • H01M10/052Li-accumulators
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/05Accumulators with non-aqueous electrolyte
    • H01M10/058Construction or manufacture
    • H01M10/0585Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/42Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/60Heating or cooling; Temperature control
    • H01M10/61Types of temperature control
    • H01M10/613Cooling or keeping cold
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/60Heating or cooling; Temperature control
    • H01M10/61Types of temperature control
    • H01M10/615Heating or keeping warm
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00Electrodes
    • H01M4/02Electrodes composed of, or comprising, active material
    • H01M4/13Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00Electrodes
    • H01M4/02Electrodes composed of, or comprising, active material
    • H01M4/62Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
    • H01M4/624Electric conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00Electrodes
    • H01M4/02Electrodes composed of, or comprising, active material
    • H01M4/62Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
    • H01M4/628Inhibitors, e.g. gassing inhibitors, corrosion inhibitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60097Applying energy, e.g. for the soldering or alloying process
    • H01L2021/60135Applying energy, e.g. for the soldering or alloying process using convection, e.g. reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00Electrodes
    • H01M4/02Electrodes composed of, or comprising, active material
    • H01M2004/021Physical characteristics, e.g. porosity, surface area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/04Construction or manufacture in general
    • H01M2010/0495Nanobatteries
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01MPROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00Secondary cells; Manufacture thereof
    • H01M10/42Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M2010/4271Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10Energy storage using batteries
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates generally to a battery package. More particularly, the present invention relates to a battery package containing one or more porous wafer batteries.
  • a battery stack contains a plurality of single cell batteries is formed.
  • a battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
  • each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
  • a plurality of wafers may be stacked in a housing.
  • the housing can be a solid housing.
  • the housing may include tabs, slots or grooves for holding the wafers in place.
  • the housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
  • Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
  • a battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries.
  • Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery.
  • Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode.
  • a first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode.
  • the battery package further comprises a plurality of heating wafers and a plurality of cooling wafers.
  • a cavity of the housing may be filled with a liquid.
  • FIG. 1 shows a side view of a battery package comprising a single porous wafer battery in examples of the present disclosure.
  • FIG. 2 shows a side view of a battery package comprising a single porous two-wafer battery in examples of the present disclosure.
  • FIG. 3 shows a side view of a battery package comprising a porous wafer battery and a porous two-wafer battery in examples of the present disclosure.
  • FIG. 4 shows a side view of a battery package comprising a plurality of slots and a plurality of spacers in examples of the present disclosure.
  • FIG. 5 shows a side view of a battery package comprising a plurality of slots in examples of the present disclosure.
  • FIG. 6 shows a side view of a battery package comprising a cooling wafer in examples of the present disclosure.
  • FIG. 7 shows a side view of a battery package comprising an anode tab and a cathode tab in examples of the present disclosure.
  • FIG. 8 shows a top view of a porous wafer and a slot in examples of the present disclosure.
  • FIG. 1 shows a side view of a battery package 100 in examples of the present disclosure.
  • the battery package 100 comprises a single porous wafer battery 140 and a housing 120 enclosing the single porous wafer battery 140 .
  • the housing 120 is shown in transparent.
  • the housing 120 comprises a cavity 122 .
  • the single porous wafer battery 140 is disposed in the cavity 122 of the housing 120 .
  • the single porous wafer battery 140 is of a circular wafer shape.
  • the housing 120 is of a cylinder shape.
  • the single porous wafer battery 140 and the housing 120 share a same centerline 150 .
  • a diameter of the single porous wafer battery 140 is 4 inches. In another example, a diameter of the single porous wafer battery 140 is 6 inches. In still another example, a diameter of the single porous wafer battery 140 is 8 inches. In yet another example, a diameter of the single porous wafer battery 140 is 12 inches. In yet still another example, a diameter of the single porous wafer battery 140 is 18 inches.
  • the single porous wafer battery 140 comprises a plurality of pores 142 (shown in dashed lines in a side view plot).
  • the battery package 100 does not contain another porous wafer battery.
  • Each of the plurality of pores 142 comprises a respective anode 143 and a respective cathode 145 .
  • Each of the plurality of pores 142 is parallel to one another.
  • a depth of each of the plurality of pores 142 is larger than a half of a thickness of the single porous wafer battery 140 .
  • the battery package 100 is communicated with an optional external system 192 (shown in dashed lines because it is optional) by a wired or wireless connection 191 .
  • the optional external system 192 may be a mobile device or a power grid in a house.
  • the battery package 100 is connected to an optional heating device 194 (shown in dashed lines because it is optional) through a pipe 193 to heat up the battery package 100 in an initial ramping up state to increase efficiency.
  • the optional heating device 194 may be a heater or a heat exchanger.
  • the battery package 100 is connected to an optional conditional device 196 (shown in dashed lines because it is optional) through a pipe 195 to reduce the temperature of the battery package 100 during operation.
  • the optional conditional device 196 may be a radiator, a compressor, or a heat sink.
  • the battery package 100 excludes a wafer-level sub-housing 121 (shown in dotted lines because of being excluded) enclosing the single porous wafer battery 140 .
  • FIG. 2 shows a side view of a battery package 200 in examples of the present disclosure.
  • the battery package 200 comprises a single porous two-wafer battery 230 and a housing 220 .
  • the single porous two-wafer battery 230 comprises a first porous wafer 240 serving as an anode and a second porous wafer 250 serving as a cathode.
  • the first porous wafer 240 comprises a first plurality of pores 242 .
  • the second porous wafer 250 comprises a second plurality of pores 252 .
  • the housing 220 is shown in transparent.
  • the housing 220 comprises a cavity 222 .
  • the single porous two-wafer battery 230 is disposed in the cavity 222 of the housing 220 .
  • the first porous wafer 240 is of a circular wafer shape.
  • the second porous wafer 250 is of a circular wafer shape.
  • the housing 220 is of a cylinder shape. The first porous wafer 240 , the second porous wafer 250 , and the housing 220 share a same centerline 251 .
  • the single porous two-wafer battery 230 does not contain another porous wafer battery.
  • the cavity 222 of the housing 220 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 200 is under shock or vibration.
  • the cavity 222 of the housing 220 is filled with water.
  • the cavity 222 of the housing 220 is filled with water containing coolant.
  • the cavity 222 of the housing 220 When the cavity 222 of the housing 220 is in a positive pressure environment, it may reduce leaching of exterior ambient substance into the battery package 200 . When the cavity 222 of the housing 220 is in a vacuum state (in one example, less than one torr), it may reduce leaching of substance of the battery package 200 into environment.
  • a plurality of inner surfaces of the housing 220 is coated with a layer 271 (shown in dashed line because of being optional) of fire retardant material.
  • a plurality of outer surfaces of the housing 220 is coated with a layer 273 (shown in dashed line because of being optional) of fire retardant material.
  • the fire retardant material may be made of Parylene-F.
  • FIG. 3 shows a side view of a battery package 300 in examples of the present disclosure.
  • the battery package 300 comprises a porous wafer battery 310 , a porous two-wafer battery 330 , a first slot 371 , a second slot 373 , a third slot 375 , and a housing 320 .
  • the porous wafer battery 310 comprises a plurality of pores 312 (shown in dashed lines in a side view plot). Each of the plurality of pores 312 comprises a respective anode and a respective cathode.
  • the porous two-wafer battery 330 comprises a first porous wafer 340 serving as an anode and a second porous wafer 350 serving as a cathode.
  • the first porous wafer 340 comprises a first plurality of pores 342 .
  • the second porous wafer 350 comprises a second plurality of pores 352 .
  • the housing 320 is shown in transparent.
  • the housing 320 comprises a cavity 322 .
  • the porous wafer battery 310 and the porous two-wafer battery 330 are disposed in the cavity 322 of the housing 320 .
  • the porous wafer battery 310 is of a circular wafer shape.
  • the first porous wafer 340 is of a circular wafer shape.
  • the second porous wafer 350 is of a circular wafer shape.
  • the housing 320 is of a cylinder shape.
  • Each of the first slot 371 , the second slot 373 , and the third slot 375 is of a circular ring shape or of arc sections of a ring shape.
  • the porous wafer battery 310 is inserted in the first slot 371 .
  • the first porous wafer 340 is inserted in the second slot 373 .
  • the second porous wafer 350 is inserted in the third slot 375 .
  • a shortest distance 381 between the porous wafer battery 310 and the porous two-wafer battery 330 is larger than a distance 383 between the first porous wafer 340 and the second porous wafer 350 .
  • FIG. 4 shows a side view of a battery package 400 in examples of the present disclosure.
  • the battery package 400 comprises a plurality of porous wafer batteries 410 , a plurality of slots 470 , a heating wafer 451 , a cooling wafer 461 , and a housing 420 .
  • the housing 420 is shown in transparent.
  • the plurality of porous wafer batteries 410 , the heating wafer 451 , and the cooling wafer 461 are inserted into the plurality of slots 470 respectively.
  • the heating wafer 451 comprises a heating element 453 .
  • the heating element 453 may include resistors, a heater or a heat exchanger.
  • the cooling wafer 461 comprising a cooling element 463 .
  • the cooling element 463 may include a radiator, a compressor, or a heat sink.
  • the housing 420 comprises a cavity 422 .
  • the cavity 422 of the housing 420 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 400 is under shock or vibration.
  • the cavity 422 of the housing 420 is filled with water.
  • the cavity 422 of the housing 420 is filled with water containing coolant.
  • the plurality of porous wafer batteries 410 are sealed. The sealing process may use one or more caps similar to those of U.S. Pat. No. 6,969,639 to Cho, et al. except that no dicing process is needed.
  • the plurality of porous wafer batteries 410 are submerged in the liquid.
  • the battery package 400 further comprises a plurality of spacers 490 (shown in dashed lines because of being optional). Each of the plurality of spacers 490 is between a respective pair of the plurality of slots 470 . Each of the plurality of spacers 490 is of a circular ring shape or of arc sections of a ring shape.
  • FIG. 5 shows a side view of a battery package 500 in examples of the present disclosure.
  • the battery package 500 comprises a plurality of porous wafer batteries 510 , a plurality of slots 570 , a temperature-adjusting wafer 551 , and a housing 520 .
  • the housing 520 is shown in transparent.
  • the plurality of porous wafer batteries 510 and the temperature-adjusting wafer 551 are inserted into the plurality of slots 570 respectively.
  • the temperature-adjusting wafer 551 comprises a heating element 553 and a cooling element 563 .
  • the heating element 553 may include resistors, a heater or a heat exchanger.
  • the cooling element 563 may include a radiator, a compressor, or a heat sink.
  • the housing 520 further comprises an anode tab 527 and a cathode tab 529 .
  • the anode tab 527 and the cathode tab 529 are on a same end of the housing 520 .
  • the battery package 500 further comprises a first plurality of conductive members 591 and a second plurality of conductive members 593 (shown in dashed lines because of being an example).
  • the first plurality of conductive members 591 connect a respective anode of each of the plurality of porous wafer batteries 510 to the anode tab 527 of the housing 520 .
  • a second plurality of conductive members 593 connect a respective cathode of each of the plurality of porous wafer batteries 510 to the cathode tab 529 of the housing 520 .
  • the first plurality of conductive members 591 and the second plurality of conductive members 593 may be conductive traces, connectors, or wires.
  • the plurality of porous wafer batteries 510 are configured in parallel in the circuit including the first plurality of conductive members 591 and the second plurality of conductive members 593 . Therefore, even the porous wafer battery corresponding to the slot 579 is removed, the battery package 500 is still functioning.
  • FIG. 6 shows a side view of a battery package 600 in examples of the present disclosure.
  • the battery package 600 comprises a plurality of porous wafer batteries 610 , a plurality of slots 670 , a cooling wafer 661 , and a housing 620 .
  • the housing 620 is shown in transparent.
  • the housing 420 comprises a cavity 422 .
  • the plurality of slots 670 are attached to an inner surface of the housing 620 .
  • the plurality of porous wafer batteries 610 are inserted into the plurality of slots 670 respectively.
  • the cooling wafer 661 comprises a cooling element 663 .
  • the cooling element 663 may include a radiator, a compressor, or a heat sink.
  • a majority portion, more than 50%, of the cooling wafer 661 is disposed external to the housing 620 .
  • a minority portion, less than 50%, of the cooling wafer is disposed in the cavity 622 of the housing 620 .
  • An entirely of the cooling element 663 is disposed external to the housing 620 .
  • FIG. 7 shows a side view of a battery package 700 in examples of the present disclosure.
  • the battery package 700 comprises a plurality of porous wafer batteries 710 , a plurality of slot 770 , a plurality of cooling wafers 750 , and a housing 720 .
  • the housing 720 is shown in transparent.
  • the housing 720 comprises a cavity 722 .
  • the plurality of porous wafer batteries 710 and the plurality of cooling wafers 750 are inserted into the plurality of slot 770 respectively.
  • the plurality of cooling wafers 750 comprises a first cooling wafer 751 and a second cooling wafer 757 .
  • the first cooling wafer 751 comprises a first cooling element 753 .
  • the second cooling wafer 757 comprises a second cooling element 759 .
  • the first cooling element 753 and the second cooling element 759 may include a radiator, a compressor, or a heat sink.
  • the housing 720 further comprises an anode tab 727 and a cathode tab 729 .
  • the anode tab 727 and the cathode tab 729 are on opposite ends of the housing 720 respectively.
  • the battery package 700 further comprises a first plurality of conductive members 791 and a second plurality of conductive members 793 (shown in dashed lines because of being an example).
  • the first plurality of conductive members 791 connect a respective anode of each of the plurality of porous wafer batteries 710 to the anode tab 727 of the housing 720 .
  • a second plurality of conductive members 793 connect a respective cathode of each of the plurality of porous wafer batteries 710 to the cathode tab 729 of the housing 720 .
  • the first plurality of conductive members 791 and the second plurality of conductive members 793 may be conductive traces, connectors, or wires.
  • FIG. 8 shows a top view of a porous wafer 810 and a slot 870 in examples of the present disclosure.
  • the porous wafer 810 comprises a plurality of pores 820 and a contact region 811 .
  • the plurality of pores 820 are symmetric with respect to a center 831 of the porous wafer 810 .
  • the plurality of pores 820 are symmetric with X-axis.
  • the plurality of pores 820 are symmetric with X-axis.
  • the plurality of pores 820 are of rectangular shapes.
  • the plurality of pores 820 are of circular shapes.
  • the slot 870 comprises a contact region 871 and a groove 872 .
  • the contact region 871 of the slot 870 directly contacts the contact region 811 of the porous wafer 810 .
  • a radius of the groove 872 is 1% to 3% smaller than a radius of the porous wafer 810 so that the porous wafer 810 is pressed fitted into the slot 870 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Weting (AREA)
  • Secondary Cells (AREA)
  • Battery Mounting, Suspending (AREA)
  • Battery Electrode And Active Subsutance (AREA)

Abstract

A battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries. Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery. Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode. A first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode. The battery package further comprises a plurality of heating wafers and a plurality of cooling wafers. A cavity of the housing may be filled with a liquid.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This patent application claims benefit of provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 because of a common inventor, Slobodan Petrovic. The disclosures made in the provisional patent applications 62/930,016, 62/930,018, 62/930,019, 62/930,020, and 62/930,021 are hereby incorporated by reference. The disclosure made in U.S. Pat. No. 6,969,639 to Cho, et al. is also hereby incorporated by reference.
  • FIELD OF THE INVENTION
  • This invention relates generally to a battery package. More particularly, the present invention relates to a battery package containing one or more porous wafer batteries.
  • BACKGROUND OF THE INVENTION
  • Applications for vehicles or stationary apparatus require large size batteries. Currently, the industry standard for large size battery is to take standardized or proprietary small scale batteries and package them together to form a large size battery. For example, hundreds or thousands of 18650-type batteries are packaged together to form a large size battery. It is inefficient because each cell requires casing, packaging or housing. Thus, it lowers the energy density of the stack. It also induces problems for cooling, longevity and maintenance, and replacement. Some current players in the industry, Panasonic and Tesla, tried to introduce the 2170-type cell. 2170-type is larger than 18650-type. The large number of individually packaging cells requires packaging with complex heat distribution capability and interconnections between the cells. Other manufacturers also introduced larger cells including cells as large as 20 Ah, in a pouch cell package. It results in packing a large number of pouch cells stacked next to one another or in strings on top of one another. It is still inefficient and faces many challenges due to non-uniform current distribution, sensitivity of welded contact tabs and excessive heat generation issue. Those batteries are also expensive because each 20 Ah cell has a pouch package. In large scale manufacturing, it still does not realize a true cost effective package and application.
  • Therefore, there is a need for a high-power density, high current and low cost battery stack facilitating efficiently scaling the size of the battery.
  • SUMMARY OF THE INVENTION
  • The present disclosure does not require special packing used in current large-size battery industry. A battery stack contains a plurality of single cell batteries is formed.
  • A battery may be made by one or more wafers. Each wafer has one or more pores. Each pore may include an anode and cathode and form a single battery. Then, the single batteries are stacked. Each wafer may include many cells or batteries.
  • In one example, each wafer does not need an individual package. Wafers can be stacked together to form a larger battery. It facilitates efficiency in production, space reduction, and cost reduction.
  • A plurality of wafers may be stacked in a housing. The housing can be a solid housing. The housing may include tabs, slots or grooves for holding the wafers in place. The housing may also include electrical connectors to transmit current to and from the wafers to an external device or destinations.
  • Liquid or gas may be within the housing. Liquid or heat facilitates heat dissipation so as to reduce the temperature of the wafers. Other wafers including cooling or heating elements may be included in the housing.
  • SUMMARY OF THE INVENTION
  • A battery package comprises a plurality of porous wafer batteries and a housing enclosing the plurality of porous wafer batteries. Each of the plurality of porous wafer batteries may be a one-wafer battery or a two-wafer battery. Each pore of a plurality of pores of the one-wafer battery comprises a respective anode and a respective cathode. A first wafer of the two-wafer battery is an anode and a second wafer of the two-wafer battery is a cathode.
  • The battery package further comprises a plurality of heating wafers and a plurality of cooling wafers. A cavity of the housing may be filled with a liquid.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a side view of a battery package comprising a single porous wafer battery in examples of the present disclosure.
  • FIG. 2 shows a side view of a battery package comprising a single porous two-wafer battery in examples of the present disclosure.
  • FIG. 3 shows a side view of a battery package comprising a porous wafer battery and a porous two-wafer battery in examples of the present disclosure.
  • FIG. 4 shows a side view of a battery package comprising a plurality of slots and a plurality of spacers in examples of the present disclosure.
  • FIG. 5 shows a side view of a battery package comprising a plurality of slots in examples of the present disclosure.
  • FIG. 6 shows a side view of a battery package comprising a cooling wafer in examples of the present disclosure.
  • FIG. 7 shows a side view of a battery package comprising an anode tab and a cathode tab in examples of the present disclosure.
  • FIG. 8 shows a top view of a porous wafer and a slot in examples of the present disclosure.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 shows a side view of a battery package 100 in examples of the present disclosure. The battery package 100 comprises a single porous wafer battery 140 and a housing 120 enclosing the single porous wafer battery 140. The housing 120 is shown in transparent. The housing 120 comprises a cavity 122. The single porous wafer battery 140 is disposed in the cavity 122 of the housing 120. In examples of the present disclosure, the single porous wafer battery 140 is of a circular wafer shape. The housing 120 is of a cylinder shape. The single porous wafer battery 140 and the housing 120 share a same centerline 150.
  • In one example, a diameter of the single porous wafer battery 140 is 4 inches. In another example, a diameter of the single porous wafer battery 140 is 6 inches. In still another example, a diameter of the single porous wafer battery 140 is 8 inches. In yet another example, a diameter of the single porous wafer battery 140 is 12 inches. In yet still another example, a diameter of the single porous wafer battery 140 is 18 inches.
  • In examples of the present disclosure, the single porous wafer battery 140 comprises a plurality of pores 142 (shown in dashed lines in a side view plot). The battery package 100 does not contain another porous wafer battery. Each of the plurality of pores 142 comprises a respective anode 143 and a respective cathode 145. Each of the plurality of pores 142 is parallel to one another. A depth of each of the plurality of pores 142 is larger than a half of a thickness of the single porous wafer battery 140.
  • In examples of the present disclosure, the battery package 100 is communicated with an optional external system 192 (shown in dashed lines because it is optional) by a wired or wireless connection 191. The optional external system 192 may be a mobile device or a power grid in a house. The battery package 100 is connected to an optional heating device 194 (shown in dashed lines because it is optional) through a pipe 193 to heat up the battery package 100 in an initial ramping up state to increase efficiency. The optional heating device 194 may be a heater or a heat exchanger. The battery package 100 is connected to an optional conditional device 196 (shown in dashed lines because it is optional) through a pipe 195 to reduce the temperature of the battery package 100 during operation. The optional conditional device 196 may be a radiator, a compressor, or a heat sink.
  • In examples of the present disclosure, the battery package 100 excludes a wafer-level sub-housing 121 (shown in dotted lines because of being excluded) enclosing the single porous wafer battery 140.
  • FIG. 2 shows a side view of a battery package 200 in examples of the present disclosure. The battery package 200 comprises a single porous two-wafer battery 230 and a housing 220. The single porous two-wafer battery 230 comprises a first porous wafer 240 serving as an anode and a second porous wafer 250 serving as a cathode. The first porous wafer 240 comprises a first plurality of pores 242. The second porous wafer 250 comprises a second plurality of pores 252. The housing 220 is shown in transparent. The housing 220 comprises a cavity 222. The single porous two-wafer battery 230 is disposed in the cavity 222 of the housing 220. In examples of the present disclosure, the first porous wafer 240 is of a circular wafer shape. The second porous wafer 250 is of a circular wafer shape. The housing 220 is of a cylinder shape. The first porous wafer 240, the second porous wafer 250, and the housing 220 share a same centerline 251.
  • In examples of the present disclosure, the single porous two-wafer battery 230 does not contain another porous wafer battery.
  • In examples of the present disclosure, the cavity 222 of the housing 220 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 200 is under shock or vibration. In one example, the cavity 222 of the housing 220 is filled with water. In another example, the cavity 222 of the housing 220 is filled with water containing coolant.
  • When the cavity 222 of the housing 220 is in a positive pressure environment, it may reduce leaching of exterior ambient substance into the battery package 200. When the cavity 222 of the housing 220 is in a vacuum state (in one example, less than one torr), it may reduce leaching of substance of the battery package 200 into environment.
  • In examples of the present disclosure, a plurality of inner surfaces of the housing 220 is coated with a layer 271 (shown in dashed line because of being optional) of fire retardant material. A plurality of outer surfaces of the housing 220 is coated with a layer 273 (shown in dashed line because of being optional) of fire retardant material. The fire retardant material may be made of Parylene-F.
  • FIG. 3 shows a side view of a battery package 300 in examples of the present disclosure. The battery package 300 comprises a porous wafer battery 310, a porous two-wafer battery 330, a first slot 371, a second slot 373, a third slot 375, and a housing 320. The porous wafer battery 310 comprises a plurality of pores 312 (shown in dashed lines in a side view plot). Each of the plurality of pores 312 comprises a respective anode and a respective cathode. The porous two-wafer battery 330 comprises a first porous wafer 340 serving as an anode and a second porous wafer 350 serving as a cathode. The first porous wafer 340 comprises a first plurality of pores 342. The second porous wafer 350 comprises a second plurality of pores 352. The housing 320 is shown in transparent. The housing 320 comprises a cavity 322. The porous wafer battery 310 and the porous two-wafer battery 330 are disposed in the cavity 322 of the housing 320. In examples of the present disclosure, the porous wafer battery 310 is of a circular wafer shape. The first porous wafer 340 is of a circular wafer shape. The second porous wafer 350 is of a circular wafer shape. The housing 320 is of a cylinder shape. Each of the first slot 371, the second slot 373, and the third slot 375 is of a circular ring shape or of arc sections of a ring shape.
  • The porous wafer battery 310 is inserted in the first slot 371. The first porous wafer 340 is inserted in the second slot 373. The second porous wafer 350 is inserted in the third slot 375. A shortest distance 381 between the porous wafer battery 310 and the porous two-wafer battery 330 is larger than a distance 383 between the first porous wafer 340 and the second porous wafer 350.
  • FIG. 4 shows a side view of a battery package 400 in examples of the present disclosure. The battery package 400 comprises a plurality of porous wafer batteries 410, a plurality of slots 470, a heating wafer 451, a cooling wafer 461, and a housing 420. The housing 420 is shown in transparent. The plurality of porous wafer batteries 410, the heating wafer 451, and the cooling wafer 461 are inserted into the plurality of slots 470 respectively. The heating wafer 451 comprises a heating element 453. The heating element 453 may include resistors, a heater or a heat exchanger. The cooling wafer 461 comprising a cooling element 463. The cooling element 463 may include a radiator, a compressor, or a heat sink.
  • The housing 420 comprises a cavity 422. The cavity 422 of the housing 420 is filled with liquid or air so as to increase damping and to reduce damage when the battery package 400 is under shock or vibration. In one example, the cavity 422 of the housing 420 is filled with water. In another example, the cavity 422 of the housing 420 is filled with water containing coolant. The plurality of porous wafer batteries 410 are sealed. The sealing process may use one or more caps similar to those of U.S. Pat. No. 6,969,639 to Cho, et al. except that no dicing process is needed. The plurality of porous wafer batteries 410 are submerged in the liquid.
  • In examples of the present disclosure, the battery package 400 further comprises a plurality of spacers 490 (shown in dashed lines because of being optional). Each of the plurality of spacers 490 is between a respective pair of the plurality of slots 470. Each of the plurality of spacers 490 is of a circular ring shape or of arc sections of a ring shape.
  • FIG. 5 shows a side view of a battery package 500 in examples of the present disclosure. The battery package 500 comprises a plurality of porous wafer batteries 510, a plurality of slots 570, a temperature-adjusting wafer 551, and a housing 520. The housing 520 is shown in transparent. The plurality of porous wafer batteries 510 and the temperature-adjusting wafer 551 are inserted into the plurality of slots 570 respectively. The temperature-adjusting wafer 551 comprises a heating element 553 and a cooling element 563. The heating element 553 may include resistors, a heater or a heat exchanger. The cooling element 563 may include a radiator, a compressor, or a heat sink.
  • In examples of the present disclosure, the housing 520 further comprises an anode tab 527 and a cathode tab 529. The anode tab 527 and the cathode tab 529 are on a same end of the housing 520. The battery package 500 further comprises a first plurality of conductive members 591 and a second plurality of conductive members 593 (shown in dashed lines because of being an example). The first plurality of conductive members 591 connect a respective anode of each of the plurality of porous wafer batteries 510 to the anode tab 527 of the housing 520. A second plurality of conductive members 593 connect a respective cathode of each of the plurality of porous wafer batteries 510 to the cathode tab 529 of the housing 520. The first plurality of conductive members 591 and the second plurality of conductive members 593 may be conductive traces, connectors, or wires.
  • In examples of the present disclosure, the plurality of porous wafer batteries 510 are configured in parallel in the circuit including the first plurality of conductive members 591 and the second plurality of conductive members 593. Therefore, even the porous wafer battery corresponding to the slot 579 is removed, the battery package 500 is still functioning.
  • FIG. 6 shows a side view of a battery package 600 in examples of the present disclosure. The battery package 600 comprises a plurality of porous wafer batteries 610, a plurality of slots 670, a cooling wafer 661, and a housing 620. The housing 620 is shown in transparent. The housing 420 comprises a cavity 422. The plurality of slots 670 are attached to an inner surface of the housing 620. The plurality of porous wafer batteries 610 are inserted into the plurality of slots 670 respectively. The cooling wafer 661 comprises a cooling element 663. The cooling element 663 may include a radiator, a compressor, or a heat sink. A majority portion, more than 50%, of the cooling wafer 661 is disposed external to the housing 620. A minority portion, less than 50%, of the cooling wafer is disposed in the cavity 622 of the housing 620. An entirely of the cooling element 663 is disposed external to the housing 620.
  • FIG. 7 shows a side view of a battery package 700 in examples of the present disclosure. The battery package 700 comprises a plurality of porous wafer batteries 710, a plurality of slot 770, a plurality of cooling wafers 750, and a housing 720. The housing 720 is shown in transparent. The housing 720 comprises a cavity 722. The plurality of porous wafer batteries 710 and the plurality of cooling wafers 750 are inserted into the plurality of slot 770 respectively. The plurality of cooling wafers 750 comprises a first cooling wafer 751 and a second cooling wafer 757. The first cooling wafer 751 comprises a first cooling element 753. The second cooling wafer 757 comprises a second cooling element 759. The first cooling element 753 and the second cooling element 759 may include a radiator, a compressor, or a heat sink.
  • In examples of the present disclosure, the housing 720 further comprises an anode tab 727 and a cathode tab 729. The anode tab 727 and the cathode tab 729 are on opposite ends of the housing 720 respectively. The battery package 700 further comprises a first plurality of conductive members 791 and a second plurality of conductive members 793 (shown in dashed lines because of being an example). The first plurality of conductive members 791 connect a respective anode of each of the plurality of porous wafer batteries 710 to the anode tab 727 of the housing 720. A second plurality of conductive members 793 connect a respective cathode of each of the plurality of porous wafer batteries 710 to the cathode tab 729 of the housing 720. The first plurality of conductive members 791 and the second plurality of conductive members 793 may be conductive traces, connectors, or wires.
  • FIG. 8 shows a top view of a porous wafer 810 and a slot 870 in examples of the present disclosure. The porous wafer 810 comprises a plurality of pores 820 and a contact region 811. The plurality of pores 820 are symmetric with respect to a center 831 of the porous wafer 810. The plurality of pores 820 are symmetric with X-axis. The plurality of pores 820 are symmetric with X-axis. In one example, the plurality of pores 820 are of rectangular shapes. In one example, the plurality of pores 820 are of circular shapes. The slot 870 comprises a contact region 871 and a groove 872. In examples of the present disclosure, the contact region 871 of the slot 870 directly contacts the contact region 811 of the porous wafer 810. In one example, a radius of the groove 872 is 1% to 3% smaller than a radius of the porous wafer 810 so that the porous wafer 810 is pressed fitted into the slot 870.
  • Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the plurality of pores may vary. A number of wafers in a battery package may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.

Claims (15)

1. A battery package comprising
one or more porous wafer batteries; and
a housing enclosing the one or more porous wafer batteries.
2. The battery package of claim 1, wherein the battery package excludes a respective wafer-level sub-housing enclosing each of the one or more porous wafer batteries.
3. The battery package of claim 1, wherein the one or more porous wafer batteries comprises
a single porous wafer battery comprising
a plurality of pores;
wherein the battery package excludes an additional porous wafer battery; and
wherein each of the plurality of pores comprises
a respective anode; and
a respective cathode.
4. The battery package of claim 1, wherein the one or more porous wafer batteries comprises
a single porous two-wafer battery comprising
a first porous wafer serving as an anode, the first porous wafer comprising
a first plurality of pores; and
a second porous wafer serving as a cathode, the second porous wafer comprising
a second plurality of pores.
5. The battery package of claim 1, wherein a plurality of inner surfaces of the housing is coated with a layer of fire retardant material.
6. The battery package of claim 1 further comprising
a heating wafer enclosed by the housing, the heating wafer comprising
a heating element.
7. The battery package of claim 1, further comprising
a cooling wafer enclosed by the housing, the cooling wafer comprising
a cooling element.
8. The battery package of claim 1, further comprising
a cooling wafer comprising
a cooling element;
wherein a majority portion of the cooling wafer is disposed external to the housing; and
wherein a minority portion of the cooling wafer is disposed in the housing.
9. The battery package of claim 1, further comprising
a temperature-adjusting wafer enclosed by the housing, the temperature-adjusting wafer comprising
a heating wafer enclosed by the housing, the heating wafer comprising
a heating element; and
a cooling wafer enclosed by the housing, the cooling wafer comprising
a cooling element.
10. The battery package of claim 1, wherein an internal volume of the housing is filled with a liquid; and
wherein the one or more porous wafer batteries are sealed; and
wherein the one or more porous wafer batteries are submerged in the liquid.
11. The battery package of claim 1, wherein the housing comprises one or more slots; and
wherein each porous wafer of the one or more porous wafers is inserted into a respective slot of the one or more slots.
12. The battery package of claim 11, wherein each slot of the one or more slots comprises a groove; and wherein a contact region of each porous wafer of the one or more porous wafers is inserted into the groove of the respective slot of the one or more slots.
13. The battery package of claim 12, wherein a spacer is between a selected slot of the one and more slots and an adjacent slot of the one and more slots.
14. The battery package of claim 12, wherein the housing further comprises
an anode tab; and
a cathode tab; and
wherein the battery package further comprises
a first plurality of conductive members connecting a respective anode of each of the one or more wafer batteries to the anode tab of the housing; and
a second plurality of conductive members connecting a respective cathode of each of the one or more wafer batteries to the cathode tab of the housing.
15. The battery package of claim 1, wherein the one or more porous wafer batteries comprises
a porous one-wafer battery comprising
a plurality of pores; and
a porous two-wafer battery comprising
a first porous wafer serving as an anode; and
a second porous wafer serving as a cathode;
wherein each of the plurality of pores of the porous one-wafer battery comprises
a respective anode; and
a respective cathode.
US17/087,604 2019-11-04 2020-11-02 Battery package containing porous wafer battery Abandoned US20210135311A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/087,604 US20210135311A1 (en) 2019-11-04 2020-11-02 Battery package containing porous wafer battery

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201962930019P 2019-11-04 2019-11-04
US201962930021P 2019-11-04 2019-11-04
US201962930018P 2019-11-04 2019-11-04
US201962930016P 2019-11-04 2019-11-04
US201962930020P 2019-11-04 2019-11-04
US17/087,604 US20210135311A1 (en) 2019-11-04 2020-11-02 Battery package containing porous wafer battery

Publications (1)

Publication Number Publication Date
US20210135311A1 true US20210135311A1 (en) 2021-05-06

Family

ID=75686355

Family Applications (5)

Application Number Title Priority Date Filing Date
US17/087,607 Active 2041-02-04 US11342625B2 (en) 2019-11-04 2020-11-02 Method of fabricating and method of using porous wafer battery
US17/087,575 Abandoned US20210135231A1 (en) 2019-11-04 2020-11-02 Porous two-wafer battery
US17/087,617 Abandoned US20210135271A1 (en) 2019-11-04 2020-11-02 Method of fabricating porous wafer battery
US17/087,604 Abandoned US20210135311A1 (en) 2019-11-04 2020-11-02 Battery package containing porous wafer battery
US17/087,600 Pending US20210135003A1 (en) 2019-11-04 2020-11-02 Single-chip containing porous-wafer battery and device and method of making the same

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US17/087,607 Active 2041-02-04 US11342625B2 (en) 2019-11-04 2020-11-02 Method of fabricating and method of using porous wafer battery
US17/087,575 Abandoned US20210135231A1 (en) 2019-11-04 2020-11-02 Porous two-wafer battery
US17/087,617 Abandoned US20210135271A1 (en) 2019-11-04 2020-11-02 Method of fabricating porous wafer battery

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/087,600 Pending US20210135003A1 (en) 2019-11-04 2020-11-02 Single-chip containing porous-wafer battery and device and method of making the same

Country Status (1)

Country Link
US (5) US11342625B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342625B2 (en) * 2019-11-04 2022-05-24 Xnrgi, Inc. Method of fabricating and method of using porous wafer battery

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090155678A1 (en) * 2007-08-21 2009-06-18 Less Gregory B Separator for electrochemical cell and method for its manufacture
US20100291431A1 (en) * 2009-05-13 2010-11-18 Front Edge Technology, Inc. Thin film battery with protective packaging
US20130244066A1 (en) * 2010-12-28 2013-09-19 Lg Chem, Ltd. Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same
US20140308576A1 (en) * 2011-11-02 2014-10-16 I-Ten Method for manufacturing all-solid-state thin-film batteries

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1210872B (en) * 1982-04-08 1989-09-29 Ates Componenti Elettron PROCESS FOR THE MANUFACTURE OF COMPLEMENTARY MOS TRANSISTORS IN HIGH DENSITY INTEGRATED CIRCUITS FOR HIGH VOLTAGES.
US6197450B1 (en) * 1998-10-22 2001-03-06 Ramot University Authority For Applied Research & Industrial Development Ltd. Micro electrochemical energy storage cells
US6432577B1 (en) * 2000-06-29 2002-08-13 Sandia Corporation Apparatus and method for fabricating a microbattery
US20030042587A1 (en) 2001-08-31 2003-03-06 Tsung-Jen Lee IC packaging and manufacturing methods
WO2004036668A2 (en) * 2002-10-17 2004-04-29 Tel-Aviv University Future Technology Development L.P. Thin-film cathode for 3-dimensional microbattery and method for preparing such cathode
CA2432397A1 (en) * 2003-06-25 2004-12-25 Hydro-Quebec Procedure for preparing an electrode from porous silicon, the electrode so obtained, and an electrochemical system containing at least one such electrode
US7295029B2 (en) * 2005-03-24 2007-11-13 Memsic, Inc. Chip-scale package for integrated circuits
US7776679B2 (en) * 2007-07-20 2010-08-17 Stmicroelectronics Crolles 2 Sas Method for forming silicon wells of different crystallographic orientations
CN102203905A (en) 2008-11-10 2011-09-28 Kelk株式会社 Apparatus and method for controlling temperature of semiconductor wafer
US9368429B2 (en) * 2011-10-25 2016-06-14 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
EP2913847B1 (en) * 2014-02-28 2018-04-18 LFoundry S.r.l. Method of fabricating a semiconductor device and semiconductor product
US9876200B2 (en) * 2015-08-07 2018-01-23 International Business Machines Corporation All-silicon hermetic package and processing for narrow, low-profile microbatteries
US10079375B2 (en) * 2015-12-30 2018-09-18 International Business Machines Corporation Dual seal microbattery and method of making
WO2018175423A1 (en) * 2017-03-20 2018-09-27 Millibatt, Inc. Battery system and production method
US10505160B2 (en) * 2017-06-26 2019-12-10 International Business Machines Corporation Micro-battery using glass package
US11233288B2 (en) * 2018-07-11 2022-01-25 International Business Machines Corporation Silicon substrate containing integrated porous silicon electrodes for energy storage devices
US10833301B2 (en) * 2019-01-02 2020-11-10 International Business Machines Corporation Through silicon via energy storage devices
US11342625B2 (en) * 2019-11-04 2022-05-24 Xnrgi, Inc. Method of fabricating and method of using porous wafer battery

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090155678A1 (en) * 2007-08-21 2009-06-18 Less Gregory B Separator for electrochemical cell and method for its manufacture
US20100291431A1 (en) * 2009-05-13 2010-11-18 Front Edge Technology, Inc. Thin film battery with protective packaging
US20130244066A1 (en) * 2010-12-28 2013-09-19 Lg Chem, Ltd. Battery module receiving apparatus, battery module thermostat, and power storage system comprising the same
US20140308576A1 (en) * 2011-11-02 2014-10-16 I-Ten Method for manufacturing all-solid-state thin-film batteries

Also Published As

Publication number Publication date
US11342625B2 (en) 2022-05-24
US20210135003A1 (en) 2021-05-06
US20210135231A1 (en) 2021-05-06
US20210134608A1 (en) 2021-05-06
US20210135271A1 (en) 2021-05-06

Similar Documents

Publication Publication Date Title
US20170237112A1 (en) Porous spacers for electrochemical cells
US8795867B2 (en) Wire mounted battery module on vertical support frame
KR100667943B1 (en) Secondary battery module
US20110183176A1 (en) Battery cell module
US20110189522A1 (en) Battery pack
CN103904381B (en) Internal temperature of battery measurement apparatus
JP6437546B2 (en) Energy storage module comprising a plurality of energy storage assemblies
KR20170132514A (en) Battery module, battery pack comprising the battery module and vehicle comprising the battery pack
US11196109B2 (en) Battery module and battery module stack for a motor vehicle
US20210135311A1 (en) Battery package containing porous wafer battery
JP2010212165A (en) Cell module and manufacturing method therefor
KR20170019229A (en) Battery module, battery pack comprising the battery module and vehicle comprising the battery pack
KR20210140775A (en) Battery module including asymmetric cell electrical connections
JP2011150902A (en) Lithium ion secondary battery
US10193196B1 (en) Internal battery cell cooling with heat pipe
US11296385B2 (en) Battery module and battery pack
CN110770965A (en) Battery module with improved cooling structure
JP2013004468A (en) Battery pack device
JP2023514326A (en) Battery cases, batteries, battery packs, battery modules and vehicles
CN111226344B (en) Battery module and battery pack including the same
KR20240023439A (en) Batteries and Electrical Appliances
JP2010272319A (en) Battery pack
CN211507807U (en) Quick radiating lithium cell structure
KR20190074796A (en) Battery module with improved cooling efficiency
CN113823865A (en) Square battery shell, battery with same, battery pack and automobile

Legal Events

Date Code Title Description
AS Assignment

Owner name: XNRGI, INC., WASHINGTON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:D'COUTO, GERARD CHRISTOPHER;REEL/FRAME:054248/0098

Effective date: 20201102

STPP Information on status: patent application and granting procedure in general

Free format text: APPLICATION DISPATCHED FROM PREEXAM, NOT YET DOCKETED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION