CN110277348B - Manufacturing process method of semiconductor TSV structure and semiconductor TSV structure - Google Patents
Manufacturing process method of semiconductor TSV structure and semiconductor TSV structure Download PDFInfo
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- CN110277348B CN110277348B CN201910485230.4A CN201910485230A CN110277348B CN 110277348 B CN110277348 B CN 110277348B CN 201910485230 A CN201910485230 A CN 201910485230A CN 110277348 B CN110277348 B CN 110277348B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
The invention relates to the technical field of semiconductor manufacturing processes, in particular to a manufacturing process method of a semiconductor TSV structure and the semiconductor TSV structure, wherein the method comprises the following steps: etching a front annular gap on the front surface of the silicon wafer, wherein the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure protruding towards the direction of the opposite side wall from top to bottom, and the silicon wafer part surrounded by the annular gap is used as a conductive structure; the insulating layers are grown on the inner wall and the outer wall of the front annular gap, and the annular gap with the convex structure is formed by etching by using the etching depth of the groove for etching the large gap, so that the difficulty of limiting the depth ratio in the small gap groove by independently etching can be reduced, the difficulty of filling the deep hole can be reduced by using the formed small gap groove, the etching efficiency is improved, the filling efficiency is improved, and the processing efficiency of the TSV structure of the semiconductor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing processes, in particular to a manufacturing process method of a semiconductor TSV structure and the semiconductor TSV structure.
Background
TSV (through Silicon vias) is a through Silicon via. The packaging technology of the TSV wafer mainly comprises the steps that a TSV hole is formed in the back face of the wafer to expose a bonding pad, a metal layer is used for leading out a lead from the bonding pad, wiring and ball planting are conducted on the back face of the wafer, when the TSV hole is manufactured, the hole diameter is small, the etching difficulty is high, when the hole diameter is large, filling is not easy, and machining efficiency is further affected. In addition, most of the existing TSV processes adopt copper electroplating processes, and the copper electroplating is used as a conductor structure, which greatly causes environmental pollution.
Therefore, how to improve the efficiency of the TSV manufacturing process is a technical problem to be solved urgently.
Disclosure of Invention
In view of the above, the present invention has been made to provide a manufacturing process of a semiconductor TSV structure and a semiconductor TSV structure that overcome or at least partially solve the above problems.
On one hand, the embodiment of the invention also provides a manufacturing process method of the TSV structure of the semiconductor, which comprises the following steps:
etching a front annular gap on the front surface of the silicon wafer, wherein the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure protruding towards the direction of the opposite side wall from top to bottom, and the silicon wafer part surrounded by the annular gap is used as a conductive structure;
and growing an insulating layer on the inner wall and the outer wall of the front annular gap.
Further, the front annular gap is specifically a front annular groove or an annular through hole.
Further, if the front annular gap is specifically a front annular groove, after the insulating layer is grown on the inner wall and the outer wall of the front annular groove, the method further includes:
and thinning the back of the silicon chip until the bottom end of the front annular groove is exposed.
Further, if the front annular gap is specifically a front annular groove, after the insulating layer is grown on the inner wall and the outer wall of the front annular groove, the method further includes:
etching a back annular groove on the back of the silicon wafer to enable the bottom end of the back annular groove to be communicated with the bottom end of the front annular groove, wherein the back annular groove comprises an inner wall, an outer wall and a bottom end, and the outer wall or the inner wall comprises more than one structure protruding towards the direction of the opposite side wall from top to bottom;
and growing an insulating layer on the inner wall and the outer wall of the back annular groove.
Further, among the more than one structures protruding from top to bottom in the direction of the opposite side wall, the protruding structure is specifically any one of the following:
semi-cylindrical structure, triangular prism structure, cuboid structure and trapezoidal body structure.
Further, when the front annular gap is specifically a front annular groove, after growing an insulating layer on the inner wall and the outer wall of the front annular groove, and/or after growing an insulating layer on the inner wall and the outer wall of the back annular groove, the method further includes:
depositing a support layer on the insulating layer.
Further, the insulating layer is specifically any one of the following: silicon oxide, silicon nitride.
Further, the supporting layer is specifically any one of the following: polysilicon, silicon oxide and silicon nitride.
Further, the cross section of the front annular gap is circular ring-shaped, square ring-shaped or triangular ring-shaped.
On the other hand, an embodiment of the present invention further provides a semiconductor TSV structure, including:
a silicon wafer and an insulating layer;
the front side of the silicon wafer is provided with a front side annular gap, the front side annular gap divides the silicon wafer into an internal conductive structure and a peripheral supporting structure, the front side annular gap comprises an inner wall and an outer wall, and the outer wall or the inner wall comprises more than one structure which is convex towards the direction of the opposite side wall from top to bottom;
the insulating layer is filled in the front annular gap.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a manufacturing process method of a semiconductor TSV structure, which comprises the steps of etching a front annular gap on the front surface of a silicon wafer, wherein the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure protruding towards the opposite side wall from top to bottom, and the part of the silicon wafer surrounded by the annular gap is used as a conductive structure; the insulating layers are grown on the inner wall and the outer wall of the front annular gap, and due to the adoption of the annular gap, the annular gap with the convex structure is etched and formed by utilizing the etching depth of the groove for etching the large gap, so that the difficulty of limiting the depth ratio in the small gap groove by independently etching can be reduced, the difficulty of filling the deep hole can be reduced by utilizing the formed small gap groove, the etching efficiency is improved, the filling efficiency is also improved, and the processing efficiency of the TSV structure of the semiconductor is further improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor TSV structure according to an embodiment of the present invention;
FIGS. 2 a-2 g are schematic views showing structures formed at each step in the fabrication of a semiconductor TSV structure in an embodiment of the present invention;
fig. 3 shows a schematic diagram of a semiconductor TSV structure in an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The general idea of the invention is as follows:
the TSV structure manufacturing process aims to solve the problems that in the existing TSV structure manufacturing process, when a groove is too large, etching is easy, but the filling difficulty is increased; when the groove is too small, the filling is easy, but the etching difficulty is increased, thereby the technical problem of influencing the processing efficiency is solved, the invention provides a manufacturing process method of a semiconductor TSV structure, a front annular gap is etched on the front surface of a silicon chip, the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure which protrudes towards the opposite side wall direction from top to bottom, then an insulating layer is grown on the inner wall and the outer wall of the front annular gap, because the front annular gap comprises more than one structure which protrudes towards the opposite side wall direction from top to bottom, when the front annular gap is etched, the etching of a larger gap (the gap of which the inner wall or the outer wall does not protrude towards the opposite side wall direction) is simultaneously carried out, the drilling is carried out from two sides of the larger gap to a smaller gap side wall (the structure which protrudes towards the opposite side wall direction on the inner wall or the outer wall and the opposite side wall form a smaller gap), therefore, in the embodiment of the invention, the etching gas is used for drilling and etching the side wall of the smaller gap while etching the larger gap, so that the aim of etching the smaller gap is achieved, and the annular gap is formed by the larger gap and the smaller gap, so that the filling efficiency is improved while the etching efficiency is improved, and the processing efficiency is integrally improved.
The following description is given in terms of specific embodiments.
Example one
The embodiment of the invention provides a manufacturing process method of a semiconductor TSV structure, which comprises the following steps of S101, etching a front annular gap on the front surface of a silicon chip, wherein the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure protruding towards the direction of the opposite side wall from top to bottom, the part of the silicon chip surrounded by the annular gap is used as a conductive structure, and after S101, the structure shown in FIG. 2a is formed, specifically taking the case that the outer wall comprises more than one structure protruding towards the direction of the opposite side wall from top to bottom as an example; s102, growing an insulating layer on the inner wall and the outer wall of the front annular gap to form the structure shown in the figure 2 b. As shown in fig. 2a to 2g, the silicon wafer 20 is shown, the front annular groove 201A, the insulating layer 202, the protrusion structure 203, the support layer 204, and the back annular groove 201B.
The front annular gap may be specifically a front annular groove 201A or an annular through hole. The front annular groove comprises a gap formed by surrounding an inner wall, an outer wall and a groove bottom, and the annular through hole comprises a gap formed by surrounding the inner wall and the outer wall.
In the embodiment of the present invention, the front annular gap is taken as an example of the front annular groove to be described in detail.
If the front annular gap is specifically the front annular groove 201A, in S102, an insulating layer 202 is grown on the inner wall and the outer wall of the front annular groove 201A, and the insulating layer 202 specifically adopts silicon oxide or silicon nitride, so that the silicon wafer structure enclosed by the front annular groove 201A is used as a conductive structure and is electrically insulated and isolated from the silicon wafer at the periphery of the insulating layer 202.
The silicon wafer 20 may be made of a low-resistance material to realize conductivity, and after S101, ions, such as boron ions and phosphorus ions, may be doped on the surface of the silicon wafer surrounded by the front annular gap 201, and the silicon wafer doped with the ions may realize conductivity. The silicon chip part surrounded by the annular gap is used as a conductive structure, so that the environmental pollution caused by the conventional copper electroplating process can be avoided.
After the insulating layer 201 is grown on the inner wall and the outer wall of the front surface annular groove 201A, the next steps are performed in two ways.
In the first implementation, as shown in fig. 2c, the back surface of the silicon wafer is directly thinned to expose the bottom end of the front annular groove 201A. And then the inner silicon wafer structure surrounded by the front annular groove 201A is communicated up and down, and the inner silicon wafer is isolated from the silicon wafer structure at the periphery of the front annular groove. The implementation is mainly directed to a relatively thin silicon wafer, and the second implementation is adopted for a thicker silicon wafer, the size thickness of the relatively thin silicon wafer 20 is generally less than 300 μm, and the size thickness of the relatively thick silicon wafer is generally greater than or equal to 400 μm. Therefore, the TSV structure can be manufactured on the silicon wafer with the thicker size.
In a second implementation manner, as shown in fig. 2d, a back annular groove 201B is etched on the back surface of the silicon wafer 20, so that the bottom end of the back annular groove 201B is connected to the bottom end of the front annular groove 201A; then, as shown in fig. 2e, an insulating layer 202 is grown on the inner and outer walls of the back surface annular groove 201B.
In the etching process, the etching depth of the front annular groove 201A is larger than or equal to half of the thickness of the silicon wafer 20, and then when the back of the silicon wafer is etched, it can be ensured that the bottom end of the back annular groove 201B is communicated with the bottom end of the front annular groove when the back of the silicon wafer is etched to the same depth, and meanwhile, because the bottom end of the front annular groove 201A is provided with an insulating layer (silicon oxide and the like), the front annular groove can be used as a self-stop layer for back etching, so that over-etching is prevented, the reason is that the deep silicon etching is mainly silicon material etching, and silicon oxide can not be etched almost.
The method for etching the back annular groove 201B on the back surface of the silicon wafer 20 is the same as the method for etching the front annular groove 201A on the front surface of the silicon wafer, and similarly, the back annular groove 201B includes an inner wall, an outer wall and a bottom end, and the outer wall or the inner wall includes more than one structure protruding from top to bottom towards the direction of the opposite side wall. The laser etching or Deep Reactive Ion Etching (DRIE) may be specifically used, and is not specifically limited in the embodiment of the present invention.
The etching method is adopted to enable the bottom end of the back annular groove 201B to be communicated with the bottom end of the front annular groove 201A, and particularly, the double-sided registration technology in the photoetching process is adopted, so that the front annular groove 201A and the back annular groove 201B can be respectively connected around the silicon chip structure inside and isolated from the peripheral silicon chip structure.
After the etching of the back surface annular groove 201B described above, an insulating layer 202 is grown on the inner wall and the outer wall of the back surface annular groove 201B. Specifically, the step of growing the insulating layer 202 in the back annular groove 201B is the same as the step of growing the insulating layer 202 in the front annular groove 201A, specifically, silicon oxide is grown, but of course, the step is not limited to silicon oxide, silicon nitride may also be used, and a method of growing silicon oxide is used, which mainly aims to achieve electrical isolation, and is more convenient than a filling method, and silicon oxide is easier to grow on a silicon wafer. And further, the processing efficiency is also improved.
If the maximum gap of the front annular trench is 8 to 10 μm and the minimum gap is 3 to 4 μm, wherein the maximum gap is the distance between the inner wall and the non-protruding structure on the opposite outer wall, and the minimum gap is the distance between the inner wall and the protruding structure on the opposite outer wall, when the insulating layer 202 is grown on the inner wall and the outer wall of the front annular trench, the thickness of the insulating layer 202 may be 1.5 to 2 μm, and further, silicon oxide may be grown on the minimum gap of the front annular trench. Of course, the present invention is not limited to the frontal annular gap of the above-described dimensional configuration.
In a specific embodiment, the front annular gap includes an inner wall, an outer wall, and the outer wall or the inner wall includes more than one structure 203 protruding from the top to the opposite side wall. Wherein, the protruding structure 203 is specifically any one of the following: semi-cylindrical structure, triangular prism structure, cuboid structure and trapezoidal body structure. The embodiments of the present invention are not limited to these several convex structures. Any protruding structure may suffice as long as the gap between the protruding structure and the inner wall is reduced.
In a preferred embodiment, after growing the insulating layer 202 on the inner wall and the outer wall of the front annular groove 201A, the method further includes: a support layer 204 is deposited on the insulating layer 202 as shown in fig. 2 f.
In a preferred embodiment, after growing the insulating layer 202 on the inner wall and the outer wall of the back annular trench 201B, the method further includes: a support layer 204 is deposited on the insulating layer 202, forming a structure as shown in fig. 2g, where the support layer 204 can serve as a support and an internal seal.
After the front annular groove 201A and the back annular groove 201B are connected, the silicon wafer structure inside the connected annular gap is separated from the peripheral silicon wafer structure, so that the support layer 204 is used for supporting the connection between the internal separated silicon wafer structure and the peripheral silicon wafer structure, so as to avoid the situation that the connection between the insulating layer 202 inside the front annular gap and the peripheral silicon wafer cannot be fixed when the insulating layer 202 grown on the front annular groove does not completely fill the minimum gap, wherein the minimum gap specifically refers to the minimum gap between the outer wall convex structure and the inner wall.
The support layer 204 used here is specifically polysilicon, but of course, not limited to polysilicon, and silicon oxide or silicon nitride may be used. Generally, a deposition method is adopted to deposit polysilicon on the insulating layer 202, the deposition of polysilicon is also easy, and the processing efficiency is also improved.
In a specific embodiment, the cross section of the front annular gap is specifically circular ring-shaped, square ring-shaped or triangular ring-shaped, but the embodiments of the present invention are not limited to these shapes.
In the embodiment of the present invention, if the front annular gap is taken as an annular through hole, since the through hole is directly formed, a support needs to be disposed on the back surface of the entire silicon wafer to prevent the middle conductive silicon wafer structure from falling down after the annular through hole is etched through. Other process steps are the same as the process steps using the front annular gap as the front annular groove, and are not described herein again.
After the supporting layer 204 is deposited on the insulating layer 202, a planarization process is performed at the front annular gap on the front surface of the silicon wafer 20, specifically, a CMP process is used to remove the insulating layer filled in the front annular gap, or the insulating layer and the supporting layer at a position higher than the front surface of the silicon wafer 20 or a position higher than the back surface of the silicon wafer, so as to facilitate the next bonding process or the electrode wire process.
Example two
Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor TSV structure, as shown in fig. 3, where fig. 3 is a top view of the semiconductor TSV structure, including: a silicon wafer 20 and an insulating layer 202.
The front surface of the silicon wafer has a front annular gap 201, the front annular gap 201 divides the silicon wafer into an inner conductive structure 2011 and a peripheral support structure 2012, the front annular gap 201 includes an inner wall and an outer wall, and the outer wall or the inner wall includes more than one structures 203 protruding from top to bottom toward the opposite side wall. Fig. 3 shows only the raised structure on the outer wall.
The insulating layer 202 fills the front annular gap 201. The insulating layer 202 shown in fig. 3 belongs to the same region as the front annular gap 201.
Wherein, the protruding structure 203 is specifically any one of the following:
semi-cylindrical structure, triangular prism structure, cuboid structure and trapezoidal body structure. Of course, it is not limited to these structures.
In a preferred embodiment, the front annular gap 201 is embodied as a front annular groove or an annular through hole. Specifically, as shown in fig. 2a and 2c, fig. 2a is a sectional view of the front annular groove, and fig. 2c is a sectional view of the annular through hole.
After the insulating layer 202 is grown on the inner and outer walls of the front annular groove with respect to the front annular groove (front annular gap 201), the support layer 204 is deposited on the insulating layer 202, and similarly, the back annular groove (back annular gap) is symmetrically etched on the back surface of the silicon wafer, and after the insulating layer 202 is grown on the inner and outer walls of the back annular groove, the support layer 204 is deposited on the insulating layer 202, thereby forming the structure shown in fig. 2 g.
The insulating layer 202 is specifically silicon oxide, but is not limited to silicon oxide. The support layer 204 is specifically polysilicon, but is not limited to polysilicon.
For the annular through hole, after an insulating layer is grown on the inner wall and the outer wall of the annular through hole, a supporting layer is directly deposited on the insulating layer.
In a preferred embodiment, the cross-section of the frontal annular gap is in particular circular, square or triangular annular. Of course, these shapes are not limited to just these.
In the above embodiments, the convex structure is disposed on the outer wall, but of course, the convex structure may also be disposed on the inner wall, and the corresponding illustration is not shown in the embodiment of the present invention.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a manufacturing process method of a semiconductor TSV structure, which comprises the steps of etching a front annular gap on the front surface of a silicon wafer, wherein the front annular gap comprises an inner wall and an outer wall, the outer wall or the inner wall comprises more than one structure protruding towards the opposite side wall from top to bottom, and the part of the silicon wafer surrounded by the annular gap is used as a conductive structure; the insulating layers are grown on the inner wall and the outer wall of the front annular gap, and due to the adoption of the annular gap, the annular gap with the convex structure is etched and formed by utilizing the etching depth of the groove for etching the large gap, so that the difficulty of limiting the depth ratio in the small gap groove by independently etching can be reduced, the difficulty of filling the deep hole can be reduced by utilizing the formed small gap groove, the etching efficiency is improved, the filling efficiency is also improved, and the processing efficiency of the TSV structure of the semiconductor is further improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A manufacturing process method of a TSV structure of a semiconductor is characterized by comprising the following steps:
etching a front annular gap on the front surface of the silicon wafer, wherein the front annular gap comprises a first inner wall and a first outer wall, the first outer wall or the first inner wall comprises more than one first protruding structure, a first protruding part of the first protruding structure faces to the direction of the opposite side wall, the first protruding structure extends from the upper end to the lower end of the first outer wall or the first inner wall, and the silicon wafer part surrounded by the annular gap is used as a conductive structure;
and growing an insulating layer on the first inner wall and the first outer wall of the front annular gap.
2. The method according to claim 1, characterized in that the front annular gap is in particular a front annular groove or an annular through hole.
3. The method of claim 2, wherein if the front annular gap is embodied as a front annular trench, after growing an insulating layer on a first inner wall and a first outer wall of the front annular trench, further comprising:
and thinning the back of the silicon chip until the bottom end of the front annular groove is exposed.
4. The method of claim 2, wherein if the front annular gap is embodied as a front annular trench, after growing an insulating layer on a first inner wall and a first outer wall of the front annular trench, further comprising:
etching a back annular groove on the back of the silicon wafer to enable the bottom end of the back annular groove to be communicated with the bottom end of the front annular groove, wherein the back annular groove comprises a second inner wall, a second outer wall and a bottom end, the second outer wall or the second inner wall comprises more than one second protruding structures, second protruding parts of the second protruding structures face the direction of the opposite side walls, and the second protruding structures extend from the lower ends to the upper ends of the second outer walls or the second inner walls;
and growing an insulating layer on the second inner wall and the second outer wall of the back annular groove.
5. The method of claim 4, wherein the one or more first raised structures and the one or more second raised structures are specifically any one of:
semi-cylindrical structure, triangular prism structure, cuboid structure and trapezoidal body structure.
6. The method of claim 4, wherein, when the front annular gap is in particular a front annular trench, after growing an insulating layer on a first inner wall and a first outer wall of the front annular trench, and/or after growing an insulating layer on a second inner wall and a second outer wall of the back annular trench, further comprising:
depositing a support layer on the insulating layer.
7. The method according to claim 1 or 4, wherein the insulating layer is in particular any one of the following: silicon oxide, silicon nitride.
8. The method of claim 6, wherein the support layer is specifically any one or more of: polysilicon, silicon oxide, silicon nitride.
9. The method according to claim 1, characterized in that the cross-section of the front annular gap is in particular circular, square or triangular.
10. A semiconductor TSV structure comprising:
a silicon wafer and an insulating layer;
the front side of the silicon wafer is provided with a front side annular gap, the front side annular gap divides the silicon wafer into an inner conductive structure and a peripheral supporting structure, the front side annular gap comprises a first inner wall and a first outer wall, the first outer wall or the first inner wall comprises more than one first protruding structures, first protruding parts of the first protruding structures face the direction of the opposite side walls, and the first protruding structures extend from the upper ends to the lower ends of the first outer wall or the first inner wall;
the insulating layer is filled in the front annular gap.
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