US20130168730A1 - Semiconductor device having lateral insulated gate bipolar transistor - Google Patents
Semiconductor device having lateral insulated gate bipolar transistor Download PDFInfo
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- US20130168730A1 US20130168730A1 US13/719,389 US201213719389A US2013168730A1 US 20130168730 A1 US20130168730 A1 US 20130168730A1 US 201213719389 A US201213719389 A US 201213719389A US 2013168730 A1 US2013168730 A1 US 2013168730A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Definitions
- the present disclosure relates generally to semiconductor devices having an insulated gate bipolar transistor (IGBT), and relates in particular to a semiconductor device having a lateral IGBT formed by using a silicon-on-insulator (SOI) substrate.
- IGBT insulated gate bipolar transistor
- SOI silicon-on-insulator
- an electric current flows based on a hole current and an electron current.
- the hole current flows based on holes injected from a collector.
- the electron current flows based on electrons injected from an emitter.
- the low ON-voltage can be achieved by increasing the amount of holes injected form the collector.
- a tail current occurs due to the holes during switching so that fast switching cannot be achieved. Therefore, to achieve a low ON-voltage and a fast switching, it is very important to increase the amount of the electron current when the IGBT is turned ON.
- the amount of injected electrons depends on the density of holes near an emitter. Therefore, to achieve a low ON-voltage and a fast switching, it is important to increase the density of holes near the emitter without excessively increasing the amount of holes injected from the collector.
- CS carrier storage
- the non-patent document 1 discloses a structure for increasing the conductivity modulation in a vertical IGBT only. In other words, the non-patent document 1 is silent on a lateral IGBT.
- a semiconductor device having a lateral insulated gate bipolar transistor includes a semiconductor substrate having a first conductivity type drift layer.
- a second conductivity type collector region is formed in a surface portion of the drift layer.
- a second conductivity type channel layer is formed in the surface portion of the drift layer and has a straight-shaped portion on each side of the collector region.
- a first conductivity type emitter region is formed in a surface portion of the channel layer and terminated inside the channel layer. The emitter region has a straight-shaped portion extending parallel to a longitudinal direction of the collector region.
- a gate insulation layer is in contact with a channel region of the channel layer. The channel region is located between the emitter region and the drift layer.
- a gate electrode is formed on a surface of the gate insulation layer.
- a collector electrode is electrically connected to the collector region.
- An emitter electrode is electrically connected to the emitter region and the channel layer.
- a hole stopper region is formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.
- FIG. 1 is a diagram illustrating a top layout view of a semiconductor device according to a first embodiment of the present disclosure
- FIG. 2A is a diagram illustrating a cross-sectional view taken along line IIA-IIA in FIG. 1
- FIG. 2B is a diagram illustrating a cross-sectional view taken along line IIB-IIB in FIG. 1 ;
- FIG. 3 is a diagram illustrating a hole density distribution in the semiconductor device along the line IIA-IIA in FIG. 1 ;
- FIG. 4 is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a first modification of the first embodiment
- FIG. 5 is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a second modification of the first embodiment
- FIG. 6A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a third modification of the first embodiment
- FIG. 6B is a diagram and illustrating an enlarged view of an area VIB in FIG. 6A ;
- FIG. 7 is a diagram illustrating a top layout view of a semiconductor device according to a second embodiment of the present disclosure.
- FIG. 8 is a diagram illustrating a top layout view of a semiconductor device according to a modification of the second embodiment
- FIG. 9 is a diagram illustrating a top layout view of a semiconductor device according to a third embodiment of the present disclosure.
- FIG. 10 is a diagram illustrating a cross-sectional view taken along line X-X in FIG. 9 ;
- FIG. 11A is a diagram illustrating a top layout view of a semiconductor device according to a fourth embodiment of the present disclosure
- FIG. 11B is a diagram illustrating an enlarged view of an area XIB in FIG. 11A ;
- FIG. 12A is a diagram illustrating a top layout view of a semiconductor device according to a modification of the fourth embodiment
- FIG. 12B is a diagram illustrating an enlarged view of an area XIIB in FIG. 12A ;
- FIG. 13A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure
- FIG. 13B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the fifth embodiment;
- FIG. 14 is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a modification of the fifth embodiment
- FIGS. 15A and 15B are diagrams illustrating manufacturing processes of the semiconductor device of FIG. 14 ;
- FIG. 16 is a diagram illustrating a top layout view of a semiconductor device according to a sixth embodiment of the present disclosure.
- FIGS. 17A and 17B are diagrams illustrating manufacturing processes of the semiconductor device of FIG. 16 taken along line XVIIA,B-XVIIA,B in FIG. 16 ;
- FIGS. 18A and 18B are diagrams illustrating manufacturing processes of the semiconductor device of FIG. 16 taken along line XVIIIA,B-XVIIIA,B in FIG. 16 ;
- FIG. 19A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a seventh embodiment of the present disclosure
- FIG. 19B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the seventh embodiment;
- FIG. 20A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to an eighth embodiment of the present disclosure
- FIG. 20B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the eighth embodiment;
- FIG. 21A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a ninth embodiment of the present disclosure
- FIG. 21B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the ninth embodiment.
- FIG. 1 is a diagram illustrating a top layout view of the semiconductor device.
- FIG. 2A is a diagram illustrating a cross-sectional view taken along the line IIA-IIA in FIG. 1 .
- FIG. 2B is a diagram illustrating a cross-sectional view taken along the line IIB-IIB in FIG. 1 .
- the lateral IGBT is formed by using a SOI substrate 1 .
- the SOI substrate 1 includes a supporting substrate 1 a , a buried oxide layer (BOX) 1 b on the supporting substrate 1 a , and an active layer is on the BOX layer 1 b .
- the supporting substrate 1 a and the active layer 1 c are made of silicon.
- the BOX layer 1 b serves as an electrical insulation layer.
- the active layer 1 c serves as a n ⁇ -type drift layer 2 . Components of the lateral IGBT are formed in a surface portion of the drift layer 2 .
- the thickness of the BOX layer 1 b is not limited to a specific value.
- the thickness and the impurity concentration of the active layer 1 c are not limited to specific values.
- the thickness of the BOX layer 1 b and the thickness and the impurity concentration of the active layer 1 c are set so that the lateral IGBT can have a predetermined breakdown voltage.
- the thickness of the BOX later 1 b can be 4 ⁇ m or more.
- the thickness of the BOX layer 1 b is 5 ⁇ m or more.
- the n-type impurity concentration of the active layer 1 c ranges from 1 ⁇ 10 14 cm ⁇ 3 to 1.2 ⁇ 10 15 cm ⁇ 3 , if the thickness of the active layer 1 c is 15 ⁇ m or less.
- the n-type impurity concentration of the active layer is ranges from 1 ⁇ 10 14 cm ⁇ 3 to 8 ⁇ 10 14 cm ⁇ 3 , if the thickness of the active layer 1 c is 20 ⁇ m.
- a LOCOS layer 3 is formed on a surface of the drift layer 2 to isolate the components of the lateral IGBT from each other.
- a p + -type collector region 4 is formed in the surface portion of the drift layer 2 and exposed outside the LOCOS layer 3 .
- the collector region 4 has a longitudinal direction parallel to the surface of the drift layer 2 .
- the collector region 4 is surrounded by a n-type buffer layer 5 .
- the buffer layer 5 has an impurity concentration greater than that of the drift layer 2 .
- a p-channel well layer 6 , a n + -type emitter region 7 , and a p + -type contact layer 8 are formed in the surface portion of the drift layer 2 around the collector region 4 and exposed outside the LOCOS layer 3 .
- a surface portion of the well layer 6 serves a channel region.
- the thickness of the well layer 6 can be 2 ⁇ m or less, and the width of the well layer 6 can be 6 ⁇ m or less.
- the well layer 6 is arranged concentrically with respect to the collector region 4 so that the collector region 4 can be entirely surrounded by the well layer 6 . That is, the well layer 6 has an ellipse shape, when viewed from the top, to surround the collector region 4 .
- the well layer 6 has a pair of straight-shaped portions and a pair of arc-shaped portions. The straight-shaped portions extend in the longitudinal direction of the collector region 4 .
- One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion.
- the well layer 6 has a body layer which is located below and around the contact layer 8 .
- a p-type impurity concentration of the body layer is so high that the body layer can reduce a voltage drop which is caused by a Hall current flowing from a collector to an emitter through the surface.
- the body layer reduces or prevents operation of a parasitic npn transistor which is constructed with the emitter region 7 , the well layer 6 , and the drift layer 2 .
- a turn-off time of the lateral IGBT can be improved.
- the emitter region 7 is formed in a surface portion of the well layer 6 and terminated inside the well layer 6 . Like the well layer 6 , the emitter region 7 has an ellipse shape, when viewed from the top, to surround the collector region 4 . Specifically, the emitter region 7 has a pair of straight-shaped portions and a pair of arch-shaped portions. The straight-shaped portions of the emitter region 7 extend in the longitudinal direction of the collector region 4 . One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion.
- the contact layer 8 is used to clamp the well layer 6 to an emitter potential.
- the contact layer 8 has an impurity concentration greater than that of the well layer 6 .
- the contact layer 8 is arranged concentrically with respect to the collector region 4 so that the collector region 4 can be entirely surrounded by the contact layer 8 . That is, the contact layer 8 has an ellipse shape, when viewed from the top, to surround the collector region 4 .
- the contact layer 8 has a pair of straight-shaped portions and a pair of arch-shaped portions.
- the straight-shaped portions of the contact layer 8 extend in the longitudinal direction of the collector region 4 .
- One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion.
- the well layer 6 , the emitter region 7 , and the contact layer 8 of the lateral IGBT is surrounded by a trench isolation structure 9 .
- the trench isolation structure 9 has a trench filled with polysilicon and an electrically insulating film.
- the lateral IGBTs are electrically isolated from each other by the trench isolation structure 9 .
- one lateral IGBT is surrounded by each trench isolation structure 9 .
- two or more lateral IGBTs can be surrounded by each trench isolation structure 9 .
- a gate insulating layer 10 is formed on the surface of the SOI substrate 1 and in contact with the surface of the well layer 6 .
- a gate electrode 11 is located on the well layer 6 through the gate insulating layer 10 .
- the gate electrode 11 can be made of doped polysilicon. The surface portion of the well layer 6 becomes the channel region, when a predetermined gate voltage is applied to the gate electrode 11 .
- a collector electrode 12 is formed on a surface of the collector region 4 and electrically connected to the collector region 4 . Further, an emitter electrode 13 is formed on surfaces of the emitter region 7 and the contact layer 8 and electrically connected to the emitter region 7 and the contact layer 8 . As shown in FIG. 1 , the collector is surrounded by the well layer 6 , the emitter region 7 , and the contact layer 8 . Accordingly, the collector electrode 12 is surrounded by the emitter electrode 13 .
- the lateral IGBT has a hole stopper region 14 .
- the hole stopper region 14 is located in the drift layer 2 between the collector and the emitter. Specifically, the hole stopper region 14 is located between the collector region 4 and the emitter region 7 .
- the hole stopper region 14 blocks the flow of the holes to narrow a hole path through which the holes move toward the emitter region 7 .
- the hole stopper region 14 concentrates the holes in the hole path shown in FIG. 2B .
- the hole stopper region 14 increases the hole density in the hole path, where the hole stopper region 14 is not formed.
- the hole stopper region 14 extends in a thickness direction of the SOI substrate 1 . According to the first embodiment, the hole stopper region 14 extends from the surface of the drift layer 2 to the BOX layer 1 b . That is, the hole stopper region 14 penetrates the drift layer 2 .
- the hole stopper region 14 can have the same structure as the trench isolation structure 9 , which has a trench filled with polysilicon and electrically insulating film. In such an approach, the trench isolation structure 9 and the hole stopper region 14 can be simultaneously formed in the same manufacturing process.
- the collector region 4 is surrounded by the hole stopper region 14 .
- the hole stopper region 14 has an ellipse shape, when viewed from the top, to surround the collector region 4 .
- the hole stopper region 14 has a pair of straight-shaped portions and a pair of arc-shaped portions. The straight-shaped portions of the hole stopper region 14 extend in the longitudinal direction of the collector region 4 .
- the arc-shaped portions of the hole stopper region 14 surround ends of the collector region 4 in the longitudinal direction of the collector region 4 . It is noted that each of the straight-shaped portion and the arc-shaped portion of the hole stopper region 14 is divided into multiple parts. That is, the hole stopper region 14 is entirely divided into multiple parts.
- the hole path is defined between adjacent divided parts of the hole stopper region 14 . Therefore, not only a region where a current flows but also a region where a current does not flow is formed between the collector and the emitter. As a result, the area serving as a channel is reduced.
- a separation distance between adjacent divided parts of the hole stopper region 14 is not limited to a specific value, and a length of each divided part of the hole stopper region 14 is not limited to a specific value. To achieve an uniform current density in the longitudinal direction of the collector region 4 , it is preferable that adjacent divided parts of the hole stopper region 14 are equally separated from each other. According to the first embodiment, the hole stopper region 14 is located as near as possible to the emitter for reasons described later.
- An interlayer dielectric film 15 is formed on the LOCOS layer 3 .
- a scroll-shaped field plate (SRFP) 16 is formed in the interlayer dielectric film 15 between the collector and the gate.
- the SRFP 16 is a resistor layer of doped polysilicon.
- the SRFP 16 serves to maintain a uniform potential gradient between the collector and the gate. Specifically, as shown in FIG. 1 , the SRFP 16 is wound in a scroll (i.e., spiral) shape around the collector electrode 12 .
- a first end portion of the SRFP 16 is electrically connected to the collector electrode 12
- a second end portion of the SRFP 16 is electrically connected to the gate electrode 11 .
- the potential of the SRFP 16 gradually decreases with the distance from the collector electrode 12 due to a voltage drop caused by an internal resistance of the SRFP 16 . That is, the potential of the SRFP 16 gradually decreases in a direction from the first end portion of the SRFP 16 to the second end portion of the SRFP 16 . In other words, the potential of the SRFP 16 gradually decreases in a direction from the collector electrode 12 to the emitter electrode 13 .
- the potential gradient in the SRFP 16 can be maintained uniform. Accordingly, the potential gradient in the drift layer 2 , which is located below the SRFP 16 across the LOCOS layer 3 and the interlayer dielectric film 15 , can be maintained uniform.
- the second electrode of the SRFP 16 can be electrically connected to the emitter electrode 13 instead of the gate electrode 11 .
- the gate voltage is applied to the gate electrode 11 , the channel region appears in the surface portion of the well layer 6 , which is located below the gate electrode 11 between the emitter region 7 and the drift layer 2 . Then, electrons are injected from the emitter electrode 13 and the emitter region 7 into the drift layer 2 through the channel region. Accordingly, holes are injected from the collector electrode 12 and the collector region 4 into the drift layer 2 . Thus, conductivity modulation occurs in the drift layer 2 so that a large current can flow between the emitter and the collector.
- the hole stopper region 14 is formed in the drift layer 2 between the collector region 4 and the emitter region 7 .
- the hole stopper region 14 blocks the flow of the holes so that the hole path can be narrowed.
- the holes are concentrated in the hole path between adjacent divided parts of the hole stopper region 14 so that the hole density can be increased in the hole path.
- FIG. 3 shows a hole density distribution in the cross section taken along the line IIA-IIA in FIG. 1 .
- a solid line represents the hole density distribution when the hole stopper region 14 is not formed
- a broken line represents the hole density distribution when the hole stopper region 14 is formed. That is, the broken line in FIG.
- FIG. 3 represents the hole density distribution in the lateral IGBT according to the first embodiment.
- the hole density drops significantly near the emitter (denoted as “E” in FIG. 3 ).
- the drop of the hole density near the emitter can be much reduced. It is noted that the amount of injected electrons depends on the hole density near the emitter. Therefore, as the hole density becomes higher near the emitter, the amount of injected electrons becomes higher. Thus, the amount of the current flowing through the hole path is increased.
- An ON-voltage of the lateral IGBT depends on an internal resistance between the emitter and the collector and also depends on the amount of the current flowing between the emitter and the collector. In particular, as the amount of the current flowing between the emitter and the collector is larger, the ON-voltage becomes smaller. According to the first embodiment, the hole path is narrowed so that the amount of the current in the hole path can be increased. Thus, the ON-voltage of the lateral IGBT can be reduced, and switching speed of the lateral IGBT can be increased.
- the hole stopper region 14 is located far away from the emitter.
- the hole path which is narrowed by the hole stopper region 14 at a position far away from the emitter, spreads near the emitter. That is, although the holes are concentrated by the hole stopper region 14 , the concentrated holes are diffused before reaching the emitter. As a result, the hole density drops near the emitter.
- the hole stopper region 14 is located as near as possible to the emitter
- the hole stopper region 14 for blocking the flows of the holes is formed in the drift layer 2 between the emitter and the collector.
- the hole path is narrowed by the hole stopper region 14 so that the holes can be concentrated in the hole path
- the hole density is increased in the hole path so that the amount of injected electrons can be increased in the hole path.
- the hole stopper region 14 is not in contact with the well layer 6 .
- the hole stopper region 14 can be in contact with the well layer 6 .
- the hole stopper region 14 is in contact with an end of the well layer 6 .
- the hole stopper region 14 is located inside the well layer 6 and in contact with the emitter region 7 . In such an approach, the amount of injected electrons are much increased so that the reduction in the ON-voltage and the increase in the switching speed of the lateral IGBT can be surely achieved.
- the divided parts of the hole stopper region 14 are equally separated from each other, and each divided part of the hole stopper region 14 has the same length.
- the divided parts of the hole stopper region 14 can be unequally separated from each other, and each divided part of the hole stopper region 14 can have a different length.
- the hole stopper region 14 can be divided into long and short parts, and the long and short parts of the hole stopper region 14 can be alternately arranged at a regular interval.
- a second embodiment of the present disclosure is described.
- a difference between the first embodiment and the second embodiment is layouts of the emitter region 7 and the hole stopper region 14 .
- FIG. 7 is a diagram illustrating a top layout view of a semiconductor device according to the second embodiment.
- the emitter region 7 is shaped like a straight line extending in the longitudinal direction of the collector region 4 . That is, the emitter region 7 has only the straight-shaped portion without the arc-shaped portion.
- the emitter region 7 is located on each side of the collector.
- the hole stopper region 14 has an ellipse shape, when viewed from the top, to surround the collector. That is, the hole stopper region 14 has both the straight-shaped portion and the arc-shaped portion. The straight-shaped portion of the hole stopper region 14 is divided into multiple sections. Unlike the first embodiment, the arc-shaped portion of the hole stopper region 14 is not divided. In other words, the arc-shaped portion of the hole stopper region 14 is continuous.
- the emitter region 7 does not have the arc-shaped portion so that the end of the collector cannot be surrounded by the emitter region 7 . Further, the arc-shaped portion of the hole stopper region 14 is not divided so that the end of the collector can be entirely surrounded by the hole stopper region 14 . Thus, it is possible to prevent the hole path from radiating from the ends of the collector.
- the emitter region 7 does not have the arc-shaped portion.
- the emitter region 7 can have both the straight-shaped portion and the arc-shaped portion while the arc-shaped portion of the hole stopper region 14 is continuous (i.e., not divided). Even in such a layout as shown in FIG. 8 , the same effect as discussed above for the second embodiment can be achieved.
- a third embodiment of the present disclosure is described below with reference to FIGS. 9 and 10 .
- a difference between the first embodiment and the third embodiment is a structure of the hole stopper region 14 .
- FIG. 9 is a diagram illustrating a top layout view of a semiconductor device according to the third embodiment
- FIG. 10 is a diagram illustrating a cross-sectional view taken along the line X-X in FIG. 9 .
- the hole stopper region 14 extends from the surface of the active layer is (i.e., the drift layer 2 ) to a predetermined depth of the drift layer 2 . That is, the hole stopper region 14 does not penetrate the drift layer 2 . In other words, the hope stopper region 14 does not reach the BOX layer 1 b .
- the hole stopper region 14 has a continuous ellipse shape, when viewed from the top, to surround the collector. That is, each of the straight-shaped portion and the arc-shaped portion of the hole stopper region 14 is continuous (i.e., not divided into multiple parts).
- the hole stopper region 14 extends from the surface of the drift layer 2 to a predetermined depth of the drift layer 2 . That is, the hole stopper region 14 is located on only the surface side of the drift layer 2 . Alternatively, the hole stopper region 14 can extend from a predetermined depth of the drift layer 2 toward the bottom of the drift layer 2 so that the flow of the holes can be concentrated near the channel region, which appears in the surface portion of the well layer 6 .
- the hole stopper region 14 is formed in the active layer is before the active layer 1 c is bonded to the supporting substrate 1 a through the BOX layer 1 b.
- each of the emitter region 7 and the hole stopper region 14 has an ellipse shape to entirely surround the collector.
- the emitter region 7 and the hole stopper region 14 can have the shape as discussed in the first and second embodiments (including their modifications).
- a fourth embodiment of the present disclosure is described below with reference to FIGS. 11A and 11B .
- a difference between the first embodiment and the fourth embodiment is a structure of the emitter region 7 .
- FIG. 11A is a diagram illustrating a top layout view of a semiconductor device according to the fourth embodiment
- FIG. 11B is a diagram illustrating an enlarged view of an area XIB in FIG. 11A
- the emitter region 7 is divided according to the layout of the hole stopper region 14 . Specifically, each divided part of the emitter region 7 is located between adjacent divided parts of the hole stopper region 14 in a direction from the collector to the emitter. That is, the emitter region 7 does not overlap the hole stopper region 14 in the direction from the collector to the emitter.
- the hole stopper region 14 narrows the hole path and concentrates the flows of the holes. Further, since the emitter region 7 is located at a position corresponding to the hole path narrowed by the hole stopper region 14 , a current capability can be improved.
- the structure of the fourth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- the emitter region 7 is divided according to the layout of the hole stopper region 14 in such a manner that the emitter region 7 does not overlap the hole stopper region 14 in the direction from the collector to the emitter.
- the emitter region 7 can be divided as shown in FIGS. 12A and 12B .
- FIG. 12A is a diagram illustrating a top layout view of a semiconductor device according to a modification of the fourth embodiment
- FIG. 12B is a diagram illustrating an enlarged view of an area XIIB in FIG. 12A .
- the emitter region 7 can be divided in the same manner as the hole stopper region 14 so that the emitter region 7 can overlap the hole stopper region 14 in the direction from the collector to the emitter.
- a fifth embodiment of the present disclosure is described below with reference to FIGS. 13A and 13B .
- a difference between the first embodiment and the fifth embodiment is a structure of the lateral IGBT.
- FIG. 13A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the fifth embodiment.
- FIG. 13B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the fifth embodiment.
- a top layout view of the semiconductor device according to the fifth embodiment is the same as that of the semiconductor device according to the first embodiment and shown in FIG. 1 .
- the lateral IGBT has a trench gate structure instead of a planar gate structure.
- a trench 17 is formed in the surface portion of the drift layer 2
- the gate electrode 11 is formed in the trench 17 through the gate insulating layer 10 .
- a side wall of the trench 17 is in contact with the well layer 6 and the emitter region 7 .
- the channel region appears in a side portion of the well layer 6 so that the lateral IGBT can act.
- the side portion of the well layer 6 is in contact which the side wall of the trench 17 and located between the emitter region 7 and the drift layer 2 .
- the lateral IGBT has a trench gate structure, and the hole stopper region 14 is formed in the drift layer 2 as shown FIG. 13A .
- the same effect as discussed for the first embodiment can be achieved.
- the structure of the fifth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- the hole stopper region 14 extends from the surface of the drift layer 2 to the BOX layer 1 b by penetrating the drift layer 2 .
- the hole stopper region 14 can extend from the surface of the drift layer 2 to a predetermined depth of the drift layer 2 without reaching the BOX layer 1 b .
- the hole stopper region 14 can have the same structure as the trench gate structure. That is, the hole stopper region 14 can be formed by filling a trench with electrically insulating film and polysilicon. In such an approach, the trench gate structure and the hole stopper region 14 can be simultaneously formed in the same manufacturing process. Thus, an addition process for forming the hole stopper region 14 is unnecessary.
- the trench isolation structure 9 is formed in the active layer 1 c (i.e., the drift layer 2 ) of the SOI substrate 1 by forming a trench, by oxidizing an inner wall of the trench, and by depositing polysilicon in the trench. Then, not only the trench 17 for the trench gate structure but also a trench 40 for the hole stopper region 14 are formed in the drift layer 2 . Then, an oxidation process is performed so that the gate insulating layer 10 can be formed on the inner wall of the trench 17 and that an electrically insulating layer 41 can be formed on an inner wall of the trench 40 .
- the hole stopper region 14 having the same structure as the trench gate structure can be formed.
- processes, such as LOCOS oxidation and ion implantation, necessary for manufacturing the lateral IGBT are performed in the same manner as described in the preceding embodiments.
- the lateral IGBT including the hole stopper region 14 having the same structure as the trench gate structure can be manufactured.
- a sixth embodiment of the present disclosure is described below with reference to FIG. 16 , FIGS. 17A and 17B , and FIGS. 18A and 18B .
- a difference between the first embodiment and the sixth embodiment is a method of forming the hole stopper region 14 .
- the hole stopper region 14 and the trench isolation structure 9 are simultaneously formed.
- FIG. 16 is a diagram illustrating a top layout view of a semiconductor device according to the sixth embodiment.
- FIGS. 17A and 17B are diagrams illustrating manufacturing processes of the semiconductor device of FIG. 16 taken along the line XVIIA,B-XVIIA,B in FIG. 16 .
- FIGS. 18A and 18B are diagrams illustrating manufacturing processes of the semiconductor device of FIG. 16 taken along the line XVIIIA,B-XVIIIA,B in FIG. 16 .
- each lateral IGBT is surrounded by the trench isolation structure 9 .
- the lateral IGBTs are isolated from each other by the trench isolation structure 9 .
- the semiconductor device shown in FIG. 16 is manufactured as follows. Firstly, as shown in FIGS. 17A and 18A , after the SOI substrate 1 is prepared, the trench isolation structure 9 and the hole stopper region 14 simultaneously formed in the active layer is (i.e., the drift layer 2 ) of the SOI substrate 1 by forming a trench, by oxidizing an inner wall of the trench, and by depositing polysilicon in the trench.
- the lateral IGBT including the hole stopper region 14 having the same structure as the trench isolation structure 9 can be manufactured.
- the trench isolation structure 9 and the hole stopper region 14 simultaneously formed in the same manufacturing processes. In such an approach, an addition process for forming the hole stopper region 14 is unnecessary.
- a seventh embodiment of the present disclosure is described below with reference to FIGS. 19A and 19B .
- a difference between the first embodiment and the seventh embodiment is that the SOI substrate 1 is not used.
- FIG. 19A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the seventh embodiment.
- FIG. 19B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the seventh embodiment.
- a top layout view of the semiconductor device according to the seventh embodiment is the same as that of the semiconductor device according to the first embodiment and shown in FIG. 1 .
- the lateral IGBT is formed by using a semiconductor substrate 20 instead of the SOI substrate 1 .
- the semiconductor substrate 20 includes a p ⁇ -type silicon substrate 21 and a n ⁇ -type layer 22 formed on the silicon substrate 21 .
- the n ⁇ -type layer 22 serves as the drift layer 2 .
- the lateral IGBT is surrounded by a deep trench isolation structure 9 .
- the deep trench isolation structure 9 extends from the surface of the n ⁇ -type layer 22 to the silicon substrate 21 by penetrating the n ⁇ -type layer 22 .
- the deep trench isolation structure 9 has a trench filled with polysilicon and an electrically insulating film.
- the lateral IGBT are electrically isolated from each other by the deep trench isolation structure 9 .
- the lateral IGBT has the hole stopper region 14 .
- the hole stopper region 14 can have the same structure as the deep trench isolation structure 9 . That is, the hole stopper region 14 can be formed by filling a trench with electrically insulating film and polysilicon. In such an approach, the deep trench isolation structure 9 and the hole stopper region 14 can be simultaneously formed in the same manufacturing process. Thus, an addition process for forming the hole stopper region 14 is unnecessary.
- the structure of the seventh embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- FIGS. 20A and 20B An eighth embodiment of the present disclosure is described below with reference to FIGS. 20A and 20B . A difference between the first embodiment and the eighth embodiment is that the SOI substrate 1 is not used.
- FIG. 20A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the eighth embodiment.
- FIG. 20B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the eight embodiment.
- a top layout view of the semiconductor device according to the eighth embodiment is the same as that of the semiconductor device according to the first embodiment and shown in FIG. 1 .
- the lateral IGBT is formed by using a semiconductor substrate 30 instead of the SOI substrate 1 .
- the semiconductor substrate 30 includes a p ⁇ -type silicon substrate 31 and a n ⁇ -type layer 32 formed on the silicon substrate 31 .
- the n ⁇ -type layer 32 serves as the drift layer 2 .
- the lateral IGBT is surrounded by a p ⁇ -type isolation region 33 .
- the p ⁇ -type isolation region 33 extends from the surface of the n ⁇ -type layer 32 to the silicon substrate 31 by penetrating the n ⁇ -type layer 32 .
- the p ⁇ -type isolation region 33 and the n ⁇ -type layer 32 form a PN junction isolation structure.
- the p ⁇ -type isolation region 33 is electrically connected to the emitter electrode 13 so that the p ⁇ -type silicon substrate 31 and the p ⁇ -type isolation region 33 can be clamped to the emitter potential.
- the lateral IGBT are electrically isolated from each other by the PN junction isolation structure.
- the structure of the eighth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- a ninth embodiment of the present disclosure is described below with reference to FIGS. 21A and 21B .
- a difference between the first embodiment and the ninth embodiment is a contact structure between the collector electrode 12 and the collector region 4 .
- FIG. 21A is a diagram, corresponding to FIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the ninth embodiment.
- FIG. 21B is a diagram, corresponding to FIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the ninth embodiment.
- a top layout view of the semiconductor device according to the ninth embodiment is the same as that of the semiconductor device according to the first embodiment and shown in FIG. 1 .
- the collector region 4 includes a p + -type layer 4 a and a p-type layer 4 b .
- An impurity concentration of the p + -type layer 4 a is greater than an impurity concentration of the p-type layer 4 b .
- the p + -type layer 4 a is surrounded by the p-type layer 4 b .
- the collector electrode 12 is electrically connected to each of the p + -type layer 4 a and the p-type layer 4 b .
- the collector electrode 12 forms an Ohmic contact with the p + -type layer 4 a and forms a Schottky contact with the p-type layer 4 b through a barrier metal 12 a . Since the p + -type layer 4 a is surrounded by the p-type layer 4 b , the p-type layer 4 b is located closer to the emitter than the p + -type layer 4 a.
- the hole stopper region 14 can increase the hole density near the emitter region 7 .
- the holes flow into the emitter at the time of turn-OFF of the lateral IGBT, it may be likely that a parasitic bipolar transistor, affecting the breakdown voltage, is turned ON.
- the collector electrode 12 forms a Schottky contact with the p-type layer 4 b .
- the Schottky contact reduces the holes injected from the collector so that the amount of accumulated carriers can be reduced. Thus, it is less likely that the parasitic bipolar transistor is turned ON. Therefore, the breakdown voltage can be maintained while achieving the low ON-voltage and the fast switching.
- the structure of the ninth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- the present disclosure can be applied to a p-channel lateral IGBT by interchanging the conductivity types in the embodiments.
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Abstract
Description
- This application is based on Japanese Patent Application No. 2011-288244 filed on Dec. 28, 2011 and No. 2012-204594 filed on Sep. 18, 2012, the contents of which are incorporated herein by reference.
- The present disclosure relates generally to semiconductor devices having an insulated gate bipolar transistor (IGBT), and relates in particular to a semiconductor device having a lateral IGBT formed by using a silicon-on-insulator (SOI) substrate.
- When an IGBT is turned ON, an electric current flows based on a hole current and an electron current. The hole current flows based on holes injected from a collector. The electron current flows based on electrons injected from an emitter. To achieve a low ON-voltage, there is a need to increase the amount of holes and electrons. The low ON-voltage can be achieved by increasing the amount of holes injected form the collector. However, when the amount of the injected holes is large, a tail current occurs due to the holes during switching so that fast switching cannot be achieved. Therefore, to achieve a low ON-voltage and a fast switching, it is very important to increase the amount of the electron current when the IGBT is turned ON. In an IGBT, the amount of injected electrons depends on the density of holes near an emitter. Therefore, to achieve a low ON-voltage and a fast switching, it is important to increase the density of holes near the emitter without excessively increasing the amount of holes injected from the collector.
- However, in an IGBT, the density of holes decreases with the distance to the emitter due to diffusion and recombination. As a result, the amount of injected electrons decreases.
- The present inventors consider that the above disadvantage can be overcome by forming a thin n-type layer, called the carrier storage (CS) layer, in an emitter layer. Further, a non-patent document 1 (M. Takei et al. Proc. ISPSD'10, pp. 383-386, June 2010) discloses that an oxide layer is formed in a drift layer of a vertical IGBT to narrow a hole path so that conductivity modulation can be increased.
- However, the CS layer may degrade a breakdown voltage and increase a manufacturing cost. Further, the
non-patent document 1 discloses a structure for increasing the conductivity modulation in a vertical IGBT only. In other words, thenon-patent document 1 is silent on a lateral IGBT. - In view of the above, it is an object of the present disclosure to provide a semiconductor device having a lateral IGBT for achieving a low ON-voltage and a fast switching.
- According to an aspect of the present disclosure, a semiconductor device having a lateral insulated gate bipolar transistor includes a semiconductor substrate having a first conductivity type drift layer. A second conductivity type collector region is formed in a surface portion of the drift layer. A second conductivity type channel layer is formed in the surface portion of the drift layer and has a straight-shaped portion on each side of the collector region. A first conductivity type emitter region is formed in a surface portion of the channel layer and terminated inside the channel layer. The emitter region has a straight-shaped portion extending parallel to a longitudinal direction of the collector region. A gate insulation layer is in contact with a channel region of the channel layer. The channel region is located between the emitter region and the drift layer. A gate electrode is formed on a surface of the gate insulation layer. A collector electrode is electrically connected to the collector region. An emitter electrode is electrically connected to the emitter region and the channel layer. A hole stopper region is formed in the drift layer and located between the collector region and the emitter region. Holes are injected from the collector region into the drift layer and flow toward the emitter region through a hole path. The hole stopper region blocks a flow of the holes and narrows the hole path to concentrate the holes.
- The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
-
FIG. 1 is a diagram illustrating a top layout view of a semiconductor device according to a first embodiment of the present disclosure; -
FIG. 2A is a diagram illustrating a cross-sectional view taken along line IIA-IIA inFIG. 1 , andFIG. 2B is a diagram illustrating a cross-sectional view taken along line IIB-IIB inFIG. 1 ; -
FIG. 3 is a diagram illustrating a hole density distribution in the semiconductor device along the line IIA-IIA inFIG. 1 ; -
FIG. 4 is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a first modification of the first embodiment; -
FIG. 5 is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a second modification of the first embodiment; -
FIG. 6A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a third modification of the first embodiment, andFIG. 6B is a diagram and illustrating an enlarged view of an area VIB inFIG. 6A ; -
FIG. 7 is a diagram illustrating a top layout view of a semiconductor device according to a second embodiment of the present disclosure; -
FIG. 8 is a diagram illustrating a top layout view of a semiconductor device according to a modification of the second embodiment; -
FIG. 9 is a diagram illustrating a top layout view of a semiconductor device according to a third embodiment of the present disclosure; -
FIG. 10 is a diagram illustrating a cross-sectional view taken along line X-X inFIG. 9 ; -
FIG. 11A is a diagram illustrating a top layout view of a semiconductor device according to a fourth embodiment of the present disclosure, andFIG. 11B is a diagram illustrating an enlarged view of an area XIB inFIG. 11A ; -
FIG. 12A is a diagram illustrating a top layout view of a semiconductor device according to a modification of the fourth embodiment, andFIG. 12B is a diagram illustrating an enlarged view of an area XIIB inFIG. 12A ; -
FIG. 13A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure, andFIG. 13B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the fifth embodiment; -
FIG. 14 is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a modification of the fifth embodiment; -
FIGS. 15A and 15B are diagrams illustrating manufacturing processes of the semiconductor device ofFIG. 14 ; -
FIG. 16 is a diagram illustrating a top layout view of a semiconductor device according to a sixth embodiment of the present disclosure; -
FIGS. 17A and 17B are diagrams illustrating manufacturing processes of the semiconductor device ofFIG. 16 taken along line XVIIA,B-XVIIA,B inFIG. 16 ; -
FIGS. 18A and 18B are diagrams illustrating manufacturing processes of the semiconductor device ofFIG. 16 taken along line XVIIIA,B-XVIIIA,B inFIG. 16 ; -
FIG. 19A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a seventh embodiment of the present disclosure, andFIG. 19B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the seventh embodiment; -
FIG. 20A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to an eighth embodiment of the present disclosure, andFIG. 20B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the eighth embodiment; and -
FIG. 21A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to a ninth embodiment of the present disclosure, andFIG. 21B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the ninth embodiment. - A semiconductor device according to a first embodiment of the present disclosure is described below. The semiconductor device has a lateral insulated gate bipolar transistor (IGBT) with a planar gate structure.
FIG. 1 is a diagram illustrating a top layout view of the semiconductor device.FIG. 2A is a diagram illustrating a cross-sectional view taken along the line IIA-IIA inFIG. 1 .FIG. 2B is a diagram illustrating a cross-sectional view taken along the line IIB-IIB inFIG. 1 . - As shown in
FIGS. 2A and 2B , according to the first embodiment, the lateral IGBT is formed by using aSOI substrate 1. TheSOI substrate 1 includes a supportingsubstrate 1 a, a buried oxide layer (BOX) 1 b on the supportingsubstrate 1 a, and an active layer is on the BOX layer 1 b. The supportingsubstrate 1 a and theactive layer 1 c are made of silicon. The BOX layer 1 b serves as an electrical insulation layer. Theactive layer 1 c serves as a n−-type drift layer 2. Components of the lateral IGBT are formed in a surface portion of thedrift layer 2. - The thickness of the BOX layer 1 b is not limited to a specific value. The thickness and the impurity concentration of the
active layer 1 c (i.e., drift layer 2) are not limited to specific values. The thickness of the BOX layer 1 b and the thickness and the impurity concentration of theactive layer 1 c are set so that the lateral IGBT can have a predetermined breakdown voltage. For example, the thickness of the BOX later 1 b can be 4 μm or more. To obtain a stable breakdown voltage of 600 volts or more, it is preferable to set the values as follows: The thickness of the BOX layer 1 b is 5 μm or more. The n-type impurity concentration of theactive layer 1 c ranges from 1×1014 cm−3 to 1.2×1015 cm−3, if the thickness of theactive layer 1 c is 15 μm or less. The n-type impurity concentration of the active layer is ranges from 1×1014 cm−3 to 8×1014 cm−3, if the thickness of theactive layer 1 c is 20 μm. - A
LOCOS layer 3 is formed on a surface of thedrift layer 2 to isolate the components of the lateral IGBT from each other. A p+-type collector region 4 is formed in the surface portion of thedrift layer 2 and exposed outside theLOCOS layer 3. Thecollector region 4 has a longitudinal direction parallel to the surface of thedrift layer 2. Thecollector region 4 is surrounded by a n-type buffer layer 5. Thebuffer layer 5 has an impurity concentration greater than that of thedrift layer 2. - Further, a p-
channel well layer 6, a n+-type emitter region 7, and a p+-type contact layer 8 are formed in the surface portion of thedrift layer 2 around thecollector region 4 and exposed outside theLOCOS layer 3. - A surface portion of the
well layer 6 serves a channel region. For example, the thickness of thewell layer 6 can be 2 μm or less, and the width of thewell layer 6 can be 6 μm or less. As shown inFIG. 1 , thewell layer 6 is arranged concentrically with respect to thecollector region 4 so that thecollector region 4 can be entirely surrounded by thewell layer 6. That is, thewell layer 6 has an ellipse shape, when viewed from the top, to surround thecollector region 4. Specifically, thewell layer 6 has a pair of straight-shaped portions and a pair of arc-shaped portions. The straight-shaped portions extend in the longitudinal direction of thecollector region 4. One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion. - The
well layer 6 has a body layer which is located below and around thecontact layer 8. A p-type impurity concentration of the body layer is so high that the body layer can reduce a voltage drop which is caused by a Hall current flowing from a collector to an emitter through the surface. The body layer reduces or prevents operation of a parasitic npn transistor which is constructed with theemitter region 7, thewell layer 6, and thedrift layer 2. Thus, a turn-off time of the lateral IGBT can be improved. - The
emitter region 7 is formed in a surface portion of thewell layer 6 and terminated inside thewell layer 6. Like thewell layer 6, theemitter region 7 has an ellipse shape, when viewed from the top, to surround thecollector region 4. Specifically, theemitter region 7 has a pair of straight-shaped portions and a pair of arch-shaped portions. The straight-shaped portions of theemitter region 7 extend in the longitudinal direction of thecollector region 4. One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion. - The
contact layer 8 is used to clamp thewell layer 6 to an emitter potential. Thecontact layer 8 has an impurity concentration greater than that of thewell layer 6. As shown inFIG. 1 , thecontact layer 8 is arranged concentrically with respect to thecollector region 4 so that thecollector region 4 can be entirely surrounded by thecontact layer 8. That is, thecontact layer 8 has an ellipse shape, when viewed from the top, to surround thecollector region 4. - Specifically, the
contact layer 8 has a pair of straight-shaped portions and a pair of arch-shaped portions. The straight-shaped portions of thecontact layer 8 extend in the longitudinal direction of thecollector region 4. One arch-shaped portion connects one end of one straight-shaped portion to one end of the other straight-shaped portion, and the other arch-shaped portion connects the other end of one straight-shaped portion to the other end of the other straight-shaped portion. - As shown in
FIG. 1 , thewell layer 6, theemitter region 7, and thecontact layer 8 of the lateral IGBT is surrounded by atrench isolation structure 9. Thetrench isolation structure 9 has a trench filled with polysilicon and an electrically insulating film. Thus, the lateral IGBTs are electrically isolated from each other by thetrench isolation structure 9. According to the first embodiment, one lateral IGBT is surrounded by eachtrench isolation structure 9. Alternatively, two or more lateral IGBTs can be surrounded by eachtrench isolation structure 9. - A
gate insulating layer 10 is formed on the surface of theSOI substrate 1 and in contact with the surface of thewell layer 6. Agate electrode 11 is located on thewell layer 6 through thegate insulating layer 10. For example, thegate electrode 11 can be made of doped polysilicon. The surface portion of thewell layer 6 becomes the channel region, when a predetermined gate voltage is applied to thegate electrode 11. - A
collector electrode 12 is formed on a surface of thecollector region 4 and electrically connected to thecollector region 4. Further, anemitter electrode 13 is formed on surfaces of theemitter region 7 and thecontact layer 8 and electrically connected to theemitter region 7 and thecontact layer 8. As shown inFIG. 1 , the collector is surrounded by thewell layer 6, theemitter region 7, and thecontact layer 8. Accordingly, thecollector electrode 12 is surrounded by theemitter electrode 13. - As shown in
FIG. 2A , the lateral IGBT has ahole stopper region 14. Thehole stopper region 14 is located in thedrift layer 2 between the collector and the emitter. Specifically, thehole stopper region 14 is located between thecollector region 4 and theemitter region 7. - When holes injected from the
collector region 4 moves from the collector to the emitter, thehole stopper region 14 blocks the flow of the holes to narrow a hole path through which the holes move toward theemitter region 7. Thus, thehole stopper region 14 concentrates the holes in the hole path shown inFIG. 2B . In this way, thehole stopper region 14 increases the hole density in the hole path, where thehole stopper region 14 is not formed. Thehole stopper region 14 extends in a thickness direction of theSOI substrate 1. According to the first embodiment, thehole stopper region 14 extends from the surface of thedrift layer 2 to the BOX layer 1 b. That is, thehole stopper region 14 penetrates thedrift layer 2. - For example, the
hole stopper region 14 can have the same structure as thetrench isolation structure 9, which has a trench filled with polysilicon and electrically insulating film. In such an approach, thetrench isolation structure 9 and thehole stopper region 14 can be simultaneously formed in the same manufacturing process. According to the first embodiment, as shown inFIG. 1 , thecollector region 4 is surrounded by thehole stopper region 14. Thehole stopper region 14 has an ellipse shape, when viewed from the top, to surround thecollector region 4. Specifically, thehole stopper region 14 has a pair of straight-shaped portions and a pair of arc-shaped portions. The straight-shaped portions of thehole stopper region 14 extend in the longitudinal direction of thecollector region 4. The arc-shaped portions of thehole stopper region 14 surround ends of thecollector region 4 in the longitudinal direction of thecollector region 4. It is noted that each of the straight-shaped portion and the arc-shaped portion of thehole stopper region 14 is divided into multiple parts. That is, thehole stopper region 14 is entirely divided into multiple parts. The hole path is defined between adjacent divided parts of thehole stopper region 14. Therefore, not only a region where a current flows but also a region where a current does not flow is formed between the collector and the emitter. As a result, the area serving as a channel is reduced. - A separation distance between adjacent divided parts of the
hole stopper region 14 is not limited to a specific value, and a length of each divided part of thehole stopper region 14 is not limited to a specific value. To achieve an uniform current density in the longitudinal direction of thecollector region 4, it is preferable that adjacent divided parts of thehole stopper region 14 are equally separated from each other. According to the first embodiment, thehole stopper region 14 is located as near as possible to the emitter for reasons described later. - An
interlayer dielectric film 15 is formed on theLOCOS layer 3. A scroll-shaped field plate (SRFP) 16 is formed in theinterlayer dielectric film 15 between the collector and the gate. TheSRFP 16 is a resistor layer of doped polysilicon. TheSRFP 16 serves to maintain a uniform potential gradient between the collector and the gate. Specifically, as shown inFIG. 1 , theSRFP 16 is wound in a scroll (i.e., spiral) shape around thecollector electrode 12. A first end portion of theSRFP 16 is electrically connected to thecollector electrode 12, and a second end portion of theSRFP 16 is electrically connected to thegate electrode 11. The potential of theSRFP 16 gradually decreases with the distance from thecollector electrode 12 due to a voltage drop caused by an internal resistance of theSRFP 16. That is, the potential of theSRFP 16 gradually decreases in a direction from the first end portion of theSRFP 16 to the second end portion of theSRFP 16. In other words, the potential of theSRFP 16 gradually decreases in a direction from thecollector electrode 12 to theemitter electrode 13. Thus, the potential gradient in theSRFP 16 can be maintained uniform. Accordingly, the potential gradient in thedrift layer 2, which is located below theSRFP 16 across theLOCOS layer 3 and theinterlayer dielectric film 15, can be maintained uniform. Thus, electric field concentration resulting from non-uniform potential gradient is reduced so that the breakdown voltage can be improved. Further, impact ionization is reduced so that an increase in turn-off switching time can be reduced. The second electrode of theSRFP 16 can be electrically connected to theemitter electrode 13 instead of thegate electrode 11. - Next, an operation of the lateral IGBT is described. When the gate voltage is applied to the
gate electrode 11, the channel region appears in the surface portion of thewell layer 6, which is located below thegate electrode 11 between theemitter region 7 and thedrift layer 2. Then, electrons are injected from theemitter electrode 13 and theemitter region 7 into thedrift layer 2 through the channel region. Accordingly, holes are injected from thecollector electrode 12 and thecollector region 4 into thedrift layer 2. Thus, conductivity modulation occurs in thedrift layer 2 so that a large current can flow between the emitter and the collector. - As described above, according to the first embodiment, the
hole stopper region 14 is formed in thedrift layer 2 between thecollector region 4 and theemitter region 7. Thehole stopper region 14 blocks the flow of the holes so that the hole path can be narrowed. Thus, the holes are concentrated in the hole path between adjacent divided parts of thehole stopper region 14 so that the hole density can be increased in the hole path.FIG. 3 shows a hole density distribution in the cross section taken along the line IIA-IIA inFIG. 1 . InFIG. 3 , a solid line represents the hole density distribution when thehole stopper region 14 is not formed, and a broken line represents the hole density distribution when thehole stopper region 14 is formed. That is, the broken line inFIG. 3 represents the hole density distribution in the lateral IGBT according to the first embodiment. As indicated by the solid line inFIG. 3 , when thehole stopper region 14 is not formed, the hole density drops significantly near the emitter (denoted as “E” inFIG. 3 ). In contrast, as indicated by the broken line inFIG. 3 , when thehole stopper region 14 is formed, the drop of the hole density near the emitter can be much reduced. It is noted that the amount of injected electrons depends on the hole density near the emitter. Therefore, as the hole density becomes higher near the emitter, the amount of injected electrons becomes higher. Thus, the amount of the current flowing through the hole path is increased. - An ON-voltage of the lateral IGBT depends on an internal resistance between the emitter and the collector and also depends on the amount of the current flowing between the emitter and the collector. In particular, as the amount of the current flowing between the emitter and the collector is larger, the ON-voltage becomes smaller. According to the first embodiment, the hole path is narrowed so that the amount of the current in the hole path can be increased. Thus, the ON-voltage of the lateral IGBT can be reduced, and switching speed of the lateral IGBT can be increased.
- Here, it is assumed that the
hole stopper region 14 is located far away from the emitter. In this case, the hole path, which is narrowed by thehole stopper region 14 at a position far away from the emitter, spreads near the emitter. That is, although the holes are concentrated by thehole stopper region 14, the concentrated holes are diffused before reaching the emitter. As a result, the hole density drops near the emitter. To prevent this disadvantage, according to the first embodiment, as shown inFIG. 2A , thehole stopper region 14 is located as near as possible to the emitter - As described above, according to the first embodiment, the
hole stopper region 14 for blocking the flows of the holes is formed in thedrift layer 2 between the emitter and the collector. In such an approach, the hole path is narrowed by thehole stopper region 14 so that the holes can be concentrated in the hole path Thus, the hole density is increased in the hole path so that the amount of injected electrons can be increased in the hole path. Thus, both the reduction in the ON-voltage and the increase in the switching speed of the lateral IGBT can be achieved. - (Modification of the First Embodiment)
- As shown in
FIG. 2A , according to the first embodiment, thehole stopper region 14 is not in contact with thewell layer 6. Alternatively, as shown inFIGS. 4 and 5 , thehole stopper region 14 can be in contact with thewell layer 6. InFIG. 4 , thehole stopper region 14 is in contact with an end of thewell layer 6. InFIG. 5 , thehole stopper region 14 is located inside thewell layer 6 and in contact with theemitter region 7. In such an approach, the amount of injected electrons are much increased so that the reduction in the ON-voltage and the increase in the switching speed of the lateral IGBT can be surely achieved. - As shown in
FIG. 1 , according to the first embodiment, the divided parts of thehole stopper region 14 are equally separated from each other, and each divided part of thehole stopper region 14 has the same length. Alternatively, the divided parts of thehole stopper region 14 can be unequally separated from each other, and each divided part of thehole stopper region 14 can have a different length. For example, as shown inFIGS. 6A and 6B , thehole stopper region 14 can be divided into long and short parts, and the long and short parts of thehole stopper region 14 can be alternately arranged at a regular interval. - A second embodiment of the present disclosure is described. A difference between the first embodiment and the second embodiment is layouts of the
emitter region 7 and thehole stopper region 14. -
FIG. 7 is a diagram illustrating a top layout view of a semiconductor device according to the second embodiment. As shown inFIG. 7 , according to the second embodiment, theemitter region 7 is shaped like a straight line extending in the longitudinal direction of thecollector region 4. That is, theemitter region 7 has only the straight-shaped portion without the arc-shaped portion. Theemitter region 7 is located on each side of the collector. - Like the first embodiment, the
hole stopper region 14 has an ellipse shape, when viewed from the top, to surround the collector. That is, thehole stopper region 14 has both the straight-shaped portion and the arc-shaped portion. The straight-shaped portion of thehole stopper region 14 is divided into multiple sections. Unlike the first embodiment, the arc-shaped portion of thehole stopper region 14 is not divided. In other words, the arc-shaped portion of thehole stopper region 14 is continuous. - As described above, according to the second embodiment, the
emitter region 7 does not have the arc-shaped portion so that the end of the collector cannot be surrounded by theemitter region 7. Further, the arc-shaped portion of thehole stopper region 14 is not divided so that the end of the collector can be entirely surrounded by thehole stopper region 14. Thus, it is possible to prevent the hole path from radiating from the ends of the collector. - In such an approach, electric field concentration on the ends of the collector is reduced so that the breakdown voltage of the lateral IGBT can be increased and stabilized.
- (Modification of the Second Embodiment)
- In the second embodiment, the
emitter region 7 does not have the arc-shaped portion. Alternatively, as shown inFIG. 8 , theemitter region 7 can have both the straight-shaped portion and the arc-shaped portion while the arc-shaped portion of thehole stopper region 14 is continuous (i.e., not divided). Even in such a layout as shown inFIG. 8 , the same effect as discussed above for the second embodiment can be achieved. - A third embodiment of the present disclosure is described below with reference to
FIGS. 9 and 10 . A difference between the first embodiment and the third embodiment is a structure of thehole stopper region 14. -
FIG. 9 is a diagram illustrating a top layout view of a semiconductor device according to the third embodiment, andFIG. 10 is a diagram illustrating a cross-sectional view taken along the line X-X inFIG. 9 . - As shown in
FIG. 10 , according to the third embodiment, thehole stopper region 14 extends from the surface of the active layer is (i.e., the drift layer 2) to a predetermined depth of thedrift layer 2. That is, thehole stopper region 14 does not penetrate thedrift layer 2. In other words, thehope stopper region 14 does not reach the BOX layer 1 b. As shown inFIG. 9 , thehole stopper region 14 has a continuous ellipse shape, when viewed from the top, to surround the collector. That is, each of the straight-shaped portion and the arc-shaped portion of thehole stopper region 14 is continuous (i.e., not divided into multiple parts). - In such an structure as shown in
FIGS. 9 and 10 , the flow of the holes is concentrated at a position below thehole stopper region 14 so that the hole density can be increased at the position below thehole stopper region 14. Accordingly, the amount of injected electrons is increased. Thus, the same effect as discussed for the first embodiment can be achieved. - (Modification of the Third Embodiment)
- In the third embodiment, the
hole stopper region 14 extends from the surface of thedrift layer 2 to a predetermined depth of thedrift layer 2. That is, thehole stopper region 14 is located on only the surface side of thedrift layer 2. Alternatively, thehole stopper region 14 can extend from a predetermined depth of thedrift layer 2 toward the bottom of thedrift layer 2 so that the flow of the holes can be concentrated near the channel region, which appears in the surface portion of thewell layer 6. - In this case, the
hole stopper region 14 is formed in the active layer is before theactive layer 1 c is bonded to the supportingsubstrate 1 a through the BOX layer 1 b. - In the third embodiment, each of the
emitter region 7 and thehole stopper region 14 has an ellipse shape to entirely surround the collector. Alternatively, theemitter region 7 and thehole stopper region 14 can have the shape as discussed in the first and second embodiments (including their modifications). - A fourth embodiment of the present disclosure is described below with reference to
FIGS. 11A and 11B . A difference between the first embodiment and the fourth embodiment is a structure of theemitter region 7. -
FIG. 11A is a diagram illustrating a top layout view of a semiconductor device according to the fourth embodiment, andFIG. 11B is a diagram illustrating an enlarged view of an area XIB inFIG. 11A . As shown inFIGS. 11A and 11B , according to the fourth embodiment, theemitter region 7 is divided according to the layout of thehole stopper region 14. Specifically, each divided part of theemitter region 7 is located between adjacent divided parts of thehole stopper region 14 in a direction from the collector to the emitter. That is, theemitter region 7 does not overlap thehole stopper region 14 in the direction from the collector to the emitter. - In such a structure as shown in
FIGS. 11A and 11B , thehole stopper region 14 narrows the hole path and concentrates the flows of the holes. Further, since theemitter region 7 is located at a position corresponding to the hole path narrowed by thehole stopper region 14, a current capability can be improved. The structure of the fourth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications). - (Modification of the Fourth Embodiment)
- In the fourth embodiment, the
emitter region 7 is divided according to the layout of thehole stopper region 14 in such a manner that theemitter region 7 does not overlap thehole stopper region 14 in the direction from the collector to the emitter. Alternatively, for example, theemitter region 7 can be divided as shown inFIGS. 12A and 12B .FIG. 12A is a diagram illustrating a top layout view of a semiconductor device according to a modification of the fourth embodiment, andFIG. 12B is a diagram illustrating an enlarged view of an area XIIB inFIG. 12A . As shown inFIGS. 12A and 12B , theemitter region 7 can be divided in the same manner as thehole stopper region 14 so that theemitter region 7 can overlap thehole stopper region 14 in the direction from the collector to the emitter. - In such a structure as shown in
FIGS. 12A and 12B , since the hole path narrowed by thehole stopper region 14 directly faces thecontact layer 8, the holes are easily drawn to thecontact layer 8 at the time of the switching operation so that the switching speed can be improved. - A fifth embodiment of the present disclosure is described below with reference to
FIGS. 13A and 13B . A difference between the first embodiment and the fifth embodiment is a structure of the lateral IGBT. -
FIG. 13A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the fifth embodiment.FIG. 13B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the fifth embodiment. A top layout view of the semiconductor device according to the fifth embodiment is the same as that of the semiconductor device according to the first embodiment and shown inFIG. 1 . - According to the fifth embodiment, the lateral IGBT has a trench gate structure instead of a planar gate structure. Specifically, as shown in
FIGS. 13A and 13B , atrench 17 is formed in the surface portion of thedrift layer 2, and thegate electrode 11 is formed in thetrench 17 through thegate insulating layer 10. A side wall of thetrench 17 is in contact with thewell layer 6 and theemitter region 7. The channel region appears in a side portion of thewell layer 6 so that the lateral IGBT can act. The side portion of thewell layer 6 is in contact which the side wall of thetrench 17 and located between theemitter region 7 and thedrift layer 2. - As described above, according to the fifth embodiment, the lateral IGBT has a trench gate structure, and the
hole stopper region 14 is formed in thedrift layer 2 as shownFIG. 13A . Thus, the same effect as discussed for the first embodiment can be achieved. The structure of the fifth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications). - (Modification of the Fifth Embodiment)
- In the fifth embodiment, the
hole stopper region 14 extends from the surface of thedrift layer 2 to the BOX layer 1 b by penetrating thedrift layer 2. Alternatively, like the third embodiment, thehole stopper region 14 can extend from the surface of thedrift layer 2 to a predetermined depth of thedrift layer 2 without reaching the BOX layer 1 b. For example, as shown inFIG. 14 , thehole stopper region 14 can have the same structure as the trench gate structure. That is, thehole stopper region 14 can be formed by filling a trench with electrically insulating film and polysilicon. In such an approach, the trench gate structure and thehole stopper region 14 can be simultaneously formed in the same manufacturing process. Thus, an addition process for forming thehole stopper region 14 is unnecessary. - Specifically, as shown in
FIG. 15A , thetrench isolation structure 9 is formed in theactive layer 1 c (i.e., the drift layer 2) of theSOI substrate 1 by forming a trench, by oxidizing an inner wall of the trench, and by depositing polysilicon in the trench. Then, not only thetrench 17 for the trench gate structure but also atrench 40 for thehole stopper region 14 are formed in thedrift layer 2. Then, an oxidation process is performed so that thegate insulating layer 10 can be formed on the inner wall of thetrench 17 and that an electrically insulatinglayer 41 can be formed on an inner wall of thetrench 40. Then, a doped-polysilicon layer is formed over the surface of the drift layer so that thetrenches gate electrode 11 can be formed in thetrench 17 and that a polysilicon layer 42 can be formed in thetrench 40. In this way, thehole stopper region 14 having the same structure as the trench gate structure can be formed. After thehole stopper region 14 and the gate isolation structure are formed, processes, such as LOCOS oxidation and ion implantation, necessary for manufacturing the lateral IGBT are performed in the same manner as described in the preceding embodiments. Thus, as shown inFIG. 15B , the lateral IGBT including thehole stopper region 14 having the same structure as the trench gate structure can be manufactured. - A sixth embodiment of the present disclosure is described below with reference to
FIG. 16 ,FIGS. 17A and 17B , andFIGS. 18A and 18B . A difference between the first embodiment and the sixth embodiment is a method of forming thehole stopper region 14. Specifically, according to the sixth embodiment, thehole stopper region 14 and thetrench isolation structure 9 are simultaneously formed. -
FIG. 16 is a diagram illustrating a top layout view of a semiconductor device according to the sixth embodiment.FIGS. 17A and 17B are diagrams illustrating manufacturing processes of the semiconductor device ofFIG. 16 taken along the line XVIIA,B-XVIIA,B inFIG. 16 .FIGS. 18A and 18B are diagrams illustrating manufacturing processes of the semiconductor device ofFIG. 16 taken along the line XVIIIA,B-XVIIIA,B inFIG. 16 . - As shown in
FIG. 16 , each lateral IGBT is surrounded by thetrench isolation structure 9. Thus, the lateral IGBTs are isolated from each other by thetrench isolation structure 9. The semiconductor device shown inFIG. 16 is manufactured as follows. Firstly, as shown inFIGS. 17A and 18A , after theSOI substrate 1 is prepared, thetrench isolation structure 9 and thehole stopper region 14 simultaneously formed in the active layer is (i.e., the drift layer 2) of theSOI substrate 1 by forming a trench, by oxidizing an inner wall of the trench, and by depositing polysilicon in the trench. Then, processes, such as LOCOS oxidation and ion implantation, necessary for manufacturing the lateral IGBT are performed in the same manner as described in the preceding embodiments. Thus, as shown inFIGS. 17B and 18B , the lateral IGBT including thehole stopper region 14 having the same structure as thetrench isolation structure 9 can be manufactured. - As described above, according to the sixth embodiment, the
trench isolation structure 9 and thehole stopper region 14 simultaneously formed in the same manufacturing processes. In such an approach, an addition process for forming thehole stopper region 14 is unnecessary. - A seventh embodiment of the present disclosure is described below with reference to
FIGS. 19A and 19B . A difference between the first embodiment and the seventh embodiment is that theSOI substrate 1 is not used. -
FIG. 19A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the seventh embodiment.FIG. 19B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the seventh embodiment. A top layout view of the semiconductor device according to the seventh embodiment is the same as that of the semiconductor device according to the first embodiment and shown inFIG. 1 . - As shown in
FIGS. 19A and 19B , according to the seventh embodiment, the lateral IGBT is formed by using asemiconductor substrate 20 instead of theSOI substrate 1. Thesemiconductor substrate 20 includes a p−-type silicon substrate 21 and a n−-type layer 22 formed on thesilicon substrate 21. The n−-type layer 22 serves as thedrift layer 2. The lateral IGBT is surrounded by a deeptrench isolation structure 9. The deeptrench isolation structure 9 extends from the surface of the n−-type layer 22 to thesilicon substrate 21 by penetrating the n−-type layer 22. For example, the deeptrench isolation structure 9 has a trench filled with polysilicon and an electrically insulating film. Thus, the lateral IGBT are electrically isolated from each other by the deeptrench isolation structure 9. - As shown in
FIG. 19A , the lateral IGBT has thehole stopper region 14. For example, thehole stopper region 14 can have the same structure as the deeptrench isolation structure 9. That is, thehole stopper region 14 can be formed by filling a trench with electrically insulating film and polysilicon. In such an approach, the deeptrench isolation structure 9 and thehole stopper region 14 can be simultaneously formed in the same manufacturing process. Thus, an addition process for forming thehole stopper region 14 is unnecessary. - The structure of the seventh embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- An eighth embodiment of the present disclosure is described below with reference to
FIGS. 20A and 20B . A difference between the first embodiment and the eighth embodiment is that theSOI substrate 1 is not used. -
FIG. 20A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the eighth embodiment.FIG. 20B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the eight embodiment. A top layout view of the semiconductor device according to the eighth embodiment is the same as that of the semiconductor device according to the first embodiment and shown inFIG. 1 . - As shown in
FIGS. 20A and 20B , according to the eighth embodiment, the lateral IGBT is formed by using asemiconductor substrate 30 instead of theSOI substrate 1. Thesemiconductor substrate 30 includes a p−-type silicon substrate 31 and a n−-type layer 32 formed on thesilicon substrate 31. The n−-type layer 32 serves as thedrift layer 2. The lateral IGBT is surrounded by a p−-type isolation region 33. The p−-type isolation region 33 extends from the surface of the n−-type layer 32 to thesilicon substrate 31 by penetrating the n−-type layer 32. Thus, the p−-type isolation region 33 and the n−-type layer 32 form a PN junction isolation structure. Specifically, the p−-type isolation region 33 is electrically connected to theemitter electrode 13 so that the p−-type silicon substrate 31 and the p−-type isolation region 33 can be clamped to the emitter potential. Thus, the lateral IGBT are electrically isolated from each other by the PN junction isolation structure. - The structure of the eighth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- A ninth embodiment of the present disclosure is described below with reference to
FIGS. 21A and 21B . A difference between the first embodiment and the ninth embodiment is a contact structure between thecollector electrode 12 and thecollector region 4. -
FIG. 21A is a diagram, corresponding toFIG. 2A , and illustrating a cross-sectional view of a semiconductor device according to the ninth embodiment.FIG. 21B is a diagram, corresponding toFIG. 2B , and illustrating a cross-sectional view of the semiconductor device according to the ninth embodiment. A top layout view of the semiconductor device according to the ninth embodiment is the same as that of the semiconductor device according to the first embodiment and shown inFIG. 1 . - As shown in
FIGS. 21A and 21B , thecollector region 4 includes a p+-type layer 4 a and a p-type layer 4 b. An impurity concentration of the p+-type layer 4 a is greater than an impurity concentration of the p-type layer 4 b. According to the ninth embodiment, the p+-type layer 4 a is surrounded by the p-type layer 4 b. Thecollector electrode 12 is electrically connected to each of the p+-type layer 4 a and the p-type layer 4 b. Specifically, thecollector electrode 12 forms an Ohmic contact with the p+-type layer 4 a and forms a Schottky contact with the p-type layer 4 b through abarrier metal 12 a. Since the p+-type layer 4 a is surrounded by the p-type layer 4 b, the p-type layer 4 b is located closer to the emitter than the p+-type layer 4 a. - As discussed in the first embodiment, the
hole stopper region 14 can increase the hole density near theemitter region 7. However, since the holes flow into the emitter at the time of turn-OFF of the lateral IGBT, it may be likely that a parasitic bipolar transistor, affecting the breakdown voltage, is turned ON. - According to the ninth embodiment, the
collector electrode 12 forms a Schottky contact with the p-type layer 4 b. The Schottky contact reduces the holes injected from the collector so that the amount of accumulated carriers can be reduced. Thus, it is less likely that the parasitic bipolar transistor is turned ON. Therefore, the breakdown voltage can be maintained while achieving the low ON-voltage and the fast switching. - The structure of the ninth embodiment can be combined with any of the structures as discussed in the preceding embodiments (including their modifications).
- (Modifications)
- While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and constructions. The present disclosure is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure.
- For example, the present disclosure can be applied to a p-channel lateral IGBT by interchanging the conductivity types in the embodiments.
Claims (16)
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JP2012-204594 | 2012-09-18 | ||
JP2012204594A JP5729364B2 (en) | 2011-12-28 | 2012-09-18 | Semiconductor device having a horizontal insulated gate bipolar transistor |
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JP (1) | JP5729364B2 (en) |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20160315189A1 (en) * | 2015-04-24 | 2016-10-27 | Vanguard International Semiconductor Corporation | Semiconductor device and method for forming the same |
US10680072B2 (en) * | 2017-09-25 | 2020-06-09 | Renesas Electronics Coporation | Semiconductor device and manufacturing method thereof |
US11043557B2 (en) * | 2019-06-27 | 2021-06-22 | Fuji Electric Co., Ltd. | Semiconductor device |
US20210305242A1 (en) * | 2020-03-24 | 2021-09-30 | Richtek Technology Corporation | Power device including lateral insulated gate bipolar transistor (ligbt) and manufacturing method thereof |
EP3951886A1 (en) * | 2020-08-03 | 2022-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device |
US11296221B2 (en) * | 2019-05-08 | 2022-04-05 | Hyundai Mobis Co., Ltd. | Power semiconductor device |
US11393899B2 (en) | 2019-02-28 | 2022-07-19 | Yangtze Memory Technologies Co., Ltd. | High-voltage semiconductor device with increased breakdown voltage |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6479533B2 (en) * | 2015-03-31 | 2019-03-06 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
US10867891B2 (en) * | 2018-10-24 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ion through-substrate via |
CN114639737B (en) * | 2022-05-17 | 2022-08-30 | 广州粤芯半导体技术有限公司 | LDMOS device and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7880227B2 (en) * | 2005-08-26 | 2011-02-01 | Sanken Electric Co., Ltd. | Trench semiconductor device of improved voltage strength |
US7977704B2 (en) * | 2008-01-28 | 2011-07-12 | Denso Corporation | Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1209751A3 (en) | 1991-08-08 | 2002-07-31 | Kabushiki Kaisha Toshiba | Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure |
JP3367747B2 (en) * | 1993-09-17 | 2003-01-20 | 株式会社東芝 | Insulated gate type semiconductor device |
JP4130643B2 (en) * | 1991-08-08 | 2008-08-06 | 株式会社東芝 | Semiconductor element |
US5448083A (en) | 1991-08-08 | 1995-09-05 | Kabushiki Kaisha Toshiba | Insulated-gate semiconductor device |
DE69528944T2 (en) | 1994-09-16 | 2003-09-04 | Toshiba Kawasaki Kk | Semiconductor device with high breakdown voltage and with a buried MOS gate structure |
JPH0888357A (en) * | 1994-09-16 | 1996-04-02 | Toshiba Corp | Lateral igbt |
JPH08330601A (en) * | 1995-03-30 | 1996-12-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
JPH10223883A (en) * | 1997-02-03 | 1998-08-21 | Mitsubishi Electric Corp | Insulated gate type bipolar transistor and its manufacture |
JPH1140807A (en) * | 1997-07-18 | 1999-02-12 | Mitsubishi Electric Corp | Igbt and manufacture thereof |
JPH1154748A (en) | 1997-08-04 | 1999-02-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
JP2008305998A (en) * | 2007-06-07 | 2008-12-18 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
JP5515248B2 (en) * | 2008-03-26 | 2014-06-11 | 富士電機株式会社 | Semiconductor device |
-
2012
- 2012-09-18 JP JP2012204594A patent/JP5729364B2/en not_active Expired - Fee Related
- 2012-12-19 US US13/719,389 patent/US8791500B2/en not_active Expired - Fee Related
- 2012-12-21 DE DE102012224291A patent/DE102012224291A1/en not_active Withdrawn
- 2012-12-28 CN CN2012105851326A patent/CN103187440A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7880227B2 (en) * | 2005-08-26 | 2011-02-01 | Sanken Electric Co., Ltd. | Trench semiconductor device of improved voltage strength |
US7977704B2 (en) * | 2008-01-28 | 2011-07-12 | Denso Corporation | Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor |
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US20160315189A1 (en) * | 2015-04-24 | 2016-10-27 | Vanguard International Semiconductor Corporation | Semiconductor device and method for forming the same |
US9818861B2 (en) * | 2015-04-24 | 2017-11-14 | Vanguard International Semiconductor Corporation | Semiconductor device and method for forming the same |
US10680072B2 (en) * | 2017-09-25 | 2020-06-09 | Renesas Electronics Coporation | Semiconductor device and manufacturing method thereof |
US11393899B2 (en) | 2019-02-28 | 2022-07-19 | Yangtze Memory Technologies Co., Ltd. | High-voltage semiconductor device with increased breakdown voltage |
US11769794B2 (en) | 2019-02-28 | 2023-09-26 | Yangtze Memory Technologies Co., Ltd. | Manufacturing method of high-voltage semiconductor device with increased breakdown voltage |
US11296221B2 (en) * | 2019-05-08 | 2022-04-05 | Hyundai Mobis Co., Ltd. | Power semiconductor device |
US11043557B2 (en) * | 2019-06-27 | 2021-06-22 | Fuji Electric Co., Ltd. | Semiconductor device |
US20210305242A1 (en) * | 2020-03-24 | 2021-09-30 | Richtek Technology Corporation | Power device including lateral insulated gate bipolar transistor (ligbt) and manufacturing method thereof |
US11876093B2 (en) * | 2020-03-24 | 2024-01-16 | Richtek Technology Corporation | Power device including lateral insulated gate bipolar transistor (LIGBT) and manufacturing method thereof |
EP3951886A1 (en) * | 2020-08-03 | 2022-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN103187440A (en) | 2013-07-03 |
US8791500B2 (en) | 2014-07-29 |
JP2013153128A (en) | 2013-08-08 |
DE102012224291A1 (en) | 2013-07-04 |
JP5729364B2 (en) | 2015-06-03 |
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