CN114639737B - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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Publication number
CN114639737B
CN114639737B CN202210532562.5A CN202210532562A CN114639737B CN 114639737 B CN114639737 B CN 114639737B CN 202210532562 A CN202210532562 A CN 202210532562A CN 114639737 B CN114639737 B CN 114639737B
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current blocking
region
silicon
layer
trench structure
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CN114639737A (en
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于绍欣
高沛雄
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Yuexin Semiconductor Technology Co.,Ltd.
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Guangzhou Yuexin Semiconductor Technology Co Ltd
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The invention relates to an LDMOS device and a manufacturing method thereof. The LDMOS device is provided with a first current blocking groove structure and a second current blocking groove structure, the first current blocking groove structure longitudinally extends into the buried oxide layer from the drift region, and the second current blocking groove structure longitudinally extends into the drift region from one side of the silicon doping layer far away from the silicon substrate. The first current blocking groove structure and the second current blocking groove structure are arranged at intervals in the transverse direction, and projection parts in the transverse direction are overlapped, the first current blocking groove structure and the second current blocking groove structure block an original short and straight current path and form a bent current channel, so that the current path of the device in an opening state is prolonged, a larger source-drain breakdown voltage BV is obtained under the condition that the transverse size of the device is smaller, and the application of the device under high voltage is facilitated.

Description

LDMOS device and manufacturing method thereof
Technical Field
The invention relates to the technical field of transistors, in particular to an LDMOS device and a manufacturing method thereof.
Background
DMOS (double diffused metal oxide semiconductor field effect transistor) devices are core devices in BCD circuits, and in order to better integrate with IC mature processes, LDMOS (lateral double diffused metal oxide semiconductor field effect transistor) devices are generally used.
Currently, LDMOS devices with various structures are continuously developed to achieve the purposes of improving performance, reducing cost, increasing density, and the like. The LDMOS device which is mature in process comprises: (1) an LDMOS device of mini-STI; (2) LDMOS devices of Mini-LOCOS; (3) an LDMOS device combining Mini-STI and Mini-LOCOS; (4) an HTO field plate device; (5) contact hole field plates, namely CFP devices and the like.
However, in order to increase the source-drain breakdown voltage BV of the conventional LDMOS device, the distance between the drain contact hole and the polysilicon gate needs to be increased, which makes the lateral size of the device larger and also limits the application of the LDMOS device under high voltage.
Disclosure of Invention
In view of the above, it is necessary to provide an LDMOS device and a method for manufacturing the same, so as to obtain a larger source-drain breakdown voltage BV in the case of a smaller lateral size of the device.
One object of the present invention is to provide an LDMOS device, which has the following scheme:
an LDMOS device comprising:
the SOI substrate comprises a silicon substrate, a buried oxide layer and a silicon doping layer which are sequentially stacked; the silicon doped layer is provided with a source region, a drain region, a channel region and a drift region, the channel region surrounds the source region, and the drift region surrounds the drain region;
the grid structure is arranged on one side of the silicon doping layer far away from the silicon substrate and is positioned between the source region and the drain region;
a first current blocking trench structure disposed in the silicon doped layer and between the source region and the drain region, the first current blocking trench structure extending longitudinally from within the drift region into the buried oxide layer; and
the second current blocking groove structure is arranged in the silicon doping layer and located between the source region and the drain region, the second current blocking groove structure longitudinally extends from one side, far away from the silicon substrate, of the silicon doping layer, one end, close to the silicon substrate, of the second current blocking groove structure is located in the drift region, the first current blocking groove structure and the second current blocking groove structure are arranged at intervals in the transverse direction, and projection portions of the first current blocking groove structure and the second current blocking groove structure in the transverse direction are overlapped.
In one embodiment, the number of the first current blocking trench structures is at least two, and the first current blocking trench structures and the second current blocking trench structures are alternately arranged in a lateral direction.
In one embodiment, the number of the first current blocking trench structures is two, and the number of the second current blocking trench structures is one.
In one embodiment, the number of the first current blocking trench structures is three, and the number of the second current blocking trench structures is two.
In one embodiment, the longitudinal dimension of the overlapping portion of the projections of the first current blocking trench structure and the second current blocking trench structure in the transverse direction is 2-8 μm.
In one embodiment, the lateral width of the first current blocking trench structure is 0.25 μm to 0.5 μm.
In one embodiment, the lateral width of the second current blocking trench structure is 0.25 μm to 0.5 μm.
In one embodiment, the first current blocking trench structure includes a first polysilicon body and a first silicon oxide layer encasing the first polysilicon body.
In one embodiment, the second current blocking trench structure includes a second polysilicon body and a second silicon oxide layer covering the second polysilicon body.
In one embodiment, the SOI substrate further has a first pocket implant region disposed around an end of the first current blocking trench structure near the silicon substrate, the first pocket implant region being of the same doping type as the channel region and having a higher ion implantation dose than the channel region.
In one embodiment, the SOI substrate further has a second pocket implant region disposed around an end of the second current blocking trench structure near the silicon substrate and located in the drift region, the second pocket implant region has the same doping type as the drift region, and the ion implantation dose is higher than that of the drift region.
In one embodiment, the LDMOS device further comprises a field plate disposed on a side of the silicon doped layer away from the silicon substrate between the source region and the drain region.
Another objective of the present invention is to provide a method for manufacturing an LDMOS device, which comprises the following steps:
a manufacturing method of an LDMOS device comprises the following steps:
providing an SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a bulk silicon layer which are sequentially stacked;
manufacturing a first current blocking groove structure in the SOI substrate;
growing an epitaxial layer on one side of the bulk silicon layer far away from the silicon substrate;
manufacturing a second current blocking groove structure in a composite layer formed by the bulk silicon layer and the epitaxial layer;
injecting ions into the composite layer to form a source region, a drain region, a channel region and a drift region, enabling the channel region to surround the source region, and enabling the drift region to surround the drain region to obtain a silicon doped layer; the first current blocking trench structure is located between the source region and the drain region and longitudinally extends into the buried oxide layer from the inside of the drift region, the second current blocking trench structure is located between the source region and the drain region and longitudinally extends into the drift region from one side, far away from the silicon substrate, of the silicon doping layer, the first current blocking trench structure and the second current blocking trench structure are arranged at intervals in the transverse direction, and projection parts of the first current blocking trench structure and the second current blocking trench structure in the transverse direction are overlapped;
and manufacturing a gate structure, wherein the gate structure is formed on one side of the silicon doped layer far away from the silicon substrate and is positioned between the source region and the drain region.
In one embodiment, the step of fabricating the first current blocking trench structure comprises:
manufacturing a first filling groove on the SOI substrate, wherein the first filling groove longitudinally extends from one side of the bulk silicon layer far away from the silicon substrate to the buried oxide layer;
performing a thermal oxidation process on the wall of the first filling groove to form a first silicon oxide layer;
and after the first silicon oxide layer is formed, filling polycrystalline silicon in the first filling groove.
In one embodiment, after forming the first silicon oxide layer and before filling the first filling trench with polysilicon, the method further includes:
and performing pocket implantation in the first filling groove to form a first pocket implantation region which is arranged around one end of the first current blocking groove structure close to the silicon substrate, wherein the doping type of the first pocket implantation region is the same as that of the channel region, and the ion implantation dosage is higher than that of the channel region.
In one embodiment, the step of fabricating the second current blocking trench structure comprises:
manufacturing a second filling groove, wherein the second filling groove longitudinally extends from one side of the epitaxial layer far away from the silicon substrate to the bulk silicon layer;
performing a thermal oxidation process on the wall of the second filling groove to form a second silicon oxide layer;
and after the second silicon oxide layer is formed, filling polycrystalline silicon in the second filling groove.
In one embodiment, after forming the second silicon oxide layer and before filling the second filling trench with polysilicon, the manufacturing method further includes the following steps:
and performing pocket implantation in the second filling groove to form a second pocket implantation region which is arranged around one end of the second current blocking trench structure close to the silicon substrate and is positioned in the drift region, wherein the doping type of the second pocket implantation region is the same as that of the drift region, and the ion implantation dosage is higher than that of the drift region.
Compared with the prior art, the LDMOS device and the manufacturing method thereof have the following beneficial effects:
the LDMOS device and the manufacturing method thereof are provided with a first current blocking groove structure and a second current blocking groove structure, wherein the first current blocking groove structure longitudinally extends into the buried oxide layer from the drift region, and the second current blocking groove structure longitudinally extends into the drift region from one side of the silicon doping layer far away from the silicon substrate. The first current blocking groove structure and the second current blocking groove structure are arranged at intervals in the transverse direction, and projection parts in the transverse direction are overlapped, the first current blocking groove structure and the second current blocking groove structure block an original short and straight current path and form a bent current channel, so that the current path of the device in an opening state is prolonged, a larger source-drain breakdown voltage BV is obtained under the condition that the transverse size of the device is smaller, and the application of the device under high voltage is facilitated.
Drawings
FIG. 1 is a schematic structural diagram of an LDMOS device according to an embodiment;
FIG. 2 is a schematic structural diagram of an LDMOS device according to another embodiment;
FIG. 3 is a mask layout of a conventional LDMOS device;
fig. 4 is a mask layout of the LDMOS device shown in fig. 1.
Description of reference numerals:
10. an LDMOS device; 100. an SOI substrate; 110. a silicon substrate; 120. an oxygen burying layer; 131. a bulk silicon layer; 132. an epitaxial layer; 130. a silicon doped layer; 133. a source region; 134. a drain region; 135. a channel region; 136. a drift region; 137. the body connects out of the injection region; 140. a gate structure; 141. a polysilicon gate; 142. a side wall; 150. a first current blocking trench structure; 151. a first polysilicon body; 152. a first silicon oxide layer; 160. a second current blocking trench structure; 161. a second polysilicon body; 162. a second silicon oxide layer; 138. a first pocket implant region; 139. a second pocket implant region; 170. a field plate; 180. a source contact hole; 190. and a drain contact hole.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 to 2, an LDMOS device 10 according to an embodiment of the present invention includes an SOI substrate 100, a gate structure 140, a first current blocking trench structure 150, and a second current blocking trench structure 160.
The SOI substrate 100 includes a silicon substrate 110, a buried oxide layer 120, and a silicon doped layer 130, which are sequentially stacked. Silicon doped layer 130 has source region 133, drain region 134, channel region 135, and drift region 136. Channel region 135 surrounds source region 133 and drift region 136 surrounds drain region 134. A gate structure 140 is disposed on a side of the doped layer 130 away from the silicon substrate 110 and between the source region 133 and the drain region 134.
In particular, a first current blocking trench structure 150 and a second current blocking trench structure 160 are provided in the LDMOS device 10. A first current blocking trench structure 150 is disposed in silicon doped layer 130 between source region 133 and drain region 134, first current blocking trench structure 150 extending longitudinally from within drift region 136 into buried oxide layer 120. A second current blocking trench structure 160 is disposed in silicon doped layer 130 between source region 133 and drain region 134, the second current blocking trench structure 160 extending longitudinally from a side of silicon doped layer 130 away from silicon substrate 110 into drift region 136. The first current blocking trench structure 150 and the second current blocking trench structure 160 are spaced apart in the lateral direction, and projections in the lateral direction partially overlap.
The LDMOS device 10 is provided with a first current blocking trench structure 150 and a second current blocking trench structure 160, the first current blocking trench structure 150 extends longitudinally from within the drift region 136 into the buried oxide layer 120, and the second current blocking trench structure 160 extends longitudinally from a side of the silicon doped layer 130 away from the silicon substrate 110 into the drift region 136. The first current blocking groove structure 150 and the second current blocking groove structure 160 are arranged at intervals in the transverse direction, and projection parts in the transverse direction are overlapped, the first current blocking groove structure 150 and the second current blocking groove structure 160 block an original short and straight current path and form a bent current channel, so that the current path in the starting state of the device is prolonged, a larger source-drain breakdown voltage BV is obtained under the condition that the transverse size of the device is smaller, and the application of the device under high voltage is facilitated.
For convenience of explanation, hereinafter, the "upper end" of the first and second current blocking trench structures 150 and 160 is defined as an end thereof away from the silicon substrate 110, and the "lower end" is defined as an end thereof close to the silicon substrate 110. The above definition does not strictly limit the "upper end" to be located above the "lower end".
It is understood that the gate structure 140 includes a gate oxide layer (not shown) and a polysilicon gate 141. The gate oxide is located between the polysilicon gate 141 and the silicon doped layer 130. Further, the gate structure 140 may further include a sidewall 142, and the sidewall 142 is disposed at two sides of the polysilicon gate 141.
In one example, LDMOS device 10 further includes a field plate 170, with field plate 170 disposed on a side of silicon doped layer 130 away from silicon substrate 110 and between source region 133 and drain region 134.
The field plate 170 corresponds to the first current blocking trench structure 150 and the second current blocking trench structure 160, and by providing the first current blocking trench structure 150 and the second current blocking trench structure 160, a current path is extended, and compared with a conventional method of increasing a distance between a drain contact hole and a polysilicon gate 141, a lateral size of a device can be reduced, and accordingly, a lateral size of the field plate 170 can also be reduced.
In the specific example shown in fig. 1 and 2, LDMOS device 10 employs an SBS structure, i.e., two source regions 133 are formed in silicon doped layer 130, and a body-tap implant region 137 is formed between the two source regions 133. The body-tie implant 137 is doped differently than the source region 133, for example, the source region 133 is doped N-type and the body-tie implant 137 is doped P-type.
In one example, there are at least two first current blocking trench structures 150, and the first current blocking trench structures 150 and the second current blocking trench structures 160 are alternately arranged in a lateral direction. Further, in one example, there are at least two second current blocking trench structures 160 and at least three first current blocking trench structures 150. Further, in one example, the first current blocking trench structure 150 is located at the outermost side in the lateral direction.
In the example shown in fig. 1, there is one second current blocking trench structure 160 in number, there is two first current blocking trench structures 150 in number, and the first current blocking trench structures 150 and the second current blocking trench structures 160 are alternately arranged in a lateral direction. The current paths in this example are shown by the arrowed lines in the figure.
According to actual needs, the number of the current blocking groove structures can be increased properly to obtain higher source-drain breakdown voltage. For example, in the example shown in fig. 2, the number of the second current blocking trench structures 160 is two, the number of the first current blocking trench structures 150 is three, and the first current blocking trench structures 150 and the second current blocking trench structures 160 are alternately arranged in the lateral direction. The current paths in this example are shown by the arrowed lines in the figure.
The first current blocking trench structure 150 includes a first polysilicon body 151 and a first silicon oxide layer 152 covering the first polysilicon body 151.
The first current blocking trench structure 150 may be formed by forming a first filling trench in the silicon doping layer 130, performing a thermal oxidation process on a trench wall of the first filling trench, and then filling the first filling trench with polysilicon.
In one example, the first silicon oxide layer 152 has a thickness of 300A-1000A.
In one example, the first current blocking trench structure 150 has a lateral width of 0.25 μm to 0.5 μm.
Due to the trench fabrication process, in the example shown in fig. 1 and 2, the first current blocking trench structure 150 has a structure that is wider at the upper end and narrower at the lower end.
The lower end of the first current blocking trench structure 150 enters the buried oxide layer 120, e.g. at a depth above 500 a into the buried oxide layer 120, avoiding current to pass from the lower end of the first current blocking trench structure 150.
In one example, the second current blocking trench structure 160 includes a second polysilicon body 161 and a second silicon oxide layer 162 covering the second polysilicon body 161.
The second current blocking trench structure 160 may be formed by forming a second filling trench in the silicon doping layer 130, performing a thermal oxidation process on a trench wall of the second filling trench, and then filling the second filling trench with polysilicon.
In one example, the second silicon oxide layer 162 has a thickness of 300A-1000A.
In one example, the second current blocking trench structure 160 has a lateral width of 0.25 μm to 0.5 μm.
Due to the trench fabrication process, in the example shown in fig. 1 and 2, the second current blocking trench structure 160 has a structure that is wider at the upper end and narrower at the lower end.
In one example, the longitudinal dimension of the overlapping portion of the projections of the first and second current blocking trench structures 150 and 160 in the lateral direction is 2 to 8 μm. That is, the longitudinal distance between the upper end of the first current blocking trench structure 150 and the lower end of the second current blocking trench structure 160 is 2 to 8 μm, specifically, for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, and the like.
In one example, the SOI substrate 100 also has a first pocket implant region 138. The first pocket implant region 138 is disposed around a lower end of the first current blocking trench structure 150. The first pocket implant 138 has the same doping type as the channel region 135 and has a higher ion implantation dose than the channel region 135. Forming the first pocket implant region 138 in this example can improve the isolation of the first current blocking trench structure 150 and improve the source-drain breakdown voltage BV.
The first pocket implantation region 138 may be formed by performing pocket implantation after the first filling groove is formed.
In one example, the doping type of the first pocket implant region 138 is P-type, such as BF2 or In implant.
In one example, the first pocket implant 138 has an ion implant dose of 1 × 10 14 cm -2 ~5×10 15 cm -2 。
In one example, the SOI substrate 100 also has a second pocket implant region 139. A second pocket implant region 139 is disposed around a lower end of the second current blocking trench structure 160 and within the drift region 136. The second pocket implant region 139 has the same doping type as the drift region 136 and has a higher ion implantation dose than the drift region 136. The second pocket injection region 139 formed in this example can widen the width of the channel when turned on, and reduce the source-drain on-resistance Rdson.
The second pocket implant region 139 may be formed by performing pocket implant after forming the second filling groove.
In one example, the doping type of the second pocket implant region 139 is N-type, and for example, a P or As implant may be used.
In one example, the ion implantation dosage of the second pocket implantation region 139 is 1 × 10 14 cm -2 ~5×10 15 cm -2 。
Further, the present invention also provides a method for manufacturing the LDMOS device 10 of any one of the above examples, including the following steps:
step S1, providing an SOI substrate 100, where the SOI substrate 100 includes a silicon substrate 110, a buried oxide layer 120, and a bulk silicon layer 131 sequentially stacked.
A first current blocking trench structure 150 is fabricated in the SOI substrate 100.
In step S2, an epitaxial layer 132 is grown on the side of the bulk silicon layer 131 remote from the silicon substrate 110.
In step S3, a second current blocking trench structure 160 is formed in the composite layer of the bulk silicon layer 131 and the epitaxial layer 132.
Step S4, implanting ions into the recombination layer to form a source region 133, a drain region 134, a channel region 135 and a drift region 136, so that the channel region 135 surrounds the source region 133 and the drift region 136 surrounds the drain region 134, thereby obtaining a silicon doped layer 130; the first current blocking trench structure 150 is located between the source region 133 and the drain region 134 and longitudinally extends from the inside of the drift region 136 into the buried oxide layer 120, the second current blocking trench structure 160 is located between the source region 133 and the drain region 134 and longitudinally extends from the side of the silicon doped layer 130 far away from the silicon substrate 110 into the drift region 136, and the first current blocking trench structure 150 and the second current blocking trench structure 160 are arranged at intervals in the transverse direction and partially overlap in projection in the transverse direction;
in step S5, a gate structure 140 is formed such that the gate structure 140 is formed on the doped silicon layer 130 on a side away from the silicon substrate 110 and between the source region 133 and the drain region 134.
The method for manufacturing the LDMOS device 10 includes providing the first current blocking trench structure 150 and the second current blocking trench structure 160, where the first current blocking trench structure 150 longitudinally extends from the drift region 136 to the buried oxide layer 120, and the second current blocking trench structure 160 longitudinally extends from the side of the silicon doped layer 130 away from the silicon substrate 110 to the drift region 136. The first current blocking groove structure 150 and the second current blocking groove structure 160 are arranged at intervals in the transverse direction, and projection parts in the transverse direction are overlapped, the first current blocking groove structure 150 and the second current blocking groove structure 160 block an original short and straight current path and form a bent current channel, so that the current path in the starting state of the device is prolonged, a larger source-drain breakdown voltage BV is obtained under the condition that the transverse size of the device is smaller, and the application of the device under high voltage is facilitated.
In one example, the step of fabricating the first current blocking trench structure 150 includes:
manufacturing a first filling groove on the SOI substrate 100, wherein the first filling groove longitudinally extends into the buried oxide layer 120 from one side of the silicon layer 131 far away from the silicon substrate 110;
performing a thermal oxidation process on the wall of the first filling groove to form a first silicon oxide layer 152;
after the first silicon oxide layer 152 is formed, the first filling trench is filled with polysilicon to form a first polysilicon body 151.
The first filling groove can be manufactured by processes of photoetching, etching and the like.
In one example, the first filling groove has a depth of 1.5 μm to 2 μm. The depth of the first filled trench into the buried oxide layer 120 is above 500 a.
After the first filling groove is filled with polysilicon, the excess polysilicon can be removed by a back etching process or a grinding process, so that the upper end of the polysilicon is flush with the bulk silicon layer 131.
In one example, after forming the first silicon oxide layer 152 and before filling the first filling trench with polysilicon, the manufacturing method further includes the following steps:
a pocket implant is performed in the first fill trench to form a first pocket implant region 138, the first pocket implant region 138 being disposed around an end of the first current blocking trench structure 150 proximate to the silicon substrate 110. The first pocket implant 138 has the same doping type as the channel region 135 and has a higher ion implantation dose than the channel region 135.
In one example, the step of fabricating the second current blocking trench structure 160 includes:
manufacturing a second filling groove, wherein the second filling groove longitudinally extends from one side of the epitaxial layer 132, which is far away from the silicon substrate 110, into the bulk silicon layer 131;
performing a thermal oxidation process on the wall of the second filling groove to form a second silicon oxide layer 162;
after the second silicon oxide layer 162 is formed, the second filling trench is filled with polysilicon to form a second polysilicon body 161.
The thickness of the bulk silicon layer 131 may be, for example, 1 to 3 μm. The thickness of the epitaxial layer 132 may be, for example, 1 to 3 μm.
The second filling groove can be manufactured by photoetching, etching and other processes.
In one example, the second filling groove has a depth of 1.5 μm to 2 μm.
After the second filling groove is filled with polysilicon, the excess polysilicon can be removed by a back etching process or a grinding process, so that the upper end of the polysilicon is flush with the epitaxial layer 132.
In one example, after forming the second silicon oxide layer 162 and before filling the second filling trench with polysilicon, the manufacturing method further includes the following steps:
pocket implants are performed in the second filled trenches to form second pocket implant regions 139, and the second pocket implant regions 139 are disposed around an end of the second current blocking trench structure 160 proximate to the silicon substrate 110 and within the drift region 136. The second pocket implant region 139 has the same doping type as the drift region 136, and has a higher ion implantation dose than the drift region 136.
In one example, the manufacturing method further comprises the following steps:
in step S7, a field plate 170 is formed on the side of the doped layer 130 away from the silicon substrate 110, the field plate 170 being located between the source region 133 and the drain region 134.
In one example, the manufacturing method further comprises the following steps:
in step S8, a crystallization layer (not shown) is formed on drain region 134.
In one example, the manufacturing method further comprises the following steps:
in step S9, a dielectric layer (not shown) is formed to cover the gate structure 140, the field plate 170 and the crystallization layer.
In one example, the manufacturing method further comprises the following steps:
in step S10, source contact hole 180 and drain contact hole 190 are formed in the dielectric layer.
In one example, the manufacturing method further comprises the following steps:
in step S11, a metal layer (not shown) is formed on the dielectric layer.
Taking the specific example shown in fig. 1 as an example, the manufacturing method includes the following steps:
step 1, providing an SOI substrate 100, wherein the SOI substrate 100 includes a silicon substrate 110, a buried oxide layer 120 and a bulk silicon layer 131 which are sequentially stacked. The thickness of the bulk silicon layer 131 is 1.5 μm.
Step 2, a first filling groove is manufactured on the SOI substrate 100 through processes such as photoetching and etching, and the first filling groove longitudinally extends into the buried oxide layer 120 from one side of the silicon layer 131 far away from the silicon substrate 110. The first filled trench has a depth of 2 μm and a depth of 5000 a into buried oxide layer 120. The number of the first filling grooves is two.
Step 3, performing a thermal oxidation process on the trench walls of the first filled trenches to form a first silicon oxide layer 152 having a thickness of 300 a.
Step 4, filling the groove in the first filling grooveA first pocket implant region 138 is formed by pocket implanting P-type ions In, and the first pocket implant region 138 is disposed around an end of the first current blocking trench structure 150 near the silicon substrate 110. The first pocket implant 138 has an ion implantation dose of 1 × 10 15 cm -2 。
And 5, filling polysilicon in the first filling grooves to form two first current blocking groove structures 150.
And 6, removing the redundant polysilicon through a back etching process or a Chemical Mechanical Polishing (CMP) process to enable the upper end of the polysilicon to be flush with the bulk silicon layer 131.
Step 7, growing an epitaxial layer 132 on the side of the bulk silicon layer 131 far away from the silicon substrate 110, wherein the thickness of the epitaxial layer 132 is 1 μm.
Step 8, a second filling trench is formed by photolithography, etching, and the like, and the second filling trench extends longitudinally into the bulk silicon layer 131 from a side of the epitaxial layer 132 away from the silicon substrate 110 and is located laterally between the two first current blocking trench structures 150. The depth of the first filled trench was 2 μm.
Step 9, performing a thermal oxidation process on the trench walls of the second filled trenches to form a second silicon oxide layer 162 with a thickness of 300 a.
Step 10, pocket implantation of N-type ions As is performed in the second filled trench to form a second pocket implantation region 139, where the second pocket implantation region 139 is disposed around one end of the second current blocking trench structure 160 close to the silicon substrate 110 and located in the drift region 136. The ion implantation dosage of the second pocket implantation region 139 is 2 × 10 15 cm -2 。
Step 11, filling polysilicon in the first filling trench to form a second current blocking trench structure 160.
Step 12, removing the excess polysilicon through a back etching process or a grinding process to make the upper end of the polysilicon flush with the epitaxial layer 132.
Step 13, implanting ions into the composite layer formed by the bulk silicon layer 131 and the epitaxial layer 132 to form a source region 133, a drain region 134, a channel region 135 and a drift region 136, so that the channel region 135 surrounds the source region 133, and the drift region 136 surrounds the drain region 134, thereby obtaining the silicon doped layer 130.
Step 14, a gate structure 140 is formed on the doped silicon layer 130 on the side away from the silicon substrate 110, including the gate oxide layer, the sidewall 142 and the polysilicon gate 141.
Step 15, a field plate 170 is fabricated on a side of the doped layer 130 away from the silicon substrate 110, the field plate 170 being located between the source region 133 and the drain region 134.
A crystallization layer is formed over drain region 134, step 16.
Step 17, a dielectric layer is fabricated covering the gate structure 140, the field plate 170 and the crystallization layer.
Step 18, source contact hole 180 and drain contact hole 190 are formed in the dielectric layer.
And step 19, manufacturing a metal layer on the dielectric layer.
Fig. 3 shows a reticle layout 10 for a conventional LDMOS device. Region 21 corresponds to the source contact region, region 22 corresponds to the drain contact region, region 23 corresponds to the polysilicon gate region, region 24 corresponds to the field plate region, and region 25 corresponds to the nucleation layer region. And under a process node of 90 nm-0.18 mu m, the distance L1 between a drain end contact hole and the polysilicon gate is 2.1 mu m.
Fig. 4 illustrates a reticle layout 20 for the LDMOS device 10 of the specific example shown in fig. 1. Wherein region 31 corresponds to the region of the source contact hole 180, region 32 corresponds to the region of the drain contact hole 190, region 33 corresponds to the region of the polysilicon gate 141, region 34 corresponds to the region of the field plate 170, region 35 corresponds to the region of the crystallization layer, regions 361 and 362 correspond to the regions of the two first current blocking trench structures 150, and region 37 corresponds to the region of the second current blocking trench structure 160.
Under a process node of 90 nm-0.18 mu m, the reference sizes are as follows: the distance L2 between the drain end contact hole and the polysilicon gate is 1.1 mu m; the width L3 of the first current blocking trench structure 150 is 0.2 μm; a distance L4 between the first current blocking trench structure 150 and the second current blocking trench structure 160 is 0.15 μm; the width L5 of the second current blocking trench structure 160 is 0.2 μm.
Under the condition that the longitudinal size of the overlapping portion of the projections of the first current blocking trench structure 150 and the second current blocking trench structure 160 in the transverse direction is 0.6um, according to theoretical analysis, the performance of the same source-drain breakdown voltage BV under the condition that L1 is 2.1 μm can be completely achieved when L2 is 1.1 μm.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. An LDMOS device, comprising:
the SOI substrate comprises a silicon substrate, a buried oxide layer and a silicon doping layer which are sequentially stacked; the silicon doped layer is provided with a source region, a drain region, a channel region and a drift region, the channel region surrounds the source region, and the drift region surrounds the drain region;
the grid structure is arranged on one side of the silicon doped layer far away from the silicon substrate and is positioned between the source region and the drain region;
the first current blocking groove structure is arranged in the silicon doping layer and located between the source region and the drain region, and the first current blocking groove structure longitudinally extends into the buried oxide layer from the inside of the drift region; and
the second current blocking trench structure is arranged in the silicon doping layer and located between the source region and the drain region, the second current blocking trench structure longitudinally extends from one side, far away from the silicon substrate, of the silicon doping layer, one end, close to the silicon substrate, of the second current blocking trench structure is located in the drift region, the first current blocking trench structure and the second current blocking trench structure are arranged at intervals in the transverse direction, and projection portions of the first current blocking trench structure and the second current blocking trench structure in the transverse direction are overlapped;
the SOI substrate is further provided with a first pocket implantation region, the first pocket implantation region is arranged around one end, close to the silicon substrate, of the first current blocking groove structure, the doping type of the first pocket implantation region is the same as that of the channel region, and the ion implantation dosage is higher than that of the channel region.
2. The LDMOS device of claim 1, wherein a number of the first current blocking trench structures is at least two, and the first current blocking trench structures and the second current blocking trench structures are alternately arranged in a lateral direction.
3. The LDMOS device of claim 2, wherein there are two of the first current blocking trench structures and one of the second current blocking trench structures; or
The number of the first current blocking trench structures is three, and the number of the second current blocking trench structures is two.
4. The LDMOS device of claim 1, wherein a longitudinal dimension of an overlapping portion of projections of the first current blocking trench structure and the second current blocking trench structure in a lateral direction is 2 μm to 8 μm.
5. The LDMOS device of claim 1, wherein a lateral width of the first current blocking trench structure is 0.25 μm to 0.5 μm; and/or
The lateral width of the second current blocking groove structure is 0.25-0.5 μm.
6. The LDMOS device of claim 1, wherein the first current blocking trench structure includes a first polysilicon body and a first silicon oxide layer encasing the first polysilicon body; and/or
The second current blocking trench structure includes a second polysilicon body and a second silicon oxide layer that encapsulates the second polysilicon body.
7. The LDMOS device of claim 1, wherein the ion implantation dose of the first pocket implant region is 1 x 10 14 cm -2 ~5×10 15 cm -2 。
8. The LDMOS device of any of claims 1-7, wherein the SOI substrate further has a second pocket implant region disposed around an end of the second current blocking trench structure proximate to the silicon substrate and within the drift region, the second pocket implant region being of a same doping type as the drift region and having a higher ion implant dose than the drift region.
9. The LDMOS device of any of claims 1-7, further comprising a field plate disposed on a side of the silicon doped layer away from the silicon substrate between the source region and the drain region.
10. A manufacturing method of an LDMOS device is characterized by comprising the following steps:
providing an SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a bulk silicon layer which are sequentially stacked;
manufacturing a first current blocking groove structure in the SOI substrate;
growing an epitaxial layer on one side of the bulk silicon layer far away from the silicon substrate;
manufacturing a second current blocking groove structure in a composite layer formed by the bulk silicon layer and the epitaxial layer;
injecting ions into the composite layer to form a source region, a drain region, a channel region and a drift region, enabling the channel region to surround the source region, and enabling the drift region to surround the drain region to obtain a silicon doped layer; the first current blocking trench structure is located between the source region and the drain region and longitudinally extends into the buried oxide layer from the inside of the drift region, the second current blocking trench structure is located between the source region and the drain region and longitudinally extends into the drift region from one side, far away from the silicon substrate, of the silicon doping layer, the first current blocking trench structure and the second current blocking trench structure are arranged at intervals in the transverse direction, and projection parts of the first current blocking trench structure and the second current blocking trench structure in the transverse direction are overlapped;
manufacturing a grid structure, wherein the grid structure is formed on one side of the silicon doping layer, which is far away from the silicon substrate, and is positioned between the source region and the drain region;
the step of fabricating the first current blocking trench structure comprises:
manufacturing a first filling groove on the SOI substrate, wherein the first filling groove longitudinally extends from one side of the bulk silicon layer far away from the silicon substrate to the buried oxide layer;
carrying out thermal oxidation process on the groove wall of the first filling groove to form a first silicon oxide layer;
after the first silicon oxide layer is formed, filling polycrystalline silicon in the first filling groove;
after forming the first silicon oxide layer and before filling the first filling groove with polysilicon, the manufacturing method further comprises the following steps:
and performing pocket implantation in the first filling groove to form a first pocket implantation region which is arranged around one end of the first current blocking groove structure close to the silicon substrate, wherein the doping type of the first pocket implantation region is the same as that of the channel region, and the ion implantation dosage is higher than that of the channel region.
11. The method of claim 10, wherein the first pocket implant region has an ion implantation dose of 1 x 10 14 cm -2 ~5×10 15 cm -2 。
12. The method of claim 10, wherein the first pocket implant region is P-type.
13. The method of fabricating of claim 11 or 12, wherein fabricating the second current blocking trench structure comprises:
manufacturing a second filling groove, wherein the second filling groove longitudinally extends from one side of the epitaxial layer far away from the silicon substrate to the bulk silicon layer;
performing a thermal oxidation process on the groove wall of the second filling groove to form a second silicon oxide layer;
and after the second silicon oxide layer is formed, filling polycrystalline silicon in the second filling groove.
14. The method of claim 13, wherein after forming the second silicon oxide layer and before filling the second trench with polysilicon, the method further comprises:
and performing pocket implantation in the second filling groove to form a second pocket implantation region which is arranged around one end of the second current blocking trench structure close to the silicon substrate and is positioned in the drift region, wherein the doping type of the second pocket implantation region is the same as that of the drift region, and the ion implantation dosage is higher than that of the drift region.
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