US20010040271A1 - BEOL decoupling capacitor - Google Patents
BEOL decoupling capacitor Download PDFInfo
- Publication number
- US20010040271A1 US20010040271A1 US09/757,154 US75715401A US2001040271A1 US 20010040271 A1 US20010040271 A1 US 20010040271A1 US 75715401 A US75715401 A US 75715401A US 2001040271 A1 US2001040271 A1 US 2001040271A1
- Authority
- US
- United States
- Prior art keywords
- metal
- insulator
- resistor
- film stack
- titanate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000003990 capacitor Substances 0.000 title claims description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 110
- 239000002184 metal Substances 0.000 claims abstract description 110
- 150000002739 metals Chemical class 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 19
- 239000012212 insulator Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910004166 TaN Inorganic materials 0.000 claims description 8
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- YIMPFANPVKETMG-UHFFFAOYSA-N barium zirconium Chemical compound [Zr].[Ba] YIMPFANPVKETMG-UHFFFAOYSA-N 0.000 claims description 3
- 150000001768 cations Chemical class 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- 230000002378 acidificating effect Effects 0.000 claims description 2
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 2
- LBSANEJBGMCTBH-UHFFFAOYSA-N manganate Chemical compound [O-][Mn]([O-])(=O)=O LBSANEJBGMCTBH-UHFFFAOYSA-N 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 2
- DKDQMLPMKQLBHQ-UHFFFAOYSA-N strontium;barium(2+);oxido(dioxo)niobium Chemical compound [Sr+2].[Ba+2].[O-][Nb](=O)=O.[O-][Nb](=O)=O.[O-][Nb](=O)=O.[O-][Nb](=O)=O DKDQMLPMKQLBHQ-UHFFFAOYSA-N 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- XBYNNYGGLWJASC-UHFFFAOYSA-N barium titanium Chemical compound [Ti].[Ba] XBYNNYGGLWJASC-UHFFFAOYSA-N 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 25
- 239000003989 dielectric material Substances 0.000 description 26
- 238000000151 deposition Methods 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000005272 metallurgy Methods 0.000 description 4
- 238000000224 chemical solution deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000005382 thermal cycling Methods 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to integrated circuits (ICs), and in particular to an integrated circuit which includes at least a resistor having low capacitance coupling to an underlying substrate and a controllable resistance value, said resistor comprising a discrete metal-insulator-metal (MIM) film stack in which metal contacts are in electrical connection therewith.
- the discrete MIM film stack of the present invention is composed of the same films as the MIM film stack of an adjacent high-capacitance capacitor.
- the present invention is also directed to a method of fabricating such integrated circuits and to the use of TaN or TaN/ ⁇ -Ta as interconnects for such integrated circuits.
- High-capacity IC capacitors on the order of 1 nF/mm 2 or above, connected across the power supply and ground buses of modern microprocessor chips are needed to reduce the power and ground noise to an acceptable level.
- the high-capacity capacitors should be placed very close to the switching circuits, and be connected to the power and ground buses by a low-resistance conductor.
- one preferred approach is to build the high-capacity capacitors into a BEOL (back end of the line) process.
- the dielectric thin film material for such BEOL decoupling capacitors must satisfy both of the following requirements: (1) a high dielectric constant as compared to conventional dielectrics such as SiO 2 and Si 3 N 4 (for example, a 100 nm thick film with a dielectric constant of 20 would give a capacitance of 1.8 nF/mm 2 ); and (2) a formation temperature which is compatible with the BEOL metallurgy and processing.
- the deposition temperature of the dielectric material used in forming the BEOL decoupling capacitor must be about 450° C. or lower. Such a low deposition temperature is required in order to avoid unwanted instability of the BEOL metallurgy used for the power and ground connections.
- capacitor and resistor devices are made from separate films.
- the use of separate films in fabricating resistors and capacitors adds additional processing steps to the overall manufacturing process which, in turn, increases the overall cost of manufacturing the IC.
- an integrated circuit is needed that includes a resistor that has low capacitance coupling to the underlying substrate, as well as a small footprint area which is required to obtain optimum sheet resistance and optimum resistor width and length. Additionally, a resistor is needed that has well controllable and reproducible values which are independent of subsequent processing such as thermal cycling. Such features cannot be meet using typical diffusion- or polysilicon-resistors whose values are functions of many more factors.
- One object of the present invention is to provide an integrated circuit (IC) comprising at least a resistor that is integrated with a high-capacitance capacitor, said resistor includes a metal-insulator-metal (MIM) film stack.
- the insulator of the film stack may be a conventional dielectric material or, more preferably, it is a thin film dielectric having a dielectric constant higher than conventional dielectric materials.
- a further object of the present invention is to provide an IC that comprises an integrated resistor/high-capacitance capacitor that has low-capacitive coupling to the underlying substrate.
- a further object of the present invention is to provide an IC which comprises an integrated resistor/high-capacitance capacitor having optimum resistance.
- a yet further object of the present invention is to provide an IC comprising an integrated resistor/high-capacitance capacitor which has well controlled resistor values which are reproducible.
- An additional object of the present invention is to provide an integrated circuit wherein the resistor and capacitor are fabricated from the same films.
- the present invention relates to an IC comprising a resistor which is coupled to a metal wiring level of an interconnect or damascene structure through metal contacts, said resistor including a discrete metal-insulator-metal film stack, wherein said metal contacts are in contact with one of said metals of said film stack.
- the insulator of the film stack may be a conventional dielectric, e.g., SiO 2 , Si 3 N 4 or Al 2 O 3 , or a high dielectric constant dielectric, such as an amorphous dielectric having a dielectric constant of 10 or greater. Combinations of various dielectric materials may also be used herein.
- the metal contacts of the inventive IC are composed of TaN or TaN/ ⁇ -Ta which have a sheet resistance of from about 3 to about 300 ohms/sq. which is significantly above the sheet resistance of typical metal contacts that are composed of Al, W, or Cu (the latter metal contacts have a sheet resistance on the order of 0.04-0.2 ohms/sq.).
- TaN or TaN/ ⁇ -Ta metal contacts in the IC design described above allows for a resistor having a size of from about 50 ohms up to the multi-Kohm range and beyond, as well as a resistor line:width ratio of about 20:1.
- the method of the present invention comprises, in one embodiment, the steps of:
- the method comprises the steps of:
- FIG. 1 is a cross-sectional representation of one possible resistor design layout of the present invention.
- FIG. 2 is a cross-sectional representation of another possible resistor design layout of the present invention.
- FIG. 3 is a cross-sectional representation of yet another possible resistor design layout of the present invention.
- FIGS. 4 A- 4 B are pictorial representations of one possible IC structure of the present invention through various views; 4 A is a top view of the inventive IC structure, and 4 B is a side view.
- the resistor is formed on the top electrode of a MIM film stack.
- the resistor design of FIG. 1 comprises a patterned, discrete metal-insulator-metal (MIM) film stack 10 which includes an insulator film 14 that is sandwiched between bottom electrode 12 and top electrode 16 .
- the inventive resistor design of FIG. 1 further includes metal contacts 18 that are formed on at least a portion of top electrode 16 and an overlying metal wiring region 20 that is formed so as to be in electrical contact with metal contacts 18 .
- FIG. 2 illustrates a cross-sectional view of another inventive resistor design of the present invention.
- FIG. 2 is composed of the same components as in FIG. 1, but for the fact that metal contacts 18 and wiring region 20 are formed beneath the discrete MIM film stack.
- FIG. 3 shows yet another resistor design of the present invention.
- the resistor design includes patterned metal-insulator-metal film stack 10 , bottom electrode 12 , insulator film 14 , top electrode 16 and contact metal 18 .
- the contact metal which may be in the form of a metal line or via, is part of a damascene structure.
- each of the above resistor design layouts represents one component of an IC structure which could be made using BEOL processes or damscene processes. Additionally, in each of the resistor design layouts shown in FIGS. 1 - 3 , the current flows laterally through either the top or bottom electrode, or both and any unused electrode of the MIM resistor is disconnected from the circuit. It should be noted that in each of the design layouts described above, the other discrete MIM film stacks may be used as resistors, or alternatively, as high-capacitance capacitors.
- Electrodes 12 and 16 are composed of conventional conductive materials including, but not limited to: TaN, Pt, Ir, ruthenium oxide, Al, Au, Cu, Ta, TaSiN and mixtures or multilayers thereof. Other conventional conductive materials can also be employed in the present invention.
- the electrodes are formed utilizing conventional deposition processes including, but not limited to: sputtering, plating, evaporation, chemical vapor deposition (CVD), plasma-assisted CVD, chemical solution deposition and other like deposition processes.
- Insulator film 14 may be composed of a conventional dielectric material such as SiO 2 , Si 3 N 4 or Al 2 O 3 , or more preferably, it is composed of a high dielectric constant dielectric (dielectric constant greater than 10). Combinations of varies dielectric materials are contemplated herein. In one highly preferred embodiment, insulator film 14 is an amorphous high dielectric constant thin film which is composed of a perovskite-type oxide.
- perovskite-type oxide is used herein to denote a material which includes at least one acidic oxide containing at least one metal selected from Group IVB (Ti, Zr or Hf), VB (V, Nb or Ta), VIB (Cr, Mo or W), VIIB (Mn or Re) or IB (Cu, Ag or Au) of the Periodic Table of Elements (CAS version) and at least one additional cation having a positive formal charge of from about 1 to about 3.
- Such perovskite-type oxides typically have the basic formula: ABO 3 wherein A is one of the above mentioned cations, and B is one of the above mentioned metals.
- Suitable perovskite-type oxides include, but are not limited to: titanate-based dielectrics, manganate-based materials, cuprate-based materials, tungsten bronze-type niobates, tantalates, or titanates, and bismuth layered-tantalates, niobates or titanates.
- barium strontium titanate BSTO
- barium titanate BTO
- lead zirconium titanate PZTO
- barium zirconium titanate BZTO
- tantalum titanate TTO
- lead lanthanum titanate PLTO
- a highly preferred perovskite-type oxide is BSTO or BZTO.
- the perovskite-type oxide employed in the present invention is preferred to be in the amorphous (or low temperature) phase since the crystalline phase of such materials is produced at temperatures which are not compatible with BEOL processing.
- amorphous phase is used herein to denote that the crystal structure of the perovskite-type oxide lacks order. This is different from the crystalline phase of the material wherein a highly ordered crystal structure is observed.
- the amorphous thin film dielectric material is formed by a suitable deposition process which is capable of operating at temperatures well below the crystallization temperature of the perovskite-type oxide and thereafter, the deposited material is annealed.
- the temperature of deposition of the amorphous thin film dielectric material is kept below 400° C. and thus the process and the material is compatible with BEOL temperature requirements. In some applications, higher BEOL temperatures may be allowed, up to 450° C. or even 500° C.
- the amorphous thin film dielectric materials of the present invention retain their properties to well above 500° C., i.e., their amorphous to crystalline transformation occurs well above 500° C.
- Suitable deposition processes that can be employed in the present invention in forming the amorphous thin film dielectric material include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted CVD, low pressure CVD, high density plasma CVD, ionized-PVD as well as chemical solution deposition (CSD).
- CVD chemical vapor deposition
- PVD physical vapor deposition
- plasma-assisted CVD low pressure CVD
- high density plasma CVD high density plasma CVD
- ionized-PVD ionized-PVD
- a sol gel technique can also be employed in the present invention to form the amorphous thin film dielectric material of the present invention.
- the annealing step used in forming the amorphous thin film dielectric material of the present invention is conducted at a temperature of from about 150° to about 450° C. for a time period of from about 0.1 to about 4 hrs. More preferably, annealing of the amorphous dielectric material is carried out at a temperature of from about 300° to about 400° C. for a time period of from about 0.5 to about 4 hrs. Oxidizing gases such as oxygen, N 2 O, ozone or mixtures such as air may be employed in the annealing step.
- the exact conditions employed in forming the amorphous thin film dielectric material of the present invention may vary depending on the specific technique employed. The only critical limitation is that the deposition and annealing temperatures be kept below the crystalline temperature of the perovskite-type oxide.
- the term “thin film” is used herein to denote that the deposition process provides a highly conformal layer of the amorphous phase of the perovskite-type oxide.
- the thickness of the amorphous thin dielectric material ranges from about 25 to about 500 nm. More preferably, the thickness of the amorphous thin film dielectric material of the present invention is in the range of from about 50 to about 200 nm. It should be noted that the above thickness are applicable for other types of insulators that can be used in the present invention as well.
- the dielectric constant, ⁇ , of the amorphous thin film dielectric material of the present invention is about 10 or greater. More preferably, the amorphous thin film dielectric material of the present invention has a dielectric constant of from about 14 to about 50. Although the dielectric constants of the amorphous thin film dielectric material of the present invention are lower than the corresponding crystalline phase of the material, the amorphous dielectric materials of the present invention have dielectric constants which are significantly higher than the typical nitrides and oxides of silicon that are used in most integrated circuits.
- the amorphous thin film dielectric material of the present invention can be fabricated at temperatures below 450° C.; therefore, the amorphous thin film material is compatible with BEOL temperature requirements, especially when Al and Cu based metallurgies are employed.
- Metal contacts 18 are composed of any conductive metallic material including, but not limited to: Al, W, Cu, TaN, TaN/ ⁇ -Ta, or mixtures and alloys thereof. Of the various metallic materials mentioned above, it is highly preferred to utilize TaN or TaN/ ⁇ -Ta metal contacts since these materials are capable of achieving a sheet resistance of from about 3 to about 300 ohms/sq.
- the metal contacts employed in the present invention are thin films having a thickness of less than about 100 nm and the contacts are formed utilizing conventional deposition processes well known to those skilled in the art. Lithography and etching may be employed in providing patterned metal contacts.
- the wiring regions 20 are composed of the same or different conductive metal as the metal contacts, with preference given to wiring that is composed Al, W and Cu.
- the wiring region is formed utilizing conventional deposition processes well known in the art and patterning may also be achieved by lithography and etching.
- the inventive resistor designs illustrated in FIGS. 1 - 3 have low capacitive coupling to the underlying substrate of the IC (not shown) because of its distance from the substrate as compared with typical gate-level defined polysilicon resistors, as well as a small footprint area due to optimized choice of metal contact, e.g., TaN or TaN/ ⁇ -Ta, thicknesses to obtain optimum sheet resistance and therefore optimum resistor width and length.
- the resistor value is well-controlled and reproducible because the resistivity is principally a function of film thickness, which is easily controlled by the planar plasma vapor deposition prior to processing. This value is also independent of any subsequent processing such as thermal cycling.
- the above-mentioned features are in sharp contrast to a typical polysilicon resistor whose values are a function of many more factors.
- the above resistor design layouts involve patterning either a thin metal top electrode, a thin metal bottom electrode or both.
- the present invention utilizes that thin metal patterned metal as a resistor by connecting it in the manner indicated above, i.e., so that current flows laterally through the top electrode, bottom electrode or both electrodes, and any unused electrode is disconnected from the circuit.
- other discrete portions of the metal-insulator-metal film stack may be used as a high-capacity capacitor simply by proper design of the under- and overlying metal contacts to the metal wiring levels.
- a high-capacity capacitor it is highly preferred to use the above-mentioned amorphous dielectric material as the insulator.
- the present invention allows integrated R, RC, LC and RLC analog networks to be added to conventional Si-based ICs. Moreover, in some circumstances wherein TaN and TaN/ ⁇ -Ta are employed as metal contacts, resistors having a size anywhere from 50 ohm (an important value for RF and Ghz applications) up to multi-Kohm range and beyond, all with reasonable resistor length:width ratios of about 20:1, can be obtained.
- Fabrication of the resistors depicted in FIGS. 1 - 3 may be broadly accomplished through definition and planarization of metal levels through standard damascene processing, deposition and patterning of the MIM film stack, followed with inter-level insulator deposition and standard contact and wiring definition.
- the capacitor design in FIG. 1 may be formed by depositing bottom electrode 12 on the surface of a material layer, e.g., metal layer, insulator, or substrate, of an interconnect structure using the above-mentioned deposition techniques.
- the material layer of the interconnect structure is not shown in FIG. 1, but would be below the MIM film stack shown
- Insulator film 14 is then deposited, either conventionally or as described above, and top electrode 16 is formed on the material layer utilizing one of the above-mentioned deposition processes.
- the metal-insulator-metal film stack is then patterned by conventional lithography and etching, e.g., reactive-ion etching, so as to form discrete MIM film stacks on the interconnect structure. It should be noted that some of the discrete MIM film stacks may be used in the present invention as a high-capacitance capacitor, while other discrete MIM film stacks are used as resistors.
- metal contacts 18 are formed on some of the discrete MIM films stacks utilizing the above-mentioned deposition processes and the contacts may thereafter be patterned by conventional lithography and etching. Wiring regions 20 are then formed, as described above, and patterned by conventional lithography and etching. It should be noted that in the areas surrounding the metal layers and the MIM resistor film, a conventional passivating or insulating material may be formed utilizing conventional techniques well known to those skilled in the art.
- FIGS. 4A and 4B are top and side views showing an IC structure of the present invention in which the resistor design of FIG. 1 is implemented and is formed on top of the last Cu metal level.
- the IC circuit depicted in these figures includes MIM resistor 50 , MIM capacitor 52 , which are formed on a surface of interconnect structure 54 .
- Interconnect structure 54 includes wiring region 56 which is surrounded by insulator 58 .
- the MIM capacitor is formed on the wiring region of the interconnect structure and the MIM resistor is formed on the insulator layer of the interconnect structure.
- BEOL metallurgy 60 also includes BEOL metallurgy 60 , nitride cap 62 , passivation layer 64 , insulator 66 , contact 68 , and metal cap 70 which are formed utilizing conventional techniques that are well known to those skilled in the art.
- the structure shown therein is formed by first forming metal contacts 18 on the surface of wiring region 20 utilizing the above mentioned deposition and patterning processes.
- Wiring region 20 may be part of an interconnect structure or a via or metal line of a damascene structure.
- the MIM film stack is formed, as described above, and patterning is conducted to provide the discrete resistor MIM film stack.
- the resistor design of FIG. 3 is formed utilizing the same basic processes as used in forming the design layout of FIG. 2 except that metal contact 18 is part of a damascene structure and no additional contact formation is required.
- the pattern for the MIM films for the resistor may be a rectangle, a meander or a tapered section.
- the resistor is formed in the top electrode of the MIM film stack, contacts and metal wiring to the resistor are generally at the ends of the resistor in the overlying films, and the underlying metal patterns are defined so that contact is not made to the bottom electrode of the MIM resistor film stack.
- the resistor is defined in the bottom electrode, contacts and metal wires are typically defined at the ends of the resistor in the underlying films, and any overlying metal patterns are defined so that contact is not made to the top resistor electrode.
- contact may be made to the upper electrode by terminal metals themselves through appropriately defined holes in the terminal via level, See FIG. 4B.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
- This application is a continuation-in-part application of U.S. application Ser. No. 09/225,526, filed Jan. 4, 1999.
- The present invention relates to integrated circuits (ICs), and in particular to an integrated circuit which includes at least a resistor having low capacitance coupling to an underlying substrate and a controllable resistance value, said resistor comprising a discrete metal-insulator-metal (MIM) film stack in which metal contacts are in electrical connection therewith. The discrete MIM film stack of the present invention is composed of the same films as the MIM film stack of an adjacent high-capacitance capacitor. The present invention is also directed to a method of fabricating such integrated circuits and to the use of TaN or TaN/α-Ta as interconnects for such integrated circuits.
- High-capacity IC capacitors, on the order of 1 nF/mm2 or above, connected across the power supply and ground buses of modern microprocessor chips are needed to reduce the power and ground noise to an acceptable level. The high-capacity capacitors should be placed very close to the switching circuits, and be connected to the power and ground buses by a low-resistance conductor. To accomplish this goal, one preferred approach is to build the high-capacity capacitors into a BEOL (back end of the line) process.
- The dielectric thin film material for such BEOL decoupling capacitors must satisfy both of the following requirements: (1) a high dielectric constant as compared to conventional dielectrics such as SiO2 and Si3N4 (for example, a 100 nm thick film with a dielectric constant of 20 would give a capacitance of 1.8 nF/mm2); and (2) a formation temperature which is compatible with the BEOL metallurgy and processing.
- The latter criteria implies that the deposition temperature of the dielectric material used in forming the BEOL decoupling capacitor must be about 450° C. or lower. Such a low deposition temperature is required in order to avoid unwanted instability of the BEOL metallurgy used for the power and ground connections.
- Although a variety of dielectric materials having high dielectric constants are known in the art, prior art dielectrics cannot be employed in BEOL processing due to their required high deposition temperatures. An example of such a high dielectric constant material is the crystalline form of certain perovskite-type oxides. Despite having dielectric constants of about 200 or above, crystalline perovskite-type oxides are typically deposited at temperatures of about 500° C. or higher, or require a post anneal step using temperatures higher than 500° C. As such, the crystalline perovskite-type oxides such as barium strontium titanate (BSTO) cannot be employed in BEOL applications.
- In a typical integrated circuit, capacitor and resistor devices are made from separate films. The use of separate films in fabricating resistors and capacitors adds additional processing steps to the overall manufacturing process which, in turn, increases the overall cost of manufacturing the IC. A need thus exists for providing an integrated circuit which includes a resistor and a capacitor that are fabricated from the same films. Such an integrated circuit would require less processing steps than a conventional integrated circuit; therefore reducing the overall cost of manufacturing the integrated circuit.
- Moreover, an integrated circuit is needed that includes a resistor that has low capacitance coupling to the underlying substrate, as well as a small footprint area which is required to obtain optimum sheet resistance and optimum resistor width and length. Additionally, a resistor is needed that has well controllable and reproducible values which are independent of subsequent processing such as thermal cycling. Such features cannot be meet using typical diffusion- or polysilicon-resistors whose values are functions of many more factors.
- One object of the present invention is to provide an integrated circuit (IC) comprising at least a resistor that is integrated with a high-capacitance capacitor, said resistor includes a metal-insulator-metal (MIM) film stack. In the present invention, the insulator of the film stack may be a conventional dielectric material or, more preferably, it is a thin film dielectric having a dielectric constant higher than conventional dielectric materials.
- A further object of the present invention is to provide an IC that comprises an integrated resistor/high-capacitance capacitor that has low-capacitive coupling to the underlying substrate.
- A further object of the present invention is to provide an IC which comprises an integrated resistor/high-capacitance capacitor having optimum resistance.
- A yet further object of the present invention is to provide an IC comprising an integrated resistor/high-capacitance capacitor which has well controlled resistor values which are reproducible.
- An additional object of the present invention is to provide an integrated circuit wherein the resistor and capacitor are fabricated from the same films.
- These and other objects and advantages are achieved in the present invention by providing discrete MIM films stacks and by connecting one of the metal electrodes of a at least one of the discrete MIM film stacks so that current flows laterally through either the top or bottom electrode, or both, and any unused electrode is disconnected from the circuit.
- Specifically, the present invention relates to an IC comprising a resistor which is coupled to a metal wiring level of an interconnect or damascene structure through metal contacts, said resistor including a discrete metal-insulator-metal film stack, wherein said metal contacts are in contact with one of said metals of said film stack. In the present invention, the insulator of the film stack may be a conventional dielectric, e.g., SiO2, Si3N4 or Al2O3, or a high dielectric constant dielectric, such as an amorphous dielectric having a dielectric constant of 10 or greater. Combinations of various dielectric materials may also be used herein.
- In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.
- In one embodiment of the present invention, the metal contacts of the inventive IC are composed of TaN or TaN/α-Ta which have a sheet resistance of from about 3 to about 300 ohms/sq. which is significantly above the sheet resistance of typical metal contacts that are composed of Al, W, or Cu (the latter metal contacts have a sheet resistance on the order of 0.04-0.2 ohms/sq.). The use of TaN or TaN/α-Ta metal contacts in the IC design described above allows for a resistor having a size of from about 50 ohms up to the multi-Kohm range and beyond, as well as a resistor line:width ratio of about 20:1.
- In another aspect of the present invention, a method of fabricating the above-described IC structure is provided. Specifically, the method of the present invention comprises, in one embodiment, the steps of:
- (a) providing a metal-insulator-metal film stack on at least a material layer of an interconnect structure;
- (b) patterning said metal-insulator-metal film stack into discrete metal-insulator-metal film stacks;
- (c) forming metal contacts on at least one of said discrete metal-insulator-metal film stacks; and
- (d) forming a wiring region connected to said metal contacts.
- In another embodiment of the present invention, the method comprises the steps of:
- (a) forming metal contacts on a surface of a metal wiring region, said metal wiring region is part of an interconnect or damascene structure; and
- (b) forming a discrete metal-insulator-metal film stack on at least said metal contacts.
- FIG. 1 is a cross-sectional representation of one possible resistor design layout of the present invention.
- FIG. 2 is a cross-sectional representation of another possible resistor design layout of the present invention.
- FIG. 3 is a cross-sectional representation of yet another possible resistor design layout of the present invention.
- FIGS.4A-4B are pictorial representations of one possible IC structure of the present invention through various views; 4A is a top view of the inventive IC structure, and 4B is a side view. In these drawings, the resistor is formed on the top electrode of a MIM film stack.
- The present invention which provides an IC structure having a resistor made from a discrete metal-insulator-metal film stack will now be described in greater detail by referring to the drawings that accompany this application. It should be noted that in the drawings like reference numerals are used for describing like and corresponding elements.
- Referring first to FIG. 1, there is shown a cross-sectional view of one possible resistor design of the present invention. Specifically, the resistor design of FIG. 1 comprises a patterned, discrete metal-insulator-metal (MIM)
film stack 10 which includes aninsulator film 14 that is sandwiched betweenbottom electrode 12 andtop electrode 16. The inventive resistor design of FIG. 1 further includesmetal contacts 18 that are formed on at least a portion oftop electrode 16 and an overlyingmetal wiring region 20 that is formed so as to be in electrical contact withmetal contacts 18. - FIG. 2 illustrates a cross-sectional view of another inventive resistor design of the present invention. FIG. 2 is composed of the same components as in FIG. 1, but for the fact that
metal contacts 18 andwiring region 20 are formed beneath the discrete MIM film stack. - FIG. 3 shows yet another resistor design of the present invention. In this drawing, the resistor design includes patterned metal-insulator-
metal film stack 10,bottom electrode 12,insulator film 14,top electrode 16 andcontact metal 18. In this design layout, the contact metal, which may be in the form of a metal line or via, is part of a damascene structure. - It is noted that each of the above resistor design layouts represents one component of an IC structure which could be made using BEOL processes or damscene processes. Additionally, in each of the resistor design layouts shown in FIGS.1-3, the current flows laterally through either the top or bottom electrode, or both and any unused electrode of the MIM resistor is disconnected from the circuit. It should be noted that in each of the design layouts described above, the other discrete MIM film stacks may be used as resistors, or alternatively, as high-capacitance capacitors.
-
Electrodes -
Insulator film 14 may be composed of a conventional dielectric material such as SiO2, Si3N4 or Al2O3, or more preferably, it is composed of a high dielectric constant dielectric (dielectric constant greater than 10). Combinations of varies dielectric materials are contemplated herein. In one highly preferred embodiment,insulator film 14 is an amorphous high dielectric constant thin film which is composed of a perovskite-type oxide. The term “perovskite-type oxide” is used herein to denote a material which includes at least one acidic oxide containing at least one metal selected from Group IVB (Ti, Zr or Hf), VB (V, Nb or Ta), VIB (Cr, Mo or W), VIIB (Mn or Re) or IB (Cu, Ag or Au) of the Periodic Table of Elements (CAS version) and at least one additional cation having a positive formal charge of from about 1 to about 3. Such perovskite-type oxides typically have the basic formula: ABO3 wherein A is one of the above mentioned cations, and B is one of the above mentioned metals. - Suitable perovskite-type oxides include, but are not limited to: titanate-based dielectrics, manganate-based materials, cuprate-based materials, tungsten bronze-type niobates, tantalates, or titanates, and bismuth layered-tantalates, niobates or titanates. Of these perovskite-type oxides, barium strontium titanate (BSTO), barium titanate (BTO), lead zirconium titanate (PZTO), barium zirconium titanate (BZTO), tantalum titanate (TTO), lead lanthanum titanate (PLTO), barium strontium niobate, barium strontium tantalate or strontium titanate (STO) are preferred in the present invention. A highly preferred perovskite-type oxide is BSTO or BZTO.
- It is emphasized that the perovskite-type oxide employed in the present invention is preferred to be in the amorphous (or low temperature) phase since the crystalline phase of such materials is produced at temperatures which are not compatible with BEOL processing. The term “amorphous phase” is used herein to denote that the crystal structure of the perovskite-type oxide lacks order. This is different from the crystalline phase of the material wherein a highly ordered crystal structure is observed.
- The amorphous thin film dielectric material is formed by a suitable deposition process which is capable of operating at temperatures well below the crystallization temperature of the perovskite-type oxide and thereafter, the deposited material is annealed.
- Typically the temperature of deposition of the amorphous thin film dielectric material is kept below 400° C. and thus the process and the material is compatible with BEOL temperature requirements. In some applications, higher BEOL temperatures may be allowed, up to 450° C. or even 500° C. The amorphous thin film dielectric materials of the present invention retain their properties to well above 500° C., i.e., their amorphous to crystalline transformation occurs well above 500° C.
- Suitable deposition processes that can be employed in the present invention in forming the amorphous thin film dielectric material include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-assisted CVD, low pressure CVD, high density plasma CVD, ionized-PVD as well as chemical solution deposition (CSD). A sol gel technique can also be employed in the present invention to form the amorphous thin film dielectric material of the present invention.
- The annealing step used in forming the amorphous thin film dielectric material of the present invention is conducted at a temperature of from about 150° to about 450° C. for a time period of from about 0.1 to about 4 hrs. More preferably, annealing of the amorphous dielectric material is carried out at a temperature of from about 300° to about 400° C. for a time period of from about 0.5 to about 4 hrs. Oxidizing gases such as oxygen, N2O, ozone or mixtures such as air may be employed in the annealing step.
- The exact conditions employed in forming the amorphous thin film dielectric material of the present invention may vary depending on the specific technique employed. The only critical limitation is that the deposition and annealing temperatures be kept below the crystalline temperature of the perovskite-type oxide. The term “thin film” is used herein to denote that the deposition process provides a highly conformal layer of the amorphous phase of the perovskite-type oxide. Typically, the thickness of the amorphous thin dielectric material ranges from about 25 to about 500 nm. More preferably, the thickness of the amorphous thin film dielectric material of the present invention is in the range of from about 50 to about 200 nm. It should be noted that the above thickness are applicable for other types of insulators that can be used in the present invention as well.
- The dielectric constant, ε, of the amorphous thin film dielectric material of the present invention is about 10 or greater. More preferably, the amorphous thin film dielectric material of the present invention has a dielectric constant of from about 14 to about 50. Although the dielectric constants of the amorphous thin film dielectric material of the present invention are lower than the corresponding crystalline phase of the material, the amorphous dielectric materials of the present invention have dielectric constants which are significantly higher than the typical nitrides and oxides of silicon that are used in most integrated circuits. As stated above, the amorphous thin film dielectric material of the present invention can be fabricated at temperatures below 450° C.; therefore, the amorphous thin film material is compatible with BEOL temperature requirements, especially when Al and Cu based metallurgies are employed.
-
Metal contacts 18 are composed of any conductive metallic material including, but not limited to: Al, W, Cu, TaN, TaN/α-Ta, or mixtures and alloys thereof. Of the various metallic materials mentioned above, it is highly preferred to utilize TaN or TaN/α-Ta metal contacts since these materials are capable of achieving a sheet resistance of from about 3 to about 300 ohms/sq. - The metal contacts employed in the present invention are thin films having a thickness of less than about 100 nm and the contacts are formed utilizing conventional deposition processes well known to those skilled in the art. Lithography and etching may be employed in providing patterned metal contacts.
- Insofar as
wiring regions 20 are concerned, the wiring regions are composed of the same or different conductive metal as the metal contacts, with preference given to wiring that is composed Al, W and Cu. The wiring region is formed utilizing conventional deposition processes well known in the art and patterning may also be achieved by lithography and etching. - The inventive resistor designs illustrated in FIGS.1-3 have low capacitive coupling to the underlying substrate of the IC (not shown) because of its distance from the substrate as compared with typical gate-level defined polysilicon resistors, as well as a small footprint area due to optimized choice of metal contact, e.g., TaN or TaN/α-Ta, thicknesses to obtain optimum sheet resistance and therefore optimum resistor width and length. Moreover, the resistor value is well-controlled and reproducible because the resistivity is principally a function of film thickness, which is easily controlled by the planar plasma vapor deposition prior to processing. This value is also independent of any subsequent processing such as thermal cycling. The above-mentioned features are in sharp contrast to a typical polysilicon resistor whose values are a function of many more factors.
- It emphasized that the above resistor design layouts involve patterning either a thin metal top electrode, a thin metal bottom electrode or both. The present invention utilizes that thin metal patterned metal as a resistor by connecting it in the manner indicated above, i.e., so that current flows laterally through the top electrode, bottom electrode or both electrodes, and any unused electrode is disconnected from the circuit. At the same time, and as will be described in greater detail hereinbelow, other discrete portions of the metal-insulator-metal film stack may be used as a high-capacity capacitor simply by proper design of the under- and overlying metal contacts to the metal wiring levels. When a high-capacity capacitor is desired, it is highly preferred to use the above-mentioned amorphous dielectric material as the insulator.
- The present invention allows integrated R, RC, LC and RLC analog networks to be added to conventional Si-based ICs. Moreover, in some circumstances wherein TaN and TaN/α-Ta are employed as metal contacts, resistors having a size anywhere from 50 ohm (an important value for RF and Ghz applications) up to multi-Kohm range and beyond, all with reasonable resistor length:width ratios of about 20:1, can be obtained.
- Fabrication of the resistors depicted in FIGS.1-3 may be broadly accomplished through definition and planarization of metal levels through standard damascene processing, deposition and patterning of the MIM film stack, followed with inter-level insulator deposition and standard contact and wiring definition.
- Specifically, the capacitor design in FIG. 1 may be formed by depositing
bottom electrode 12 on the surface of a material layer, e.g., metal layer, insulator, or substrate, of an interconnect structure using the above-mentioned deposition techniques. The material layer of the interconnect structure is not shown in FIG. 1, but would be below the MIM film stack shownInsulator film 14 is then deposited, either conventionally or as described above, andtop electrode 16 is formed on the material layer utilizing one of the above-mentioned deposition processes. The metal-insulator-metal film stack is then patterned by conventional lithography and etching, e.g., reactive-ion etching, so as to form discrete MIM film stacks on the interconnect structure. It should be noted that some of the discrete MIM film stacks may be used in the present invention as a high-capacitance capacitor, while other discrete MIM film stacks are used as resistors. - Next,
metal contacts 18, are formed on some of the discrete MIM films stacks utilizing the above-mentioned deposition processes and the contacts may thereafter be patterned by conventional lithography and etching.Wiring regions 20 are then formed, as described above, and patterned by conventional lithography and etching. It should be noted that in the areas surrounding the metal layers and the MIM resistor film, a conventional passivating or insulating material may be formed utilizing conventional techniques well known to those skilled in the art. - FIGS. 4A and 4B are top and side views showing an IC structure of the present invention in which the resistor design of FIG. 1 is implemented and is formed on top of the last Cu metal level. Specifically, the IC circuit depicted in these figures includes
MIM resistor 50,MIM capacitor 52, which are formed on a surface ofinterconnect structure 54.Interconnect structure 54 includeswiring region 56 which is surrounded byinsulator 58. As shown in FIG. 4B, the MIM capacitor is formed on the wiring region of the interconnect structure and the MIM resistor is formed on the insulator layer of the interconnect structure. The structure in FIG. 4B also includes BEOL metallurgy 60,nitride cap 62,passivation layer 64,insulator 66, contact 68, andmetal cap 70 which are formed utilizing conventional techniques that are well known to those skilled in the art. - Insofar as the design layout of FIG. 2 is concerned, the structure shown therein is formed by first forming
metal contacts 18 on the surface ofwiring region 20 utilizing the above mentioned deposition and patterning processes.Wiring region 20 may be part of an interconnect structure or a via or metal line of a damascene structure. Next, the MIM film stack is formed, as described above, and patterning is conducted to provide the discrete resistor MIM film stack. - The resistor design of FIG. 3 is formed utilizing the same basic processes as used in forming the design layout of FIG. 2 except that
metal contact 18 is part of a damascene structure and no additional contact formation is required. - It is further noted that in the various resistor design layouts of the present invention, the pattern for the MIM films for the resistor may be a rectangle, a meander or a tapered section. Moreover, if the resistor is formed in the top electrode of the MIM film stack, contacts and metal wiring to the resistor are generally at the ends of the resistor in the overlying films, and the underlying metal patterns are defined so that contact is not made to the bottom electrode of the MIM resistor film stack. If, on the other hand, the resistor is defined in the bottom electrode, contacts and metal wires are typically defined at the ends of the resistor in the underlying films, and any overlying metal patterns are defined so that contact is not made to the top resistor electrode. In cases wherein an MIM capacitor and resistor are formed on top of the last metal level of an interconnect or damascene structure, contact may be made to the upper electrode by terminal metals themselves through appropriately defined holes in the terminal via level, See FIG. 4B.
- While this invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (22)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/757,154 US20010040271A1 (en) | 1999-01-04 | 2001-01-09 | BEOL decoupling capacitor |
US10/320,185 US20030085447A1 (en) | 1999-01-04 | 2002-12-16 | Beol decoupling capacitor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/225,526 US20010013660A1 (en) | 1999-01-04 | 1999-01-04 | Beol decoupling capacitor |
US09/757,154 US20010040271A1 (en) | 1999-01-04 | 2001-01-09 | BEOL decoupling capacitor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/225,526 Continuation-In-Part US20010013660A1 (en) | 1999-01-04 | 1999-01-04 | Beol decoupling capacitor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/320,185 Division US20030085447A1 (en) | 1999-01-04 | 2002-12-16 | Beol decoupling capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20010040271A1 true US20010040271A1 (en) | 2001-11-15 |
Family
ID=22845233
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/225,526 Abandoned US20010013660A1 (en) | 1999-01-04 | 1999-01-04 | Beol decoupling capacitor |
US09/757,154 Abandoned US20010040271A1 (en) | 1999-01-04 | 2001-01-09 | BEOL decoupling capacitor |
US10/055,704 Expired - Lifetime US6525427B2 (en) | 1999-01-04 | 2002-01-22 | BEOL decoupling capacitor |
US10/320,185 Abandoned US20030085447A1 (en) | 1999-01-04 | 2002-12-16 | Beol decoupling capacitor |
US10/323,132 Expired - Lifetime US6777809B2 (en) | 1999-01-04 | 2002-12-19 | BEOL decoupling capacitor |
US10/830,798 Abandoned US20040195694A1 (en) | 1999-01-04 | 2004-04-23 | BEOL decoupling capacitor |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/225,526 Abandoned US20010013660A1 (en) | 1999-01-04 | 1999-01-04 | Beol decoupling capacitor |
Family Applications After (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/055,704 Expired - Lifetime US6525427B2 (en) | 1999-01-04 | 2002-01-22 | BEOL decoupling capacitor |
US10/320,185 Abandoned US20030085447A1 (en) | 1999-01-04 | 2002-12-16 | Beol decoupling capacitor |
US10/323,132 Expired - Lifetime US6777809B2 (en) | 1999-01-04 | 2002-12-19 | BEOL decoupling capacitor |
US10/830,798 Abandoned US20040195694A1 (en) | 1999-01-04 | 2004-04-23 | BEOL decoupling capacitor |
Country Status (4)
Country | Link |
---|---|
US (6) | US20010013660A1 (en) |
JP (1) | JP2000200877A (en) |
KR (1) | KR100418738B1 (en) |
TW (1) | TW452857B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6432725B1 (en) * | 2001-09-28 | 2002-08-13 | Infineon Technologies Ag | Methods for crystallizing metallic oxide dielectric films at low temperature |
US6524908B2 (en) * | 2001-06-01 | 2003-02-25 | International Business Machines Corporation | Method for forming refractory metal-silicon-nitrogen capacitors and structures formed |
EP1435665A2 (en) | 2002-12-31 | 2004-07-07 | Texas Instruments Inc. | MIM capacitors and methods for fabricating same |
US7378310B1 (en) * | 2005-04-27 | 2008-05-27 | Spansion Llc | Method for manufacturing a memory device having a nanocrystal charge storage region |
US20080233704A1 (en) * | 2007-03-23 | 2008-09-25 | Honeywell International Inc. | Integrated Resistor Capacitor Structure |
US20080237800A1 (en) * | 2007-03-28 | 2008-10-02 | International Business Machiness Corporation | Integrated circuit having resistor between beol interconnect and feol structure and related method |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6384468B1 (en) * | 2000-02-07 | 2002-05-07 | International Business Machines Corporation | Capacitor and method for forming same |
US6706584B2 (en) * | 2001-06-29 | 2004-03-16 | Intel Corporation | On-die de-coupling capacitor using bumps or bars and method of making same |
US6559014B1 (en) * | 2001-10-15 | 2003-05-06 | Advanced Micro Devices, Inc. | Preparation of composite high-K / standard-K dielectrics for semiconductor devices |
US6770521B2 (en) * | 2001-11-30 | 2004-08-03 | Texas Instruments Incorporated | Method of making multiple work function gates by implanting metals with metallic alloying additives |
DE10219116A1 (en) * | 2002-04-29 | 2003-11-13 | Infineon Technologies Ag | Integrated circuit arrangement with connection layers and associated manufacturing processes |
US8182719B2 (en) * | 2003-06-11 | 2012-05-22 | Yeda Research And Development Company Ltd. | Pyroelectric compound and method of its preparation |
US20050063136A1 (en) * | 2003-09-18 | 2005-03-24 | Philofsky Elliott Malcolm | Decoupling capacitor and method |
US7245477B2 (en) * | 2003-09-18 | 2007-07-17 | Applied Ceramics Research | Decoupling capacitor and method |
US20050070097A1 (en) * | 2003-09-29 | 2005-03-31 | International Business Machines Corporation | Atomic laminates for diffusion barrier applications |
JP4243214B2 (en) * | 2004-04-12 | 2009-03-25 | パナソニック株式会社 | Semiconductor integrated circuit device, semiconductor integrated circuit device pattern generation method, semiconductor integrated circuit device manufacturing method, and semiconductor integrated circuit device pattern generation device |
DE102005035346A1 (en) * | 2004-08-19 | 2006-03-09 | Atmel Germany Gmbh | Power loss optimized high frequency coupling capacitor and rectifier circuit |
US7064043B1 (en) * | 2004-12-09 | 2006-06-20 | Texas Instruments Incorporated | Wafer bonded MOS decoupling capacitor |
US20060163731A1 (en) * | 2005-01-21 | 2006-07-27 | Keishi Inoue | Dual damascene interconnections employing a copper alloy at the copper/barrier interface |
US20060166491A1 (en) * | 2005-01-21 | 2006-07-27 | Kensaku Ida | Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process |
US7262127B2 (en) * | 2005-01-21 | 2007-08-28 | Sony Corporation | Method for Cu metallization of highly reliable dual damascene structures |
US7700984B2 (en) * | 2005-05-20 | 2010-04-20 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device including memory cell |
US20060291174A1 (en) | 2005-06-28 | 2006-12-28 | Myat Myitzu S | Embedding thin film resistors in substrates in power delivery networks |
KR100723237B1 (en) * | 2005-12-12 | 2007-05-29 | 삼성전기주식회사 | On chip decoupling capacitor, ic semiconductor device and method for manufacturing the same |
US20070152332A1 (en) * | 2006-01-04 | 2007-07-05 | International Business Machines Corporation | Single or dual damascene via level wirings and/or devices, and methods of fabricating same |
US7300868B2 (en) | 2006-03-30 | 2007-11-27 | Sony Corporation | Damascene interconnection having porous low k layer with a hard mask reduced in thickness |
US20070232062A1 (en) * | 2006-03-31 | 2007-10-04 | Takeshi Nogami | Damascene interconnection having porous low k layer followed by a nonporous low k layer |
JP2007311610A (en) * | 2006-05-19 | 2007-11-29 | Elpida Memory Inc | Semiconductor device, and its manufacturing method |
US20080096630A1 (en) * | 2006-09-13 | 2008-04-24 | Next Gaming Llc | Systems and methods for server based lottery and casino gaming machines |
KR100881182B1 (en) | 2006-11-21 | 2009-02-05 | 삼성전자주식회사 | De-coupling capacitor formed between wafers, wafer stack package comprising the same capacitor, and method of fabricating the same package |
US7701037B2 (en) * | 2007-07-31 | 2010-04-20 | International Business Machines Corporation | Orientation-independent multi-layer BEOL capacitor |
US8866260B2 (en) * | 2009-02-27 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | MIM decoupling capacitors under a contact pad |
US8455364B2 (en) * | 2009-11-06 | 2013-06-04 | International Business Machines Corporation | Sidewall image transfer using the lithographic stack as the mandrel |
CN102117699B (en) * | 2010-12-15 | 2013-04-24 | 中国科学院上海微***与信息技术研究所 | Silicon-based Al2O3 film chip capacitor and making method thereof |
US9711346B2 (en) | 2015-07-23 | 2017-07-18 | Globalfoundries Inc. | Method to fabricate a high performance capacitor in a back end of line (BEOL) |
KR20180038597A (en) * | 2016-10-06 | 2018-04-17 | 현대자동차주식회사 | Double-side cooling type power module and producing method thereof |
CN112086441A (en) * | 2020-08-26 | 2020-12-15 | 中国电子科技集团公司第十三研究所 | Passive device preparation method and passive device |
CN112899586B (en) * | 2021-01-15 | 2022-02-15 | 广东工业大学 | Manganese-based amorphous alloy and preparation method and application thereof |
Family Cites Families (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5856268B2 (en) * | 1978-12-26 | 1983-12-14 | 超エル・エス・アイ技術研究組合 | Manufacturing method of semiconductor device |
US4408254A (en) * | 1981-11-18 | 1983-10-04 | International Business Machines Corporation | Thin film capacitors |
US4638400A (en) * | 1985-10-24 | 1987-01-20 | General Electric Company | Refractory metal capacitor structures, particularly for analog integrated circuit devices |
US4786612A (en) * | 1986-02-03 | 1988-11-22 | Intel Corporation | Plasma enhanced chemical vapor deposited vertical silicon nitride resistor |
US4886502A (en) * | 1986-12-09 | 1989-12-12 | Thermedics, Inc. | Peritoneal access catheter |
DE3714672A1 (en) | 1987-05-02 | 1988-11-17 | Telefunken Electronic Gmbh | RC LINE |
JPH0279463A (en) * | 1988-09-14 | 1990-03-20 | Mitsubishi Electric Corp | Semiconductor memory |
JPH02133952A (en) | 1988-11-15 | 1990-05-23 | Seiko Epson Corp | Semiconductor device |
US4897153A (en) * | 1989-04-24 | 1990-01-30 | General Electric Company | Method of processing siloxane-polyimides for electronic packaging applications |
JPH02296361A (en) | 1989-05-11 | 1990-12-06 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
JPH03293775A (en) | 1989-12-25 | 1991-12-25 | Toshiba Corp | Ferroelectric capacitor and semiconductor device |
DE69020127T2 (en) * | 1989-12-29 | 1995-10-26 | Fujitsu Ltd | Josephson integrated circuit with a resistance element. |
US5272101A (en) * | 1990-04-12 | 1993-12-21 | Actel Corporation | Electrically programmable antifuse and fabrication processes |
US5866926A (en) * | 1990-09-28 | 1999-02-02 | Ramtron International Corporation | Ferroelectric memory device with capacitor electrode in direct contact with source region |
JPH05299601A (en) | 1992-02-20 | 1993-11-12 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
EP0571691B1 (en) * | 1992-05-27 | 1996-09-18 | STMicroelectronics S.r.l. | Metallization over tungsten plugs |
JPH0685173A (en) * | 1992-07-17 | 1994-03-25 | Toshiba Corp | Capacitor for semiconductor integrated circuit |
US5390072A (en) | 1992-09-17 | 1995-02-14 | Research Foundation Of State University Of New York | Thin film capacitors |
US5587870A (en) | 1992-09-17 | 1996-12-24 | Research Foundation Of State University Of New York | Nanocrystalline layer thin film capacitors |
US5440174A (en) * | 1992-10-20 | 1995-08-08 | Matsushita Electric Industrial Co., Ltd. | Plurality of passive elements in a semiconductor integrated circuit and semiconductor integrated circuit in which passive elements are arranged |
JP2749489B2 (en) | 1992-10-29 | 1998-05-13 | 京セラ株式会社 | Circuit board |
US5394294A (en) * | 1992-12-17 | 1995-02-28 | International Business Machines Corporation | Self protective decoupling capacitor structure |
US5258093A (en) * | 1992-12-21 | 1993-11-02 | Motorola, Inc. | Procss for fabricating a ferroelectric capacitor in a semiconductor device |
JP2550852B2 (en) * | 1993-04-12 | 1996-11-06 | 日本電気株式会社 | Method of manufacturing thin film capacitor |
US5407855A (en) * | 1993-06-07 | 1995-04-18 | Motorola, Inc. | Process for forming a semiconductor device having a reducing/oxidizing conductive material |
JP3319869B2 (en) * | 1993-06-24 | 2002-09-03 | 三菱電機株式会社 | Semiconductor storage device and method of manufacturing the same |
US5439840A (en) * | 1993-08-02 | 1995-08-08 | Motorola, Inc. | Method of forming a nonvolatile random access memory capacitor cell having a metal-oxide dielectric |
JPH0778727A (en) * | 1993-09-09 | 1995-03-20 | Toshiba Corp | Thin film capacitor |
JP3989027B2 (en) | 1994-07-12 | 2007-10-10 | テキサス インスツルメンツ インコーポレイテツド | Capacitor and manufacturing method thereof |
US5625232A (en) * | 1994-07-15 | 1997-04-29 | Texas Instruments Incorporated | Reliability of metal leads in high speed LSI semiconductors using dummy vias |
US5566045A (en) * | 1994-08-01 | 1996-10-15 | Texas Instruments, Inc. | High-dielectric-constant material electrodes comprising thin platinum layers |
US5563762A (en) | 1994-11-28 | 1996-10-08 | Northern Telecom Limited | Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an integrated circuit |
US5728603A (en) | 1994-11-28 | 1998-03-17 | Northern Telecom Limited | Method of forming a crystalline ferroelectric dielectric material for an integrated circuit |
US5576240A (en) * | 1994-12-09 | 1996-11-19 | Lucent Technologies Inc. | Method for making a metal to metal capacitor |
US5629240A (en) | 1994-12-09 | 1997-05-13 | Sun Microsystems, Inc. | Method for direct attachment of an on-chip bypass capacitor in an integrated circuit |
JP3369827B2 (en) * | 1995-01-30 | 2003-01-20 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP3160198B2 (en) * | 1995-02-08 | 2001-04-23 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Semiconductor substrate on which decoupling capacitor is formed and method of manufacturing the same |
WO1996029725A1 (en) * | 1995-03-21 | 1996-09-26 | Northern Telecom Limited | Ferroelectric dielectric for integrated circuit applications at microwave frequencies |
JPH08330519A (en) | 1995-06-01 | 1996-12-13 | Hitachi Ltd | Compound semiconductor integrated circuit device |
JP3246274B2 (en) | 1995-06-22 | 2002-01-15 | 松下電器産業株式会社 | Semiconductor device |
DE69630758T2 (en) * | 1995-09-08 | 2004-05-27 | Fujitsu Ltd., Kawasaki | Ferroelectric memory and data reading method from this memory |
KR0183739B1 (en) * | 1995-09-19 | 1999-03-20 | 김광호 | Apparatus and method of manufacturing semiconductor device including decoupling capacitor |
US5708559A (en) * | 1995-10-27 | 1998-01-13 | International Business Machines Corporation | Precision analog metal-metal capacitor |
US5736448A (en) * | 1995-12-04 | 1998-04-07 | General Electric Company | Fabrication method for thin film capacitors |
JPH09213904A (en) | 1996-02-01 | 1997-08-15 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
US5926359A (en) | 1996-04-01 | 1999-07-20 | International Business Machines Corporation | Metal-insulator-metal capacitor |
US5978207A (en) | 1996-10-30 | 1999-11-02 | The Research Foundation Of The State University Of New York | Thin film capacitor |
KR100219506B1 (en) * | 1996-12-04 | 1999-09-01 | 윤종용 | A capacitor manufacturing method of semiconductor device |
JPH10229080A (en) | 1996-12-10 | 1998-08-25 | Sony Corp | Processing method of oxide, deposition method of amorphous oxide film and amorphous tantalun oxide film |
US6146905A (en) * | 1996-12-12 | 2000-11-14 | Nortell Networks Limited | Ferroelectric dielectric for integrated circuit applications at microwave frequencies |
US6104597A (en) * | 1997-05-30 | 2000-08-15 | Kyocera Corporation | Thin-film capacitor |
TW365065B (en) * | 1997-07-19 | 1999-07-21 | United Microelectronics Corp | Embedded memory structure and manufacturing method thereof |
US6100184A (en) * | 1997-08-20 | 2000-08-08 | Sematech, Inc. | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6037644A (en) * | 1997-09-12 | 2000-03-14 | The Whitaker Corporation | Semi-transparent monitor detector for surface emitting light emitting devices |
JP3527074B2 (en) * | 1997-10-08 | 2004-05-17 | シャープ株式会社 | Display device manufacturing method |
KR100275121B1 (en) * | 1997-12-30 | 2001-01-15 | 김영환 | Method for manufacturing ferroelectric capacitor |
US6251740B1 (en) * | 1998-12-23 | 2001-06-26 | Lsi Logic Corporation | Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit |
US6441419B1 (en) * | 1998-03-31 | 2002-08-27 | Lsi Logic Corporation | Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same |
US5916823A (en) * | 1998-10-13 | 1999-06-29 | Worldwide Semiconductor Manufacturing Corporation | Method for making dual damascene contact |
US6777320B1 (en) * | 1998-11-13 | 2004-08-17 | Intel Corporation | In-plane on-chip decoupling capacitors and method for making same |
US6500724B1 (en) * | 2000-08-21 | 2002-12-31 | Motorola, Inc. | Method of making semiconductor device having passive elements including forming capacitor electrode and resistor from same layer of material |
-
1999
- 1999-01-04 US US09/225,526 patent/US20010013660A1/en not_active Abandoned
- 1999-12-22 JP JP11364510A patent/JP2000200877A/en active Pending
- 1999-12-24 TW TW088122946A patent/TW452857B/en not_active IP Right Cessation
-
2000
- 2000-01-03 KR KR10-2000-0000002A patent/KR100418738B1/en not_active IP Right Cessation
-
2001
- 2001-01-09 US US09/757,154 patent/US20010040271A1/en not_active Abandoned
-
2002
- 2002-01-22 US US10/055,704 patent/US6525427B2/en not_active Expired - Lifetime
- 2002-12-16 US US10/320,185 patent/US20030085447A1/en not_active Abandoned
- 2002-12-19 US US10/323,132 patent/US6777809B2/en not_active Expired - Lifetime
-
2004
- 2004-04-23 US US10/830,798 patent/US20040195694A1/en not_active Abandoned
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524908B2 (en) * | 2001-06-01 | 2003-02-25 | International Business Machines Corporation | Method for forming refractory metal-silicon-nitrogen capacitors and structures formed |
US6432725B1 (en) * | 2001-09-28 | 2002-08-13 | Infineon Technologies Ag | Methods for crystallizing metallic oxide dielectric films at low temperature |
EP1435665A2 (en) | 2002-12-31 | 2004-07-07 | Texas Instruments Inc. | MIM capacitors and methods for fabricating same |
EP1435665A3 (en) * | 2002-12-31 | 2008-04-30 | Texas Instruments Inc. | MIM capacitors and methods for fabricating same |
US7378310B1 (en) * | 2005-04-27 | 2008-05-27 | Spansion Llc | Method for manufacturing a memory device having a nanocrystal charge storage region |
US20080233704A1 (en) * | 2007-03-23 | 2008-09-25 | Honeywell International Inc. | Integrated Resistor Capacitor Structure |
US20080237800A1 (en) * | 2007-03-28 | 2008-10-02 | International Business Machiness Corporation | Integrated circuit having resistor between beol interconnect and feol structure and related method |
US8013394B2 (en) | 2007-03-28 | 2011-09-06 | International Business Machines Corporation | Integrated circuit having resistor between BEOL interconnect and FEOL structure and related method |
Also Published As
Publication number | Publication date |
---|---|
KR20000053364A (en) | 2000-08-25 |
KR100418738B1 (en) | 2004-02-14 |
US20010013660A1 (en) | 2001-08-16 |
US6777809B2 (en) | 2004-08-17 |
JP2000200877A (en) | 2000-07-18 |
TW452857B (en) | 2001-09-01 |
US6525427B2 (en) | 2003-02-25 |
US20040195694A1 (en) | 2004-10-07 |
US20030085447A1 (en) | 2003-05-08 |
US20020066919A1 (en) | 2002-06-06 |
US20030089943A1 (en) | 2003-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20010040271A1 (en) | BEOL decoupling capacitor | |
EP1723673B1 (en) | Method of making a semiconductor device | |
KR100284721B1 (en) | Semiconductor device | |
US7898059B2 (en) | Semiconductor device comprising passive components | |
US6940117B2 (en) | Prevention of Ta2O5 mim cap shorting in the beol anneal cycles | |
US20030011043A1 (en) | MIM capacitor structure and process for making the same | |
US7026680B2 (en) | Thin film capacitive element, method for producing same and electronic device | |
US20070290359A1 (en) | Inexpensive method of fabricating a higher performance capacitance density mimcap integrable into a copper interconnect scheme | |
US9299765B2 (en) | Altering capacitance of MIM capacitor having reactive layer therein | |
US5440174A (en) | Plurality of passive elements in a semiconductor integrated circuit and semiconductor integrated circuit in which passive elements are arranged | |
US20040135189A1 (en) | Semiconductor device | |
US7855431B2 (en) | Capacitor unit and method of forming the same | |
US20230081749A1 (en) | Integrated circuit structure including a metal-insulator-metal (mim) capacitor module and a thin-film resistor (tfr) module | |
US20220302018A1 (en) | Metal-insulator-metal (mim) capacitor and thin-film resistor (tfr) formed in an integrated circuit structure | |
US20080090376A1 (en) | Method of fabricating semiconductor device | |
KR100240647B1 (en) | Method of manufacturing a capacitor of semiconductor device | |
US6040616A (en) | Device and method of forming a metal to metal capacitor within an integrated circuit | |
US20030006480A1 (en) | MIMCap with high dielectric constant insulator | |
US7170736B2 (en) | Capacitor having low resistance electrode including a thin silicon layer | |
US7781819B2 (en) | Semiconductor devices having a contact plug and fabrication methods thereof | |
TWI232472B (en) | Metal-insulator-metal (MIM) capacitor and fabrication method for making the same | |
JPH08306862A (en) | Electrostatic capacity element for semiconductor integrated circuit and its manufacture | |
KR100723237B1 (en) | On chip decoupling capacitor, ic semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DUNCOMBE, PETER RICHARD;EDELSTEIN, DANIEL CHARLES;LAIBOWITZ, ROBERT BENJAMIN;AND OTHERS;REEL/FRAME:011476/0762;SIGNING DATES FROM 20001215 TO 20010102 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |