US20010019152A1

US20010019152A1 - Semiconductor device and method of fabricating the same

Info

Publication number: US20010019152A1
Application number: US09/814,702
Authority: US
Inventors: Hisataka Meguro
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2000-01-07
Filing date: 2001-03-23
Publication date: 2001-09-06
Also published as: US6235589B1; JP2001196476A

Abstract

Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≦a=x<c/2 is satisfied where x is the thickness of the sidewall spacers, a is a distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film, b is the thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 12-001834, filed Jan. 7, 2000, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a non-volatile semiconductor memory and, more particularly, to a semiconductor device having a memory cell array structure and a method of fabricating the same.

There is a non-volatile semiconductor memory which has a gate electrode with a miniaturized double-layer stacked structure and memory transistors. The following describes a method of fabricating a non-volatile semiconductor memory having a memory cell array structure according to one prior art.

First, as shown in FIG. 23, a

gate oxide film

12 having a thickness of, for example, 80 Å is formed on a silicon substrate 11, and a first polycrystalline silicon film 13 having a thickness of, for example, 1000 Å is formed on this gate oxide film 12. Formed on this first polycrystalline silicon film 13 is a silicon nitride film 14 with a thickness of, for example, 1500 Å, which becomes an etching mask material.

Next, as shown in FIG. 24, a

resist

14 a is formed on the silicon nitride film 14 and is then patterned by photolithography. With the patterned resist 14 a as a mask, the silicon nitride film 14 is removed by anisotropic dry etching. Thereafter, the resist 14 a is removed by wet etching.

Then, as shown in FIG. 25, with the patterned

silicon nitride film

14 as a mask, the first polycrystalline silicon film 13, the gate oxide film 12 and the silicon substrate 11 are etched to a desired depth by anisotropic dry etching, thereby forming trenches 15.

Then, as shown in FIG. 26, an

oxide film

16 having a thickness of, for example, 100 Å is formed on the exposed surfaces of the silicon substrate 11 and the first polycrystalline silicon film 13 in order to recover from the damage on the etched surface of the silicon substrate 11.

Next, a buried

insulating film

17 with a thickness of, for example, 6000 Å is formed on the entire surface, burying the trenches 15, as shown in FIG. 27. The buried insulating film 17 is then planarized to the desired height by CMP (Chemical Mechanical Polish), thus exposing the surface of the silicon nitride film 14. Thereafter, the silicon nitride film 14 is removed by wet etching, forming device regions 11 a and device isolation regions 11 b, as shown in FIG. 28.

Then, as shown in FIG. 29, a second

polycrystalline silicon film

18 having a thickness of, for example, 1000 Å is formed on the entire surface. Then, a resist 14 b is deposited on the second polycrystalline silicon film 18 and is patterned as shown in FIG. 30. With this patterned resist 14 b as a mask, the second polycrystalline silicon film 18 is removed by anisotropic dry etching, thereby forming slits 18 b, as shown in FIG. 31. Thereafter, the resist 14 b is removed.

Then, an ONO film (a multilayer film consisting of a silicon oxide film/silicon nitride film/silicon oxide film) 19 having a thickness of, for example, 120 Å is formed on is formed on the entire surface, as shown in FIG. 32. Then, as shown in FIG. 33, a third polycrystalline silicon film 20 with a thickness of, for example, 1000 Å is formed on the ONO film 19, a high-melting-point silicide film 21 with a thickness of, for example, 500 Å is formed on is formed on this third polycrystalline silicon film 20.

Thereafter, to form word lines, the high-melting-

point silicide film

21, the third polycrystalline silicon film 20, the ONO film 19, the second polycrystalline silicon film 18 and the first polycrystalline silicon film 13 are processed in order by anisotropic dry etching. Through the above procedures, memory cells (not shown) are formed.

According to this conventional non-volatile memory, a voltage of about 20 V is applied to the high-melting-

point silicide film

21, thereby generating FN (Fowler-Nordherm) current in the gate oxide film 12. As a result, electrons are injected into the first polycrystalline silicon film 13. Meanwhile, a voltage of about 20 V is applied to the silicon substrate 11, thereby generating FN current in the gate oxide film 12. Accordingly, electrons are emitted from the first polycrystalline silicon film 13.

The injection and emission of electrons are accomplished by the FN current that is generated in the

gate oxide film

12. The level of this FN current is determined by the potential of the floating gate electrode that is comprised of the first and second

polycrystalline silicon films

13 and 18. The potential of this floating gate electrode is determined by the coupling ratio of the capacitance of the gate oxide film 12 to that of the ONO film 19. That is, the coupling ratio of the capacitance of the gate oxide film 12 to that of the ONO film 19 becomes important at the time of electron injection and emission.

Given that the capacitance of the

gate oxide film

12 is C1 and the capacitance of the ONO film 19 is C2, the coupling ratio satisfies the relationship of an equation 1 below.

C=C/b 2 /(C1+C2) (1)

The capacitance C 2 of the ONO film 19 satisfies the relationship of the following equation 2:

C2=ε×S/d (2)

where S is the surface area of the

ONO film

19, d is the thickness of the ONO film 19 and ε is a dielectric constant.

To increase the potential of the floating gate electrode, the coupling ratio C given by the equation 1 should be increased. To increase the coupling ratio C, the thickness of the

ONO film

19 may be reduced or the surface area of the ONO film 19 may be increased as apparent from the equation 2.

If the ONO

film

19 becomes thinner, however, the leak current is produced. As a result, the reliability of the ONO film 19 cannot be secured. Further, the surface area of the ONO film 19 depends on the size of the opening of the slits 18 b. In the formation of the slits 18 b shown in FIG. 31, however, the demanded precision for the slits 18 b is severer than the one that can be adjusted by the state-of-the-art technology. It is therefore difficult to meet the strict size precision for the slits 18 b according to the current design rules. This makes it hard to increase the surface are of the ONO film 19.

As apparent from the above, the use of the conventional fabrication method faces a difficulty in designing miniaturized devices, and cannot provide highly reliable semiconductor devices.

BRIEF SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a semiconductor device which facilitates designing of miniaturized devices and has an improved reliability, and a method of fabricating this semiconductor device.

To achieve this object, according to one aspect of this invention, there is provided a semiconductor device comprising a trench for isolating device regions in a semiconductor substrate; a gate oxide film formed on the device regions; a first polycrystalline silicon film formed on the gate oxide film; a first insulating film for exposing an upper portion of the first polycrystalline silicon film and burying the trench; sidewall spacers comprised of a second polycrystalline silicon film formed on sides of the exposed upper portion of the first polycrystalline silicon film; and an ONO film formed on an entire surface.

In this semiconductor device, a relationship of b≦a=x<c/2 may be satisfied where x is a thickness of the sidewall spacers, a is a distance from a surface of the first insulating film to a surface of the first polycrystalline silicon film, b is a thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

The semiconductor device may further comprise a second insulating film formed between the first polycrystalline silicon film and the sidewall spacers; and recesses formed in upper portions of the sidewall spacers and an upper edge portion of the first polycrystalline silicon film.

In this modification of the semiconductor device, a relationship of b≦a=x<c/2 may be satisfied where x is a thickness of the sidewall spacers, a is a distance from a surface of the first insulating film to a surface of the first polycrystalline silicon film, b is a thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

The second insulating film may have a thickness of 20 Å to 40 Å. Further, impurities of a same kind may be doped in the first polycrystalline silicon film and the second polycrystalline silicon film.

According to another aspect of this invention, there is provided a method of fabricating a semiconductor device comprising the steps of forming a gate oxide film on a semiconductor substrate; forming a first polycrystalline silicon film on the gate oxide film; forming a first insulating film on the first polycrystalline silicon film and then patterning the first insulating film; removing the first polycrystalline silicon film and the gate oxide film with the patterned first insulating film used as a mask, thereby exposing a surface of the semiconductor substrate; removing the exposed area of the semiconductor substrate to a desired depth, thereby forming a trench in the semiconductor substrate; forming an oxide film on exposed surfaces of the semiconductor substrate and the first polycrystalline silicon film; forming a second insulating film on an entire surface, thereby burying the trench; planarizing the second insulating film, thereby exposing a surface of the first insulating film; removing the first insulating film; removing the second insulating film and the oxide film, thereby exposing an upper portion of the first polycrystalline silicon film; forming a second polycrystalline silicon film on an entire surface; removing the second polycrystalline silicon film, thereby forming sidewall spacers on sides of the first polycrystalline silicon film; and forming an ONO film on an entire surface.

In this fabrication method, a relationship of b≦a=x<c/2 may be satisfied where x is a thickness of the sidewall spacers, a is a distance from a surface of the first insulating film to a surface of the first polycrystalline silicon film, b is a thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

In this method, impurities of a same kind may be doped in the first polycrystalline silicon film and the second polycrystalline silicon film. Further, the sidewall spacers may be formed by anisotropic dry etching.

According to a still further aspect of this invention, there is provided a method of fabricating a semiconductor device comprising the steps of forming a gate oxide film on a semiconductor substrate; forming a first polycrystalline silicon film on the gate oxide film; forming a first insulating film on the first polycrystalline silicon film and then patterning the first insulating film; removing the first polycrystalline silicon film and the gate oxide film with the patterned first insulating film used as a mask, thereby exposing a surface of the semiconductor substrate; removing the exposed area of the semiconductor substrate to a desired depth, thereby forming a trench in the semiconductor substrate; forming an oxide film on exposed surfaces of the semiconductor substrate and the first polycrystalline silicon film; forming a second insulating film on an entire surface, thereby burying the trench; planarizing the second insulating film, thereby exposing a surface of the first insulating film; removing the first insulating film; removing the second insulating film and the oxide film, thereby exposing an upper portion of the first polycrystalline silicon film; forming a third insulating film in such a way as to cover the exposed upper portion of the first polycrystalline silicon film; forming a second polycrystalline silicon film on an entire surface; removing the second polycrystalline silicon film and the third insulating film, thereby forming sidewall spacers on sides of the first polycrystalline silicon film via the third insulating film; etching back parts of the sidewall spacers and the first polycrystalline silicon film, thereby forming recesses in upper portions of the sidewall spacers and an upper edge portion of the first polycrystalline silicon film; and forming an ONO film on an entire surface.

In the method, impurities of a same kind may be doped in the first polycrystalline silicon film and the second polycrystalline silicon film. Further, the sidewall spacers may be formed by anisotropic dry etching. Furthermore, the second insulating film may have a thickness of 20 Å to 40 Å.

As described above, the present invention to provide a semiconductor device which facilitates designing of miniaturized devices and has an improved reliability, and a method of fabricating this semiconductor device.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention. [0034]
FIG. 1 is a cross-sectional view of a step of fabrication of a semiconductor device according to a first embodiment of this invention; [0035]
FIG. 2 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 1; [0036]
FIG. 3 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 2; [0037]
FIG. 4 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 3; [0038]
FIG. 5 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 4; [0039]
FIG. 6 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 5; [0040]
FIG. 7 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 6; [0041]
FIG. 8 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 7; [0042]
FIG. 9 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 8; [0043]
FIG. 10 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 9; [0044]
FIG. 11 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 10; [0045]
FIG. 12 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 11; [0046]
FIG. 13 is a diagram illustrating a relationship between the height, a, of a gate electrode and the thickness, b, of a second polycrystalline silicon film according to the first embodiment of this invention; [0047]
FIG. 14 is a diagram illustrating a relationship between the thickness b of the second polycrystalline silicon film and a distance c between adjoining gate electrodes according to the first embodiment of this invention; [0048]
FIGS. 15A and 15B are diagrams showing a relationship between the height a of the gate electrode and the thickness b of the second polycrystalline silicon film according to the first embodiment of this invention; [0049]
FIG. 16 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 3; [0050]
FIG. 17 is a cross-sectional view of a step of fabrication of the semiconductor device according to the first embodiment of this invention, following the step of FIG. 4; [0051]
FIG. 18 is a cross-sectional view of a step of fabrication of a semiconductor device according to a second embodiment of this invention; [0052]
FIG. 19 is a cross-sectional view of a step of fabrication of the semiconductor device according to the second embodiment of this invention, following the step of FIG. 18; [0053]
FIG. 20 is a cross-sectional view of a step of fabrication of the semiconductor device according to the second embodiment of this invention, following the step of FIG. 19; [0054]
FIG. 21 is a cross-sectional view of a step of fabrication of the semiconductor device according to the second embodiment of this invention, following the step of FIG. 20; [0055]
FIG. 22 is a cross-sectional view of a step of fabrication of the semiconductor device according to the second embodiment of this invention, following the step of FIG. 21; [0056]
FIG. 23 is a cross-sectional view of a step of fabrication of a semiconductor device according to prior art; [0057]
FIG. 24 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 23; [0058]
FIG. 25 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 24; [0059]
FIG. 26 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 25; [0060]
FIG. 27 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 26; [0061]
FIG. 28 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 27; [0062]
FIG. 29 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 28; [0063]
FIG. 30 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 29; [0064]
FIG. 31 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 30; [0065]
FIG. 32 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 31; and [0066]
FIG. 33 is a cross-sectional view of a step of fabrication of the semiconductor device according to the prior art, following the step of FIG. 32. [0067]

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. [0068]

First Embodiment

First, as shown in FIG. 1, a [0069] gate oxide film 12 having a thickness of, for example, 80 Å is formed on the flat surface of a silicon substrate 11, and a first polycrystalline silicon film 13 having a thickness of, for example, 1500 Å is formed on this gate oxide film 12. Formed on this first polycrystalline silicon film 13 is a silicon nitride film 14 with a thickness of, for example, 1500 Å, which becomes an etching mask material.
Next, as shown in FIG. 2, a resist [0070] 14 a is formed on the silicon nitride film 14 and is then patterned by photolithography. With the patterned resist 14 a as a mask, the silicon nitride film 14 is removed by anisotropic dry etching. Thereafter, the resist 14 a is removed by wet etching.
Then, as shown in FIG. 3, with the patterned [0071] silicon nitride film 14 as a mask, the first polycrystalline silicon film 13 and the gate oxide film 12 are etched.
Then, as shown in FIG. 4, the [0072] silicon substrate 11 is etched to a desired depth by anisotropic dry etching, thereby forming trenches 15 in the silicon substrate 11. Thereafter, in order to recover from the damage on the etched surface of the silicon substrate 11, an oxide film 16 having a thickness of, for example, 100 Å is formed on the exposed surfaces of the silicon substrate 11 and the first polycrystalline silicon film 13 as shown in FIG. 5.
Next, a buried insulating [0073] film 17 with a thickness of, for example, 6000 Å is formed on the entire surface, burying the trenches 15, as shown in FIG. 6. The buried insulating film 17 is then planarized to the desired height by CMP, thus exposing the surface of the silicon nitride film 14. Thereafter, the silicon nitride film 14 is removed by wet etching, forming device regions 11 a and device isolation regions 11 b, as shown in FIG. 7.
Then, the buried insulating [0074] film 17 and the oxide film 16 are removed, thus exposing the upper portion of the first polycrystalline silicon film 13, as shown in FIG. 8. Then, as shown in FIG. 9, a second polycrystalline silicon film 18 having a thickness of, for example, 600 Å is formed on the entire surface. The second polycrystalline silicon film 18 is doped with an impurity of the same kind as the one doped in the first polycrystalline silicon film 13. Then, the second polycrystalline silicon film 18 is removed by anisotropic dry etching, thereby forming sidewall spacers 18 a on the sides of the first polycrystalline silicon film 13, as shown in FIG. 10.
Then, an [0075] ONO film 19 having a thickness of, for example, 120 Å is formed on the entire surface, as shown in FIG. 11. Then, as shown in FIG. 12, a third polycrystalline silicon film 20 with a thickness of, for example, 1000 Å is formed on the ONO film 19, a high-melting-point silicide film 21 with a thickness of, for example, 500 Å is formed on this third polycrystalline silicon film 20.
Thereafter, to form word lines, the high-melting-[0076] point silicide film 21, the third polycrystalline silicon film 20, the ONO film 19, the second polycrystalline silicon film 18 and the first polycrystalline silicon film 13 are processed in order by anisotropic dry etching. Through the above procedures, memory cells (not shown) are formed.
Referring now to FIGS. [0077] 13 to 15, a description will now be given of the conditions that maximize the thickness x of the sidewall spacers 18 a in order to secure a large surface area of the ONO film.
To begin with, the range for the thickness b of the second [0078] polycrystalline silicon film 18 will be discussed as the first condition. As shown in FIG. 13, to adequately form the sidewall spacers 18 a on the sides of the gate electrode 22 comprised of the first polycrystalline silicon film 13, the height a of the gate electrode 22 and the thickness b of the second polycrystalline silicon film 18 should satisfy the relationship of an equation 3 below.
a≧b (3)
The second condition will now be discussed. As shown in FIG. 14, when the thickness b of the second [0079] polycrystalline silicon film 18 is larger than half the distance c between the adjoining gate electrodes 22, the space between the adjoining gate electrodes 22 is buried with the second polycrystalline silicon film 18 so that those gate electrodes 22 contact each other. This therefore demands that the thickness b of the second polycrystalline silicon film 18 be smaller than half the distance c between the adjoining gate electrodes 22, as apparent from the following equation 4.
b<c/2 (4)
Now, the maximum value of the thickness x of the [0080] sidewall spacers 18 a will be discussed as the third condition. This thickness x of the sidewall spacers 18 a is determined by the thickness b of the second polycrystalline silicon film 18. As shown in FIGS. 15A and 15B, if the height a of the gate electrode 22 is set twice as high, i.e., 2 a, the second polycrystalline silicon film 18 can be formed to 2 b, double the original thickness. To maximize the thickness b of the second polycrystalline silicon film 18, therefore, the thickness b of the second polycrystalline silicon film 18 should be made equal to the height a of the gate electrode 22. That is, setting the thickness x of the sidewall spacers 18 a equal to the height a of the gate electrode 22, maximizes the thickness x of the sidewall spacers 18 a.
From the first to third conditions, therefore, the thickness x of the [0081] sidewall spacers 18 a becomes maximum when the relationship of the following equation 5 is met. This makes it possible to secure a sufficient surface area for the ONO film.
b≦a=x<c/2 (5)
Next, the height a[0082] 2 of the gate electrode 22 b and the thickness x of the sidewall spacers 18 a according to the first embodiment are calculated using the equation 5.
Assume that the height a[0083] 1 of the gate electrode 22 a according to the prior art is 0.06μ, the distance c between the adjoining gate electrodes 22 a is 0.175 μm, the wing length W of the gate electrode 22 a is 0.06 μm and the unit surface area of one wing length portion, Si, is equal to W+a1, as shown in FIG. 16. Also assume that the gate electrode 22 b according to the first embodiment has a height a2, the distance between the adjoining gate electrodes 22 b is c, the thickness of the sidewall spacers 18 a is x and the unit surface area of one sidewall spacer 18 a is S2 (=2πx/4), as shown in FIG. 17.
To secure a larger surface area for the ONO film (not shown), it is desirable to make large the surface area of the [0084] gate electrode 22 b of the first embodiment greater than that of the conventional gate electrode 22 a. From S1<S2, therefore, an equation 6 below is derived.
x>4W/π (6)
From this equation 6, the condition for the thickness x of the [0085] sidewall spacers 18 a is acquired as given by the following equation 7.
x>0.076 μm (7)
To prevent adjoining [0086] sidewall spacers 18 a from contacting each other, as indicated by the equation 5, the thickness x of the sidewall spacers 18 a is made smaller than half the distance c between the adjoining gate electrodes 22 b. Given that the distance c between the adjoining gate electrodes 22 b is 0.175 μm, therefore, the range for the thickness x of the sidewall spacers 18 a is obtained as given by the following equation 8.
0.076 μm<x<0.0875 μm (8)[0087]
From the equation 5, the height a[0088] 2 of the gate electrode 22 b is equal to the thickness x of the sidewall spacers 18 a. From this, therefore, the range for the height a2 of the gate electrode 22 b is obtained as given by an equation 9 below.
0.076 μm<a2<0.0875 μm (9)
If the distance c between the adjoining [0089] gate electrodes 22 b is set to 0.175 μm, it is apparent from the above that the height a2 of the gate electrode 22 b and the thickness x of the sidewall spacers 18 a should be set to, for example, 0.08 μm. Therefore, the unit surface area S2 in the first embodiment becomes 0.3512 μm²whereas the unit surface area S1 in the prior art was 0.34 μm². Apparently, the surface area of the ONO film can be made larger than that permitted by the prior art.
According to the first embodiment, the [0090] sidewall spacers 18 a is formed by adjusting its thickness. Unlike the prior art, therefore, this embodiment can isolate adjoining gate electrodes from each other without forming a slit therebetween while providing the fabricated device with the same device characteristics as those of the prior art. This can permit design of miniaturized devices and can thus improve the reliability of the semiconductor device fabricated.

Second Embodiment

A second embodiment is designed to be able to secure a larger surface area for the ONO film than the first embodiment. The description of those steps of the second embodiment which are the same as the corresponding steps of the first embodiment will not be repeated, and only different steps will be discussed below. [0091]
First, the buried insulating [0092] film 17 and oxide film 16 are removed as shown in FIGS. 1 to 8 as per the first embodiment, thereby exposing the upper portion of the first polycrystalline silicon film 13. Thereafter, an oxide film 23 is formed in such a way as to cover the exposed first polycrystalline silicon film 13 as shown in FIG. 18. If the thickness of the oxide film 23 is set to 20 to 40 Å, the direct current is generated, thus ensuring electric connection to the second polycrystalline silicon film 18 which will be discussed later.
Next, as shown in FIG. 19, the second [0093] polycrystalline silicon film 18 is formed on the entire surface. Then, the second polycrystalline silicon film 18 is removed by anisotropic dry etching, forming the sidewall spacers 18 a on the side of the first polycrystalline silicon film 13 via the oxide film 23, as shown in FIG. 20.
Then, as shown in FIG. 21, parts of the [0094] sidewall spacers 18 a, comprised of the second polycrystalline silicon film 18, and the first polycrystalline silicon film 13 are etched back, thus forming recesses 24 in the upper portions of the sidewall spacers 18 a and the upper edge portion of the first polycrystalline silicon film 13. The recesses 24 are illustrated in enlargement in FIG. 22. At the time of the formation of the recesses 24, the oxide film 23 is removed at the same time. The etch-back is carried out by reducing the etching rate ratio of the second polycrystalline silicon film 18 to the oxide film 23. Then, isotropic etching such as CDE (Chemical Dry Etching) or a wet process is performed.
Thereafter, as shown in FIGS. 11 and 12, the [0095] ONO film 19, the third polycrystalline silicon film 20 and the high-melting-point silicide film 21 are formed in the same manner as done in the first embodiment. Through the above procedures, memory cells (not shown) are formed.
The second embodiment has the same advantages as those of the first embodiment. In addition, the [0096] recesses 24 are formed in the upper portions of the sidewall spacers 18 a and the upper edge portion of the first polycrystalline silicon film 13. This can increase the surface area of the ONO film 19 that is to be formed in a later step.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [0097]

Claims

What is claimed is:

1. A semiconductor device comprising:

a trench for isolating device regions in a semiconductor substrate;

a gate oxide film formed on said device regions;

a first polycrystalline silicon film formed on said gate oxide film;

a first insulating film for exposing an upper portion of said first polycrystalline silicon film and burying said trench;

sidewall spacers comprised of a second polycrystalline silicon film formed on sides of said exposed upper portion of said first polycrystalline silicon film; and

an ONO film formed on an entire surface.

2. The semiconductor device according to

claim 1

, wherein a relationship of b≦a=x<c/2 is satisfied where x is a thickness of said sidewall spacers, a is a distance from a surface of said first insulating film to a surface of said first polycrystalline silicon film, b is a thickness of said second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

3. The semiconductor device according to

claim 1

, further comprising:

a second insulating film formed between said first polycrystalline silicon film and said sidewall spacers; and

recesses formed in upper portions of said sidewall spacers and an upper edge portion of said first polycrystalline silicon film.

4. The semiconductor device according to

claim 1

, further comprising:

recesses formed in upper portions of said sidewall spacers and an upper edge portion of said first polycrystalline silicon film; and

wherein a relationship of b≦a=x<c/2 is satisfied where x is a thickness of said sidewall spacers, a is a distance from a surface of said first insulating film to a surface of said first polycrystalline silicon film, b is a thickness of said second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.

5. The semiconductor device according to

claim 1

, further comprising:

wherein said second insulating film has a thickness of 20 Å to 40 Å.

6. The semiconductor device according to

claim 1

, wherein impurities of a same kind are doped in said first polycrystalline silicon film and said second polycrystalline silicon film.

7. A method of fabricating a semiconductor device comprising the steps of:

forming a gate oxide film on a semiconductor substrate;

forming a first polycrystalline silicon film on said gate oxide film;

forming a first insulating film on said first polycrystalline silicon film and then patterning said first insulating film;

removing said first polycrystalline silicon film and said gate oxide film with said patterned first insulating film used as a mask, thereby exposing a surface of said semiconductor substrate;

removing said exposed area of said semiconductor substrate to a desired depth, thereby forming a trench in said semiconductor substrate;

forming an oxide film on exposed surfaces of said semiconductor substrate and said first polycrystalline silicon film;

forming a second insulating film on an entire surface, thereby burying said trench;

planarizing said second insulating film, thereby exposing a surface of said first insulating film;

removing said first insulating film;

removing said second insulating film and said oxide film, thereby exposing an upper portion of said first polycrystalline silicon film;

forming a second polycrystalline silicon film on an entire surface;

removing said second polycrystalline silicon film, thereby forming sidewall spacers on sides of said first polycrystalline silicon film; and

forming an ONO film on an entire surface.

8. The method according to

claim 7

9. The method according to

claim 7

10. The method according to

claim 7

, wherein said sidewall spacers are formed by anisotropic dry etching.

11. A method of fabricating a semiconductor device comprising the steps of:

forming a gate oxide film on a semiconductor substrate;

forming a first polycrystalline silicon film on said gate oxide film;

removing said first insulating film;

forming a third insulating film in such a way as to cover said exposed upper portion of said first polycrystalline silicon film;

forming a second polycrystalline silicon film on an entire surface;

removing said second polycrystalline silicon film and said third insulating film, thereby forming sidewall spacers on sides of said first polycrystalline silicon film via said third insulating film;

etching back parts of said sidewall spacers and said first polycrystalline silicon film, thereby forming recesses in upper portions of said sidewall spacers and an upper edge portion of said first polycrystalline silicon film; and

forming an ONO film on an entire surface.

12. The method according to

claim 11

13. The method according to

claim 11

14. The method according to

claim 11

, wherein said sidewall spacers are formed by anisotropic dry etching.

15. The method according to

claim 11

, wherein said second insulating film has a thickness of 20 Å to 40 Å.