JPH0758221A - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory deviceInfo
- Publication number
- JPH0758221A JPH0758221A JP20243893A JP20243893A JPH0758221A JP H0758221 A JPH0758221 A JP H0758221A JP 20243893 A JP20243893 A JP 20243893A JP 20243893 A JP20243893 A JP 20243893A JP H0758221 A JPH0758221 A JP H0758221A
- Authority
- JP
- Japan
- Prior art keywords
- floating gate
- oxide film
- window
- semiconductor memory
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は不揮発性半導体記憶素子
のゲ−ト構造の改良に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of the gate structure of a non-volatile semiconductor memory device.
【０００２】[0002]
【従来の技術】現在多くの分野で利用されている不揮発
性半導体記憶素子を図１乃至図７に示す製造工程により
説明する。先ず公知の選択酸化法によりシリコン基板１
の表面付近に複数のフィ−ルド酸化膜を形成して（図１
参照）素子分離領域２として機能させる。次に図２に明
らかにするように第１ゲ−ト酸化膜３を露出するシリコ
ン基板１の表面に形成後（図２参照）、図３に示すよう
に浮遊ゲ−ト４を構成する多結晶珪素を堆積する。2. Description of the Related Art A non-volatile semiconductor memory element currently used in many fields will be described with reference to manufacturing steps shown in FIGS. First, the silicon substrate 1 is formed by a known selective oxidation method.
Forming a plurality of field oxide films near the surface of the
(See reference) Function as the element isolation region 2. Next, as shown in FIG. 2, after the first gate oxide film 3 is formed on the surface of the silicon substrate 1 (see FIG. 2), the floating gate 4 is formed as shown in FIG. Deposit crystalline silicon.
【０００３】レジスト５を利用するフォトリソグラフィ
工程（図３参照）により素子分離領域２に対応する浮遊
ゲ−ト４をパタ−ニングして（図４参照）窓６を設置し
て素子分離領域２部分を露出後、レジスト５を除去して
多結晶珪素４ならびに露出するフィ−ルド酸化膜部分に
連続する第２ゲ−ト酸化膜７を形成する。最終には制御
電極８として動作する多結晶珪素を堆積して不揮発性半
導体記憶素子ゲ−トを完成する。The floating gate 4 corresponding to the element isolation region 2 is patterned by the photolithography process using the resist 5 (see FIG. 3) (see FIG. 4) and the window 6 is installed to provide the element isolation region 2 After exposing the portion, the resist 5 is removed to form the polycrystalline silicon 4 and the second gate oxide film 7 continuous with the exposed field oxide film portion. Finally, polycrystalline silicon that operates as the control electrode 8 is deposited to complete the gate of the nonvolatile semiconductor memory element.
【０００４】[0004]
【発明が解決しようとする課題】素子分離領域２に重ね
て形成する浮遊ゲ−ト４に窓６を形成するには、ドライ
エッチング即ち異方性エッチングにより加工するが、素
子分離領域２の膜厚の段差により鋭角状になることが断
面ＴＥＭ観察により明らかになった。鋭角状の端部を備
える浮遊ゲ−トに第２ゲ−ト酸化膜７を形成すると、電
界集中が鋭角状の端部に発生して耐圧リ−ク特性が劣化
する。In order to form the window 6 in the floating gate 4 formed overlying the element isolation region 2, the window 6 is processed by dry etching, that is, anisotropic etching. It was revealed by the cross-sectional TEM observation that the thickness was changed to an acute angle. When the second gate oxide film 7 is formed on the floating gate having the acute-angled end portion, electric field concentration occurs at the acute-angled end portion, and the breakdown voltage leak characteristic deteriorates.
【０００５】一方浮遊ゲ−トを構成する多結晶珪素から
形成する酸化膜耐圧は単結晶シリコン酸化膜に比べると
表面の凹凸の影響から低下し、酸化膜の形成温度の低温
化によりこの凹凸が加速される。この結果ＴＤＤＢ特性
における真性破壊寿命の著しい低下を発生させている。On the other hand, the withstand voltage of the oxide film formed from the polycrystalline silicon forming the floating gate is lower than that of the single crystal silicon oxide film due to the effect of surface irregularities, and the irregularities are formed by lowering the oxide film formation temperature. Be accelerated. As a result, the intrinsic breakdown life of the TDDB characteristic is significantly reduced.
【０００６】従ってプロセス温度の低温化ならびに浮遊
ゲ−トの薄膜化により鋭角状の浮遊ゲ−トが特に問題に
なっている。更に第２ゲ−ト酸化膜をＣＶＤ法により堆
積することも可能であるが、凸部に堆積する膜程薄膜化
してしまい浮遊ゲ−ト端部での電界集中による耐圧リ−
ク特性の劣化や絶縁破壊が発生する。Therefore, due to the lowering of the process temperature and the thinning of the floating gate, the acute-angled floating gate becomes a particular problem. It is also possible to deposit the second gate oxide film by the CVD method, but the film deposited on the convex portion becomes thinner and the breakdown voltage is increased by the electric field concentration at the end portion of the floating gate.
Deterioration of the characteristics and insulation breakdown.
【０００７】以上のように浮遊ゲ−ト端部が鋭角状の部
分に電界集中が発生することにより耐圧リ−ク特性が劣
化すると、不揮発性記憶素子の特性にとって重要な電荷
保持特性が低下するなどの難点がある。As described above, when the breakdown voltage leak characteristic is deteriorated by the concentration of an electric field in the portion where the floating gate end has an acute angle, the charge retention characteristic, which is important for the characteristic of the non-volatile memory element, deteriorates. There are some difficulties.
【０００８】本発明はこのような事情により成されたも
ので、新規な不揮発性半導体記憶素子を提供する。The present invention has been made under these circumstances, and provides a novel nonvolatile semiconductor memory device.
【０００９】[0009]
【課題を解決するための手段】半導体基板表面付近に位
置する複数の素子分離領域と，この半導体基板の露出表
面を覆う第１ゲ−ト酸化膜と，この第１ゲ−ト酸化膜か
ら前記素子分離領域にかけて重ねる浮遊ゲ−トと，この
浮遊ゲ−ト及び前記素子分離領域部分を被覆する第２ゲ
−ト酸化膜と，この第２ゲ−ト酸化膜に積層する制御ゲ
−トと，前記素子分離領域に連続する前記第２ゲ−ト酸
化膜部分に隣接する前記浮遊ゲ−トの窓と，この窓の上
端付近を構成する稜角が９０度以上の面とに本発明に係
わる不揮発性半導体記憶素子の特徴がある。A plurality of element isolation regions located near the surface of a semiconductor substrate, a first gate oxide film covering the exposed surface of the semiconductor substrate, and the first gate oxide film from the first gate oxide film A floating gate overlaid over the element isolation region, a second gate oxide film covering the floating gate and the element isolation region portion, and a control gate overlaid on the second gate oxide film. According to the present invention, a window of the floating gate adjacent to the second gate oxide film portion continuous to the element isolation region, and a surface having an edge angle of 90 degrees or more which constitutes the vicinity of the upper end of the window. There is a feature of the nonvolatile semiconductor memory element.
【００１０】[0010]
【作用】浮遊ゲ−トに形成する窓の上端に生じる鋭角状
の形状が不揮発性半導体記憶素子の特性に影響するとの
知見を基に本発明は完成しており、この窓の上端付近を
構成する稜角を９０度以上の面を形成することにより解
決できることを確認した。The present invention has been completed based on the finding that the acute-angled shape formed at the upper end of the window formed in the floating gate affects the characteristics of the nonvolatile semiconductor memory element, and the vicinity of the upper end of the window is constructed. It was confirmed that the problem can be solved by forming a surface having a ridge angle of 90 degrees or more.
【００１１】即ち丸みを帯びた浮遊ゲ−トの窓の端部の
形成に伴って電界集中による絶縁膜の耐圧リ−ク特性低
下が防止できる。That is, it is possible to prevent the breakdown voltage of the insulating film from being deteriorated due to the electric field concentration due to the formation of the rounded floating gate window end portion.
【００１２】[0012]
【実施例】本発明に係わる実施例を図８乃至図１６を参
照して説明する。Embodiments of the present invention will be described with reference to FIGS.
【００１３】実施例１ 公知の選択酸化法によりシリコ
ン基板１０の表面付近に複数のフィ−ルド酸化膜を形成
して（図８参照）素子分離領域１１として機能させる。
次に図９に明らかにするように第１ゲ−ト酸化膜１２を
露出するシリコン基板１０の表面に形成後、図１０に示
すように浮遊ゲ−ト１３を構成する多結晶珪素を堆積す
る。Example 1 A plurality of field oxide films are formed in the vicinity of the surface of a silicon substrate 10 by a known selective oxidation method (see FIG. 8) to function as element isolation regions 11.
Next, as shown in FIG. 9, after the first gate oxide film 12 is formed on the surface of the silicon substrate 10 exposed, the polycrystalline silicon forming the floating gate 13 is deposited as shown in FIG. .
【００１４】引続いてレジスト１４を利用するフォトリ
ソグラフィ工程（図１１参照）により素子分離領域１１
に対応する浮遊ゲ−ト１３上端を露出し（図１２参
照）、浮遊ゲ−ト１３をエッチングして窓１５を設置し
て素子分離領域１１部分を露出（図１３参照）後、レジ
スト１４を除去して多結晶珪素ならびに露出するフィ−
ルド酸化膜部分に連続する第２ゲ−ト酸化膜１６を形成
する（図１４参照）。最終には制御電極１７として動作
する多結晶珪素を堆積して（図１５参照）不揮発性半導
体記憶素子ゲ−トを完成する。Subsequently, a device isolation region 11 is formed by a photolithography process using the resist 14 (see FIG. 11).
After exposing the upper end of the floating gate 13 (see FIG. 12), etching the floating gate 13 and installing a window 15 to expose the element isolation region 11 portion (see FIG. 13), the resist 14 is removed. Polysilicon that is removed and exposed
A second gate oxide film 16 continuous with the field oxide film portion is formed (see FIG. 14). Finally, polycrystalline silicon that operates as the control electrode 17 is deposited (see FIG. 15) to complete the gate of the nonvolatile semiconductor memory element.
【００１５】図１１、図１２ならびに図１３に示す工程
について詳述すると、レジスト１４を利用するフォトリ
ソグラフィ工程により素子分離領域１１に対応する浮遊
ゲ−ト１３部分に対向するレジスト１４をパタ−ニング
後（図１１参照）、レジスト１４をマスクとして浮遊ゲ
−ト１３部分に等方性エッチングができるケミカルドラ
イエッチング法により浮遊ゲ−ト１３の上端を丸める。
上端とはレジスト１４に隣接する浮遊ゲ−ト１３部分で
ある。The steps shown in FIGS. 11, 12 and 13 will be described in detail. The resist 14 facing the floating gate 13 corresponding to the element isolation region 11 is patterned by a photolithography process using the resist 14. After that (see FIG. 11), the upper end of the floating gate 13 is rounded by a chemical dry etching method capable of performing isotropic etching on the floating gate 13 portion using the resist 14 as a mask.
The upper end is a portion of the floating gate 13 adjacent to the resist 14.
【００１６】次に異方性エッチングにより浮遊ゲ−ト１
３部分に窓１５を形成して、素子分離領域１１部分を露
出する。この結果浮遊ゲ−ト１３に形成する窓１３の上
端は稜角が９０度以上の面で構成され、鋭角状の尖った
形状がなくなって丸みを帯びた形となる。この結果窓１
５上端付近は９０度以上の稜角を備えた面により構成す
ることになる。Next, the floating gate 1 is formed by anisotropic etching.
Windows 15 are formed in the three portions to expose the element isolation region 11 portion. As a result, the upper end of the window 13 formed in the floating gate 13 is formed by a surface having a ridge angle of 90 degrees or more, and the sharp shape of the acute angle disappears to form a rounded shape. This result window 1
5 The vicinity of the upper end is constituted by a surface having a ridge angle of 90 degrees or more.
【００１７】続いて形成する第２ゲ−ト酸化膜１６に積
層する制御電極１７には、不純物としてリンを含有する
多結晶珪素を堆積して構成する。The control electrode 17 laminated on the second gate oxide film 16 to be subsequently formed is formed by depositing polycrystalline silicon containing phosphorus as an impurity.
【００１８】不揮発性半導体記憶素子として完成するに
はワ−ド線が不可欠であるために、セルフアライン法に
より制御電極１７、第２ゲ−ト酸化膜１６ならびに浮遊
ゲ−ト１３の順に夫々を部分的にドライエッチングによ
る等方性エッチングを行う。また浮遊ゲ−ト１３上端の
整形に際してはケミカルドライエッチング法に代えウエ
ットエッチング法により処理することも可能である。Since the word line is indispensable for completing the nonvolatile semiconductor memory device, the control electrode 17, the second gate oxide film 16 and the floating gate 13 are sequentially formed by the self-align method. Isotropic etching is partially performed by dry etching. Further, when shaping the upper end of the floating gate 13, it is possible to use a wet etching method instead of the chemical dry etching method.
【００１９】実施例２ 浮遊ゲ−ト１３に形成する窓１
３の上端に丸みを持たせるには、表面研磨即ちポリッシ
ング法を用いて窓１５の上端を後退させることができ、
図１６がこの工程を表している。Example 2 Window 1 formed in floating gate 13
In order to make the upper end of 3 round, the upper end of the window 15 can be retracted by using a surface polishing or polishing method.
FIG. 16 shows this step.
【００２０】なお実施例１の図８乃至図１２までと、図
１４及び図１５に示す工程は実施例１と同じであり、第
１実施例の図１２に示すようにレジスト１４をパタ−ニ
ングする際にケミカルドライエッチング法中の等方性エ
ッチングで加工するのに対して、本実施例においてはレ
ジスト１４をパタ−ニング後除去してからポリッシング
法を用いて先端部分をほぼ平坦にする。引続いて異方性
エッチングにより浮遊ゲ−ト１３部分に窓１５を形成す
るのは実施例１と同じである。8 to 12 of the first embodiment and the steps shown in FIGS. 14 and 15 are the same as those of the first embodiment, and the resist 14 is patterned as shown in FIG. 12 of the first embodiment. In contrast to the isotropic etching in the chemical dry etching method, the resist 14 is removed after patterning in this embodiment, and then the tip portion is made substantially flat by the polishing method. Subsequently, the window 15 is formed in the floating gate 13 portion by anisotropic etching as in the first embodiment.
【００２１】この工程により窓１５上端付近は９０度以
上の稜角を備えた面により構成することになる。By this step, the vicinity of the upper end of the window 15 is constituted by a surface having a ridge angle of 90 degrees or more.
【００２２】[0022]
【発明の効果】以上のように浮遊ゲ−ト１３に形成する
窓１５上端の鋭角状の形状を改善することにより電界集
中を抑制でき、第２酸化膜の耐圧リ−ク特性が向上する
と共にＴＤＤＢ特性中の真性破壊寿命が改善される。更
に第２酸化膜の信頼性の向上により浮遊ゲ−トに貯えら
れた電荷の抜け量も低下させることができるために、高
品質の不揮発性半導体記憶装置が得られる。As described above, the electric field concentration can be suppressed by improving the acute-angled shape of the upper end of the window 15 formed in the floating gate 13, and the withstand voltage leak characteristic of the second oxide film is improved. The intrinsic breakdown life in the TDDB characteristic is improved. Furthermore, since the reliability of the second oxide film can be improved, the amount of charges stored in the floating gate can be reduced, so that a high-quality nonvolatile semiconductor memory device can be obtained.
【図１】従来の不揮発性半導体記憶装置の製造工程を示
す断面図である。FIG. 1 is a cross-sectional view showing a manufacturing process of a conventional nonvolatile semiconductor memory device.
【図２】図１に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG.
【図３】図２に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 2;
【図４】図３に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 4 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, which is subsequent to FIG. 3;
【図５】図４に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 4;
【図６】図５に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 5;
【図７】図６に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。FIG. 7 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, which is subsequent to FIG. 6;
【図８】本発明の不揮発性半導体記憶装置の製造工程を
示す断面図である。FIG. 8 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device of the present invention.
【図９】図８に続く不揮発性半導体記憶装置の製造工程
を示す断面図である。9 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 8;
【図１０】図９に続く不揮発性半導体記憶装置の製造工
程を示す断面図である。FIG. 10 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 9;
【図１１】図１０に続く不揮発性半導体記憶装置の製造
工程を示す断面図である。FIG. 11 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, which is subsequent to FIG. 10;
【図１２】図１１に続く不揮発性半導体記憶装置の製造
工程を示す断面図である。FIG. 12 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, which is subsequent to FIG. 11;
【図１３】図１２に続く不揮発性半導体記憶装置の製造
工程を示す断面図である。FIG. 13 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 12;
【図１４】図１３に続く不揮発性半導体記憶装置の製造
工程を示す断面図である。FIG. 14 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 13;
【図１５】図１４に続く不揮発性半導体記憶装置の製造
工程を示す断面図である。FIG. 15 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device, following FIG. 14;
【図１６】本発明の不揮発性半導体記憶装置の他の実施
例の特徴的な製造工程を示す断面図である。FIG. 16 is a cross-sectional view showing a characteristic manufacturing process of another embodiment of the nonvolatile semiconductor memory device of the present invention.
１、１０：半導体基板、 ２、１１：素子分離領域、 ３、１２：第１酸化膜、 ４、１３：浮遊ゲ−ト、 ５、１４：レジスト、 ６、１５：窓、 ７、１６：第２酸化膜、 ８、１７：制御電極、 1, 10: semiconductor substrate, 2, 11: element isolation region, 3, 12: first oxide film, 4, 13: floating gate, 5, 14: resist, 6, 15: window, 7, 16: first 2 oxide film, 8, 17: control electrode,
Claims (1)
子分離領域と，この半導体基板の露出表面を覆う第１ゲ
−ト酸化膜と，この第１ゲ−ト酸化膜から前記素子分離
領域にかけて重ねる浮遊ゲ−トと，この浮遊ゲ−ト及び
前記素子分離領域部分を被覆する第２ゲ−ト酸化膜と，
この第２ゲ−ト酸化膜に積層する制御ゲ−トと，前記素
子分離領域に連続する前記第２ゲ−ト酸化膜部分に隣接
する前記浮遊ゲ−トの窓と，この窓の上端付近を構成す
る稜角が９０度以上の面とを具備することを特徴とする
不揮発性半導体記憶素子1. A plurality of element isolation regions located near the surface of a semiconductor substrate, a first gate oxide film covering an exposed surface of the semiconductor substrate, and a region extending from the first gate oxide film to the element isolation region. An overlapping floating gate, and a second gate oxide film covering the floating gate and the element isolation region portion,
A control gate laminated on the second gate oxide film, a window of the floating gate adjacent to the second gate oxide film portion continuous to the element isolation region, and the vicinity of the upper end of this window A non-volatile semiconductor memory device having a ridge angle of 90 degrees or more
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20243893A JPH0758221A (en) | 1993-08-17 | 1993-08-17 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20243893A JPH0758221A (en) | 1993-08-17 | 1993-08-17 | Nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0758221A true JPH0758221A (en) | 1995-03-03 |
Family
ID=16457530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20243893A Pending JPH0758221A (en) | 1993-08-17 | 1993-08-17 | Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758221A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235589B1 (en) | 2000-01-07 | 2001-05-22 | Kabushiki Kaisha Toshiba | Method of making non-volatile memory with polysilicon spacers |
| KR100339420B1 (en) * | 1999-11-03 | 2002-05-31 | 박종섭 | Method for fabricating semiconductor memory device |
| US6689659B2 (en) | 2001-05-29 | 2004-02-10 | Samsung Electronics Co., Ltd. | Method of making semiconductor memory device having a floating gate with a rounded edge |
| KR100466192B1 (en) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US7348267B2 (en) * | 2005-01-13 | 2008-03-25 | Samsung Electronics Co., Ltd. | Flash memory and method of fabricating the same |
| US7445997B2 (en) | 2004-05-11 | 2008-11-04 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices having floating gate electrodes |
-
1993
- 1993-08-17 JP JP20243893A patent/JPH0758221A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100339420B1 (en) * | 1999-11-03 | 2002-05-31 | 박종섭 | Method for fabricating semiconductor memory device |
| US6235589B1 (en) | 2000-01-07 | 2001-05-22 | Kabushiki Kaisha Toshiba | Method of making non-volatile memory with polysilicon spacers |
| US6689659B2 (en) | 2001-05-29 | 2004-02-10 | Samsung Electronics Co., Ltd. | Method of making semiconductor memory device having a floating gate with a rounded edge |
| KR100466192B1 (en) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US7445997B2 (en) | 2004-05-11 | 2008-11-04 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices having floating gate electrodes |
| US7348267B2 (en) * | 2005-01-13 | 2008-03-25 | Samsung Electronics Co., Ltd. | Flash memory and method of fabricating the same |
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