US11889624B2 - Flexible printed circuit board and method of manufacturing flexible printed circuit board - Google Patents
Flexible printed circuit board and method of manufacturing flexible printed circuit board Download PDFInfo
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- 230000009975 flexible effect Effects 0.000 title claims abstract description 115
- 238000004519 manufacturing process Methods 0.000 title claims description 45
- 238000007747 plating Methods 0.000 claims description 233
- 239000007769 metal material Substances 0.000 claims description 35
- 238000009713 electroplating Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 27
- 239000010408 film Substances 0.000 description 100
- 238000005530 etching Methods 0.000 description 40
- 239000000243 solution Substances 0.000 description 26
- 239000000463 material Substances 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 239000010949 copper Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000011651 chromium Substances 0.000 description 8
- 238000010030 laminating Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- 239000000057 synthetic resin Substances 0.000 description 3
- HZAXFHJVJLSVMW-UHFFFAOYSA-N 2-Aminoethan-1-ol Chemical compound NCCO HZAXFHJVJLSVMW-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- LSNNMFCWUKXFEE-UHFFFAOYSA-M Bisulfite Chemical compound OS([O-])=O LSNNMFCWUKXFEE-UHFFFAOYSA-M 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 150000004996 alkyl benzenes Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000002216 antistatic agent Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000004811 fluoropolymer Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 239000002798 polar solvent Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- -1 polyethylene terephthalates Polymers 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
Definitions
- the present disclosure relates to a flexible printed circuit board and a method of manufacturing the flexible printed circuit board.
- Flexible printed circuit boards are widely used to constitute circuitry of various electronic devices. As the size of electronic devices has been reduced in recent years, the size of flexible printed circuit boards is significantly reduced and the density of interconnects of flexible printed circuit boards significantly increases.
- a flexible printed circuit board including a sheet-like insulating substrate and interconnects laminated to a surface of the substrate by plating has been proposed (see Patent Document 1).
- the thickness of the plating film that is, the thickness of the interconnects is made uniform.
- current lines and the like for transmitting the current for supplying power may be provided as interconnects. It is desirable that an electrical resistance of the current line is small, because it is desirable for as much current to be able to flow as possible in the current line.
- Flexible printed circuit boards are typically used by being bent at a predetermined position. Thus, it is desirable to be flexible, that is, have excellent flexibility.
- Patent Document 1 Japanese Laid-Open Patent Publication No. 2018-195681
- a flexible printed circuit board includes a base film having an insulating property, and one or more interconnects laminated to at least one surface side of the base film. At least one of the one or more interconnects includes, in a longitudinal direction, a first portion and a second portion that is a portion other than the first portion, an average thickness of the second portion being greater than an average thickness of the first portion. A ratio of the average thickness of the second portion to the average thickness of the first portion is greater than or equal to 1.5 and less than or equal to 50.
- the method includes forming one or more first plating bodies extending in the longitudinal direction by electroplating a first metallic material on a conductive underlayer of the base film by using a first resist pattern, the conductive underlayer being laminated to at least one surface side of the base film, removing the first resist pattern and non-laminated regions of the conductive underlayer where the one or more first plating bodies are not laminated after the forming one or
- the method includes forming one or more third plating bodies extending in the longitudinal direction by electroplating a third metallic material on a conductive underlayer of the base film by using a third resist pattern, the conductive underlayer being laminated to at least one surface side of the base film, removing the third resist pattern after the forming one or more third plating bodies, forming one or more fourth plating bodies extending in the longitudinal direction by electroplating
- FIG. 1 is a schematic top view illustrating a flexible printed circuit board according to a first embodiment
- FIG. 2 is a schematic end view illustrating the flexible printed circuit board illustrated in FIG. 1 viewed in the same direction as the arrow direction at the B-B line of FIG. 1 ;
- FIG. 3 is a schematic end view illustrating a modified example of a second portion viewed in the same direction as the arrow direction at the B-B line of FIG. 1 ;
- FIG. 4 is a schematic end view illustrating a modified example of the second portion viewed in the same direction as the arrow direction at the B-B line of FIG. 1 ;
- FIG. 5 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 1 and FIG. 2 , viewed in the same direction as the arrow direction at the A-A line of FIG. 1 ;
- FIG. 6 is a schematic end view for describing the method of manufacturing the flexible printed circuit board illustrated in FIG. 1 and FIG. 2 , viewed in the same direction as the arrow direction at the A-A line of FIG. 1 ;
- FIG. 7 is a schematic end view for describing the method of manufacturing the flexible printed circuit board illustrated in FIG. 1 and FIG. 2 , viewed in the same direction as the arrow direction at the A-A line of FIG. 1 ;
- FIG. 8 is a schematic end view for describing the method of manufacturing the flexible printed circuit board illustrated in FIG. 1 and FIG. 2 , viewed in the same direction as the arrow direction at the B-B line of FIG. 1 ;
- FIG. 9 is a schematic end view for describing the method of manufacturing the flexible printed circuit board illustrated in FIG. 1 and FIG. 2 , viewed in the same direction as the arrow direction at the B-B line of FIG. 1 ;
- FIG. 10 is a schematic top view illustrating a flexible printed circuit board according to a second embodiment
- FIG. 11 is a schematic end view illustrating the flexible printed circuit board illustrated in FIG. 10 viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 12 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 10 and FIG. 11 , viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 13 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 10 and FIG. 11 , viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 14 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 10 and FIG. 11 , viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 15 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 10 and FIG. 11 , viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 16 is a schematic end view for describing a method of manufacturing the flexible printed circuit board illustrated in FIG. 10 and FIG. 11 , viewed in the same direction as the arrow direction at the C-C line of FIG. 10 ;
- FIG. 17 is a schematic end view illustrating another example of a first portion and the second portion, viewed in the same direction as the arrow direction at the C-C line of FIG. 10 .
- a flexible printed circuit board is a flexible printed circuit board including a base film having an insulating property and one or more interconnects laminated to at least one surface side of the base film. At least one of the one or more interconnects includes one or more first portions and one or more second portions that are other than the one or more first portions, in a longitudinal direction of the flexible printed circuit board.
- the average thickness of the second portion is greater than the average thickness of the first portion.
- a ratio of the average thickness of the second portion to the average thickness of the first portion is greater than or equal to 1.5 and less than or equal to 50.
- the thickness of the interconnect is increased as a measure for reducing the electrical resistance of the interconnect.
- the thickness of the interconnect is increased, the flexibility of the flexible printed circuit board might be reduced.
- the thickness of the interconnect is increased too great, a mounting portion might become too thick when the flexible printed circuit board is mounted, or a connecting portion might become too thick when another circuit board is connected, so that achieving film thinning (i.e., space-savings) might be difficult.
- film thinning i.e., space-savings
- it is conceivable to increase the line width of the interconnect it is conceivable to increase the line width of the interconnect. However, if the line width of the interconnect is increased as described above, there is a possibility that space-savings cannot be achieved.
- the ratio of the average thickness of the second portion to the average thickness of the first portion is within the above-described range.
- the average thickness of the first portion is less than the average thickness of the second portion, so that the flexibility of the flexible printed circuit board can be improved.
- the average thickness of the second portion is greater than the average thickness of the first portion, so that the electrical resistance of the interconnect can be reduced.
- the average thickness of the second portion is greater than the average thickness of the first portion, so that greater space-savings of the flexible printed circuit board can be achieved in comparison with a case in which the line width of the interconnect is increased. Therefore, the flexible printed circuit board has improved flexibility, can reduce the electrical resistance, and can achieve space-savings.
- the average line width of the interconnect is preferably greater than or equal to 3 ⁇ m and less than or equal to 100 ⁇ m, and the average interval of the interconnects is preferably greater than or equal to 3 ⁇ m and less than or equal to 100 ⁇ m.
- the average line width of the interconnect and the average interval of the interconnects are within the above-described range, so that greater space-savings of the flexible printed circuit board can be achieved.
- a ratio of a minimum cross-sectional area of the second portion in the thickness direction to a minimum cross-sectional area of the first portion in the thickness direction is preferably greater than or equal to 0.5 and less than or equal to 200.
- the ratio of the minimum cross-sectional area of the second portion to the minimum cross-sectional area of the first portion is within the above-described range, so that space-savings of the flexible printed circuit board can be achieved and the electrical resistance of an entirety of the interconnect (i.e., the sum of the electrical resistances of the first portion and the second portion) can be reduced.
- a ratio of the average thickness to the minimum line width in the first portion is preferably greater than or equal to 0.3 and less than or equal to 5, and a ratio of the average thickness to the minimum line width in the second portion is preferably greater than or equal to 0.5 and less than or equal to 10.
- the ratio of the average thickness to the minimum line width in the first portion is within the above-described range
- the ratio of the average thickness to the minimum line width in the second portion is within the above-described range, so that space-savings of the flexible printed circuit board can be achieved.
- a method of manufacturing a flexible printed circuit board is a method of manufacturing a flexible printed circuit board including a base film having an insulating property and one or more interconnects laminated to at least one side surface of the base film.
- At least one interconnect includes one or more first portions and one or more second portions that are other than the one or more interconnects in the longitudinal direction.
- the average thickness of the second portion is greater than the average thickness of the first portion.
- the ratio of the average thickness of the second portion to the average thickness of the first portion is greater than or equal to 1.5 and less than or equal to 50.
- the method includes a first plating step of forming one or more first plating bodies by electroplating a first metallic material on a conductive underlayer of the base film by using a first resist pattern, the conductive underlayer being laminated to at least one side surface of the base film, a first removing step of removing the first resist pattern and non-laminated regions of the conductive underlayer where the first plating bodies are not laminated after the first plating step, a second plating step of forming one or more second plating bodies by electroplating a second metallic material on one or more portions of each of the one or more first plating bodies in the longitudinal direction by using a second resist pattern after the first removing step, and a second removing step of removing the second resist pattern after the second plating step.
- the first portion is formed as a first laminated structure including the conductive underlayer and the first plating body.
- the second portion is formed as a second laminated structure including the conductive underlayer, the first plating body, and the second plating body.
- the flexible printed circuit board described above can be manufactured. That is, the flexible printed circuit board that has improved flexibility, that can reduce the electrical resistance, and that can achieve space-savings can be manufactured.
- a method of manufacturing a flexible printed circuit board is a method of manufacturing a flexible printed circuit board including a base film having an insulating property and one or more interconnects laminated to at least one side surface of the base film.
- At least one interconnect includes one or more first portions and one or more second portions that are portions other than the one or more first portions in the longitudinal direction.
- the average thickness of the second portion is greater than the average thickness of the first portion.
- a ratio of the average thickness of the second portion to the average thickness of the first portion is greater than or equal to 1.5 and less than or equal to 50.
- the method includes a third plating step of forming one or more third plating bodies extending in the longitudinal direction by electroplating a third metallic material on a conductive underlayer of the base film by using a third resist pattern, the conductive underlayer being laminated to at least one side surface of the base film, a third removing step of removing the third resist pattern after the third plating step, a fourth plating step of forming one or more fourth plating bodies that extend in the longitudinal direction by electroplating a fourth metallic material so as to at least include non-laminated regions of the conductive underlayer where the third plating bodies are not laminated and connect the third plating bodies in the longitudinal direction by using a fourth resist pattern after the third removing step, and the average thickness of the fourth plating body being greater than the average thickness of the third plating body, a fourth removing step of removing the fourth resist pattern and the non-laminated regions of the conductive underlayer where the third plating bodies and the fourth plating bodies are not laminated after the fourth plating method.
- the first portion
- the “average thickness” indicates an average of the thickness measured at any ten points of each of the first portion and the second portion in a single interconnect.
- the “thickness” indicates a distance between the base film and a top edge of the interconnect in a direction normal to the base film.
- the “line width” indicates the dimension in a direction perpendicular to the longitudinal direction in a single interconnect.
- the “interval” indicates a distance between adjacent surfaces of two interconnects facing each other, and the “average interval” indicates a value obtained by measuring the distances between respective adjacent surfaces at multiple positions in the longitudinal direction of the interconnect, and calculating an average value of the measurement results.
- the “average line width” indicates a value obtained by measuring the maximum width of the interconnect at multiple positions in the longitudinal direction, in a cross section perpendicular to the longitudinal direction of the interconnect, and calculating an average value of the measurement results.
- the “minimum cross-sectional area” indicates a minimum value of a cross-sectional area perpendicular to the longitudinal direction of each of the first portion and the second portion in a single interconnect.
- the “minimum line width” indicates a minimum value of the line width of each of the first portion and the second portion in a single interconnect.
- a land portion including a via (a through-hole, a blind via, and a field via) for connecting between interconnects, a land portion connected to mounting components, a land portion used for connecting to another printed circuit board or a connector, and the like will be excluded from measuring the “thickness,” the “line width,” the “interval”, and the “cross-sectional area” specified above.
- the “interconnect” corresponds to a “wiring layer”.
- a “front surface side” refers to a side in the thickness direction of the base film where the interconnects are laminated, and the front and the back in the embodiment is not meant to determine the front and the back when the flexible printed circuit board is used.
- a flexible printed circuit board 10 mainly includes a base film 3 having an insulating property and interconnects 11 laminated to one side (i.e., the front surface side) of the base film 3 .
- the flexible printed circuit board 10 may further include a cover film on the front surface side of the base film 3 or the interconnects 11 .
- the base film 3 is a layer made of a synthetic resin having an insulating property.
- the base film 3 also has a flexible property.
- the base film 3 is also a substrate for forming the interconnects 11 .
- a material of forming the base film 3 a low dielectric constant synthetic resin film formed as a sheet may be employed, although the material is not particularly limited as long as the base film is made of a material having an insulating property and a flexible property.
- a main component of the synthetic resin film include polyimides, polyethylene terephthalates, liquid crystal polymers, fluoropolymers, and the like.
- the term “main component” indicates a component contained with the highest percentage and, for example, a component occupying 50 mass % or more of forming materials.
- the base film 3 may contain another resin other than example resins such as polyimides, and may contain antistatic agents and the like.
- the lower limit of the average thickness of the base film 3 is not particularly limited, but is preferably 3 ⁇ m, more preferably 5 ⁇ m, and even more preferably 10 ⁇ m.
- the upper limit of the average thickness of the base film 3 is not particularly limited, but is preferably 200 ⁇ m, more preferably 150 ⁇ m, and even more preferably 100 ⁇ m. If the average thickness of the base film 3 is below the lower limit, the insulation strength and mechanical strength of the base film 3 might be insufficient. If the average thickness of the base film 3 exceeds the upper limit, the flexible printed circuit board 10 might become unnecessarily thick.
- the “average thickness” indicates an average of the thickness measured at any 10 points, as described above.
- the interconnect 11 is laminated directly or through another layer on the front surface side of the base film 3 .
- the interconnect 11 includes multiple first portions 11 a in the longitudinal direction (i.e., the left and right direction in FIG. 1 and FIG. 2 ) and a second portion 11 b that is a portion other than the first portion 11 a and that has an average thickness H 2 greater than an average thickness H 1 of the first portion 11 a .
- the ratio of the average thickness H 2 of the second portion 11 b to the average thickness H 1 of the first portion 11 a is greater than or equal to 1.5 and less than or equal to 50.
- the interconnect 11 includes a first conductive underlayer 13 laminated to the front surface side of the base film 3 and a first plating layer 15 laminated to the first conductive underlayer 13 on a side opposite to the base film 3 (i.e., the front surface side) and multiple second plating layers 17 partially laminated to the first plating layer 15 on a side opposite to the first conductive underlayer 13 (i.e., the front surface side) in the longitudinal direction.
- a first laminated structure including the first conductive underlayer 13 and the first plating layer 15 constitutes the first portion 11 a .
- a second laminated structure including the first conductive underlayer 13 , the first plating layer 15 , and the second plating layer 17 constitutes the second portion 11 b .
- Examples of the interconnect 11 include a signal line for transmitting a signal, a current line for supplying a current for power supply, and a current line for supplying a current for generating a magnetic field.
- FIG. 2 illustrates that the interconnect 11 is disposed only on one side of the base film 3 , but it is more preferable that the interconnect 11 is disposed on each side of the base film 3 to achieve greater space-savings.
- the material forming the first conductive underlayer 13 examples include copper (Cu), silver (Ag), gold (Au), nickel (Ni), titanium (Ti), chromium (Cr), alloys of these materials, and the like.
- the first conductive underlayer 13 includes a layer (i.e., a first layer) that contains at least one selected from a group consisting of nickel, chromium, titanium, and silver on a side being in contact with the base film 3 (e.g., polyimides).
- the first conductive underlayer 13 includes a layer (i.e., the first layer) that contains at least one selected from nickel and chromium that are easily removable and that easily maintain an insulating property. Additionally, it is more preferable that the first conductive underlayer 13 includes a layer (i.e., a second layer) having copper as a main material on an upper side of the first inner layer (i.e., a side opposite to the base film 3 ). The layer having copper as a main material is disposed, so that the work time required when the interconnect 11 is formed by electroplating can be shortened.
- the lower limit of the average thickness of the first layer is preferably 1 nm and more preferably 2 nm.
- the upper limit of the average thickness of the first layer is preferably 15 nm and more preferably 8 nm. If the average thickness is below the lower limit, thermal degradation of the adhesive force of the interconnect 11 to the base film 3 might not be easily suppressed. If the average thickness exceeds the upper limit, the first layer might not be easily removable and the insulating property between the interconnects 11 may not be sufficiently maintained.
- the first layer may be formed by a sputtering method, an electroplating method, an electroless plating method, or the like.
- the lower limit of the average thickness of the second layer is preferably 0.1 ⁇ m and more preferably 0.2 ⁇ m.
- the upper limit of the average thickness of the second layer is preferably 2 ⁇ m and more preferably 1 ⁇ m. If the average thickness is below the lower limit, the work time required for forming the interconnects 11 by electroplating might be excessively long. If the average thickness exceeds the upper limit, the second layer might not be easily removable and the insulating property between the interconnects 11 might not be sufficiently maintained.
- the second layer is preferably formed by a sputtering method, an electroplating method, an electroless plating method, or the like, and may be formed by combining these methods.
- an electroless copper plating layer is disposed on a top surface side of the first conductive underlayer 13 , so that when the inner layer is formed by a sputtering method, any defect or the like that may be caused by the sputtering method can be covered.
- the first conductive underlayer 13 is formed such that the line width of a region where the second plating layer 17 is laminated is less than the line width of another region.
- the first metallic material for forming the first plating layer 15 examples include copper, aluminum, silver, gold, nickel, an alloy of these materials, and the like. Among these materials, copper or a copper alloy are preferable from the viewpoint of improving conductivity and reducing cost.
- the first plating layer 15 is formed in the same shape as the first conductive underlayer 13 viewed in a direction perpendicular to the base film 3 .
- Examples of a second metallic material for forming the second plating layer 17 include a material similar to the first metallic material. It is preferable that the second metallic material is of the same kind as the first metallic material.
- the line width of the second plating layer 17 may be the same as or different from the line width of non-laminated region of the first plating layer 15 where the second plating layer 17 is not laminated, viewed in a direction perpendicular to the base film 3 .
- the line width of the second plating layer 17 is preferably greater than the line width of the non-laminated region because the electrical resistance of an entirety of the interconnect 11 can be reduced.
- the lower limit of the average line width L 1 of the interconnect 11 is preferably 3 ⁇ m, more preferably 5 ⁇ m, and even more preferably 10 ⁇ m.
- the upper limit of the average line width L 1 of the interconnect 11 is preferably 100 ⁇ m, more preferably 75 ⁇ m, and even more preferably 50 ⁇ m. If the average line width L 1 of the interconnect 11 is below the lower limit, the mechanical strength of the interconnect 11 might be insufficient. If the average line width L 1 of the interconnect 11 exceeds the upper limit, there is a possibility that sufficient space-savings cannot be achieved.
- the “average line width” is a value obtained by exposing a cross-section of the flexible printed circuit board 10 by using a cross-sectional processing device such as a microtome, measuring the width at multiple positions in the interconnect 11 by using a measuring microscope or the like that can measure the length of a widest portion in the width, and calculating an average value of measured values.
- the “average line width” of other members and the like is also measured in substantially the same manner.
- the lower limit of the average interval S 1 of the interconnects 11 is preferably 3 ⁇ m, more preferably 5 ⁇ m, and even more preferably 10 ⁇ m.
- the upper limit of the average interval S 1 of the interconnects 11 is preferably 100 ⁇ m, more preferably 75 ⁇ m, and even more preferably 50 ⁇ m. If the average interval S 1 of the interconnects 11 is below the lower limit, a short circuit might occur. If the average interval S 1 of the interconnects 11 exceeds the upper limit, there is a possibility that sufficient space-savings cannot be achieved.
- the “average interval” is a value obtained by exposing a cross-section of the flexible printed circuit board 10 by using a cross-sectional processing device such as a microtome, measuring the distances between respective interconnects 11 at multiple positions by using a microscope or the like that can measure the smallest distance, and calculating an average value of measured results.
- a cross-sectional processing device such as a microtome
- the first plating layer 15 and the second plating layer 17 are much thicker than the first conductive underlayer 13 .
- the thickness of the first portion 11 a can be determined mainly by the thickness of the first plating layer 15 .
- the thickness of the second portion 11 b can be determined mainly by the thickness of the first plating layer 15 and the second plating layer 17 .
- the average thickness H 1 of the first portion 11 a can be suitably set so that the ratio of the average thickness H 2 of the second portion 11 b to the average thickness H 1 of the first portion 11 a is greater than or equal to 1.5 and less than or equal to 50.
- the lower limit of the average thickness H 1 of the first portion 11 a is preferably 3 ⁇ m, more preferably 5 ⁇ m, and even more preferably 10 ⁇ m.
- the upper limit of the average thickness H 1 of the first portion 11 a is preferably 30 ⁇ m, more preferably 25 ⁇ m, and even more preferably 20 ⁇ m. If the average thickness H 1 is below the lower limit, the mechanical strength of the first portion 11 a might be insufficient.
- the “average thickness” is a value obtained for each given first portion 11 a by exposing a cross-section of the flexible printed circuit board 10 by using a cross-section processing device such as a microtome, measuring the thickness obtained by cross-section observations at any ten points in the given first portion 11 a , and calculating an average value of the measurement results.
- the “average thickness” of other members and the like is a value measured in substantially the same manner.
- the lower limit of the ratio of the average thickness H 1 to the minimum line width (which is not illustrated) of the first portion 11 a is preferably 0.3, more preferably 0.5, and even more preferably 0.7.
- the upper limit of the ratio is preferably 5, more preferably 2, and even more preferably 1.0. If the ratio is below the lower limit, there is a possibility that sufficient space-savings cannot be achieved. If the ratio exceeds the upper limit, there is a possibility that sufficient space-savings cannot be achieved.
- the “minimum line width” is a value obtained for each given first portion 11 a by exposing the cross-section of the flexible printed circuit board 10 by using a cross-section processing device such as a microtome, and measuring the width by using a microscope or the like that can measure the length of a narrowest portion of the given first portion 11 a of the interconnect 11 .
- the “minimum line width” is the width of the narrowest portion in a region excluding any defective region of the first portion 11 a .
- the defective region to be removed from regions to be measured is a region that is recessed inward (or missing) from at least one edge in the width direction when the microscope observation is performed as described above.
- the defective region is a region in which the width of a missing portion at maximum is 1 ⁇ 4 or more of the average line width of the other regions (i.e., regions other than the defective region) in the longitudinal direction of the first portion 11 a .
- the average line width is measured in a manner similar to the method of measuring the “average line width” described above.
- the “minimum line width” of other members and the like is also measured in substantially the same manner.
- the minimum line width of the first portion 11 a may be suitably set to satisfy, for example, the aspect ratio described above.
- the lower limit of the minimum line width of the first portion 11 a is preferably 3 ⁇ m, more preferably 5 ⁇ m, and even more preferably 10 ⁇ m.
- the upper limit of the minimum line width of the first portion 11 a is preferably 30 ⁇ m, more preferably 25 ⁇ m, and even more preferably 20 ⁇ m. If the minimum line width is below the lower limit, the mechanical strength of the first portion 11 a might be insufficient. If the minimum line width exceeds the upper limit, there is a possibility that sufficient space-savings cannot be achieved.
- the minimum cross-sectional area in the thickness direction of the first portion 11 a may be suitably set so that the ratio of the minimum cross-sectional area in the thickness direction of the second portion 11 b to the minimum cross-sectional area in the thickness direction of the first portion 11 a (i.e., the minimum cross-sectional area of the second portion 11 b /the minimum cross-sectional area of the first portion 11 a ) is within a predetermined range.
- the lower limit of the ratio for example, is preferably 0.5, and more preferably 0.7.
- the upper limit of the ratio is preferably 200, and more preferably 20. If the ratio is below the lower limit, the electrical resistance of the interconnect 11 might become excessively large.
- the line width of the second portion 11 b might be relatively too great to achieve sufficient space-savings.
- the “minimum cross-sectional area” is calculated by multiplying the average thickness H 1 by the minimum line width. In the following, the “minimum cross-sectional area” of other members and the like is measured in substantially the same manner.
- the average thickness H 2 of the second portion 11 b can be suitably set so that the ratio of the average thickness H 2 of the second portion 11 b to the average thickness H 1 of the first portion 11 a described above is greater than or equal to 1.5 and less than or equal to 50.
- the lower limit of the average thickness H 2 of the second portion 11 b is preferably 5 ⁇ m, more preferably 10 ⁇ m, and even more preferably 20 ⁇ m.
- the upper limit of the average thickness H 2 of the second portion 11 b is preferably 100 ⁇ m, more preferably 75 ⁇ m, and even more preferably 50 ⁇ m. If the average thickness H 2 is below the lower limit, the electrical resistance of the interconnect 11 might become excessively large. If the average thickness H 2 exceeds the upper limit, it might be necessary to increase the line width in order to form the second portion 11 b , and there is a possibility that sufficient space-savings cannot be achieved.
- the lower limit of the ratio of the average thickness H 2 to the minimum line width (which is not illustrated) of the second portion 11 b is preferably 0.5, more preferably 1, and even more preferably 2.
- the upper limit of the ratio is preferably 10, more preferably 7, and even more preferably 5. If the ratio is below the lower limit, there is a possibility that sufficient space-savings cannot be achieved. If the ratio exceeds the upper limit, there is also a possibility that the interconnect 11 will easily deform or become broken during formation of the interconnect 11 or at a step after the formation of the interconnect 11 in manufacturing the flexible printed circuit board 10 .
- the minimum line width of the second portion 11 b may be suitably set to satisfy, for example, the aspect ratio described above.
- the lower limit of the minimum line width of the second portion 11 b is preferably 5 ⁇ m, more preferably 10 ⁇ m, and even more preferably 15 ⁇ m.
- the upper limit of the minimum line width of the second portion 11 b is preferably 100 ⁇ m, more preferably 75 ⁇ m, and even more preferably 50 ⁇ m. If the minimum line width is below the lower limit, the mechanical strength of the second portion 11 b might be insufficient. If the minimum line width exceeds the upper limit, there is a possibility that sufficient space-savings cannot be achieved.
- the minimum cross-sectional area of the second portion 11 b in the thickness direction may be suitably set so that the ratio of the minimum cross-sectional area of the second portion 11 b to the minimum cross-sectional area of the first portion 11 a in the thickness direction is within the predetermined range as described above.
- the lower limit of the ratio of the average thickness H 2 of the second portion 11 b to the average thickness H 1 of the first portion 11 a is 1.5 as described above, preferably 2, and more preferably 3.
- the upper limit of the ratio is 50 as described above, and preferably 20, and more preferably 5. If the ratio is below the lower limit, there is a possibility that the electrical resistance of the entirety of the interconnect cannot be reduced. Additionally, there is a possibility that the flexibility cannot be improved. Further, there is a possibility that sufficient space-savings cannot be achieved. If the ratio exceeds the upper limit, there is also a possibility that sufficient space-savings cannot be achieved.
- a longitudinal cross-sectional shape (i.e., a cross-sectional shape in the longitudinal direction) of a region in the second portion 11 b located above the first portion 11 a that is, a longitudinal cross-sectional shape of ends (i.e., boundaries) of the second plating layer 17 that are adjacent to the first portions 11 a is not particularly limited, and can be suitably set.
- the shape of the end may be rectangular.
- the longitudinal cross-sectional shape of lower end edges 11 b ′a at boundaries of the second portion 11 b ′ may be a curved shape.
- This shape can be formed by treating the second portion 11 b ′ with a chemical that can etch the second portion 11 b ′. Since the longitudinal cross-sectional shape of the lower end edges 11 b ′a is a curved shape, breakage due to stress caused by temperature change and breakage due to external force generated when the insulating layer is formed on the flexible printed circuit board 10 can be prevented.
- a curved shape may include, for example, an arc shape having a radius of curvature R.
- the lower limit of the radius of the curvature R is preferably 0.2 ⁇ m, more preferably 0.5 ⁇ m, and even more preferably 1.0 ⁇ m.
- the upper limit of the radius of the curvature R is preferably 4 ⁇ m, more preferably 3 ⁇ m, and even more preferably 2 ⁇ m. If the radius of the curvature R is below the lower limit, it might be difficult to reduce the above-mentioned stress and external force, and it might be difficult to prevent the above-mentioned breakage. If the radius of the curvature R exceeds the upper limit, treatment to form the arc shape might cause the interconnect 11 to be etched entirely, and as a result, an electrical resistance of the entirety of the interconnect 11 might increase.
- a longitudinal cross-sectional shape of upper end edges 11 b ′′b at the boundaries of the second portion 11 b may be a curved shape.
- This shape can be formed by treating the second portion 11 b ′′ with a chemical that can etch the second portion 11 b ′′. Since the longitudinal cross-sectional shape of the upper edge 11 b ′′b is a curved shape, breakage due to stress caused by temperature change and breakage due to external force generated when the insulating layer is formed on the flexible printed circuit board 10 can be prevented.
- a curved shape may include, for example, an arc shape having a radius of curvature r.
- the lower limit of the radius of the curvature r is preferably 0.2 ⁇ m, more preferably 0.5 ⁇ m, even more preferably 1.0 ⁇ m.
- the upper limit of the radius of the curvature r is preferably 4 ⁇ m, more preferably 3 ⁇ m, and even more preferably 2 ⁇ m. If the radius of the curvature r is below the lower limit, it might be difficult to reduce the above-mentioned stress and external force, and it might be difficult to prevent the above-mentioned breakage. If the radius of the curvature r exceeds the upper limit, treatment to form the arc shape might cause the interconnect 11 to be etched entirely, and as a result, an electrical resistance of the entirety of the interconnect 11 might increase.
- the ratio of the average thickness H 2 of the second portion 11 b of the interconnect 11 to the average thickness H 1 of the first portion 11 a of the interconnect 11 is greater than or equal to 1.5 and less than or equal to 50.
- the average thickness H 1 of the first portion 11 a is less than the average thickness H 2 of the second portion 11 b , so that the flexibility of the flexible printed circuit board 10 can be improved.
- the average thickness H 2 of the second portion 11 b is greater than the average thickness H 1 of the first portion 11 a , the electrical resistance of the interconnect 11 can be reduced.
- the average thickness H 2 of the second portion 11 b is greater than the average thickness H 1 of the first portion 11 a , so that more space-savings of the flexible printed circuit board 10 can be achieved in comparison with a case in which the line width of the interconnect 11 is increased.
- the flexible printed circuit board 10 has improved flexibility, can reduce the electrical resistance, and can achieve space-savings.
- FIGS. 5 to 7 are schematic end views for describing the manufacturing method, viewed in the same direction as the arrow direction at the A-A line of FIG. 1 .
- FIGS. 8 and 9 are schematic end views for describing the manufacturing method, viewed in the same direction as the arrow direction at the B-B line of FIG. 1 .
- the direction normal to the paper surface of FIGS. 5 to 7 and the left and right direction of FIGS. 8 and 9 are in the longitudinal direction.
- the method of manufacturing the flexible printed circuit board 10 includes a first plating step of forming multiple first plating bodies X 1 by electroplating the first metallic material on a conductive underlayer M of the base film 3 by using a first resist pattern R 1 , the conductive underlayer M being laminated to one surface side (i.e., a front surface side) of the base film 3 , a first removing step of removing the first resist pattern R 1 and non-laminated regions of the conductive underlayer M where the first plating body X 1 is not laminated after the first plating step, a second plating step of forming multiple second plating bodies X 2 by electroplating the second metallic material on multiple regions of the first plating body X 1 in the longitudinal direction by using a second resist pattern R 2 after the first removing step, and a second removing step of removing the second resist pattern R 2 after the second plating step.
- the first portion 11 a is formed as a first laminated structure including a portion of the conductive underlayer M (i.e., the first conductive underlayer 13 ) and the first plating body X 1 .
- the second portion 11 b is formed as a second laminated structure including a portion of the conductive underlayer M (i.e., the first conductive underlayer 13 ), the first plating body X 1 , and the second plating body X 2 .
- the conductive underlayer M is laminated to the front surface side of the base film 3 .
- the conductive underlayer M is previously laminated to the entire surface of the base film 3 on the front surface side.
- a portion of the conductive underlayer M i.e., the first conductive underlayer 13 ) is ultimately provided such that the portion of the conductive underlayer M is sandwiched between the base film 3 and the first plating body X 1 of the first portion 11 a in the interconnect 11 .
- Examples of a material of forming the conductive underlayer M include copper (Cu), silver (Ag), gold (Au), nickel (Ni), titanium (Ti), chromium (Cr), alloys of these materials, and the like.
- the conductive underlayer M includes a layer (i.e., a first layer) containing at least one selected from a group consisting of nickel, chromium, titanium, and silver on a side being in contact with the base film 3 (e.g., polyimides) in order to suppress thermal degradation of the adhesion force of the interconnect 11 to the base film 3 .
- the conductive underlayer M includes a layer (i.e., the first layer) containing at least one selected from nickel and chromium that are easily removable and that easily maintain an insulating property. Additionally, it is more preferable that the conductive underlayer M includes a layer mainly composed of copper (i.e., a second layer) on the upper side of the first inner layer (i.e., a side opposite to the base film 3 ). By providing the layer mainly composed of copper, the work time required for forming the interconnect 11 by electroplating can be shortened.
- the lower limit of the average thickness of the first layer is preferably 1 nm and more preferably 2 nm.
- the upper limit of the average thickness of the first layer is preferably 15 nm and more preferably 8 nm. If the average thickness of the first layer is below the lower limit, it might be difficult to suppress thermal degradation of the adhesion force of the interconnect 11 to the base film 3 . If the average thickness of the first layer exceeds the upper limit, the first layer might not be easily removable, and there is a possibility that the insulating property between the interconnects 11 cannot be sufficiently maintained.
- the first layer may be formed by a sputtering method, an electroplating method, an electroless plating method, or the like.
- the lower limit of the average thickness of the second layer is preferably 0.1 ⁇ m and more preferably 0.2 ⁇ m.
- the upper limit of the average thickness of the second layer is preferably 2 ⁇ m and more preferably 1 ⁇ m. If the average thickness of the second layer is below the lower limit, the time required for forming the interconnects 11 by electroplating might be excessively long. If the average thickness of the second layer exceeds the upper limit, the second layer might not be easily removable and there is a possibility that the insulating property between the interconnects 11 cannot be sufficiently maintained.
- the second layer is preferably formed by a sputtering method, an electroplating method, an electroless plating method, or the like, or may be formed by combining these methods.
- an electroless copper plating layer is disposed on a top surface side of the conductive underlayer M, so that any defect or the like that may be caused by a sputtering method when the inner layer is formed by the sputtering method can be covered.
- the first plating step includes a first resist pattern forming step of forming the first resist pattern R 1 on the front surface of the conductive underlayer M and a first plating body forming step of forming multiple first plating bodies X 1 by electroplating the first metallic material on the conductive underlayer M by using the formed first resist pattern R 1 .
- the first resist pattern R 1 is formed on the front surface of the conductive underlayer M as illustrated in FIG. 5 .
- the first resist pattern R 1 having a predetermined pattern is formed by laminating a resist film, such as a photosensitive film, on the front surface of the conductive underlayer M and exposing and developing the laminated resist film.
- a method of laminating the resist film include a method of applying a resist composition to the front surface of the conductive underlayer M and a method of laminating a dry film photoresist to the front surface of the conductive underlayer M.
- the exposure and development condition of the resist film may be adjusted depending on the resist composition to be used or the like.
- An opening of the first resist pattern R 1 may be suitably set depending on the first plating bodies X 1 to be formed, that is, the conductive underlayer M of the interconnect 11 .
- first plating bodies forming step multiple first plating bodies X 1 extending in the longitudinal direction are formed on regions of the conductive underlayer M where the resist pattern R 1 is not laminated as illustrated in FIG. 6 by electroplating the first metallic material while energizing the conductive underlayer M.
- the first removing step includes a first stripping step of stripping the first resist pattern R 1 from the conductive underlayer M and a first etching step of etching non-laminated regions (i.e., unnecessary regions) of the conductive underlayer M where the first plating bodies X 1 are not laminated.
- the first resist pattern R 1 is stripped from the conductive underlayer M.
- a stripping solution a known solution can be used.
- an alkaline aqueous solution such as sodium hydroxide and potassium hydroxide
- an organic acid solution such as alkylbenzene sulfonic acid
- compound liquid of an organic amine such as ethanolamine and a polar solvent, or the like can be used.
- the conductive underlayer M is etched using the first plating bodies X 1 as a mask.
- a laminated structure in which the first plating bodies X 1 are laminated to the base film 3 through the first conductive underlayer 13 as illustrated in FIG. 7 can be obtained.
- an etching solution that erodes the metal forming the conductive underlayer M is used.
- a semi-additive method is preferably used in the manufacturing process.
- the second plating step includes a step of forming the second resist pattern R 2 so as to cover the exposed base film 3 and regions on the first plating bodies X 1 to which the second plating bodies X 2 is not to be laminated after the first removing step, and a second plating body forming step of forming the second plating bodies X 2 on each of the first plating bodies X 1 by electroplating the second metallic material on multiple regions of each of the first plating bodies X 1 in the longitudinal direction by using the formed second resist pattern R 2 .
- the second resist pattern R 2 having a predetermined pattern is formed by laminating a resist film, such as a photosensitive film, so as to cover an entirety of the exposed base film 3 , the first conductive underlayer 13 , and the first plating bodies X 1 , and exposing and developing regions to which the second plating bodies X 2 is to be laminated in the laminated resist film.
- a method of laminating the resist film include a method of applying a resist composition so as to cover the entirety, and a method of laminating a dry film photoresist to the entirety. The exposure and development condition of the resist film can be adjusted depending on the resist composition to be used or the like.
- the second resist pattern R 2 masks regions on the first plating body X 1 to which the second plating body X 2 is not to be laminated (here, regions in which the line width is larger than the line width of other regions).
- An opening of the second resist pattern R 2 can be suitably set depending on the second plating body X 2 to be formed, that is, the second plating layer 17 of the second portion 11 b .
- the height of the second resist pattern R 2 can be suitably set in accordance with the height of the second portion 11 b.
- the second plating bodies X 2 are formed on each of the first plating bodies X 1 so as to partially cover the first plating body X 1 in the longitudinal direction (i.e., the left and right direction in FIG. 9 ) and partially cover the first conductive underlayer 13 , by electroplating the second metallic material while energizing the first plating bodies X 1 by using the second resist pattern R 2 , as illustrated in FIG. 9 .
- the second resist pattern R 2 is removed from the base film 3 .
- the second resist pattern R 2 is stripped from the base film 3 .
- the stripping solution may be similar to the stripping solution used in the first stripping step described above.
- a first laminated structure formed by the first conductive underlayer 13 and the first plating layer 15 constitutes the first portion 11 a
- a second laminated structure formed by the first conductive underlayer 13 , the first plating layer 15 , and the second plating layer 17 constitutes the second portion 11 b.
- the manufacturing method by further adding a step of dissolving a portion including the lower end edge at a boundary adjacent to the first portion 11 a in the formed second plating body X 2 (i.e., the second plating layer 17 of the second portion 11 b ) with the etching solution after the second removal step, the ability to enable flow of the etching solution at the lower end edge is reduced relative to the ability to enable flow around the lower end edge, and the etching rate is reduced.
- the etching solution used in this step is similar to the etching solution used in the above-described first etching step.
- the manufacturing method may further include an upper end edge dissolving step of partially dissolving the upper end edge at the boundary adjacent to the first portion 11 a in the formed second plating body X 2 (i.e., the second plating layer 17 of the second portion 11 b ) after the second removal step.
- the ability to enable flow of the etching solution at the lower end edge is improved relative to the ability to enable flow around the upper end edge by further adding a step of dissolving a portion including the upper end edge at the boundary with the etching solution, thereby increasing the etching rate.
- the etching solution used in the upper end edge dissolving step is similar to the etching solution used in the above-described first etching step.
- the flexible printed circuit board 10 described above can be manufactured. That is, the flexible printed circuit board 10 that has improved flexibility, that can reduce the electrical resistance, and that can achieve space-savings can be manufactured.
- a flexible printed circuit board 20 mainly includes the base film 3 having an insulating property and an interconnect 21 laminated to one side (i.e., the front surface side) of the base film 3 .
- the flexible printed circuit board 20 may further include a cover film on the front surface side of the base film 3 or the interconnects 21 .
- the interconnect 21 is laminated directly or through another layer to the front surface side of the base film 3 .
- the interconnect 21 includes, in the longitudinal direction, a first portion 21 a and a second portion 21 b that is a portion other than the first portion 21 a and that have an average thickness H 21 greater than an average thickness H 11 of the first portion 21 a .
- a ratio of the average thickness H 21 of the second portion 21 b to the average thickness H 11 of the first portion 21 a is greater than or equal to 1.5 and less than or equal to 50.
- the interconnect 21 includes a second conductive underlayer 23 laminated to the front surface side of the base film 3 , multiple third plating layers 25 laminated to multiple regions of the second conductive underlayer 23 , in the longitudinal direction on a side opposite to the base film 3 (i.e., the front surface side) and multiple fourth plating layers 27 connecting to the third plating layers 25 in the longitudinal direction (i.e., the left and right direction in FIG. 10 and FIG. 11 ) on the side of the second conductive underlayer 23 opposite to the base film 3 (i.e., the front surface side).
- a third laminated structure including the second conductive underlayer 23 and the third plating layer 25 constitutes the first portion 21 a .
- a fourth laminated structure including the second conductive underlayer 23 and the fourth plating layer 27 constitutes the second portion 21 b .
- the interconnect 21 include a signal line for transmitting a signal, a current line for supplying the current for power supply, and a current line for supplying the current for generating a magnetic field.
- a material of forming the second conductive underlayer 23 may be similar to the material of forming the first conductive underlayer 13 according to the first embodiment described above.
- the average thickness of the second conductive underlayer 23 can be set as the thickness similar to the average thickness of the first conductive underlayer 13 of the first embodiment described above.
- a third metallic material of forming the third plating layer 25 may be similar to the first metallic material according to the first embodiment described above, for example.
- the line width of the third plating layer 25 can be set to be the same as the line width of the second conductive underlayer 23 , for example.
- a fourth metallic material of forming the fourth plating layer 27 may be similar to the first metallic material according to the first embodiment described above, for example.
- the fourth metallic material is preferably of the same kind as the third metal material.
- the line width of the fourth plating layer 27 can be set to be the same as the line width of the second conductive underlayer 23 .
- the average line width L 11 and the average interval S 11 of the interconnects 21 can be set in a manner similar to the average line width L 1 and the average interval S 1 of the interconnects 11 of the first embodiment described above.
- the third plating layer 25 and the fourth plating layer 27 are much thicker than the second conductive underlayer 23 .
- the thickness of the first portion 21 a can be determined mainly by the thickness of the third plating layer 25 .
- the thickness of the second portion 21 b can be determined mainly by the thickness of the fourth plating layer 27 .
- the average thickness H 11 of the first portion 21 a , the ratio of the average thickness H 11 to the minimum line width (which is not illustrated) of the first portion 21 a (i.e., the aspect ratio), the minimum line width of the first portion 21 a , the minimum cross-sectional area of the first portion 21 a in the thickness direction, and the like can be set in a manner similar to the first portion 11 a of the first embodiment described above.
- the average thickness H 21 of the second portion 21 b , the ratio of the average thickness H 21 to the minimum line width (which is not illustrated) of the second portion 21 b (i.e., the aspect ratio), the minimum line width of the second portion 21 b , the minimum cross-sectional area of the second portion 21 b in the thickness direction, and the like can be set in a manner similar to the second portion 11 b of the first embodiment described above.
- lower end edges 21 b ′a at boundaries adjacent to the first portions 21 a in the second portion 21 b ′ may have a curved shape as illustrated in FIG. 3 .
- upper end edges 21 b ′′b at boundaries adjacent to the first portions 21 a in the second portion 21 b ′′ may be a curved shape as illustrated in FIG. 4 above.
- the ratio of the average thickness H 21 of the second portion 21 b to the average thickness H 11 of the first portion 21 a can be set in a similar manner to the ratio of the average thickness H 2 of the second portion 11 b to the average thickness H 1 of the first portion 11 a of the above described first embodiment. That is, the lower limit of the ratio is 1.5, preferably 2, and more preferably 3, as described above. The upper limit of the ratio is 50, preferably 20, and more preferably 5, as described above. Similarly with the above-described first embodiment, when the interconnect 21 includes the multiple first portions 21 a , the average thickness H 11 of each of the first portions 21 a is set so as to satisfy the ratio with respect to the average thickness H 21 of each of the second portions 21 b .
- the average thickness H 21 of each of the second portions 21 b is set so as to satisfy the ratio with respect to the average thickness H 11 of the first portion 21 a (i.e., the average thickness H 11 of each of the first portions 21 a when multiple first portions 21 a are included).
- the ratio of the average thickness H 21 of the second portion 21 b to the average thickness H 11 of the first portion 21 a of the interconnect 21 is greater than or equal to 1.5 and less than or equal to 50.
- the average thickness H 11 of the first portion 21 a is less than the average thickness H 21 of the second portion 21 b , so that the flexibility of the flexible printed circuit board 20 can be improved.
- the average thickness H 21 of the second portion 21 b is greater than the average thickness H 11 of the first portion 21 a , so that the electrical resistance of the interconnect 21 can be reduced.
- the average thickness H 21 of the second portion 21 b is greater than the average thickness H 11 of the first portion 21 a , so that more space-savings of the flexible printed circuit board 20 can be achieved in comparison with a case in which the line width of the interconnect 21 is increased. Therefore, the flexible printed circuit board 20 has improved flexibility, can reduce electrical resistance, and can achieve space-savings.
- FIGS. 12 to 16 are schematic end views for illustrating the manufacturing method, viewed in the same direction as the arrow direction at the C-C line of FIG. 10 .
- the left and right direction of FIGS. 12 to 16 is the longitudinal direction.
- a method of manufacturing the flexible printed circuit board 20 includes a third plating step of forming multiple third plating bodies X 3 extending in the longitudinal direction by electroplating the third metallic material on the conductive underlayer M of the base film 3 by using a third resist pattern R 3 , the conductive underlayer M being laminated to one side (i.e., the front surface side) of the base film 3 , a third removing step of removing the third resist pattern R 3 after the third plating step, a fourth plating step of forming multiple fourth plating bodies X 4 extending in the longitudinal direction by electroplating the fourth metallic material so as to include at least a non-laminated region of the conductive underlayer M where the third plating bodies X 3 are not laminated and longitudinally connect to both end edges of the third plating bodies X 3 in the longitudinal direction by using a fourth resist pattern R 4 after the third removing step, the average thickness of the fourth plating body X 4 being greater than the average thickness of the third plating body X 3 , and a fourth removing
- the first portion 21 a is formed as a third laminated structure including a portion of the conductive underlayer M (i.e., the second conductive underlayer 23 ) and the third plating body X 3 .
- the second portion 21 b is formed as a fourth laminated structure including a portion of the conductive underlayer M (i.e., the second conductive underlayer 23 ) and the fourth plating body X 4 .
- the conductive underlayer M may be similar to the conductive underlayer M used in the first embodiment described above. Therefore, the detailed description of the conductive underlayer M is omitted.
- the third plating step includes a third resist pattern forming step of forming the third resist pattern R 3 on the front surface of the conductive underlayer M and a third plating body forming step of forming the multiple third plating bodies X 3 extending in the longitudinal direction by electroplating the third metallic material on the conductive underlayer M by using the formed third resist pattern R 3 .
- the third resist pattern R 3 is formed on the front surface of the conductive underlayer M as illustrated in FIG. 12 .
- the third resist pattern R 3 having a predetermined pattern is formed in a manner similar to the first resist pattern forming step according to the first embodiment.
- the third resist pattern R 3 can be suitably set in accordance with the third plating bodies X 3 to be formed.
- the third plating bodies X 3 extending in the longitudinal direction are formed with intervals in the width direction on regions of the conductive underlayer M where the third resist pattern R 3 is not laminated as illustrated in FIG. 13 by electroplating the third metallic material while energizing the conductive underlayer M.
- the third resist pattern R 3 is removed from the conductive underlayer M. Specifically, the third resist pattern R 3 is stripped from the conductive underlayer M.
- the stripping solution is similar to the stripping solution used in the first stripping step of the first embodiment. By this removal, a laminated structure in which the third plating body X 3 is laminated to the conductive underlayer M as illustrated in FIG. 14 can be obtained.
- the fourth plating step includes a forth resist pattern forming step of forming the fourth resist pattern R 4 so as to cover the exposed conductive underlayer M and the third plating bodies X 3 after the third removing step described above, and a fourth plating body forming step of forming the fourth plating bodies X 5 extending in the longitudinal direction by electroplating the fourth metallic material by using the formed fourth resist pattern R 4 .
- the fourth resist pattern R 4 is formed on the third plating bodies X 3 as illustrated in FIG. 16 .
- the fourth resist pattern R 4 having a predetermined pattern is formed by laminating a resist film such as a photosensitive film so as to cover the entirety of the exposed conductive underlayer M and the third plating bodies X 3 , and exposing and developing regions of the laminated resist film that include at least a non-laminated region where the third plating bodies X 3 are not laminated and that connect to third plating bodies X 3 in the longitudinal direction (i.e., the left and right direction in FIG. 13 ).
- a method of laminating the resist film is similar to the method of forming the first resist pattern according to the first embodiment described above.
- the fourth resist pattern R 4 can be suitably set in accordance with a position of the fourth plating layer 27 of the interconnect 21 to be formed.
- the height of the fourth resist pattern R 4 can be suitably set to be greater than the height of the third resist pattern R 3 in accordance with the height of the fourth plating layer 27 of the interconnect 21 .
- the multiple fourth plating bodies X 4 that connect both end edges of the respective third plating bodies X 3 in the longitudinal direction and that extend in the longitudinal direction are formed so as to longitudinally connect both end edges of the respective third plating bodies X 3 in the longitudinal direction (i.e., the left and right direction in FIG. 16 ) that are disposed on non-laminated regions of the conductive underlayer M where the fourth plating bodies X 4 are not laminated as illustrated in FIG. 16 by electroplating the fourth metallic material while energizing the conductive underlayer M.
- the fourth removing step includes a second stripping step of stripping the fourth resist pattern R 4 from the conductive underlayer M, and a second etching step of etching non-laminated regions (i.e., unnecessary region) of the conductive underlayer M where the third plating bodies X 3 and the fourth plating bodies X 4 are not laminated.
- the fourth resist pattern R 4 is stripped from the conductive underlayer M.
- the stripping solution is similar to the striping solution used in the first stripping step according to the first embodiment described above.
- the conductive underlayer M is etched using the third plating bodies X 3 and the fourth plating bodies X 4 as a mask.
- a third laminated structure (corresponding to the first portion 21 a ) in which the second conductive underlayer 23 and the third plating body X 3 (corresponding to the third plating layer 25 ) are laminated to the base film 3 is obtained.
- a fourth laminated structure (corresponding to the second portion 21 b ) in which the second conductive underlayer 23 and the fourth plating body X 4 (corresponding to the fourth plating layer 27 ) are laminated to the base film 3 is obtained.
- an etching solution that erodes the metal forming the second conductive underlayer 23 is used.
- the manufacturing method may further include a lower end edge dissolving step of dissolving a portion including the lower end edge at the boundary adjacent to the first portion 21 a in the formed fourth plating body X 4 (that is, the fourth plating layer 27 of the second portion 21 b ) with the etching solution after the fourth removal step, which reduces the ability to enable flow of the etching solution at the lower end edge relative to the ability to enable flow around the lower end edge, thereby reducing the etching rate.
- the etching solution used in the lower end edge dissolving step is similar to the etching solution used in the second etching step.
- the lower end edge may be dissolved by controlling the etching amount in the second etching step in the fourth removing step.
- the manufacturing method may further include an upper end edge dissolving step of partially dissolving the upper end edge at the boundary adjacent to the first portion 21 a in the formed fourth plating body X 4 (that is, the fourth plating layer 27 of the second portion 21 b ) with an etching solution after the fourth removing step.
- the etching solution used in the upper end edge dissolving step is similar to the etching solution used in the second etching step above.
- the upper end edge may be dissolved by controlling the etching amount in the second etching step in the fourth removing step.
- the flexible printed circuit board 20 described above can be manufactured. That is, the flexible printed circuit board 20 that has improved flexibility, that can reduce the electrical resistance, and that can achieve space-savings can be manufactured.
- a flexible printed circuit board including a single base film and multiple interconnects laminated to one side of the base film has been described, but the flexible printed circuit board may be a flexible printed circuit board in which multiple interconnects are laminated to both sides of the single base film.
- the flexible printed circuit board may also be a multi-layer printed circuit board including multiple base films each having multiple interconnects on either one side or both sides.
- the flexible printed circuit board includes multiple interconnects
- the flexible printed circuit board may include a single interconnect.
- the line width of the first portion is the same as the line width of the second portion has been described, but these line widths may be different.
- the line width of the first portion may be greater than the line width of the second portion.
- the line width of the second portion may be greater than the line width of the first portion.
- rectangular portions viewed in a direction perpendicular to the base film 3 may be used.
- the interconnect may include a single first portion and a single second portion, may include multiple first portions and a single second portion, and may include multiple first portions and multiple second portions.
- the line width of the first portion may be greater than the line width of the second portion.
- the line width of the region where the second plating layer 17 is formed in the longitudinal direction is less than another region has been described.
- the line width of the region may be the same as or greater than the line width of another region.
- the second resist pattern R 2 masks only a region of the first plating body X 1 in the longitudinal direction
- the second resist pattern may also mask a region between regions to which the second plating body X 2 is to be laminated in addition to the region of the first plating body X 1 described above.
- the first portion 21 a and the second portion 21 b may be partially overlapped as illustrated in FIG. 17 .
- the structure can be manufactured by modifying a region of the resist pattern R 4 illustrated in FIG. 15 . Even if the position of the resist pattern R 2 is misaligned in manufacturing, this can enable manufacturing of the interconnect 11 without breaking the interconnect, can improve manufacturing yield, and can reduce distortion at the boundary between the first portion 21 a and the second portion 21 b . Therefore, the structure described above is more preferable.
- the flexible printed circuit board according to the embodiments of the present disclosure and a flexible printed circuit board manufactured by a method of manufacturing the flexible printed circuit board, has improved flexibility, can reduce the electrical resistance, and can achieve space-savings. Therefore, the flexible printed circuit board can be suitably used, for example, in small electronic devices.
Abstract
Description
Claims (9)
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JP2020003239A JP2021111711A (en) | 2020-01-10 | 2020-01-10 | Flexible printed wiring board and manufacturing method thereof |
JP2020-003239 | 2020-01-10 |
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US20210219425A1 US20210219425A1 (en) | 2021-07-15 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000012991A (en) | 1998-06-18 | 2000-01-14 | Nitto Denko Corp | Circuit board forming member having variable thickness conductor layer and circuit board using the same |
JP2004014672A (en) | 2002-06-05 | 2004-01-15 | Toppan Printing Co Ltd | Substrate for semiconductor device and its manufacturing method |
US20090025963A1 (en) * | 2005-02-09 | 2009-01-29 | Nitto Denko Corporation | Wired circuit board and production method thereof |
JP2018195681A (en) | 2017-05-16 | 2018-12-06 | 住友電気工業株式会社 | Substrate for printed wiring board and method for manufacturing printed wiring board |
US20210212208A1 (en) * | 2018-06-01 | 2021-07-08 | Nitto Denko Corporation | Wiring circuit board |
-
2020
- 2020-01-10 JP JP2020003239A patent/JP2021111711A/en active Pending
- 2020-12-18 US US17/126,339 patent/US11889624B2/en active Active
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012991A (en) | 1998-06-18 | 2000-01-14 | Nitto Denko Corp | Circuit board forming member having variable thickness conductor layer and circuit board using the same |
JP2004014672A (en) | 2002-06-05 | 2004-01-15 | Toppan Printing Co Ltd | Substrate for semiconductor device and its manufacturing method |
US20090025963A1 (en) * | 2005-02-09 | 2009-01-29 | Nitto Denko Corporation | Wired circuit board and production method thereof |
JP2018195681A (en) | 2017-05-16 | 2018-12-06 | 住友電気工業株式会社 | Substrate for printed wiring board and method for manufacturing printed wiring board |
US10548217B1 (en) | 2017-05-16 | 2020-01-28 | Sumitomo Electric Industries, Ltd. | Base material for printed interconnect boards and manufacturing method of printed interconnect boards |
US20210212208A1 (en) * | 2018-06-01 | 2021-07-08 | Nitto Denko Corporation | Wiring circuit board |
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US20210219425A1 (en) | 2021-07-15 |
JP2024038334A (en) | 2024-03-19 |
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