US11348512B2 - Pixel and display device having the same - Google Patents

Pixel and display device having the same Download PDF

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Publication number
US11348512B2
US11348512B2 US16/881,738 US202016881738A US11348512B2 US 11348512 B2 US11348512 B2 US 11348512B2 US 202016881738 A US202016881738 A US 202016881738A US 11348512 B2 US11348512 B2 US 11348512B2
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transistor
scan
node
electrically connected
turned
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US20210125543A1 (en
Inventor
Na Young Kim
Dong Hwi Kim
Jin Jeon
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JEON, JIN, KIM, DONG HWI, KIM, NA YOUNG
Publication of US20210125543A1 publication Critical patent/US20210125543A1/en
Priority to US17/740,965 priority Critical patent/US11682344B2/en
Application granted granted Critical
Publication of US11348512B2 publication Critical patent/US11348512B2/en
Priority to US18/315,263 priority patent/US20230282161A1/en
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Definitions

  • Embodiments relate to a display device, and, to a pixel and a display device including the pixel.
  • a display device may include pixels.
  • Each of the pixels may include transistors, a light-emitting element electrically coupled or electrically connected to the transistors, and a capacitor.
  • the transistors may be turned on in response to respective signals provided through lines, and a predetermined driving current may be generated by the turned-on transistors.
  • the light-emitting element may emit light in response to the driving current.
  • this background of the technology section is, in part, intended to provide useful background for understanding the technology.
  • this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein.
  • Embodiments are directed to a pixel which may periodically apply a bias to a driving transistor during low-frequency driving.
  • Embodiments are directed to a display device that has the pixel and that is driven at various driving frequencies.
  • An embodiment may provide for a pixel for a display device.
  • the pixel may include a light-emitting element, a first transistor that may include a first electrode electrically connected to a first node electrically connected to a first power source, and controls a driving current based on a voltage of a second node, a second transistor that may be electrically connected between a data line and the first node, and may be turned on in response to a first scan signal supplied through a first scan line, a third transistor that may be electrically connected between the second node and a third node electrically connected to a second electrode of the first transistor, and may be turned on in response to the first scan signal, and a fourth transistor that may be turned on in response to a second scan signal supplied through a second scan line and may apply a bias voltage to the first transistor.
  • the fourth transistor may be turned on at a first frequency
  • the second transistor and the third transistor may be turned on at a second frequency different from the first frequency.
  • the second frequency may be lower than the first frequency.
  • the second frequency may be identical to an image refresh rate and may be an aliquot of the first frequency.
  • the pixel may further include a fifth transistor that may be electrically connected between the first power source and the first node and may be turned off in response to an emission control signal supplied through an emission control line, a sixth transistor that may be electrically connected between the third node and a fourth node electrically connected to a first electrode of the light-emitting element, and may be turned off in response to the emission control signal, a seventh transistor that may be electrically connected between the fourth node and a first initialization power source, and may be turned on in response to the second scan signal, an eighth transistor that may be electrically connected between the second node and a second initialization power source, and may be turned on in response to a third scan signal supplied through a third scan line, and a storage capacitor electrically connected between the first power source and the second node.
  • a fifth transistor that may be electrically connected between the first power source and the first node and may be turned off in response to an emission control signal supplied through an emission control line
  • a sixth transistor that may be electrically connected between the third node and
  • the fifth to seventh transistors may be turned off at the first frequency, and the eighth transistor may be turned on at the second frequency.
  • the fourth transistor may be electrically connected between the emission control line and the third node, and may apply the emission control signal, as the bias voltage, to the third node in response to the second scan signal.
  • the fourth transistor may be electrically connected between the emission control line and the first node, and may apply the emission control signal, as the bias voltage, to the third node in response to the second scan signal.
  • the fourth transistor may be electrically connected between a bias power source and the third node or between the bias power source and the first node, and may apply a voltage of the bias power source, as the bias voltage, to the third node or the first node in response to the second scan signal.
  • An embodiment may provide for a pixel of a display device.
  • the pixel may include a light-emitting element, a first transistor that may include a first electrode electrically connected to a first node electrically connected to a first power source, and controls a driving current based on a voltage of a second node, a second transistor that may be electrically connected between a data line and the first node, and may be turned on in response to a first scan signal supplied through a first scan line, a third transistor that may be electrically connected between the second node and a third node electrically connected to a second electrode of the first transistor, and may be turned on in response to a second scan signal supplied through a second scan line, and a fourth transistor that may be turned on in response to a third scan signal supplied through a third scan line and may apply a bias voltage to the first transistor.
  • the fourth transistor may be turned on at a first frequency
  • the second transistor and the third transistor may be turned on at a second frequency lower than the first frequency
  • a length of a turn-on period of the second transistor and a length of a turn-on period of the third transistor may be different from each other.
  • the second frequency may be identical to that of an image refresh rate and correspond to an aliquot of the first frequency.
  • the pixel may further include a fifth transistor that may be electrically connected between the first power source and the first node and is turned off in response to an emission control signal supplied through a first emission control line, a sixth transistor that may be electrically connected between the third node a fourth node electrically connected to a first electrode of the light-emitting element, and may be turned off in response to an emission control signal supplied through a second emission control line, a seventh transistor that may be electrically connected between the fourth node and an initialization power source, and may be turned on in response to the third scan signal supplied through a fourth scan line, and a storage capacitor electrically connected between the first power source and the second node.
  • the fifth and sixth transistors may be turned off at the first frequency.
  • a part of a turn-off period of the fifth transistor may overlap a part of a turn-on period of the sixth transistor, and the third transistor and the seventh transistor may be simultaneously controlled.
  • a turn-on period of the fourth transistor may not overlap a turn-on period of the third transistor and a turn-on period of the seventh transistor.
  • the fourth transistor may be electrically connected between the first emission control line and the third node or between the first emission control line and the first node, and may apply the emission control signal, as the bias voltage, to the third node or the first node in response to the third scan signal.
  • the fourth transistor may be electrically connected between a bias power source and the third node or between the bias power source and the first node, and may apply a voltage of the bias power source, as the bias voltage, to the third node or the first node in response to the third scan signal.
  • An embodiment may provide for a display device.
  • the display device may include pixels electrically connected to first scan lines, second scan lines, emission control lines, and data lines, a scan driver may supply a second scan signal to the second scan lines at a first frequency, and supply a first scan signal to the first scan lines at a second frequency corresponding to an image refresh rate of the pixels, an emission driver that may supply an emission control signal to the emission control lines at the first frequency, a data driver that may supply data signals to respective data lines at the second frequency, and a timing controller that may control driving of the scan driver, the emission driver, and the data driver.
  • a pixel may be disposed in an i-th horizontal line (where i is a natural number) may include a light-emitting element, a first transistor that may include a first electrode electrically connected to a first node electrically connected to a first power source and controls a driving current based on a voltage of a second node, a second transistor that may be electrically connected between a data line and the first node, and may be turned on in response to a first scan signal supplied through an i-th first scan line, a third transistor that may be electrically connected between the second node and a third node electrically connected to a second electrode of the first transistor, and may be turned on in response to the first scan signal, and a fourth transistor that may be turned on in response to a second scan signal supplied through an i-th second scan line and may apply a bias voltage to the first transistor.
  • the second frequency may be an aliquot of the first frequency.
  • the scan driver may include a first scan driver that may supply the first scan signal to each of the first scan lines at the second frequency, and a second scan driver that may supply the second scan signal to each of the second scan lines at the second frequency.
  • the first scan driver may supply the first scan signal during a display-scan period of one frame period, and may not supply the first scan signal during a self-scan period of the one frame period
  • the second scan driver may supply the second scan signal during the display-scan period and the self-scan period
  • the emission driver may supply the emission control signal during the display-scan period and the self-scan period
  • the data signals may be written to the pixels during the display-scan period.
  • the pixel disposed in the i-th horizontal line may further include a fifth transistor that may be electrically connected between the first power source and the first node, and may be turned off in response to the emission control signal supplied through an i-th emission control line, a sixth transistor that may be electrically connected between the third node and a fourth node electrically connected to a first electrode of the light-emitting element, and may be turned off in response to the emission control signal supplied through the i-th emission control line, a seventh transistor that may be electrically connected between the fourth node and a first initialization power source, and may be turned on in response to the second scan signal supplied through the i-th second scan line, an eighth transistor that may be electrically connected between the second node and a second initialization power source, and may be turned on in response to the first scan signal supplied through an i ⁇ 1-th first scan line, and a storage capacitor electrically connected between the first power source and the second node.
  • the fourth transistor may be electrically connected between the i-th emission control line and the third node.
  • FIG. 1 is a block diagram illustrating a display device according to an embodiment.
  • FIG. 2A is an equivalent circuit diagram illustrating a pixel according to an embodiment.
  • FIG. 2B is an equivalent circuit diagram illustrating a modification of the pixel of FIG. 2A .
  • FIG. 3A is a timing diagram illustrating an example of driving of the pixel of FIG. 2A .
  • FIG. 3B is a timing diagram illustrating an example of driving of the pixel of FIG. 2A .
  • FIGS. 4A to 4D are timing diagrams illustrating examples of start pulses supplied to an emission driver and a scan driver included in the display device depending on image refresh rates.
  • FIG. 5 is a diagram illustrating an example of a method of driving a display device depending on image refresh rates.
  • FIGS. 6 and 7 are equivalent circuit diagrams illustrating examples of the pixel included in the display device of FIG. 1 .
  • FIG. 8 is a block diagram illustrating an example of the display device of FIG. 1 .
  • FIG. 9 is an equivalent circuit diagram illustrating an example of a pixel included in the display device of FIG. 8 .
  • FIG. 10 is a timing diagram illustrating an example of driving of the pixel of FIG. 9 .
  • FIG. 12A is a timing diagram illustrating an example of driving of the pixel of FIG. 11 .
  • FIGS. 13 to 15 are equivalent circuit diagrams illustrating modifications of the pixel of FIG. 11 .
  • a layer, film, region, substrate, or area When a layer, film, region, substrate, or area, is referred to as being “on” another layer, film, region, substrate, or area, it may be directly on the other film, region, substrate, or area, or intervening films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly on” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween.
  • a layer, film, region, substrate, or area is referred to as being “below” another layer, film, region, substrate, or area, it may be directly below the other layer, film, region, substrate, or area, or intervening layers, films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly below” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity.
  • the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation.
  • “A and/or B” may be understood to mean “A, B, or A and B.”
  • the terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.”
  • the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation.
  • “at least one of A and B” may be understood to mean “A, B, or A and B.”
  • FIG. 1 is a block diagram illustrating a display device according to an embodiment.
  • a display device 1000 may include a pixel unit 100 , scan drivers 200 and 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .
  • the scan drivers 200 and 300 may be divided into the first scan driver 200 and the second scan driver 300 according to a configuration and operation thereof. However, the division of the scan drivers is intended for convenience of description, and at least some of the scan drivers and the emission driver may be integrated into a single driving circuit, module or the like according to design.
  • the display device 1000 may adjust the output frequencies of the first and second scan drivers 200 and 300 and the output frequency of the data driver 500 corresponding thereto depending on the driving conditions.
  • the display device 1000 may display an image or images in accordance with various image refresh rates in a range of about 1 Hz to about 120 Hz.
  • this is only exemplary, and the display device 1000 may also display an image or images at an image refresh rate of about 120 Hz or higher (e.g., about 240 Hz or about 480 Hz).
  • the timing controller 600 may generate a data driving control signal DCS based on the input image data IRGB and timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK.
  • the data driving control signal DCS may be supplied to the data driver 500 .
  • the timing controller 600 may rearrange the input image data IRGB and may provide the rearranged data to the data driver 500 .
  • the timing controller 600 may supply an emission start pulse ESP and the clock signals CLK to the emission driver 400 based on the timing signals.
  • the emission start pulse ESP may control the first timing of an emission control signal.
  • the clock signals may be used to shift the emission start pulse.
  • the first gate start pulse GSP 1 may control the first timing of a scan signal (e.g., a first scan signal) supplied from the first scan driver 200 .
  • the clock signals CLK may be used to shift the first gate start pulse GSP 1 .
  • the second gate start pulse GSP 2 may control the first timing of a scan signal (e.g., a second scan signal) supplied from the second scan driver 300 .
  • the clock signals CLK may be used to shift a second gate start pulse GSP 2 .
  • pulse widths of the first and second gate start pulses GSP 1 and GSP 2 may differ from each other. Therefore, the widths of scan signals corresponding to respective gate start pulses may also differ from each other.
  • the data driver 500 may convert the rearranged image data RGB into analog data signals.
  • the data driver 500 may supply data signals to data lines D in response to the data driving control signal DCS.
  • the data signals supplied through the data lines D may be supplied to pixels PX selected by the scan signals.
  • the data driver 500 may supply data signals to the data lines D during one frame period in accordance with the image refresh rate.
  • the data driver 500 may supply data signals to the data lines D at the same frequency as the image refresh rate.
  • the data signals supplied through the data lines D may be synchronized with the scan signals supplied through first scan lines S 1 .
  • the first scan driver 200 supplies the scan signals to the first scan lines S 1 in response to the first gate start pulse GSP 1 .
  • the first scan driver 200 may sequentially supply the scan signals to the first scan lines S 1 .
  • each scan signal may be set to a gate-on voltage (e.g., a logic low voltage) so that a transistor included in the corresponding pixel PX can be turned on.
  • data signals may be supplied to the pixels PX in response to the first scan signals supplied through the first scan lines S 1 .
  • the first scan driver 200 may supply the scan signals to the first scan lines S 1 at the same frequency (e.g., a second frequency) as the image refresh rate of the display device 1000 .
  • the second frequency may correspond to the output frequency of the first gate start pulse GSP 1 that may be supplied from the timing controller 600 to the first scan driver 200 .
  • the second frequency may be set to an aliquot of the first frequency at which the emission driver 400 may be driven.
  • the first scan driver 200 may supply the scan signals to the first scan lines S 1 during a display-scan period of one frame.
  • the first scan driver 200 may supply at least one scan signal to each of the first scan lines S 1 during the display-scan period.
  • the second scan driver 300 may supply scan signals to second scan lines S 2 in response to the second gate start pulse GSP 2 .
  • the second scan driver 300 may sequentially supply second scan signals to the second scan lines S 2 .
  • each scan signal supplied from the second scan driver 300 may be set to a gate-on voltage (e.g., a logic low voltage) so that a transistor included in the corresponding pixel PX may be turned on.
  • a voltage for applying a bias to the driving transistors of the pixels PX may be supplied in response to the second scan signals supplied through the second scan lines S 2 .
  • a predetermined bias voltage may be applied to a source electrode and/or a drain electrode of the driving transistor of the pixel PX, and the driving transistor may be on-biased.
  • the second scan driver 300 may supply the scan signals to the second scan lines S 2 at the first frequency that may always be constant regardless of the frequency of the image refresh rate.
  • the first frequency may correspond to the output frequency of the second gate start pulse GSP 2 that may be supplied from the timing controller 600 to the second scan driver 300 .
  • the first frequency at which the second scan driver 300 may supply the scan signals may be higher than that of the image refresh rate.
  • the frequency (and the second frequency) of the image refresh rate may be set to an aliquot of the first frequency.
  • the first frequency may be set to about twice that of the maximum refresh rate of the display device 1000 (i.e., the maximum driving frequency set in the display device 1000 ).
  • the maximum refresh rate of the display device 1000 is about 120 Hz
  • the first frequency may be set to about 240 Hz. Therefore, during one frame period, a scanning operation of sequentially outputting scan signals to the second scan lines S 2 may be periodically repeated several times at predetermined intervals.
  • the second scan driver 300 may perform scanning once during a display-scan period and may perform scanning at least once according to the image refresh rate during a self-scan period.
  • the scan signals may be sequentially output once to respective second scan lines S 2 during the display-scan period, and the scan signals may be sequentially output once or more to respective second scan lines S 2 during the self-scan period.
  • the number of repetitions of an operation in which the second scan driver 300 may supply scan signals to respective second scan lines S 2 during one frame period may increase.
  • the emission driver 400 may supply emission control signals to emission control lines E in response to an emission start pulse ESP. For example, the emission driver 400 may sequentially supply the emission control signals to the emission control lines E. When the emission control signals are sequentially supplied through the emission control lines E, the pixels PX may become non-emissive on a horizontal line basis. For this operation, each emission control signal may be set to a gate-off voltage (e.g., a logic high voltage) so that some transistors (e.g., P-type transistors) included in the pixels PX may be turned off.
  • a gate-off voltage e.g., a logic high voltage
  • the emission driver 400 may supply the emission control signals to the emission control lines E at the first frequency. Therefore, during one frame period, the emission control signals supplied through respective emission control lines E may be repeatedly supplied at predetermined intervals.
  • the number of repetitions of the operation of supplying emission control signals during one frame period may increase.
  • Each of the first and second scan drivers 200 and 300 and the emission driver 300 may be individually mounted on a substrate through a thin-film process.
  • Each of the first and second scan drivers 200 and 300 may be located or disposed on both sides of the pixel unit 100 .
  • the emission driver 400 may also be located or disposed on both sides of the pixel unit 100 .
  • the disclosure is not limited thereto.
  • the pixel unit 100 may include pixels PX which may be located or disposed to be electrically coupled or electrically connected to the data lines D, the scan lines S 1 and S 2 , and the emission control lines E.
  • the pixels PX may be supplied with voltages of a first power source VDD, a second power source VSS, and an initialization power source Vint from external devices.
  • the signal lines S 1 , S 2 , emission control lines E, and data lines D electrically coupled or electrically connected to each pixel PX may be set in various forms depending on the circuit structure of the pixel PX.
  • Pixels PX located or disposed on a current horizontal line may be additionally electrically coupled or electrically connected to scan lines located or disposed on a previous horizontal line (or a previous pixel row) and/or scan lines located or disposed on a subsequent horizontal line (or a subsequent pixel row) depending on the circuit structure of the pixels PX.
  • dummy scan lines and/or dummy emission control lines which are not illustrated, may be additionally formed.
  • FIG. 2A is an equivalent circuit diagram illustrating a pixel according to an embodiment.
  • FIG. 2A for the convenience of description, a pixel which may be located or disposed on an i-th horizontal line and may be electrically coupled or electrically connected to a j-th data line Dj is illustrated.
  • a pixel 10 may include a light-emitting element LD, first to eighth transistors M 1 to M 8 , and a storage capacitor Cst.
  • a first electrode (an anode electrode or a cathode electrode) of the light-emitting element LD may be electrically coupled or electrically connected to a fourth node N 4 , and a second electrode thereof (a cathode electrode or an anode electrode) may be electrically coupled or electrically connected to a second power source VSS.
  • the light-emitting element LD may generate light with predetermined luminance in accordance with the amount of current supplied from the first transistor M 1 .
  • the light-emitting element LD may be an organic light-emitting diode including an organic light-emitting layer.
  • the light-emitting element LD may be an inorganic light-emitting element formed of an inorganic material.
  • the light-emitting element LD may have a form or structure in which inorganic light-emitting elements may be electrically coupled or electrically connected in parallel and/or in series between the second power source VSS and the fourth node N 4 .
  • a first electrode of the first transistor M 1 (or driving transistor) may be electrically coupled or electrically connected to a first node N 1 , and a second electrode thereof may be electrically coupled or electrically connected to a third node N 3 .
  • a gate electrode of the first transistor M 1 may be electrically coupled or electrically connected to a second node N 2 .
  • the first transistor M 1 may control the amount of current flowing from the first power source VDD into the second power source VSS via the light-emitting element LD in accordance with the voltage of the second node N 2 . For this operation, the voltage of the first power source VDD may be set to a voltage higher than that of the second power source VSS.
  • the second transistor M 2 may be electrically coupled or electrically connected between the data line Dj and the first node N 1 .
  • a gate electrode of the second transistor M 2 may be electrically coupled or electrically connected to an i-th first scan line S 1 i .
  • the second transistor M 2 may be turned on when a scan signal (e.g., a first scan signal) may be supplied through the i-th first scan line S 1 i , and may then electrically couple or electrically connect the data line Dj to the first node N 1 .
  • a scan signal e.g., a first scan signal
  • the third transistor M 3 may be electrically coupled or electrically connected between the second electrode of the first transistor M 1 (i.e., the third node N 3 ) and the second node N 2 .
  • a gate electrode of the third transistor M 3 may be electrically coupled or electrically connected to the i-th first scan line S 1 i .
  • the third transistor M 3 may be turned on, and may then electrically couple or electrically connect the second electrode of the first transistor M 1 to the second node N 2 .
  • the second transistor M 2 and the third transistor M 3 may be simultaneously controlled.
  • the third transistor M 3 When the third transistor M 3 is turned on, the first transistor M 1 may be electrically coupled or electrically connected in a diode configuration. Accordingly, writing of data to the first transistor M 1 and the compensation of a threshold voltage may be performed together.
  • the fourth transistor M 4 may be electrically coupled or electrically connected between the third node N 3 and the i-th emission control line Ei.
  • a gate electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to an i-th second scan line S 2 i .
  • the fourth transistor M 4 may be turned on when a scan signal (e.g., a second scan signal) is supplied through the i-th second scan line S 2 i , and may then supply the voltage of the i-th emission control line Ei to the third node N 3 .
  • the emission control signal e.g., a gate-off voltage or a logic high voltage
  • the gate-off voltage i.e., the emission control signal
  • the gate-off voltage may be in a range of about 5 to about 7V.
  • a predetermined high voltage may be applied, as a bias voltage, to the drain electrode (and the source electrode) of the first transistor M 1 by the turn-on operation of the fourth transistor M 4 , and the first transistor M 1 may have an on-bias state (i.e., on-biased).
  • the fifth transistor M 5 may be electrically coupled or electrically connected between the first power source VDD and the first node N 1 .
  • a gate electrode of the fifth transistor M 5 may be electrically coupled or electrically connected to the i-th emission control line Ei.
  • the fifth transistor M 5 may be turned off in a case where the emission control signal is supplied through the i-th emission control line Ei, and may be turned on in the remaining cases.
  • the sixth transistor M 6 may be electrically coupled or electrically connected between the second electrode of the first transistor M 1 (i.e., the third node N 3 ) and the first electrode of the light-emitting element LD (i.e., the fourth node N 4 ).
  • a gate electrode of the sixth transistor M 6 may be electrically coupled or electrically connected to the i-th emission control line Ei.
  • the sixth transistor M 6 may be turned off in a case where the emission control signal is supplied through the i-th emission control line Ei, and may be turned on in the remaining cases. Therefore, the fifth transistor M 5 and the sixth transistor M 6 may be simultaneously controlled.
  • the seventh transistor M 7 may be electrically coupled or electrically connected between the first electrode of the light emitting element LD (i.e., the fourth node N 4 ) and a first initialization power source Vint 1 .
  • a gate electrode of the seventh transistor M 7 may be electrically coupled or electrically connected to the i-th second scan line S 2 i .
  • the seventh transistor M 7 may be turned on when a scan signal is supplied through the i-th second scan line S 2 i , and may then supply the voltage of the first initialization power source Vint 1 to the first electrode of the light-emitting element LD (i.e., the fourth node N 4 ).
  • a parasitic capacitor of the light-emitting element LD may be discharged. As a residual voltage charged in the parasitic capacitor is discharged (eliminated), unintended fine light emission may be prevented. Therefore, black representation capability of the pixel 10 may be improved.
  • the eighth transistor M 8 may be electrically coupled or electrically connected between the second node N 2 and a second initialization power source Vint 2 .
  • a gate electrode of the eighth transistor M 8 may be electrically coupled or electrically connected to a third scan line (or an i ⁇ 1-th first scan line S 1 i ⁇ 1).
  • the eighth transistor M 8 may be turned on when a scan signal (e.g., a first scan signal) is supplied through the i ⁇ 1-th first scan line S 1 i ⁇ 1, and may then supply the voltage of the second initialization power source Vint 2 to the second node N 2 (i.e., the gate electrode of the first transistor M 1 ). Therefore, the gate voltage of the first transistor M 1 may be initialized.
  • the first initialization power source Vint 1 and the second initialization power source Vint 2 may generate different voltages.
  • the voltage for initializing the second node N 2 and the voltage for initializing the fourth node N 4 may be set to different voltages.
  • the voltage of the second initialization power source Vint 2 to be supplied to the second node N 2 is excessively low during low-frequency driving at which the length of one frame period increases, a change in the hysteresis of the first transistor M 1 in the corresponding frame period may be worsened. Such hysteresis may cause a flicker phenomenon at low frequency driving. Therefore, in the display device driven at low frequency, the voltage of the second initialization power source Vint 2 higher than that of the second power source VSS may be required.
  • the pixel 10 and the display device (e.g., 1000 of FIG. 1 ) having the pixel 10 may periodically apply a bias, as a constant voltage, to the drain electrode (and/or the source electrode) of the first transistor M 1 using the fourth transistor M 4 . Therefore, the hysteresis deviation attributable to the grayscale difference between adjacent pixels may be removed, and thus an image blur attributable to the hysteresis deviation may be reduced (or eliminated).
  • a bias as a constant voltage
  • the first to eighth transistors M 1 to M 8 may be formed of polysilicon semiconductor transistors.
  • each of the first to eighth transistors M 1 to M 8 may include, as an active layer (channel), a polysilicon semiconductor layer formed through a Low-temperature polycrystalline silicon (LTPS) process.
  • LTPS Low-temperature polycrystalline silicon
  • FIG. 2B is an equivalent circuit diagram illustrating a modification of the pixel of FIG. 2A .
  • a pixel 10 ′ of FIG. 2B may be identical or similar to that of FIG. 2A except for the coupling relationship of the fourth transistor, the same reference numerals are used to designate the same or corresponding components, and thus a repeated description thereof will be omitted.
  • the pixel 10 ′ may include a light-emitting element LD, first to eighth transistors M 1 to M 8 , and a storage capacitor Cst.
  • a gate electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to an i-th emission control line Ei.
  • a second electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to a first node N 1 (i.e., a source electrode of the first transistor M 1 ).
  • a logic high voltage may be supplied to the i-th emission control line Ei. Therefore, when the fourth transistor M 4 is turned on, a logic high voltage may be supplied, as a bias voltage, to the source electrode of the first transistor M 1 , and the first transistor M 1 may have an on-bias state.
  • the first transistor M 1 when one electrode of the fourth transistor M 4 is electrically coupled or electrically connected to any one of the source electrode and the drain electrode of the first transistor M 1 , the first transistor M 1 may be on-biased during a predetermined period.
  • FIG. 3A is a timing diagram illustrating an example of driving of the pixel of FIG. 2A .
  • the pixel 10 may be supplied with signals for displaying an image during a display-scan period.
  • the display-scan period may include a period during which a data signal DVi corresponding to an output image may be written.
  • an i-th emission control line Ei may be used as an emission control line Ei
  • an i-th first scan line S 1 i may be used as a first scan line S 1 i
  • an i-th second scan line S 2 i may be used as a second scan line S 2 i
  • an i ⁇ 1-th first scan line S 1 i ⁇ 1 may be used as a previous first scan line S 1 i ⁇ 1.
  • the first scan signals that may be supplied through the first scan lines S 1 i ⁇ 1 and S 1 i may have a pulse width of 1 horizontal period (1H) or less.
  • the first scan signal and the second scan signal supplied through the second scan line S 2 i may be defined as logic low voltages, and emission control signals for turning off the fifth and sixth transistors M 5 and M 6 may be defined as logic high voltages.
  • this is merely exemplary, so that the pulse widths and logical levels of the scan signals and emission control signals are not limited thereto, and may be changed depending on the pixel structures, the types of transistors, or the like within the spirit and scope of the disclosure.
  • An emission control signal may be supplied through an emission control line Ei.
  • the emission control signal may be maintained during a first period P 1 to a third period P 3 .
  • the emission control signal may be supplied through the emission control line Ei, and the first scan signal may be supplied through the previous first scan line S 1 i ⁇ 1.
  • the fifth and sixth transistors M 5 and M 6 may be turned off in response to the emission control signal.
  • the eighth transistor M 8 may be turned on in response to the first scan signal supplied through the previous first scan line S 1 i ⁇ 1.
  • the supply of the driving current to the light-emitting element LD may be stopped. Since the eighth transistor M 8 is turned on, the voltage of the second initialization power source Vint 2 may be supplied to the gate electrode of the first transistor M 1 (i.e., the second node N 2 ). Therefore, the gate voltage of the first transistor M 1 may be initialized during the first period P 1 .
  • the first scan signal may be supplied through the first scan line S 1 i (or the current first scan line). Accordingly, the second and third transistors M 2 and M 3 may be turned on. The second transistor M 2 may be turned on, so that an i-th data signal DVi may be supplied to the first node N 1 through the data line Dj.
  • the first transistor M 1 may be electrically coupled or electrically connected in a diode configuration.
  • the second period P 2 may be a data writing and threshold voltage compensation period.
  • the second scan signal may be supplied through the second scan line S 2 i . Accordingly, the fourth and seventh transistors M 4 and M 7 may be turned on.
  • the voltage of the first initialization power source Vint 1 may be supplied to the fourth node N 4 . Therefore, the voltage of the first electrode (e.g., the anode electrode) of the light-emitting element LD may be initialized, and the voltage of the parasitic capacitor formed in the light-emitting element LD may be discharged (or removed).
  • the first electrode e.g., the anode electrode
  • a gate-off voltage (e.g., a logic high voltage) of the emission control signal may be supplied to the third node N 3 .
  • the emission control signal i.e., logic high voltage of the emission control signal
  • the first transistor M 1 may be on-biased during the third period P 3 .
  • the second scan signal may have a pulse width of about 4 horizontal periods (4H) or more. Therefore, for a sufficient period of time, the logic high voltage of the emission control signal may be supplied to the first transistor M 1 .
  • the first transistors M 1 of all pixels arranged or disposed in an i-th pixel row may be on-biased in response to the emission control signal, and thus the difference between bias voltages may be removed. Therefore, the hysteresis deviation between pixels may be removed (or reduced).
  • a turn-on period of the third transistor M 3 and a turn-on period of the fourth transistor M 4 may not overlap each other.
  • the initialization/compensation period and the bias period of the first transistor M 1 may be separated from each other.
  • the supply of the emission control signal may be stopped and the fifth and sixth transistors M 5 and M 6 may be turned on.
  • a driving current generated based on the data signal DVi may be supplied to the light-emitting element LD, and the light-emitting element LD may emit light with luminance corresponding to the driving current.
  • the fourth period P 4 may be an emission period.
  • the display-scan period may include an initialization period (e.g., the first period P 1 ), the write and compensation period (e.g., the second period P 2 ), the bias period (e.g., the third period P 3 ), and the emission period (e.g., the fourth period P 4 ).
  • the first to third periods P 1 to P 3 may correspond to a non-emission period of the pixel 10 .
  • An operation corresponding to the display-scan period may be implemented in response to scan signals supplied through the first scan lines S 1 i ⁇ 1 and S 1 i , and may be synchronized with the frequency at which the first scan driver 200 may be driven (e.g., this frequency may be described as being the second frequency.
  • the pixel 10 ′ of FIG. 2B may also perform the same operation as the above-described operation during the display-scan period.
  • first scan signals may be supplied through each of the first scan lines S 1 i ⁇ 1 and S 1 i during the first period P 1 and the second period P 2 in FIG. 3A .
  • first scan signals may be supplied through each of the first scan lines S 1 i ⁇ 1 and S 1 i .
  • the actual operating process may be identical to that of FIG. 3A , and thus a detailed description thereof will be omitted.
  • FIG. 3B is a timing diagram illustrating an example of driving of the pixel of FIG. 2A .
  • an emission control signal may be applied to one electrode (e.g., the drain electrode or the third node N 3 ) of the first transistor M 1 during a self-scan period.
  • a single frame may include at least one self-scan period depending on the image frame rate.
  • the self-scan period may include a bias period (e.g., the third period P 3 ) and an emission period (e.g., the fourth period P 4 ).
  • an operation corresponding to the self-scan period may be substantially the same as that of the display-scan period except that the first scan signal may not be supplied.
  • scan signals may not be supplied to the second and third transistors M 2 and M 3 .
  • Scan signals may not be supplied to the eighth transistor M 8 .
  • first scan signals supplied through the first scan lines S 1 i ⁇ 1 and S 1 i may have gate-off voltages (e.g., logic high voltages).
  • the self-scan period may not include the initialization period (e.g., the first period P 1 of FIG. 3A ) and the write and compensation period (e.g., the second period P 2 of FIG. 3A ).
  • the gate voltage (i.e., the voltage of the second node N 2 ) of the first transistor M 1 may not be influenced by driving in the self-scan period.
  • the fourth to seventh transistors M 4 to M 7 may be turned on at the first frequency
  • the second, third, and eighth transistors M 2 , M 3 , and M 8 may be turned on at the second frequency that may be different from the first frequency.
  • the second frequency may be lower than the first frequency.
  • the second scan signal may be supplied through the second scan line S 2 i .
  • the fourth transistor M 4 may be turned on in response to the second scan signal.
  • a logic high voltage of the emission control signal may be supplied to the third node N 3 . Accordingly, since an on-bias may be applied to the first transistor M 1 during the third period P 3 , a flicker at low-frequency driving may be improved.
  • the second scan signal and the emission control signal may be supplied at the first frequency regardless of the image refresh rate. Therefore, the application of an on-bias during the third period P 3 may always be periodically performed even when the image refresh rate may be changed. Therefore, in accordance with various image refresh rates (for example, in low-frequency driving), a flicker may be improved.
  • the first transistor M 4 may be turned off, and the fifth and sixth transistors M 5 and M 6 may be turned on. Therefore, during the fourth period P 4 , the pixel 10 may emit light based on the data signal DVi supplied during the previous display-scan period.
  • the data driver 500 may not supply the data signal DVi to the pixel unit 100 . Therefore, power consumption may be further reduced.
  • P-type transistors are described as being included in the pixels 10 and 10 ′, the disclosure is not limited thereto, and at least one of the first to eighth transistors M 1 to M 8 may be an N-type transistor. Waveforms of scan signals or emission control signals supplied to respective transistors may change depending on the type of transistor.
  • FIGS. 4A to 4D are timing diagrams illustrating examples of start pulses supplied to an emission driver and a scan driver included in the display device depending on image refresh rates.
  • FIG. 5 is a diagram illustrating an example of a method of driving a display device depending on image refresh rates.
  • the output frequency of the first gate start pulse GSP 1 may vary depending on the image refresh rate RR.
  • the pulse width of the emission start pulse ESP may be greater than those of the first and second gate pulses GSP 1 and GSP 2 .
  • the timing controller 600 may output the emission start pulse ESP and the second gate start pulse GSP 2 at a predetermined frequency (e.g., the first frequency).
  • a predetermined frequency e.g., the first frequency
  • the output frequency of the emission start pulse ESP and the second gate start pulse GSP 2 may be set to about twice the maximum refresh rate of the display device 1000 .
  • the timing controller 600 may output the first gate start pulse GSP 1 at the same frequency (e.g., the second frequency) as that of the image refresh rate RR.
  • One frame period of the display device 1000 may be determined by the output period of the first gate start pulse GSP 1 .
  • the one frame period of the display device 1000 may be determined according to the period of the scan signals supplied to the second, third, and eighth transistors (i.e., M 2 , M 3 , and M 8 of FIG. 2A ) of the pixel (e.g., 10 of FIG. 2A ).
  • all of the emission start pulse ESP, the first gate start pulse GSP 1 , and the second gate start pulse GSP 2 may be output.
  • each of the pixels PX may perform driving of FIG. 3A .
  • each of the pixels PX may store data signals corresponding to an image to be displayed.
  • the emission start pulse ESP and the second gate start pulse GSP 2 may be output.
  • each of the pixels PX may perform driving of FIG. 3B .
  • a predetermined high voltage for applying a bias may be supplied to the first electrode and/or the second electrode of the first transistor (e.g., M 1 of FIG. 2A ) in each pixel (e.g., 10 of FIG. 2A ).
  • the length of a single display-scan period DSP may be substantially the same as that of a single self-scan period SSP.
  • the number of self-scan periods SSP included in one frame period may be determined according to the image refresh rate RR.
  • one frame period may include a single display-scan period DSP and a single self-scan period SSP.
  • the emission start pulse ESP may be supplied at the same frequency as the second gate start pulse GSP 2 .
  • the pixels PX may alternately repeat emission and non-emission twice during the frame period.
  • the number of first gate start pulses GSP 1 supplied during one frame period may be about 1 ⁇ 3 of the number of second gate start pulses GSP 2 . Therefore, when the display device is driven at the image refresh rate RR of about 80 Hz, one frame period may include one display-scan period DSP and two consecutive self-scan periods SSP. Here, the pixels PX may alternately repeat emission and non-emission three times.
  • the number of first gate start pulses GSP 1 supplied during one frame period may be about 1 ⁇ 4 of the number of second gate start pulses GSP 2 . Therefore, when the display device is driven at the image refresh rate RR of about 60 Hz, one frame period may include one display-scan period DSP and three consecutive self-scan periods SSP. Here, the pixels PX may alternately repeat emission and non-emission four times.
  • the number of first gate start pulses GSP 1 supplied during one frame period may be about 1 ⁇ 5 of the number of second gate start pulses GSP 2 . Therefore, when the display device is driven at the image refresh rate RR of about 48 Hz, one frame period may include one display-scan period DSP and four consecutive self-scan periods SSP.
  • the pixels PX may alternately repeat emission and non-emission five times.
  • the display device 1000 may be driven at various driving frequencies of about 60 Hz, about 30 Hz, about 24 Hz, about 12 Hz, about 8 Hz, about 6 Hz, about 5 Hz, about 4 Hz, about 3 Hz, about 2 Hz, about 1 Hz by adjusting the number of self-scan periods SSP included in one frame period.
  • the display device 1000 may support various image refresh rates RR with frequencies corresponding to aliquots of the first frequency.
  • the driving frequency decreases, the number of self-scan periods SSP increases, and thus an on-bias having a predetermined magnitude may be periodically applied to each of the first transistors M 1 included in the pixel unit 100 . Therefore, a decrease in luminance, a flicker (flickering) or an image blur occurring at low-frequency driving may be improved.
  • FIGS. 6 and 7 are equivalent circuit diagrams illustrating examples of the pixel included in the display device of FIG. 1 .
  • pixels 11 and 11 ′ of FIGS. 6 and 7 may be identical or similar to that of FIG. 2A except for the configuration of the fourth transistor, the same reference numerals are used to designate the same or corresponding component, and thus a repeated description thereof will be omitted.
  • each of the pixels 11 and 11 ′ may include a light-emitting element LD, first to eighth transistors M 1 to M 8 , and a storage capacitor Cst.
  • the fourth transistor M 4 may be electrically coupled or electrically connected between a predetermined bias power source VEH and a third node N 3 (i.e., a drain electrode of the first transistor M 1 ).
  • the fourth transistor M 4 may be turned on in response to a second scan signal supplied through a second scan line S 2 i.
  • the bias power source VEH may have a voltage level in a range of about 5 to about 8 V. Depending on the driving conditions of the display device 1000 , the voltage level of the bias power source VEH may be easily controlled.
  • the bias power source VEH may be implemented as a DC voltage source, and thus the bias difference between first transistors M 1 may be further reduced.
  • the fourth transistor M 4 may also be electrically coupled or electrically connected between a predetermined bias power source VEH and a first node N 1 (i.e., a source electrode of the first transistor M 1 ).
  • a predetermined bias power source VEH i.e., a source electrode of the first transistor M 1
  • the first transistor M 1 may be on-biased during a predetermined period.
  • the pixels 11 and 11 ′ of FIGS. 6 and 7 may display an image or images through the same driving as in the case of the timing diagrams of FIGS. 3A and 3B .
  • FIG. 8 is a block diagram illustrating an example of the display device of FIG. 1 .
  • the display device of FIG. 8 may be identical or similar to that of FIG. 1 except for the configuration of a third scan driver 350 , the same reference numerals are used to designate the same or corresponding components, and thus a repeated description thereof will be omitted.
  • a display device 1001 may include a pixel unit 100 , a first scan driver 200 , a second scan driver 300 , the third scan driver 350 , an emission driver 400 , a data driver 500 , and a timing controller 600 .
  • the timing controller 600 may supply gate start pulses GSP 1 , GSP 2 , and GSP 3 and clock signals CLK to the first scan driver 200 , the second scan driver 300 , and the third scan driver 350 based on timing signals Vsync, Hsync, DE, and CLK.
  • the first gate start pulse GSP 1 may control the first timing of a scan signal (e.g., a first scan signal) output from the first scan driver 200 .
  • the second gate start pulse GSP 2 may control the first timing of a scan signal (e.g., a second scan signal) output from the second scan driver 300 .
  • the third gate start pulse GSP 3 may control the first timing of a scan signal (e.g., a third scan signal) output from the third scan driver 350 .
  • a scan signal e.g., a third scan signal
  • the pulse width of at least one of the first to third gate start pulses GSP 1 to GSP 3 may differ from that of the remaining gate start pulses. Therefore, the widths of scan signals corresponding to respective gate start pulses may also vary.
  • the data driver 500 may supply data signals to data lines D in response to a data driving control signal DCS.
  • the data signals supplied through the data lines D may be supplied to pixels PX selected by the scan signals.
  • the first scan driver 200 may supply the scan signals to the first scan lines S 1 in response to the first gate start pulse GSP 1 .
  • the first scan driver 200 may supply the scan signals to the first scan lines S 1 at a second frequency corresponding to an image refresh rate.
  • the first scan driver 200 may output the scan signals only during a display-scan period.
  • the second scan driver 300 may supply the scan signals to the second scan lines S 2 in response to the second gate start pulse GSP 2 .
  • the second scan driver 300 may supply scan signals to the second scan lines S 2 at a first frequency unrelated to the refresh rate.
  • the second scan driver 300 may output the scan signals during a display-scan period and a self-scan period.
  • the third scan driver 350 may supply the scan signals to the third scan lines S 3 in response to the third gate start pulse GSP 3 .
  • the third scan driver 350 may supply the scan signals to the third scan lines S 3 at the second frequency.
  • the emission driver 400 may supply emission control signals to emission control lines E in response to an emission start pulse ESP.
  • the emission driver 400 may supply the emission control signals to the emission control lines E at the first frequency.
  • the emission driver 400 may output the scan signals during the display-scan period and the self-scan period.
  • first to third scan drivers 200 , 300 , and 350 may be driven at the first frequency, and the remaining scan drivers may be driven at the second frequency depending on the structure of the pixel PX.
  • Scan drivers may be excluded or added depending on the structure of the pixel PX.
  • FIG. 9 is an equivalent circuit diagram illustrating an example of the pixel included in the display device of FIG. 8
  • FIG. 10 is a timing diagram illustrating an example of driving of the pixel of FIG. 9 .
  • a pixel of FIG. 9 may be identical or similar to that of FIG. 2A except for some coupling components of the third transistor, the same reference numerals are used to designate the same or corresponding components, and thus a repeated description thereof will be omitted.
  • the timing diagram of FIG. 10 may be identical or similar to that of FIG. 3A except for the width of a signal supplied through a third scan line S 3 i , a repeated description thereof will be omitted.
  • a pixel 12 may include a light-emitting element LD, first to eighth transistors M 1 to M 8 , and a storage capacitor Cst.
  • the third transistor M 3 and the second transistor M 2 may be controlled in response to different scan signals.
  • a gate electrode of the third transistor M 3 may be electrically coupled or electrically connected to the third scan line S 3 i , and the third transistor M 3 may be turned on in response to a third scan signal supplied through the third scan line S 3 i.
  • the pixel 12 may perform operations corresponding to first to fourth periods P 1 to P 4 .
  • the third scan signal supplied through the third scan line S 3 i may overlap a first scan signal supplied through a first scan line S 1 i .
  • the pulse width of the third scan signal may be greater than that of the first scan signal, and the length of a second period P 2 during which data writing and threshold voltage compensation are performed may increase.
  • a time required for threshold voltage compensation may increase.
  • the difference between the gate voltage and the source voltage of the first transistor M 1 may decrease. Therefore, image quality may be further improved.
  • FIG. 11 is an equivalent circuit diagram illustrating an example of the pixel included in the display device of FIG. 8 .
  • a pixel 13 may include a light-emitting element LD, first to seventh transistors M 1 to M 7 , and a storage capacitor Cst.
  • the first transistor M 1 , and the second transistor M 2 may be substantially the same as that of the pixel 10 of FIG. 2A , a repeated description thereof will be omitted.
  • the third transistor M 3 may be electrically coupled or electrically connected between a second electrode of the first transistor M 1 (i.e., a third node N 3 ) and a second node N 2 .
  • a gate electrode of the third transistor M 3 may be electrically coupled or electrically connected to an i-th second scan line S 2 i .
  • the third transistor M 3 may be turned on, and may then electrically connect or couple the second electrode of the first transistor M 1 to the second node N 2 . Therefore, when the third transistor M 3 is turned on, the first transistor M 1 may be electrically coupled or electrically connected in a diode configuration.
  • the voltage of an initialization power source Vint may be supplied to the gate electrode of the first transistor M 1 through the third transistor M 3 .
  • the fourth transistor M 4 may be electrically coupled or electrically connected between the third node N 3 and an i-th emission control line Ei.
  • a gate electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to an i+q-th third scan line S 3 i +q.
  • the fourth transistor M 4 may be turned on when a scan signal (e.g., a third scan signal) is supplied through the i+q-th third scan line S 3 i +q (where q is a natural number), and may then supply the voltage of the i-th emission control line Ei to the third node N 3 .
  • the gate electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to an i+5-th third scan line S 3 i +5.
  • the third scan signal supplied through the i+5-th third scan line S 3 i +5 may be a signal obtained by delaying a third scan signal, which may be supplied through the i-th third scan line S 3 i , by 5 horizontal periods (5H).
  • this is merely exemplary, and the third scan line S 3 i +q electrically coupled or electrically connected to the gate electrode of the fourth transistor M 4 is not limited thereto.
  • a gate-off voltage (or a logic high voltage) may be supplied through the i-th emission control line Ei.
  • the gate-off voltage may be in a range of about 5 to about 7 V.
  • a predetermined high voltage may be applied to the drain electrode (and the source electrode) of the first transistor M 1 by the turn-on operation of the fourth transistor M 4 , and the first transistor M 1 may have an on-bias state.
  • the fifth transistor M 5 may be electrically coupled or electrically connected between a first power source VDD and the first node N 1 .
  • a gate electrode of the fifth transistor M 5 may be electrically coupled or electrically connected to the i-th emission control line Ei.
  • the fifth transistor M 5 may be turned off in a case where the emission control signal may be supplied through the i-th emission control line Ei, and may be turned on in the remaining cases.
  • the sixth transistor M 6 may be electrically coupled or electrically connected between the second electrode of the first transistor M 1 (i.e., the third node N 3 ) and the first electrode of the light-emitting element LD (i.e., the fourth node N 4 ).
  • a gate electrode of the sixth transistor M 6 may be electrically coupled or electrically connected to an i+p-th emission control line Ei+p (where p is a natural number).
  • the sixth transistor M 6 may be turned off in a case where the emission control signal may be supplied through the i+p-th emission control line Ei+p, and may be turned on in the remaining cases. Therefore, the turn-on periods of the fifth transistor M 5 and the sixth transistor M 6 may merely partially overlap each other.
  • the gate electrode of the sixth transistor M 6 may be electrically coupled or electrically connected to an i+4-th emission control line Ei+4.
  • the emission control signal supplied through the i+4-th emission control line Ei+4 may be a signal obtained by delaying the emission control signal supplied through the i-th emission control line Ei by 4 horizontal periods (4H).
  • the seventh transistor M 7 may be electrically coupled or electrically connected between the first electrode (i.e., the fourth node N 4 ) of the light-emitting element LD and the initialization power source Vint.
  • a gate electrode of the seventh transistor M 7 may be electrically coupled or electrically connected to the i-th third scan line S 3 i .
  • the seventh transistor M 7 may be turned on when the emission control signal is supplied through the i-th third scan line S 3 i , and may then supply the voltage of the initialization power source Vint to the first electrode of the light-emitting element LD and the fourth node N 4 .
  • the turn-on periods of the seventh transistor M 7 and the sixth transistor M 6 may not overlap each other.
  • the fourth to seventh transistors M 4 to M 7 may be turned on at a first frequency, and the second and third transistors M 2 and M 3 may be turned on at a second frequency different from that of the first frequency.
  • the second frequency may be lower than the first frequency.
  • the second frequency may be an aliquot of the first frequency.
  • the pixel 13 of FIG. 11 includes fewer transistors less than that of the pixel of FIG. 2A , a layout of the pixel may be simplified, and the implementation of high resolution may be facilitated.
  • FIG. 12A is a timing diagram illustrating an example of driving of the pixel of FIG. 11 .
  • the pixel 13 may be supplied with signals for displaying an image during a display-scan period.
  • the display-scan period may include a period during which a data signal DVi corresponding to an output image may be written.
  • an i-th emission control line Ei may be used as an emission control line Ei
  • an i+p-th emission control line Ei+p may be used a subsequent emission control line Ei+p
  • an i-th first scan line S 1 i may be used as a first scan line S 1 i
  • an i-th second scan line S 2 i may be used as a second scan line S 2 i
  • an i-th third scan line S 3 i may be used as a third scan line S 3 i
  • an i+q-th third scan line S 3 i +q may be used as a subsequent third scan line S 3 i +q.
  • the emission control signal may be supplied through the emission control line Ei
  • the second scan signal may be supplied through the second scan line S 2 i
  • the third scan signal may be supplied through the third scan line S 3 i .
  • the fifth transistor M 5 may be turned off in response to the emission control signal. Since the second scan signal may be supplied through the second scan line S 2 i and the third scan signal may be supplied through the third scan line S 3 i , the third and seventh transistors M 3 and M 7 may be turned on. Since an emission control signal may not be supplied through the subsequent emission control line Ei+p, the sixth transistor M 6 may remain turned on.
  • the supply of a driving current to the light-emitting element LD may be stopped.
  • the seventh transistor M 7 When the seventh transistor M 7 is turned on, the voltage of the initialization power source Vint may be supplied to the fourth node N 4 .
  • the voltage of the initialization power source Vint may be supplied to the gate electrode (i.e., the second node N 2 ) of the first transistor M 1 through the third and sixth transistors M 3 and M 6 that may be turned on.
  • the initialization of the voltage on the first electrode of the light-emitting element LD i.e., discharging of a parasitic capacitor
  • the initialization of the gate voltage of the first transistor M 1 may be performed.
  • the first period P 1 may be an initialization period.
  • the sixth transistor M 6 may be turned off.
  • the fifth transistor M 5 may be turned off, and the sixth transistor M 6 may be turned on.
  • the length of the first period P 1 may be about 4 horizontal periods (4H) or more.
  • the first scan signal may be supplied through the first scan line S 1 i during the second period P 2 .
  • the second transistor M 2 may be turned on, so that an i-th data signal DVi may be supplied to the first node N 1 through the data line Dj. Since the third transistor M 3 may be in a turned-on state, the first transistor M 1 may be electrically coupled or electrically connected in a diode configuration.
  • the second period P 2 may be a data writing and threshold voltage compensation period.
  • the supply of the second scan signal to the second scan line S 2 i may be stopped, and the supply of the third scan signal to the third scan line S 3 i may be stopped. Accordingly, the third and seventh transistors M 3 and M 7 may be turned off. In an embodiment, the third and seventh transistors M 3 and M 7 may be simultaneously controlled.
  • the third scan signal may be supplied through the subsequent third scan line S 3 i +q.
  • the fourth transistor M 4 may be turned on in response to the third scan signal.
  • a gate-off voltage e.g., a logic high voltage
  • the emission control signal may be supplied to the third node N 3 .
  • the first transistor M 1 may be on-biased.
  • the third scan signal may have a pulse width of about 4 horizontal periods (4H) or more. Therefore, for a sufficient period of time, the logic high voltage of the emission control signal may be supplied to the first transistor M 1 .
  • a turn-on period of the third transistor M 3 and a turn-on period of the fourth transistor M 4 may not overlap each other.
  • the initialization/compensation period and the bias period of the first transistor M 1 may be separated from each other.
  • a turn-on period of the fourth transistor M 4 and a turn-on period of the seventh transistor M 7 may not overlap each other.
  • the supply of emission control signals to the emission control line Ei and the subsequent emission control line Ei+p may be sequentially stopped, and the fifth and sixth transistors M 5 and M 6 may be sequentially turned on.
  • a driving current generated based on the data signal DVi may be supplied to the light-emitting element LD, and the light-emitting element LD may emit light with luminance corresponding to the driving current.
  • the fourth period P 4 during which both the fifth and sixth transistors M 5 and M 6 may be turned on may be an emission period.
  • An operation corresponding to the display-scan period may be implemented in accordance with the frequency of the scan signals supplied to the first scan line S 1 i .
  • the display-scan period may be represented by the above-described second frequency.
  • FIG. 12B is a timing diagram illustrating an example of driving of the pixel of FIG. 11 .
  • an emission control signal may be applied to one electrode (e.g., the drain electrode or the third node N 3 ) of the first transistor M 1 during a self-scan period.
  • the self-scan period may include a bias period (e.g., the third period P 3 ) and an emission period (e.g., the fourth period P 4 ).
  • an operation corresponding to the self-scan period may be substantially the same as that of the display-scan period except that a first scan signal and a second scan signal may not be supplied.
  • scan signals may not be supplied to the second and third transistors M 2 and M 3 .
  • the first scan signal supplied through the first scan line S 1 i may have a gate-off voltage (e.g., a logic high voltage).
  • the gate voltage of the first transistor M 1 may not be influenced by the driving of the self-scan period.
  • the fourth to seventh transistors M 4 to M 7 may be turned on at a first frequency
  • the second and third transistors M 2 and M 3 may be turned on at a second frequency that may be different from that of the first frequency.
  • the second frequency may be lower than the first frequency.
  • the third scan signal may be supplied through the third scan lines S 3 i and S 3 i +q.
  • the fourth transistor M 4 may be turned on in response to the third scan signal.
  • a logic high voltage of the emission control signal may be supplied to the third node N 3 . Accordingly, since an on-bias may be applied to the first transistor M 1 during the third period P 3 , a flicker occurring at low-frequency driving may be improved.
  • the fifth and sixth transistors M 5 and M 6 may be turned on. Therefore, during the fourth period P 4 , the pixel 13 may emit light based on the data signal DVi supplied during the previous display-scan period.
  • FIGS. 13 to 15 are equivalent circuit diagrams illustrating modifications of the pixel of FIG. 11 .
  • pixels 13 ′, 14 , and 14 ′ of FIGS. 13 to 15 may be identical or similar to that of FIG. 2A except for the configuration of the fourth transistor, the same reference numerals are used to designate the same or corresponding components, and thus a repeated description thereof will be omitted.
  • each of the pixels 13 ′, 14 , and 14 ′ may include a light-emitting element LD, first to seventh transistors M 1 to M 7 , and a storage capacitor Cst.
  • the pixel 13 ′ may include the fourth transistor M 4 electrically coupled or electrically connected between an i-th emission control line Ei and a first node N 1 .
  • a logic high voltage may be supplied, as a bias voltage, to the source electrode of the first transistor M 1 , and the first transistor M 1 may have an on-bias state.
  • the fourth transistor M 4 of the pixel 14 may be electrically coupled or electrically connected between a bias power source VEH and a third node N 3 (i.e., the drain electrode of the first transistor M 1 ).
  • the fourth transistor M 4 may be turned on in response to a third scan signal supplied through an i+q-th third scan line S 3 i +q.
  • the voltage of the bias power source VEH may be supplied, as a bias voltage, to the drain electrode of the first transistor M 1 , and the first transistor M 1 may have an on-bias state.
  • the fourth transistor M 4 of the pixel 14 ′ may be electrically coupled or electrically connected between the bias power source VEH and the first node N 1 (i.e., the source electrode of the first transistor M 1 ).
  • the fourth transistor M 4 may be turned on in response to a third scan signal supplied through the i+q-th third scan line S 3 i +q.
  • the pixels 13 ′, 14 , and 14 ′ of FIGS. 13 to 15 may display an image or images through the driving of FIGS. 12A and 12B .
  • FIGS. 16 to 19 are equivalent circuit diagrams illustrating modifications of the pixel of FIG. 11 .
  • pixels 15 , 15 ′, 16 , and 16 ′ of FIGS. 16 to 19 may be identical to those of FIGS. 11, 13, 14, and 15 , respectively, except for the coupling relationship between the third transistor M 3 and the seventh transistor M 7 , the same reference numerals are used to designate identical or corresponding components, and repeated descriptions thereof will be omitted.
  • each of the pixels 15 , 15 ′, 16 , and 16 ′ may include a light-emitting element LD, first to seventh transistors M 1 to M 7 , and a storage capacitor Cst.
  • a gate electrode of the third transistor M 3 and a gate electrode of the seventh transistor M 7 may be electrically coupled or electrically connected in common to a second scan line S 2 i . Therefore, the third transistor M 3 and the seventh transistor M 7 may be controlled in common. Since the second scan signal supplied through the second scan line S 2 i may be driven at a second frequency corresponding to the image frame rate, the third and seventh transistors M 3 and M 7 may be turned on at the second frequency.
  • a gate electrode of the fourth transistor M 4 may be electrically coupled or electrically connected to an i+q-th third scan line S 3 i +q for supplying a third scan signal.
  • the fourth transistor M 4 may be turned on at the first frequency in a way similar to that of the fifth and sixth transistors M 5 and M 6 . For example, an on-bias may be supplied to the first transistor M 1 at the first frequency.
  • the seventh transistor may be turned on at the second frequency, but the fourth transistor M 4 may be turned on at the first frequency so as to supply an on-bias voltage during both a display-scan period and a self-scan period.
  • the third scan signal may be supplied at the first frequency
  • the second scan signal may be supplied at the second frequency lower than the first frequency.
  • the second frequency for example, may be different from that of the first frequency.
  • the third scan signal may have the same waveform as the second scan signal, and a third scan signal supplied through the i+q-th third scan line S 3 i +q may correspond to a signal obtained by delaying the second scan signal supplied through the i-th second scan line S 2 i by q horizontal periods (qH).
  • a third scan signal supplied through the i+q-th third scan line S 3 i +q may correspond to a signal obtained by delaying the second scan signal supplied through the i-th second scan line S 2 i by q horizontal periods (qH).
  • this is merely exemplary, and the pulse width of the third scan signal and the pulse width of the second scan signal may differ from each other.
  • the second scan signal may be supplied during about 5 horizontal periods (5H)
  • the third scan signal may be supplied during 6H.
  • the fourth transistor M 4 of the pixel 15 may supply an emission control signal, as a bias voltage, to the third node N 3 (i.e., the drain electrode of the first transistor M 1 ).
  • the fourth transistor M 4 of the pixel 15 ′ may supply an emission control signal, as a bias voltage, to the first node N 1 (i.e., the source electrode of the first transistor M 1 ).
  • the fourth transistor M 4 of the pixel 16 may supply the voltage of a bias power source VEH, as a bias voltage, to the third node N 3 (i.e., the drain electrode of the first transistor M 1 ).
  • the fourth transistor M 4 of the pixel 16 ′ may supply the voltage of a bias power source VEH, as a bias voltage, to the first node N 1 (i.e., the source electrode of the first transistor M 1 ).
  • the pixel and the display device having the pixel may support the display of images at various driving frequencies by allowing one display-scan period and at least one self-scan period to be included in one frame. For example, as the driving frequency decreases, the number of self-scan periods may increase, and thus a decrease in luminance and perception of a flicker occurring at low-frequency driving may be improved.
  • Hysteresis i.e., the differences between threshold voltage shifts attributable to an on-bias difference (and a grayscale difference) between adjacent pixels may be overcome by periodically applying a constant bias voltage for on-biasing the first transistor to a first transistor through a fourth transistor regardless of data signals and image grayscale levels. Therefore, a motion blur (i.e., a ghost phenomenon) attributable to hysteresis deviation may be improved (or removed).

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US20220270546A1 (en) * 2019-10-25 2022-08-25 Samsung Display Co., Ltd. Pixel and display device having the same
US20230386409A1 (en) * 2022-03-02 2023-11-30 Samsung Display Co., Ltd. Pixel and display device including pixel
US11978403B2 (en) 2022-08-30 2024-05-07 Samsung Display Co., Ltd. Display device and driving method thereof

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