M363678 五、新型說明： 【新型所屬之技術領域】 本創作是有關於一種托 封裝體的托盤。 寺別是有關於一種承載晶片 【先前技術】 一般用以承載晶片封萝驊 料作為托盤的材質，以避免带皿」多半以抗靜電的複合材 常見的托盤只能用以$電錢而損壞晶#封裝體。 封襄體的尺寸規格有戶 尺寸規格的晶片封裝體。當晶片 有尺寸固定的凹槽，呈方須重新設計。傳統的托盤具 底面直接承载晶片封I體^ edl)排列。純盤以凹槽的 凹槽的底面接觸而、皮占护备/面（bal1 Slde)時，銲球面與 免與晶片封裝體的Ϊ球°因此’傳統的乾盤為了避 的承靠面的凹样，以改盖f觸、計了一種可承靠晶片封裝艘 成損傷或㈣。日t上述畴球面與凹槽的底面接觸所造 的托ίί考^ 1A及圖1B，其分別為習知—種承載晶片封褒體 102用?Γ:圖及凹槽區域的剖面示意圖。托盤100的凹槽 sr署二:载曰晶片封裝體110。晶片封裝體110的承靠面110a 緣夕固銲球’而最外侧的鲜球JΜ相對於基板外側周 1八，目1^ —適當寬度h1，以使晶片封裝體110的承靠面U〇a 另1承f在凹槽102的至少二水平壁面上，然而採用上述的 承罪面U〇a必須事先預留足夠的間距，因而佔用了銲 球114的配晋办p弓 .. 二夏二間。此外，當凹槽102的二水平壁面的寬度 f大於承#面U〇a的寬度hl時，晶片封裝體11〇在運送過 '、易在凹槽1 〇2内產生側向位移，或配置的過程中定位不 M363678 良產生偏移，造成最外側的銲球114與水平壁面或垂直側壁相 碰觸。上述的缺點需進—步的改善，以尋找出最佳化的解決方 案。 【新型内容】 本創作提供一種承載晶片封裝體的托盤，避免晶片封裝體 ‘產生側向位移及定位不良，進而避免最外側的銲球與側壁碰觸 -而損傷。 本創作提出一種托盤，適於承載多個晶片封裝體，此托盤 包括一盤體以及多個位於盤體的開口部，這些開口部分別具有 一容納空間，用以容納這些晶片封裝體，且這些開口部的至少 二相對側壁限制這些晶片封裝體於各容納空間中的側向位 移，其中上述至少二相對側壁分別包括一上部壁面、一下部卷 面以及由上部壁面延伸至下部壁面的一收斂壁，而上述晶片圭 裝體的外侧周緣與上部壁面相隔—水平間距 的，二外側邊分別承靠於各收傲壁上，且上述;; 承罪面與收斂壁相夾一收斂角。 在本創作之—實施例中，上述的上部壁面、收斂壁以及1 #壁面為一曲面，且收斂壁的曲率大於上部玄 部壁面的曲率。 ㈣半請上。卩壁_曲率以幻 線盘Γ例中，上述的收敛角為收敛壁上的-線與上述日日片封裝體的承靠面相交處的-夹角Θ 在本紹k-實補巾，上述的晶 有多個銲球，而最外側鮮球的中心位=體的承罪耐M363678 V. New description: [New technical field] This creation is about a tray for the package. The temple is about a kind of carrier wafer. [Prior Art] It is generally used to carry the wafer sealing material as the material of the tray to avoid the tape. Most of the trays with antistatic composites can only be damaged by electricity. Crystal # package. The size of the package is in the size of the chip package. When the wafer has a fixed-size groove, the square must be redesigned. The conventional tray has a bottom surface directly carrying the wafer package body ed1). The pure disc is in contact with the bottom surface of the groove of the groove, and the surface of the solder ball is free from the ball of the chip package when the skin is occupied by the bale, so the 'traditional dry disk is used to avoid the bearing surface. The concave shape is used to cover the f-touch, and a kind of damage can be made to bear the chip package or (4). The contact between the spherical surface of the above-mentioned domain and the bottom surface of the groove is shown in FIG. 1A and FIG. 1B, which are schematic cross-sectional views of the conventional carrier-type wafer sealing body 102. The groove of the tray 100 is sr: the chip package 110 is mounted. The bearing surface 110a of the chip package 110 is soldered to the ball and the outermost fresh ball J is aligned with the outer side of the substrate by an appropriate width h1 so that the bearing surface of the chip package 110 is 〇 a The other bearing f is on at least two horizontal walls of the groove 102, however, the above-mentioned sin-bearing surface U〇a must be reserved in advance with sufficient spacing, thus occupying the matching ball of the solder ball 114. Two rooms. In addition, when the width f of the two horizontal walls of the recess 102 is larger than the width hl of the receiving surface U〇a, the chip package 11 is transported over, and lateral displacement is easily generated in the recess 1 〇 2, or is configured. The positioning of the M363678 does not shift well, causing the outermost solder balls 114 to touch the horizontal or vertical sidewalls. The above shortcomings require further improvements to find an optimal solution. [New content] The present invention provides a tray for carrying a chip package, which avoids the lateral displacement and poor positioning of the chip package, thereby preventing the outermost solder ball from touching the side wall and being damaged. The present invention provides a tray for carrying a plurality of chip packages, the tray including a disk body and a plurality of openings in the disk body, the openings respectively having a receiving space for accommodating the chip packages, and At least two opposite sidewalls of the opening portion limit lateral displacement of the chip package in each of the receiving spaces, wherein the at least two opposing sidewalls respectively include an upper wall surface, a lower winding surface, and a converging wall extending from the upper wall surface to the lower wall surface The outer peripheral edge of the above-mentioned wafer body is separated from the upper wall surface by a horizontal interval, and the outer side edges are respectively supported by the respective arrogant walls, and the above; the sin surface and the astringent wall are sandwiched by a convergence angle. In the present embodiment, the upper wall, the converging wall, and the 1# wall surface are a curved surface, and the curvature of the converging wall is greater than the curvature of the upper sulking wall surface. (4) Please ask half. In the example of the 卩 _ 曲率 曲率 曲率 曲率 曲率 , 曲率 曲率 曲率 曲率 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The above crystal has a plurality of solder balls, and the center of the outermost fresh ball = the tolerance of the body
水平寬度a，財平寬度a私 、相周緣相R 乘上央角Θ的正切值大於或等二 M363678 (a-r ) tan 0 2 b。 在本創作之-實施例中，上述的收傲壁為一斜面 角的正切值為該斜面的斜率。 在本創作之-實施例巾，上述至少二收缝的下 的間距為W ’而上述晶片封裝體的外側周緣具有声、H， 且上述晶片封裝體的承靠面配置有多個鮮球，最鲜The horizontal width a, the margin width a private, the phase peripheral phase R multiplied by the central angle Θ tangent value is greater than or equal to two M363678 (a-r) tan 0 2 b. In the present invention, the tangential value of the slanting angle is a slope of the slope. In the embodiment of the present invention, the distance between the at least two slits is W', and the outer periphery of the chip package has sound and H, and a plurality of fresh balls are disposed on the bearing surface of the chip package. Freshest
於該外側周緣相隔—第一水平寬度ai，其中〜小二= 大於 Wl-2ai。 ^ W 在本創作之-實施财，上述晶片封裝體的承靠面配 夕個鮮球，而最外側銲球相對於外侧周緣相隔一第—水 h ’且收斂壁的上死點與下死點之間具有 &， 其中a】大於a2。 κ十見度a2 多個ΪΠΪ；—彳實闕^以“賴翻承靠面配置有 夕们知球*最外側_相對於外側周緣相隔—第 收斂㈣，點與下死點之間具有—第二水平寬度&， 上收斂角θ的正切值大於或等於鲜球 亘同度t>，表不為aitan6> 。 梯面=創5之—實施例中，上述的收斂壁為-階梯面，且階 梯面具有mum — 相連接，而第二_下死點與下部壁面相連接。…F土面 在本創作之-實施例中，上述的第—面為—斜面或垂直 :平面為—水平面’且上述晶片封裝體的承靠面承靠於 之間實施例中’上述至少二相對第—面的下死點 上、f曰H 辨，而上述晶片封裝體位於各容納空間中時， 上述日日片封衣體的外側周緣的寬度約略小於W2。 M363678 上述曰Ϊ片本例中’上述的水平面具有—寬度cU， 心位置相對於外側周有多：銲球’而最外側銲球的中 銲球的半徑r、及兮^目^水平見度a’且水平寬度a減去 收敛角Θ的正H平面的寬度&所得到的數值㈣D乘上 等於鮮球的垂直高度b，表示為 y dn6^b，且 a_r>d卜 ’第一 =另—實施例中’上述的階梯面還具有連接於該 ，上述^ 録面，該水平面具有—寬度 的中:位置相對置rt >d]o U直间度b，表不為（a-OtanUb，且a_r 在本創作之一實施例t，盤體具有一上表面， imr還具有—向上延伸面，向上延伸面傾斜地連接^ 二：。=’盤體具有一下表面，且下表面與下部壁面之間 ，向下延伸面傾斜地連接至下表面。 體，作制最錄料触财承載晶片封裝 二的:二^ 咖，下文特舉實 【實施方式】 θ 目2C刀別為本創作—實施例的把盤的俯視示意 M363678 圖，而圖3為本創作第一實施例的托盤沿著〗_[線的剖面示意 圖。 請參考圖2A〜圖2C ’本實施例的托盤的盤體2〇〇具有三 種態樣的開口部202a〜202c (僅紛示其一），分別由盤體2〇〇 的上表面200a貫穿延伸至盤體200的下表面2〇〇b。這三種態 樣的開口部202a〜202c的上邊緣P1圍成較大尺寸的空間，而 開口部202a~202c的側壁swl〜sw4由上邊緣pi朝下邊緣p2 向内延伸，以形成較小尺寸的一容納空間（凹槽）c，以使晶 片封裝體210 (見圖3)能由上而下放置於此容納空間（凹槽） C中，並且晶片封裝體210能夠承載於開口部的至少二相對侧 壁swl〜sw4 (本實施例繪示四個壁面）上，以限制晶片封裝 體210於容納空間C中的側向位移，如圖3所示。在本實施例 中’晶片封裝體210例如是球腳格狀陣列（Ball Gdd Army， BGA)封裝之晶片封裝體。 在圖2A中’開口部202a的側壁是由四個連續的壁面swi 〜sw4所圍成的，以使晶片封裝體21〇的四個外侧邊分別承靠 在四個連續的壁面swl〜SW4上。在圖2B中，開口部202b的 側壁是由四個獨立的壁面SW1〜sw4所組成的，以使晶片封裝 體210的四個外側邊分別承靠在四個獨立的壁面swl〜sw4 上。在圖2C中，開口部202c的側壁是由四個獨立角形的壁面 swl〜sw4所組成的，以使晶片封裝體21〇的四個角落分別承 罪在四個獨立角形的壁面swl〜sw4上。然而，由圖3可知， 在同一方向的I-Ι剖面上，晶片封裝體21〇只要能夠承靠在至 少二相對側壁上即可，不限定其開口部的態樣。 以下介紹上述其中一種態樣的開口部的二相對側壁的細 部構造，共有四種具體的實施方式，但並非用以限制本創作。 M363678 請先參考圖3的剖面示意圖，由盤體200的上表面2〇0&往下 表面200b延伸的剖面圖中，開口部的二相對側壁2〇〇c分別具 有上部壁面R1、收斂壁R2以及下部壁面R3。值得注意的是'， 上部壁面R1、收斂壁R2以及下部壁面R3例如為連續曲率變 化的曲面（亦可為不連續曲率），以曲率的大小來論，、收敛壁 R2的中心處可為曲率最大的壁面，也就是晶片封裝體21〇承 -靠所在處，而上部壁面R1的曲率以及下部壁面R3的曲率分 .別小於收斂壁R2的中心處的曲率，如此，曲面漸漸由中心處 φ 向上、下兩側擴張，以使晶片封裝體210的外侧周緣212與上 部壁面R1相隔一水平間距d(例如沿著上部壁面R1向上漸增 或為固定值），而晶片封裝體210的承靠面21〇a的至少二夕曰卜 側邊s分別承靠於收斂壁R2上，且晶片封裝體21〇的承靠面 210a與收斂壁;R2相夾一收斂角θ。 承上所述，當收斂壁R2為曲面時，收斂壁R2上任一點 的切線（tangent)斜率會隨著曲率的變化而改變，以本實施例 而二，在收斂壁R2的中心處上的切線τ與晶片封裝體21〇的 承罪面210a相交處的夾角0定義為收斂角。值得注竜的是， # 纽斂^符合下列的公式⑴，可避免最外側的鋅球Vl4 (配 置於承靠面21〇a)與下部壁面R3接觸而損傷，公式(1)為： (a-r) tan0 其中’a為最外側銲球214的中心位置相對於外側周緣2i2 相的水平寬度’ r為鐸球214的半徑，而b為銲球214的垂 直高度，tan6>為夾角的正切值。 在公式(1)中，當水平寬度a減去銲球214的半徑r所得到 的數乘上夾角θ的正切值大於或等於鲜球214的垂直高 度b時’即可避免晶片封裝體21〇的縣214在容納空間c M363678 中被直接碰觸而損壞。 接著’在圖3之-較佳實施例中，盤體2〇〇的上表面細& 與上部壁面R1之間還射—向上延伸面R4，向上延伸面似 傾斜地連接至上表面2_，可使開口部更寬廣，更容易放置 晶片封裝體210。此外，盤體的下表面懸與下部壁面 R3之間退具有一向下延伸面R5，向下延伸面傾斜地連接 至下表面鳩，並增加銲球214下方㈣間，可 以4碰撞到下表面2〇〇b的風險。 战少知球 本領域具有通常知識者可理解，上述的向上延伸面則鱼 面R5不限定配置於圖3的實施例中，_度地配 置於本巧作的其他實施财，故不再於其他實施例中費述。 —立接著’ ^ 4為本創作第二實施觸減沿著H線的剖面 不思圖。請蒼考圖4，開口部的二相對側壁2_分 ，壁面U、收斂壁L2以及下部壁面u。值得注意的是，收 斂壁L2例如為向下傾斜的斜面，此斜面的上死點與上部壁面 例如疋垂直壁面）相連接，而下死點與下部壁面U (例 壁面）相連接，而當晶片封裝體21G的至少二外側邊 =承罪於各收斂壁L2的中心處時，晶片封賴_的外側 與上部壁面L1相隔—水平間距d，晶片封裝體21〇 的承罪面210a與收斂壁L2相夹一收斂角0，例如是3〇度〜 =度’故可避免晶片封裝體21〇產生側向位移。由圖4可:口， 收斂角0的正切值為收斂壁L2 (斜面）的斜率。 有關收斂角的計算方式，請參考公式⑴：（a_〇tanUb， 但'不以ith卷Ρϋ。 周緣 在公式(1)中，a為最外側銲球214的中心位置相對於外側 212相隔的水平寬度，r為銲球214的半徑，而b為婷球 M363678 214的垂直高度。 為了使斜面能確實承載晶片封裝體210’圖4的開口部的 尺寸可配合晶片封裝體210的尺寸做最佳化設計。首先，定義 w為至少二收斂.L2的下死點之間的間距，而d為水平間距， ai為最外側銲球214相對於外側周緣212相隔的水平寬度，且 知為收斂壁L2的上死點與下死點之間相隔的水平寬度，其中 〜大於处。接著，定義晶片封裝體210的外側周緣212具有一 -寬度wi ’其中w小於W1，且w大於W1_2ai，以避免晶 封褒體210位於容納空間C中時，無法完全地承靠在斜面上。 在另-實施例t，當ai小於％時，&乘上μ θ的正切值大 於或等於銲球214的垂直高度b，表示為altanGb，也可避 免在放置過程中晶片封裳體210沿收敛壁L2滑動時，下部辟 面u與最外側的銲球214相碰觸。 下4 土 面亍=，’ LIB為ί創作第三實施例的著W線的剖 圖二而圖5B為圖5A的晶片封裝體配置於容納空 過程中的放大示意圖。喑夂本θ n门 η工门的 側壁200e分別具有上^ ^ 5Α及圖犯，開口部的二相對 面S4。值得注意的是，^S、收f壁S2、S3以及下部壁 面具有相交的第-面S2i^1 s 3^_^’此階梯 疋玉直壁面）相連接，而當- =點與下雜面S4 (糾_錢 I 3的下 當晶片封裝體21〇的承靠而，ln逐接在圖5B中， 滑落至第二面S3 (水第—面S2 (斜面）向下 犯與上部壁面S1相隔，匕 裝曰體210的外侧周緣 靠面210a盥收斂壁的第 日日片封裝體210的承 ” 土的弟〜面S2 (例如是斜面）於滑 -收敛角Θ，例如約6〇声 ㈣；〜约相夾 度〜80度。由圖5A可知，當 11 M363678 展 位於各容納空間c中時，至少二相對第—面S2的下 死點之間的間距為W2，而晶片封裝體21〇的外側周緣加的 寬度W1約略小於W2，因此可避免產生侧向位移。、' η此外’在圖5B中，當收斂角Θ符合下列的公式⑵，{避 免最外側的銲ί求214與下部壁面S4接觸而損傷，公 (a-r-dl) taMgb，且 a-r>dl ^外側銲球214的中心位置相對於外側周緣21 ϋΐ 為銲球214的半徑，以為第二面％ (水:The outer circumference is separated by a first horizontal width ai, wherein ~ small two = greater than Wl-2ai. ^ W In this creation-implementation, the bearing surface of the above chip package is matched with a fresh ball, and the outermost solder ball is separated from the outer circumference by a water-h' and the top dead center of the convergence wall is dead. There is & between points, where a] is greater than a2. κ 十见度a2 A plurality of ΪΠΪ; - 彳 阙 以 ^ "" 翻 承 承 配置 配置 配置 配置 配置 配置 配置 配置 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * The second horizontal width &, the tangent value of the convergence angle θ is greater than or equal to the fresh ball uniformity t>, which is not aitan6>. The ladder surface = the fifth one - in the embodiment, the above-mentioned convergence wall is a - step surface And the step surface has a mum - connected, and the second bottom dead point is connected to the lower wall surface. ...F soil surface in the present embodiment - in the embodiment, the first surface is - bevel or vertical: plane is - The water level 'and the bearing surface of the chip package bears against the bottom dead center of the at least two opposite first faces in the embodiment, and the chip package is located in each of the receiving spaces The width of the outer circumference of the above-mentioned Japanese and Japanese piece seal body is about slightly smaller than W2. M363678 The above-mentioned bracts in this example 'the above-mentioned horizontal plane has a width cU, and the heart position is relatively more than the outer circumference: the solder ball' and the outermost solder ball The radius r of the middle solder ball, and the ^^目^level visibility a' and the horizontal width a Subtracting the width of the positive H-plane of the convergence angle && the obtained value (4) D multiplied by the vertical height b of the fresh ball, denoted as y dn6^b, and a_r>d 卜 'first=other-in the embodiment' The step surface is further connected to the above-mentioned recording surface, wherein the horizontal plane has a width of - a position relative to rt > d] o U straightness b, which is not (a-OtanUb, and a_r is in the present In an embodiment t, the disk body has an upper surface, and the imr further has an upwardly extending surface, and the upwardly extending surface is obliquely connected. The two sides of the disk have a lower surface and a lower surface and a lower wall surface. The extension surface is obliquely connected to the lower surface. The body is made of the most recorded material to carry the chip package 2: 2, the coffee, the following is a special implementation [embodiment] θ 2C knife is the original creation - the embodiment of the disk FIG. 3 is a schematic cross-sectional view of the tray of the first embodiment of the present invention taken along the line _[. Referring to FIG. 2A to FIG. 2C, the tray body 2 of the tray of the present embodiment has three aspects. Openings 202a to 202c (only one of them is shown), respectively, by the upper side of the disk 2 The surface 200a extends through the lower surface 2〇〇b of the disk body 200. The upper edges P1 of the three kinds of openings 202a to 202c enclose a space of a larger size, and the side walls sw1 to sw4 of the openings 202a to 202c are The upper edge pi extends inwardly toward the lower edge p2 to form a receiving space (groove) c of a smaller size so that the chip package 210 (see FIG. 3) can be placed from above to below in the receiving space (groove) C, and the chip package 210 can be carried on at least two opposite sidewalls sw1 to sw4 of the opening (four walls in this embodiment) to limit the lateral displacement of the chip package 210 in the receiving space C ,As shown in Figure 3. In the present embodiment, the chip package 210 is, for example, a chip package of a Ball Gdd Army (BGA) package. In FIG. 2A, the side wall of the opening portion 202a is surrounded by four continuous wall surfaces swi to sw4 so that the four outer side edges of the chip package body 21 are respectively supported by the four continuous wall faces sw1 to SW4. . In Fig. 2B, the side wall of the opening portion 202b is composed of four independent wall faces SW1 to sw4 so that the four outer side edges of the chip package body 210 are respectively supported on the four independent wall faces sw1 to sw4. In FIG. 2C, the side wall of the opening portion 202c is composed of four independent angular wall faces sw1 to sw4, so that the four corners of the chip package body 21 are respectively invaded on the four independent angular wall faces sw1 to sw4. . However, as is apparent from Fig. 3, in the I-Ι cross section in the same direction, the chip package 21 can be placed on at least two opposing side walls, and the opening portion is not limited. The detailed construction of the opposite side walls of the opening portion of one of the above aspects will be described below. There are four specific embodiments, but are not intended to limit the present invention. M363678 Referring to the cross-sectional view of FIG. 3, in the cross-sectional view of the upper surface 2〇0 of the disk 200 extending toward the lower surface 200b, the opposite side walls 2〇〇c of the opening have an upper wall surface R1 and a converging wall R2, respectively. And the lower wall R3. It is worth noting that the upper wall R1, the convergent wall R2 and the lower wall R3 are, for example, curved surfaces with continuous curvature changes (which may also be discontinuous curvatures). The curvature may be in the center of the convergent wall R2. The largest wall surface, that is, the wafer package body 21 is located at the same place, and the curvature of the upper wall surface R1 and the curvature of the lower wall surface R3 are not smaller than the curvature at the center of the convergence wall R2, so that the surface gradually becomes φ from the center. The upper and lower sides are expanded so that the outer peripheral edge 212 of the chip package 210 is separated from the upper wall surface R1 by a horizontal interval d (for example, increasing upward or fixed along the upper wall surface R1), and the chip package 210 is supported. At least two sides of the surface 21〇a s are respectively supported by the converging wall R2, and the bearing surface 210a of the chip package 21〇 and the astringent wall; R2 are sandwiched by a convergence angle θ. As described above, when the convergent wall R2 is a curved surface, the tangent slope of any point on the convergent wall R2 changes with the change of the curvature, in this embodiment and the tangent at the center of the convergent wall R2. An angle 0 at which τ intersects the sinus surface 210a of the chip package 21A is defined as a convergence angle. It is worth noting that #纽引^ conforms to the following formula (1), which avoids the damage of the outermost zinc ball Vl4 (disposed on the bearing surface 21〇a) and the lower wall surface R3, and the formula (1) is: (ar Tan0 where 'a is the horizontal width of the center position of the outermost solder ball 214 with respect to the outer peripheral edge 2i2, r is the radius of the ball 214, and b is the vertical height of the solder ball 214, and tan6> is the tangent of the angle. In the formula (1), when the horizontal width a minus the radius r of the solder ball 214 multiplied by the tangent of the included angle θ is greater than or equal to the vertical height b of the fresh ball 214, the chip package 21 can be avoided. The county 214 was damaged by direct contact in the accommodation space c M363678. Then, in the preferred embodiment of FIG. 3, the upper surface of the disk body 2 is thinner and the upper wall surface R1 is further incident with the upwardly extending surface R4, and the upwardly extending surface is obliquely connected to the upper surface 2_. The opening portion is wider, and the chip package 210 is more easily placed. In addition, the lower surface of the disk body and the lower wall surface R3 have a downward extending surface R5, and the downward extending surface is obliquely connected to the lower surface 鸠, and the bottom (4) of the solder ball 214 is increased, and the lower surface 2 can be collided. The risk of 〇b. It is understood by those skilled in the art that the above-mentioned upwardly extending surface, the fish surface R5 is not limited to be arranged in the embodiment of FIG. 3, and is disposed in other implementations of the present invention. It is stated in other embodiments. —Let' then follow the ^ ^ 4 for the second implementation of the creation to reduce the profile along the H line. Please refer to Fig. 4, the opposite side walls of the opening 2_, the wall U, the convergent wall L2 and the lower wall u. It should be noted that the convergent wall L2 is, for example, a downwardly inclined slope, the top dead center of which is connected to the upper wall surface, for example, a vertical wall surface, and the bottom dead center is connected to the lower wall surface U (such as a wall surface). When at least two outer sides of the chip package 21G are at the center of each of the convergent walls L2, the outer side of the wafer encapsulation is separated from the upper wall surface L1 by a horizontal pitch d, and the sinus surface 210a of the chip package 21 is The convergence wall L2 is sandwiched by a convergence angle of 0, for example, 3 degrees to = degrees, so that lateral displacement of the chip package 21 is prevented. From Fig. 4, the tangent of the convergence angle 0 is the slope of the convergence wall L2 (bevel). For the calculation of the convergence angle, please refer to the formula (1): (a_〇tanUb, but 'not ith Ρϋ. The circumference is in the formula (1), a is the center position of the outermost solder ball 214 is separated from the outer side 212 The horizontal width, r is the radius of the solder ball 214, and b is the vertical height of the T-ball M363678 214. In order to enable the bevel to reliably carry the chip package 210', the size of the opening of FIG. 4 can be matched to the size of the chip package 210. First, define w as at least two convergence. The spacing between the bottom dead centers of L2, and d is the horizontal spacing, ai is the horizontal width of the outermost solder balls 214 with respect to the outer circumference 212, and is known as convergence. a horizontal width between the top dead center and the bottom dead center of the wall L2, wherein ~ is greater than. Next, the outer peripheral edge 212 defining the chip package 210 has a width -w, where w is less than W1, and w is greater than W1_2ai, When the crystal sealing body 210 is prevented from being located in the accommodating space C, it cannot completely bear on the inclined surface. In another embodiment t, when ai is less than %, the tangent value of & multiplied by μ θ is greater than or equal to the solder ball 214. The vertical height b, expressed as altanGb, is also available When the wafer sealing body 210 slides along the converging wall L2 during the placement process, the lower surface u touches the outermost solder ball 214. The lower 4 soil surface 亍 =, ' LIB is ί created the third embodiment FIG. 5B is an enlarged schematic view showing the chip package of FIG. 5A disposed in the accommodating process. The side wall 200e of the θ n gate η gate has an upper surface and a pattern, respectively. The opposite side of the S4. It is worth noting that the ^S, the receiving wall S2, S3 and the lower wall have intersecting first-surface S2i^1 s 3^_^' this step is the straight wall surface of the jade, and when - = point and lower surface S4 (correction of money I 3 under the chip package 21 而, ln is connected in Figure 5B, sliding down to the second side S3 (water first - surface S2 (bevel) The downward sin is separated from the upper wall surface S1, and the outer peripheral edge of the armored body 210 is opposite to the surface 210a. The first day of the solar cell package 210 of the converging wall is the "slope" of the soil-surface S2 (for example, a slope) at the slip-convergence angle. Θ, for example, about 6 hum (4); ~ about 夹 ～ 80 degrees. As can be seen from Fig. 5A, when 11 M363678 is located in each accommodating space c, at least two relative first faces The spacing between the bottom dead centers of S2 is W2, and the width W1 of the outer peripheral edge of the chip package 21〇 is slightly smaller than W2, so that lateral displacement can be avoided. 'ηη' in Fig. 5B, when convergence angle ΘCompliant with the following formula (2), {avoid the outermost weld 214 from contact with the lower wall surface S4 to damage, the male (ar-dl) taMgb, and the a-r> dl ^ the outer position of the outer solder ball 214 relative to the outer periphery 21 ϋΐ is the radius of the solder ball 214, which is the second side % (water:
=的寬度’ * b為銲球214的垂直高度，t㈣為央角的』 而的ίίί/2)中’當水平寬度a減去鲜球214的半徑r及水， 到的數值㈣υ乘上夾角0的正切值大於邊 ί έ Γ直高度b時，即可避免晶片封農體⑽的舞 表 在合、、、内二間c中被直接碰觸而損壞。 接著’圖6A為本創作另—實關的托盤沿著n 1剖面示意圖’而® 6B為圖6A的晶片封裝體配置於容納; 間的過私中的放大示意圖。請參考圖6A，開The width of = ' b is the vertical height of the solder ball 214, t (four) is the central angle of the ί ί /2) 'When the horizontal width a minus the radius r of the fresh ball 214 and the water, the value (4) υ multiplied by the angle When the tangent value of 0 is greater than the edge ί Γ Γ straight height b, the dance table of the wafer sealing body (10) can be prevented from being directly touched and damaged by the inner and the inner c. Next, FIG. 6A is an enlarged schematic view of the tray in which the substrate is disposed along the n 1 cross-section and the 6B is the chip package of FIG. 6A. Please refer to Figure 6A, open
壁冨分別具有上部壁面S1、收敛壁幻、％、幻 壁面S4。值得注意的是，收斂壁S2、V卜S3例如為階梯面 =梯面具有-第—面S2、—第二面S3以及連接於^梯面面§ ^-面S3之間的—垂直面v卜垂直面％的高度為匕，市 弟面S2的上死點與上部壁面S1 (例如是斜面）相連接，筹 二面S3的下死點與下部壁面如（例如是垂直壁面）相連接< 在圖6B中，當晶片封裝體210的承靠面21〇a沿著第—面s, (斜面）向下滑落至第二面S3 (水平面）時，，晶片 楚 210的外侧周緣212與上部壁面S1相隔一水平間距4，且^ > 12 M363678 封衣體210的承靠面21〇a與收斂壁的第—面於滑落時相爽 一收斂角Θ ’例如約6〇度〜8〇度。如同圖5A所述，由於 封裝體210的外侧周、緣212喊度W1約略小於％，因:可 避免產生側向位移。。 门另外，在圖6B中，當收斂角0符合下列的公式⑶，可避 免最外側轉球214與下部壁面84或收斂壁接觸而損傷，公 式(3)為： (a-r ) tan 61 2b，且 a-r> dl 其中’a為最外側銲球214的中心位置相對於外側 i2 相隔的水平寬度，r為銲球叫的半徑，dl為第二面％ (水平 面）的寬度，* b為銲球214的垂直高度，_為失角的正 切值。 在公式(3)中，當水平寬度a減去銲球214的半徑r所得到 的數值㈣乘上夾角Θ的正切值大於或等於鲜球214的垂 度b時’即可避免晶片封裝體21G的輝球214在容納 中被直接碰觸而損壞。 綜上料，賴作_最佳化設計触錄㈣晶片封裝 體’可避免晶片封裝體在運送過程中產生側向位移或在配置的 棘中良產生偏移，進㈣免最相的銲球與側壁碰觸 而損傷。同時’本創作可廣泛地應用於各式設計的晶 體’以符合使用者不同的需求。 、 車巳 雖然本創作已以實施例揭露如上，然其並非用以限定 任何所屬技觸域巾具有通f知識者，在不脫離本創作之 精神和範圍内，當可作些許之更動與潤飾，故本創作之保 圍當視後附之申請專利範圍所界定者為準。 13 M363678 【圖式簡單說明】 圖1A及圖1B分別為習知一種承載晶片封裝體的托盤的 示意圖及凹槽區域的剖面示意圖。 圖2A〜圖2C分別為本創作一實施例的托盤的俯視示意 圖。 圖3為本創作第一實施例的托盤沿著I-Ι線的剖面示意圖。 圖4為本創作第二實施例的托盤沿著I-Ι線的剖面示意圖。 圖5A為本創作第三實施例的托盤沿著I-Ι線的剖面示意 圖。 圖5B為圖5A的晶片封裝體配置於容納空間的過程中的 放大示意圖。 圖6A為本創作另一實施例的托盤沿著I-Ι線的局部剖面 示意圖。 圖6B為圖6A的晶片封裝體配置於容納空間的過程中的 放大示意圖。 【主要元件符號說明】 100 :托盤的盤體 102 :凹槽 110 :晶片封裝體 112 :外側周緣 110a :承靠面 114 :銲球 hi、h2 :寬度 200 :托盤的盤體 202a〜202c :開口部 M363678 200a :上表面 200b :下表面 200c、200d、200e、200f ··側壁 210 :晶片封裝體 212 :外側周緣 210a :承靠面 . 214 :銲球 . P1 :上邊緣 P2 :下邊緣 • swl〜sw4 :侧壁（壁面） C:容納空間（凹槽） ίϋ、U、S1 :上部壁面 R2、L2、S2、S3 :收斂壁 R3、L3、S4 :下部壁面 R4 :向上延伸面 R5 :向下延伸面 d ·水平間距 • dl :寬度 6» :收斂角 T :切線 S :外侧邊 b ·垂直南度 ‘ r:銲球的半徑 - W :間距 W1 :寬度 W2 :間距 15 M363678 ai:第一水平寬度 a2 :第二水平寬度 52 :第一面 53 :第二面 VI :垂直面The niches have an upper wall surface S1, a convergence wall illusion, a %, and a phantom wall surface S4, respectively. It is to be noted that the ablation wall S2, Vb, S3 is, for example, a step surface = a step surface having a -th surface S2, a second surface S3, and a vertical plane v connected between the θ ^- plane S3 of the plane surface The height of the vertical plane % is 匕, and the top dead center of the city side S2 is connected to the upper wall surface S1 (for example, a slope), and the bottom dead center of the two sides S3 is connected with the lower wall surface (for example, a vertical wall surface) In FIG. 6B, when the bearing surface 21〇a of the chip package 210 slides down along the first surface s (the inclined surface) to the second surface S3 (horizontal plane), the outer peripheral edge 212 of the wafer 210 is The upper wall surface S1 is separated by a horizontal interval 4, and the bearing surface 21〇a of the sealing body 210 and the first surface of the astringent wall are cool at a certain angle of convergence 例如 ', for example, about 6 degrees ～8 〇度. As shown in Fig. 5A, since the outer circumference and edge 212 of the package body 210 are slightly less than %, the lateral displacement can be avoided. . In addition, in FIG. 6B, when the convergence angle 0 satisfies the following formula (3), the outermost ball 214 can be prevented from being damaged by contact with the lower wall surface 84 or the astringent wall, and the formula (3) is: (ar) tan 61 2b, and A-r> dl where 'a is the horizontal width of the center position of the outermost solder ball 214 with respect to the outer side i2, r is the radius of the solder ball, dl is the width of the second side % (horizontal plane), * b is the welding The vertical height of the ball 214, _ is the tangent of the corner. In the formula (3), when the horizontal width a minus the radius r of the solder ball 214 is obtained by multiplying the value of the angle Θ by the tangent of the angle 大于 greater than or equal to the sag b of the fresh ball 214, the chip package 21G can be avoided. The glow ball 214 is directly damaged by the touch in the accommodation. In summary, the _optimized design touch (4) chip package 'can avoid the lateral displacement of the chip package during transport or offset in the configuration of the spine, into (four) free of the most suitable solder balls Damaged by touching the side wall. At the same time, 'this creation can be widely applied to crystals of various designs' to meet the different needs of users. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the knowledge of any of the technical touches, and it is possible to make some changes and refinements without departing from the spirit and scope of the present creation. Therefore, the scope of the patent application scope of this creation is subject to the definition of the patent application scope. 13 M363678 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B are respectively a schematic view of a conventional carrier carrying a chip package and a schematic cross-sectional view of a groove region. 2A to 2C are plan views schematically showing a tray of an embodiment of the present invention. Figure 3 is a cross-sectional view of the tray of the first embodiment of the present invention taken along the I-Ι line. 4 is a cross-sectional view of the tray of the second embodiment of the present invention taken along the I-Ι line. Fig. 5A is a schematic cross-sectional view of the tray of the third embodiment of the present invention taken along the line I-Ι. Fig. 5B is an enlarged schematic view showing the process of disposing the chip package of Fig. 5A in the accommodating space. Figure 6A is a partial cross-sectional view of the tray along the I-Ι line of another embodiment of the present invention. Fig. 6B is an enlarged schematic view showing the process of disposing the chip package of Fig. 6A in the accommodating space. [Main component symbol description] 100: tray body 102: groove 110: chip package 112: outer circumference 110a: bearing surface 114: solder balls hi, h2: width 200: tray trays 202a to 202c: opening Part M363678 200a: upper surface 200b: lower surface 200c, 200d, 200e, 200f · side wall 210: chip package 212: outer circumference 210a: bearing surface. 214: solder ball. P1: upper edge P2: lower edge • swl ~sw4 : Side wall (wall surface) C: Storage space (groove) ϋ , U, S1 : Upper wall surface R2 , L2 , S2 , S3 : Convergence wall R3 , L3 , S4 : Lower wall surface R4 : Upward extension surface R5 : Direction Lower extension surface d · Horizontal spacing • dl : Width 6» : Convergence angle T : Tangent S: Outer side b · Vertical south degree ' r: Radius of solder ball - W : Spacing W1 : Width W2 : Spacing 15 M363678 ai: a horizontal width a2: a second horizontal width 52: a first side 53: a second side VI: a vertical surface