TWI834973B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI834973B
TWI834973B TW110119216A TW110119216A TWI834973B TW I834973 B TWI834973 B TW I834973B TW 110119216 A TW110119216 A TW 110119216A TW 110119216 A TW110119216 A TW 110119216A TW I834973 B TWI834973 B TW I834973B
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Taiwan
Prior art keywords
interposer
main surface
semiconductor
mentioned
semiconductor device
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TW110119216A
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English (en)
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TW202238854A (zh
Inventor
茨木聡一郎
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日商鎧俠股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一個實施型態係以提供可以提升被安裝之半導體晶片之可靠性的半導體裝置為目的。 若藉由一個實施型態時，在半導體裝置中，第1中介層具有第1主面。第2中介層被配置在第1主面。第2中介層在第1中介層之相反側具有第2主面。第2中介層和第1中介層材質不同。第1半導體晶片具有第1表面。第1半導體晶片係在第1表面面對於第2主面之狀態下，隔著複數凸塊電極被安裝於第2主面。第1半導體晶片具有揮發性記憶體電路。第2半導體晶片係經由複數接合引線而被安裝於配置在第1主面或第2主面的複數電極圖案。第2中介層在垂直於第1主面的方向，與第1半導體晶片重疊。

Description

半導體裝置
本揭示係關於半導體裝置。 [相關申請案] 本申請案享有作為基礎申請的日本專利申請案第2021-042091號(申請日：2021年3月16日)的優先權。本申請藉由參照該基礎申請而包含基礎申請的全部內容。
有在中介層之主面隔著複數凸塊電極安裝半導體晶片而構成半導體裝置之情形。此時，以提升被安裝的半導體晶片之可靠性為佳。
一個實施型態係以提供可以提升被安裝之半導體晶片之可靠性的半導體裝置為目的。 若藉由一個實施型態時，提供具有第1中介層和第2中介層和第1半導體晶片和第2半導體晶片之半導體裝置。第1中介層具有第1主面。第2中介層被配置在第1主面。第2中介層在第1中介層之相反側具有第2主面。第2中介層和第1中介層材質不同。第1半導體晶片具有第1表面。第1半導體晶片係在第1表面面對於第2主面之狀態下，隔著複數凸塊電極被安裝於第2主面。第1半導體晶片具有揮發性記憶體電路。第2半導體晶片係經由複數接合引線而被安裝於配置在第1主面或第2主面的複數電極圖案。第2中介層在垂直於第1主面的方向，與第1半導體晶片重疊。
以下，參照附件圖面，詳細說明實施型態所涉及之半導體裝置。並且，並不藉由該些實施型態限定本發明。 (實施型態) 實施型態所涉及之半導體裝置係混載複數種半導體晶片之混合型之半導體裝置。例如，隨著以智慧型手機為代表的攜帶機器之高性能、高功能化和輕薄短小化之進展，有要求被搭載於機器之記憶體半導體裝置之大容量化和封裝體之輕薄短小化之相容的情形。因應如此之要求，在半導體裝置中，能混載彼此種類不同的第1半導體晶片和第2半導體晶片。第1半導體晶片係例如記憶體控制器，第2半導體晶片係例如快閃記憶體等之記憶體晶片。第2半導體晶片為了爭取記憶體容量，被構成尺寸大於第1半導體晶片。第1半導體晶片之能夠配置的區域會因應第2半導體晶片之配置而被限定。 例如，混合記憶體模組之一型態在作為代表性的安裝記憶體的UFS(Universal Flash Storage)中，藉由外部規格團體，外圍器之縱橫尺寸被規定，封裝體之設計自由度小。若為大容器製品時，為了提升安裝密度，可考慮採用階段狀地疊層第2半導體晶片之構造。晶片和封裝體之長邊尺寸幾乎相同的CSP(Chip Scale Package)型之封裝體之情況，為了實現與主機側的高速訊號之接收發送，有在被疊層為階段狀的複數第2半導體晶片之最下段正下方配置第1半導體晶片之情形。並且，為了減少第1半導體晶片之主機介面之接合引線之寄生LCR成分所致的負載而縮短電長度，再者，為了對應於隨著第1半導體晶片之高功能化的多接腳化，考慮以倒裝晶片構造安裝第1半導體晶片。 第1半導體晶片係在記憶體控制器之情況，能搭載揮發性記憶體電路作為快取區域等。揮發性記憶體電路為例如SRAM(Static Random Access Memory)。第1半導體晶片有SRAM藉由系統規模之大規模化而被大容量、低電壓化之傾向，該些要素與每單位裝置之軟性錯誤率(FIT)和取捨有關。 例如，考慮第1半導體晶片被安裝於第1中介層之構成。第1中介層從成本等之觀點來看，能使用包含放射線源之有機中介層。第1半導體晶片係當以倒裝晶片構造被安裝於第1中介層時，比起以接合引線構造被安裝在第1中介層之情況，能與第1中介層內之放射線源的距離更接近。依此，被搭載於第1半導體晶片之SRAM容易引起軟性錯誤，有位翻轉(bit flip)耐性等的軟性錯誤耐性下降的可能性。 再者，在第1半導體晶片採用倒裝晶片構造之情況，能實現第1半導體晶片之超多接腳化所致的低背凸塊且窄間距的倒裝晶片連接。因此，藉由第1中介層(例如，有機中介層)和第1半導體晶片之線膨脹係數的錯誤配對，藉由電極之接合部分斷裂，有連接可靠性，即是機械性可靠性下降的可能性。 再者，電路密度由於第1半導體晶片之高性能、高功能化而上升，但晶片面積有收縮傾向時，則有在第1半導體晶片的發熱密度變高的傾向。因此，有第1半導體晶片之溫度更上升所致的半導體裝置之品質、性能的可靠性，即是熱性的可靠性下降的可能性。 於是，本實施型態中，在半導體裝置中，於第1中介層和第1半導體晶片之間追加第2中介層，將第1半導體晶片倒裝晶片安裝於第2中介層。第2中介層能由放射線之遮蔽能力較第1中介層強，機械性、熱性的特定更接近於第1半導體晶片的材質形成。依此，在半導體裝置中，能謀求軟性錯誤耐性之提升和機械性、熱性之可靠性的提升。 具體而言，半導體裝置1能被構成如圖1及圖2所示般。圖1為表示半導體裝置1之構成的剖面圖。圖2為表示半導體裝置1之構成的俯視圖。 半導體裝置1具有中介層(第1中介層)10、半導體晶片(第1半導體晶片)20、中介層(第2中介層)30、複數半導體晶片(複數第2半導體晶片)40-1、40-2、密封樹脂50、外部電極60及間隔件70。在以下中，將垂直於中介層10之面積最大的面之中的一個(表面10a、第1主面)的方向設為Z方向，將在垂直於Z方向之平面內彼此正交的2方向設為X方向及Y方向。 中介層10在+Z側具有面積最大的面(表面10a、第1主面)，在-Z側具有面積最大的另外之面(背面10b、第2主面)。在中介層10之表面10a，配置中介層30，隔著中介層30而安裝半導體晶片20。再者，在中介層10之表面10a側，隔著接著層81及間隔件70而安裝複數半導體晶片40-1、40-2。 在中介層10之表面10a配置有開口部10a1。在開口部10a1內配置中介層30。即是例如中介層30之背面30b以接著劑等被接著於開口部10a1之底面亦可。中介層30係在XY俯視下為略矩形狀，在YZ俯視下為略矩形狀。 開口部10a1具有對應於中介層30的平面形狀。例如，開口部10a1係藉由使用雷射或鑽頭而對中介層10之表面10a進行鍯孔加工而被形成。因此，開口部10a1即使在XY俯視下，如圖2例示般，被辨識為由於製程性的主要原因在角部多少具有圓角或倒角的大概矩形狀的形狀亦可。在圖2中，例示複數半導體晶片40-1、40-2及密封樹脂50被去除之狀態的平面構成。開口部10a之X方向寬度係對應於中介層30之X方向寬度，具有在中介層30之X方向寬度加上餘裕的大小。開口部10a之Y方向寬度係對應於中介層30之Y方向寬度，具有在中介層30之Y方向寬度加上餘裕的大小。在從Z方向透視之情況，開口部10a1在內側包含中介層30。 開口部10a1具有對應於中介層30的剖面形狀。開口部10a1在YZ俯視下如圖1所示為略矩形狀。開口部10a之Z方向深度對應於中介層30之Z方向厚度。即使開口部10a之Z方向深度與中介層30之Z方向厚度略相等亦可。在此情況，即使被配置在開口部10a內的中介層30之表面與中介層10之表面10a略同一平面亦可。依此，因容易將中介層30之Z方向之安裝高度抑制成較低，故可以有助於將半導體裝置1全體之安裝高度抑制成較低。 另外，即使開口部10a1之Z方向深度比中介層30之Z方向厚度些許小亦可。即使在情況，因容易因應開口部10a1之Z方向深度而將中介層30之Z方向之安裝高度抑制成較低，故可以有助於將半導體裝置1全體之安裝高度抑制成較低。 在中介層10之背面10b安裝外部電極60。被安裝於中介層10之表面10a側的半導體晶片20、中介層30及複數半導體晶片40係藉由密封樹脂50被密封。被安裝於中介層10之背面10b側的外部電極60能由以導電物為主成分的材料而形成，並且其表面被露出，能從外部被電性連接。 即使中介層10為例如包含印刷配線板等的有機物的有機中介層亦可。中介層10係體積占較大比例的部分能由有機物形成。中介層10具有焊料光阻層11、預浸體層12、核心層13、導電層14及通孔電極15。焊料光阻層11能由以絕緣物(例如，絕緣性之有機系物質)為主成分的材料而形成。焊料光阻層11之材料能包含微量的放射性物質。預浸體層12能由以絕緣物(例如，塑膠等之有機系物質)為主成分的材料而形成。預浸體層12之材料能包含微量的放射性物質。核心層13能由以絕緣物(例如，塑膠等之有機系物質)為主成分的材料而形成。核心層13之材料能包含微量的放射性物質。導電層14能由導電物(例如，銅)為主成分的材料而形成。通孔電極15能由導電物(例如，銅)為主成分的材料而形成。 半導體晶片20為例如控制器晶片。半導體晶片20在-Z側具有面積最大的面(表面20a、第3主面)，在+Z側具有面積最大的另外之面(背面20b、第4主面)。在半導體裝置1為SSD之情況，半導體晶片20能以例如控制器晶片、倒裝晶片方式被安裝於中介層10。半導體晶片20之表面20a面對於中介層30之表面30a。半導體晶片20係隔著複數凸塊電極21而以面朝下方式(倒裝晶片方式)被安裝於中介層30之表面30a。即是，半導體晶片20係在表面20a面對於中介層30之表面30a之狀態，隔著複數凸塊電極21被安裝於中介層30之表面30a。 在半導體晶片20之表面20a，配置有複數墊片電極，複數墊片電極係經由複數凸塊電極21而與中介層30內之配線電性連接。中介層30內之配線係被電性連接於中介層10中之導電層14及通孔電極15。依此，能從外部電極60經由導電層14及通孔電極15、中介層30內之配線而對半導體晶片20發送接收特定訊號。 能電性連接中介層30內之配線的導電層14係在中介層10之開口部10a1之底面上，具有在圖2中以虛線表示之複數電極圖案141-1～141-n(n為任意的2以上之整數)。複數電極圖案141-1～141-n在XY方向被二次元地配列。圖2為表示中介層10之構成的俯視圖。各電極圖案141-1～141-n為了能傳送彼此不同的訊號，在開口部10a1之底面上能彼此電性分離。即使各電極圖案141-1～141-n之配置間距大於凸塊電極21之配置間距亦可。 在中介層30內，例如圖3所示般，設置用以將凸塊電極21連接於電極圖案141之配線。圖3為表示中介層30之構成的剖面圖。中介層30具有基板33、貫通電極31及再配線層32。基板33係沿著XY方向而平板狀地延伸。貫通電極31係在Z方向延伸而從+Z側朝-Z側貫通基板33。貫通電極31能由導電物(例如，銅等之金屬)為而形成。在基板33之 -Z側之面配置再配線層32。貫通電極31係+Z側之面與凸塊電極21接觸且被電性連接，+Z側之面經由再配線層32而與電極圖案141電性連接。再配線層32係配線部分由導電物(例如，銅等之金屬)而被形成，除此之外的部分能由絕緣物(例如，氧化矽物)而形成。電極圖案141經由導電層14及通孔電極15而被電性連接於外部電極60。 另外，用以將中介層30中之凸塊電極21連接於導電層14的配線，即使以引線接合構造來取代貫通電極31及再配線層32亦可。即使在中介層30中之表面30a上設置連接凸塊電極21之電極，引線從其電極朝導電層14被接合亦可。 在圖1所示的半導體晶片20之表面20a側，搭載CPU和揮發性記憶體電路。揮發性記憶體電路為例如SRAM電路。SRAM電路係作為CPU所致的作業區域，暫時記憶資料。中介層30之表面30a具有圖2所示的區域FRG1。區域FRG1係在半導體晶片20以倒裝晶片方式被安裝於中介層30之時，從垂直於中介層30之表面30a的方向(Z方向)透視之情況與SRAM電路重疊。區域FRG1係面積與SRAM電路略相等(例如，與SRAM電路數學性大概一致)。區域FRG1被包含在區域FRG2之內側。區域FRG2係在半導體晶片20以倒裝晶片方式被安裝於中介層30之時，從Z方向透視之情況與半導體晶片20重疊。區域FRG2係面積與半導體晶片20略相等(例如，與半導體晶片20數學性大概一致)。即是，區域FRG2係從Z方向透視之情況下與半導體晶片20重疊的區域，從Z方向透視之情況下在內側包含SRAM電路的區域。中介層30之XY面積對應於半導體晶片20之XY面積，即使為在半導體晶片20之XY面積加上配置餘裕之面積的面積亦可。 中介層30與中介層10材質不同。中介層30能由放射線之遮蔽能力較中介層10高的材質而形成。中介層30能由機械性、熱性特性較中介層10更接近於半導體晶片20的材質而形成。中介層30之線膨脹係數和半導體晶片20之線膨脹係數之差小於中介層10之線膨脹係數和半導體晶片20之線膨脹係數之差。中介層30能由熱傳導率較中介層10大的材質而形成。 例如，中介層30即使為包含半導體之半導體中介層亦可。中介層30係體積占較大比例的部分能由半導體形成。中介層30被配置在中介層10之表面10a之開口部10a1內。例如，中介層30係覆蓋半導體晶片20之表面20a中之區域FRG2(參照圖1)。中介層30在從Z方向透視之情況與SRAM電路重疊。中介層30在從Z方向透視之情況在內側包含SRAM電路。在從Z方向透視之情況，中介層30在區域FRG2與半導體晶片20重疊。在中介層30中，基板33(參照圖3)能由以半導體(例如，矽)為主成分的材料而形成。在中介層10為有機中介層且中介層30為半導體中介層之情況，中介層30比起中介層10，放射線之遮蔽能力較高。 例如，α粒子之能量和矽中的射程(飛距離)之相關關係如圖4所示般。圖4為表示α粒子之能量和矽中之射程的相關關係的圖。 從中介層10所含的放射性物質飛來的放射線(例如，α線)之能量為9MeV以下之情況，α粒子之矽中之射程約58 μm。在中介層30藉由以矽為主成分的材料形成之情況，即使中介層30之Z方向厚度為58μm以上亦可。依此，可以以中介層30有效果地遮蔽從中介層10所含的放射性物質飛來的放射線(例如，α線)。再者，即使中介層30之Z方向厚度小於中介層10之Z方向厚度亦可。依此，可以在中介層10之表面10a之開口部10a1大致收容中介層30，可以效果地降中介層30之安裝高度。 從中介層10所含的放射性物質飛來的放射線(例如，α線)之能量為6MeV以下之情況，α粒子之矽中之射程約32 μm。在中介層30藉由以矽為主成分的材料形成之情況，即使中介層30之Z方向厚度為32μm以上亦可。依此，可以以中介層30有效果地遮蔽從中介層10所含的放射性物質飛來的放射線(例如，α線)。再者，即使中介層30之Z方向厚度小於中介層10之Z方向厚度亦可。依此，可以在中介層10之表面10a之開口部10a1大致收容中介層30，可以有效果地減少中介層30之安裝高度。 另外，在中介層30中，圖3所示的基板33能設為電位性浮動的狀態。其結果，能確實地進行中介層30內之配線所致的各凸塊電極21及外部電極60間之訊號的發送接收。 再者，圖1所示之中介層30之線膨脹係數和半導體晶片20之線膨脹係數之差小於中介層10之線膨脹係數和半導體晶片20之線膨脹係數之差。例如，中介層10為有機中介層，且中介層30為半導體中介層之情況，中介層30比起中介層10，機械性、熱性特性較接近於半導體晶片20。中介層30之線膨脹係數比起中介層10之線膨脹係數，更接近於半導體晶片20之線膨脹係數。依此，半導體裝置1被置放在高溫環境下等之時，經由凸塊電極21而作用於中介層30和半導體晶片20之間的應力，比起半導體晶片20被安裝於中介層10之情況可以更減少。依此，可以提升在中介層30及半導體晶片20之間的機械性連接可靠性。 再者，中介層30之熱傳導率高於中介層10之熱傳導率。例如，在中介層10為有機中介層且中介層30為半導體中介層之情況，中介層30之熱傳導率高於中介層10之熱傳導率。依此，在由於半導體晶片20之高性能、高功能化，而有電路密度上升，晶片面積收縮傾向，發熱密度變高之情況，中介層30可以作為將半導體晶片20之熱朝XY平面方向排出且散熱至周邊環境中的散熱板而發揮功能。依此，可以抑制半導體晶片20之溫度上升，可以提升半導體裝置1之品質、可靠性。 複數半導體晶片40例如分別為記憶體晶片，相對於半導體晶片(控制器晶片)20以間隔件構造被安裝。即是，在XY方向相對於半導體晶片20間隔開的位置，配置較從中介層10之表面10a起算的半導體晶片20之安裝高度更厚的間隔件70。複數半導體晶片40係在間隔件70之+Z側被疊層。間隔件70係-Z側之面隔著接著層81而被接著於中介層10之表面10a。半導體晶片40-1係-Z側之面隔著接著層80-1而被接著於間隔件70之+Z側之面。半導體晶片40-2係-Z側之面隔著接著層80-2而被接著於半導體晶片40-1之+Z側之面。接著劑81、80-1、80-2即使分別為例如DAF(Die Attach Film)亦可。 複數半導體晶片40能以引線接合方式被安裝於中介層10。此時，能電性連接在中介層10的複數接合引線41之導電層14係在表面(+Z側之主面)10a上，具有如圖2所示的複數電極圖案142-1～142-2k(k為任意的2以上之整數)。複數半導體晶片40係經由複數接合引線41而被安裝於複數電極圖案142-1～142-2k。依此，複數半導體晶片40能由引線接合方式以間隔構造被安裝於中介層10。 如上述般，在實施型態中，半導體裝置1中，於中介層10和半導體晶片20之間追加中介層30，將半導體晶片20倒裝晶片安裝於中介層30。中介層30能由比起中介層10，放射線之遮蔽能力高較高，機械性、熱性特性更接近於半導體晶片20的材質而形成。依此，因可以以中介層30有效果地遮蔽從中介層10所含的放射性物質飛來的放射線(例如，α線)，故可以在半導體裝置1中提升軟性錯誤耐性。再者，因可以減少半導體裝置1被置放在高溫環境下等之時，經由凸塊電極21而作用於中介層30和半導體晶片20之間的應力，故可以提升中介層30及半導體晶片20之間的機械性連接可靠性。再者，因中介層30可以作為將半導體晶片20之熱朝XY平面方向排出且散熱至周邊環境中的散熱板而發揮功能，故可以抑制半導體晶片20之溫度上升，可以提升半導體裝置1之品質，可以提升熱性可靠性。 另外，作為實施型態之第1變形例，半導體裝置1j即使如圖5所示般，省略間隔件70，以配置較從中介層10之表面10a起算的半導體晶片20之安裝高度更厚的接著層80j-1的構造來取代亦可。圖5為表示半導體裝置1j之構成的剖面圖。接著層80j-1係將半導體晶片40-1接著於中介層10之表面10a，同時覆蓋半導體晶片(控制器晶片)20而確保凸塊電極21及半導體晶片20之安裝高度。依此，因可以不使用間隔件70而實現相當於間隔件構造的構造，故可以減少安裝成本。 再者，作為實施型態之第2變形例，半導體裝置1k係如圖6所示般，即使在半導體晶片20及中介層30之間的複數凸塊電極21之間隙填充底部填充樹脂90亦可。圖6為表示半導體裝置1k之構成的剖面圖。底部填充樹脂90可以使用混入二氧化矽作為填料的環氧樹脂。此時，填料之平均例粒徑可以設定在0.5～3μm之範圍內。填料之含有量可以設定在60～75wt%之範圍內。依此，即使不使密封樹脂50填充於半導體晶片20及中介層30之間，亦可以確實地使複數凸塊電極21間絕緣，可以提升作為半導體裝置1k之封裝體的可靠性。 再者，作為實施型態之第3變形例，即使半導體裝置1n如圖7及圖8所示般，中介層30n之面積對應於中介層10n之面積亦可。圖7為表示半導體裝置1n之構成的剖面圖。圖8為表示半導體裝置1n之構成的俯視圖。在中介層10n之表面10a在整個全面配置開口部10a1n。開口部10a1n具有對應於中介層30n之平面形狀、剖面形狀之點與實施型態相同。在此情況，中介層30n在其表面30a具有圖8所示般之複數電極圖案34-1～34-2k(k為任意的2以上之整數)。複數半導體晶片40(參照圖1)能經由複數接合引線41被安裝於複數電極圖案34-1～34-2k。複數電極圖案34-1～34-2k係經由中介層30n內之配線且經由中介層10n之導電層14及通孔電極15而與外部電極60電性連接。 中介層30n能由比起中介層10n，放射線之遮蔽能力高較高，機械性、熱性特性更接近於半導體晶片20的材質而形成之點，與實施型態相同。依此，可以在更寬廣的面積有效果地遮蔽從中介層10n所含的放射性物質飛來的放射線(例如，α線)。再者，因中介層30n可以更寬廣地確保散熱面積，故可以更抑制半導體晶片20之溫度上升。 再者，作為實施型態之第4變形例，即使半導體裝置1p如圖9及圖10所示般，中介層30被黏貼於中介層10p之表面10a亦可。圖9為表示半導體裝置1p之構成的剖面圖。圖10為表示半導體裝置1p之構成的俯視圖。中介層30之XY面積對應於半導體晶片20之XY面積，即使為在半導體晶片20之XY面積加上配置餘裕之面積的面積亦可。在中介層10n之表面10a不配置開口部10a1(參照圖1、圖2)。中介層30能經由接著材(無圖示)而被黏貼於中介層10n之表面10a。或是，中介層30在背面30b具有電極之情況，藉由其電極與中介層10n之表面10a上之電極合金接合，能被貼合於中介層10n之表面10a。依此，因可以省略在中介層10p之表面10a形成開口部10a1之加工處理，故可以減少半導體裝置1p之安裝成本。 再者，作為實施型態之第5變形例，即使半導體裝置1s如圖11及圖12所示般，中介層30n之面積對應於中介層10p之面積，中介層30n被黏貼於中介層10p之表面10a亦可。圖11為表示半導體裝置1s之構成的剖面圖。圖12為表示半導體裝置1s之構成的俯視圖。即使中介層30n具有第3變形例之中介層30n相同之形狀及尺寸亦可。即使中介層10p具有第4變形例之中介層30n相同之形狀及尺寸亦可。 中介層30n能以比起中介層10p，放射線之遮蔽能力高較高，機械性、熱性特性更接近於半導體晶片20的材質而形成之點，與實施型態相同。依此，可以在更寬廣的面積有效果地遮蔽從中介層10p所含的放射性物質飛來的放射線(例如，α線)。再者，因中介層30n可以更寬廣地確保散熱面積，故可以更抑制半導體晶片20之溫度上升。再者，因可以省略在中介層10p之表面10a形成開口部10a1(參照圖1、圖2)之加工處理，故可以減少半導體裝置1s之安裝成本。 再者，作為實施型態之第6變形例，半導體裝置1t係如圖13及圖14所示般，即使以並列構造而被安裝亦可。圖13為表示半導體裝置1t之構成的剖面圖。圖14為表示半導體裝置1t之構成的俯視圖。 在XY方向相對於半導體晶片20間隔開的位置，在+Z側從中介層10t之表面10a疊層複數半導體晶片40-1、40-2。複數半導體晶片40-1、40-2能以引線接合方式被安裝於中介層10t。此時，能電性連接在中介層10t的複數接合引線41之導電層14係在表面(+Z側之主面)10a上，具有複數電極圖案142-1～142-2k(k為任意的2以上之整數)(參照圖2)。依此，複數半導體晶片40-1、40-2能藉由引線接合方式以並列構造被安裝於中介層10t。 在此情況，在半導體裝置1t中，使中介層30安插於中介層10t和半導體晶片20之間。即使中介層30被貼合於中介層10t之表面10a亦可。例如，中介層30係在Z方向與半導體晶片20重疊。中介層30能以比起中介層10t，放射線之遮蔽能力高較高，機械性、熱性特性更接近於半導體晶片20的材質而形成之點，與實施型態相同。依此，可以以中介層30有效果地遮蔽從中介層10t所含的放射性物質飛來的放射線(例如，α線)。再者，可以減少在半導體裝置1t被放置在高溫環境下等之時，經由凸塊電極21而作用於中介層30和半導體晶片20之間的應力。再者，中介層30可以作為將半導體晶片20之熱朝XY平面排出且散熱至周邊環境中的散熱板而發揮功能。 雖然說明本發明之幾個實施型態，但是該些實施型態僅為例示，並無限定發明之範圍的意圖。該些嶄新的實施型態可以其他各種型態來實施，只要在不脫離發明之主旨的範圍下，可進行各種省略、置換、變更。該些實施型態或其變形，包含在發明之範圍或主旨，同時也包含在申請專利範圍所記載之發明和其均等之範圍內。
1,1j,1k,1n,1p,1s,1t:半導體裝置 10,10n,10p,10t,30,30n:中介層 20,40,40-1,40-2:半導體晶片
[圖1]為表示實施型態所涉及之半導體裝置之構成的剖面圖。 [圖2]為表示實施型態所涉及之半導體裝置之構成的俯視圖。 [圖3]為表示實施型態所涉及之中介層之構成的剖面圖。 [圖4]為表示α粒子之能量和矽中之射程的相關關係的圖。 [圖5]為表示實施型態之第1變形例所涉及之半導體裝置之構成的剖面圖。 [圖6]為表示實施型態之第2變形例所涉及之半導體裝置之構成的剖面圖。 [圖7]為表示實施型態之第3變形例所涉及之半導體裝置之構成的剖面圖。 [圖8]為表示實施型態之第3變形例所涉及之半導體裝置之構成的剖面圖。 [圖9]為表示實施型態之第4變形例所涉及之半導體裝置之構成的剖面圖。 [圖10]為表示實施型態之第4變形例所涉及之半導體裝置之構成的剖面圖。 [圖11]為表示實施型態之第5變形例所涉及之半導體裝置之構成的剖面圖。 [圖12]為表示實施型態之第5變形例所涉及之半導體裝置之構成的剖面圖。 [圖13]為表示實施型態之第6變形例所涉及之半導體裝置之構成的剖面圖。 [圖14]為表示實施型態之第6變形例所涉及之半導體裝置之構成的剖面圖。
1:半導體裝置
10:中介層
10a:表面
10b:背面
10a1:開口部
11:焊料光阻層
12:預浸體層
13:核心層
14:導電層
15:通孔電極
20,40-1,40-2:半導體晶片
20a:表面
20b:背面
21:凸塊電極
30:中介層
30a:表面
30b:背面
41:接合引線
50:密封樹脂
60:外部電極
70:間隔件
80-1:接著層
80-2:接著層
81:接著層

Claims (11)

  1. 一種半導體裝置，具備：第1中介層，其具有第1主面；第2中介層，其係被配置在上述第1主面，在上述第1中介層之相反側具有第2主面，與上述第1中介層之材質不同；具有揮發性記憶體電路的第1半導體晶片，其具有第1表面，在上述第1表面面對於上述第2主面之狀態下，隔著複數凸塊電極被安裝於上述第2主面；及第2半導體晶片，其係經由複數接合引線安裝於被配置在上述第1主面或上述第2主面的複數電極圖案，上述第2中介層在垂直於上述第1主面的方向，與上述第1半導體晶片重疊，上述第1中介層包含放射性物質，上述第2中介層比起上述第1中介層，放射線之遮蔽能力較高。
  2. 一種半導體裝置，具備：第1中介層，其具有第1主面；第2中介層，其係被配置在上述第1主面，在上述第1中介層之相反側具有第2主面，與上述第1中介層之材質不同；具有揮發性記憶體電路的第1半導體晶片，其具有第1表面，在上述第1表面面對於上述第2主面之狀態下，隔著複數凸塊電極被安裝於上述第2主面；及 第2半導體晶片，其係經由複數接合引線安裝於被配置在上述第1主面或上述第2主面的複數電極圖案，上述第2中介層在垂直於上述第1主面的方向，與上述第1半導體晶片重疊，上述第2中介層之線膨脹係數和上述第1半導體晶片之線膨脹係數之差，小於上述第1中介層之線膨脹係數和上述第1半導體晶片之線膨脹係數之差。
  3. 一種半導體裝置，具備：第1中介層，其具有第1主面；第2中介層，其係被配置在上述第1主面，在上述第1中介層之相反側具有第2主面，與上述第1中介層之材質不同；具有揮發性記憶體電路的第1半導體晶片，其具有第1表面，在上述第1表面面對於上述第2主面之狀態下，隔著複數凸塊電極被安裝於上述第2主面；及第2半導體晶片，其係經由複數接合引線安裝於被配置在上述第1主面或上述第2主面的複數電極圖案，上述第2中介層在垂直於上述第1主面的方向，與上述第1半導體晶片重疊，上述第2中介層被貼合在上述第1主面。
  4. 如請求項1至3中之任一項之半導體裝置，其中上述第2中介層之面積對應於上述第1中介層之面積。
  5. 一種半導體裝置，具備： 第1中介層，其具有第1主面；第2中介層，其係被配置在上述第1主面，在上述第1中介層之相反側具有第2主面，與上述第1中介層之材質不同；具有揮發性記憶體電路的第1半導體晶片，其具有第1表面，在上述第1表面面對於上述第2主面之狀態下，隔著複數凸塊電極被安裝於上述第2主面；及第2半導體晶片，其係經由複數接合引線安裝於被配置在上述第1主面或上述第2主面的複數電極圖案，上述第2中介層在垂直於上述第1主面的方向，與上述第1半導體晶片重疊，上述第1中介層在上述第1主面上具有開口部，上述第2中介層被配置在上述開口部內。
  6. 如請求項1至3、5中之任一項之半導體裝置，其中上述第2中介層之熱傳導率高於上述第1中介層之熱傳導率。
  7. 如請求項1至3、5中之任一項之半導體裝置，其中上述第1中介層為有機中介層，上述第2中介層為半導體中介層。
  8. 如請求項1至3、5中之任一項之半導體裝置，其中上述第2中介層之面積對應於上述第1半導體晶片之面 積。
  9. 如請求項1至3、5中之任一項之半導體裝置，其中上述第2中介層之厚度較上述第1中介層之厚度薄。
  10. 如請求項9之半導體裝置，其中上述第2中介層之厚度為58μm以上。
  11. 如請求項9之半導體裝置，其中上述第2中介層之厚度為32μm以上。
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