TWI826075B - 具電磁干擾屏蔽層的晶片封裝結構及其製造方法 - Google Patents

具電磁干擾屏蔽層的晶片封裝結構及其製造方法 Download PDF

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TWI826075B
TWI826075B TW111140642A TW111140642A TWI826075B TW I826075 B TWI826075 B TW I826075B TW 111140642 A TW111140642 A TW 111140642A TW 111140642 A TW111140642 A TW 111140642A TW I826075 B TWI826075 B TW I826075B
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layer
chip
electromagnetic interference
interference shielding
circumferential wall
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TW111140642A
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TW202418490A (zh
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于鴻祺
林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111140642A priority Critical patent/TWI826075B/zh
Priority to US18/243,672 priority patent/US20240145404A1/en
Priority to KR2020230001991U priority patent/KR20240000727U/ko
Priority to JP2023003760U priority patent/JP3244957U/ja
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Publication of TW202418490A publication Critical patent/TW202418490A/zh

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Abstract

一種具電磁干擾屏蔽層的晶片封裝結構及其製造方法，其中該晶片封裝結構包含一晶片、一重佈線層、一絕緣層及一電磁干擾屏蔽層；其中該絕緣層是在該絕緣層的至少一第一開口的環周圍處形成有一環周壁以包圍住各該第一開口，並使在該環周壁的外圍區域形成一凹下的平臺，且該平臺的水平高度是低於該環周壁的水平高度；其中該電磁干擾屏蔽層是覆蓋地設於該絕緣層的該平臺上供用以防止各該導接線路及該晶片受到電磁干擾；其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣，以提升產品的信賴度而增加產品的市場競爭力。

Description

具電磁干擾屏蔽層的晶片封裝結構及其製造方法
本發明係一種晶片封裝結構及其製造方法，尤指一種具電磁干擾屏蔽層的晶片封裝結構及其製造方法。
隨著科技的進步與人們的使用需求改變，5G技術或未來6G技術都會陸續應用於各個電子產品上，各個電子產品免不了要使用晶片產品。
電子產品中的晶片或內部線路的溫度隨著使用時間增加容易升高，導致產品短路或故障，甚至是損毀，容易降低產品的信賴度。此外，日常生活中亦有受電磁干擾(EMI，Electromagnetic Interference)的問題，電子產品中的晶片或內部線路若受到電磁干擾會導致產品短路或故障，容易降低產品的信賴度。
由上可知，電子產品若應用在交通或醫療領域上更會有人身安全的問題考量，因此必須改善電子產品中的晶片或內部線路因高溫及電磁干擾而導致產品短路或故障的問題。
因此，一種能改善晶片或內部線路因高溫及電磁干擾而導致產品短路或故障的問題的具電磁干擾屏蔽層的晶片封裝結構及其製造方法，為目前相關產業之迫切期待者。
本發明之主要目的在於提供一種具電磁干擾屏蔽層的晶片封裝結構及其製造方法，其中該晶片封裝結構包含一晶片、一重佈線層、一絕緣層及一電磁干擾屏蔽層；其中該絕緣層是在該絕緣層的至少一第一開口的環周圍處形成有一環周壁以包圍住各該第一開口，並使在該環周壁的外圍區域形成一凹下的平臺，且該平臺的水平高度是低於該環周壁的水平高度；其中該電磁干擾屏蔽層是覆蓋地設於該絕緣層的該平臺上供用以防止各該導接線路及該晶片受到電磁干擾；其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣，有效地解決電子產品中的晶片或內部線路因高溫及電磁干擾而導致產品短路或故障的問題。
為達成上述目的，本發明提供一種具電磁干擾屏蔽層的晶片封裝結構，該晶片封裝結構包含一晶片、一重佈線層(RDL，Redistribution Layer)、一絕緣層及一電磁干擾屏蔽層；其中該晶片具有一表面，該表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，其中該晶片係由一晶圓上所分割下來形成；其中該重佈線層是設在該晶片的各該晶片保護層的一表面上，該重佈線層具有至少一導接線路以與該晶片的各該晶墊對應電性連結，且各該導接線路具有至少一銲墊(Pad)，各該銲墊外露於重佈線層的一表面以對外電性連結；其中該絕緣層是全面地覆設在該重佈線層的該表面上，該絕緣層上具有至少一第一開口，以使各該導接線路上的各該銲墊能藉由各該第一開口以對外露出，其中該絕緣層是在各該第一開口的環周圍處形成有一環周壁以包圍住各該第一開口，並使在該環周壁的外圍區域形成一凹下的平臺，其中該平臺的水平高度是低於該環周壁的水平高度；其中該電磁干擾屏蔽層是由金屬材料所構成，該電磁干擾屏蔽層是覆蓋地設於該絕緣層的該平臺上供用以防止各該導接線路及該 晶片受到電磁干擾；其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣。
在本發明一較佳實施例中，該電磁干擾屏蔽層進一步是由銀(Ag)膠材料所製成。
在本發明一較佳實施例中，該電磁干擾屏蔽層的水平高度進一步是不高過該絕緣層的於該環周壁的水平高度。
在本發明一較佳實施例中，該絕緣層的各該第一開口上進一步設有至少一錫球，使各該導接線路上的各該銲墊能藉各該錫球對外電性連結，其中各該錫球是藉由該絕緣層的該環周壁以與該電磁干擾屏蔽層隔離並電性絕緣。
在本發明一較佳實施例中，該電磁干擾屏蔽層的一表面上進一步設有至少一外護層。
在本發明一較佳實施例中，各該外護層進一步是由鎳(Ni)或金(Au)金屬材料所製成。
在本發明一較佳實施例中，該重佈線層進一步包含至少一第一介電層及至少一第二介電層；其中各該第一介電層是覆設於該晶片的各該晶片保護層的一表面上，且各該第一介電層上形成有至少一第一凹槽，使各該晶墊能由各該第一凹槽對外露出；其中各該第二介電層是覆設於各該第一介電層的一表面上，且各該第二介電層上形成有至少一第二凹槽，各該第二凹槽與各該第一介電層的各該第一凹槽相通；其中各該導接線路進一步是由一金屬膏平整地填滿在各該第一凹槽及各該第二凹槽內所構成，使各該晶墊藉此能與各該導接線路電性連結。
在本發明一較佳實施例中，各該導接線路進一步是由銀(Ag)膠材料所製成。
在本發明一較佳實施例中，各該導接線路上進一步包含一凸塊，該凸塊是由鎳(Ni)或金(Au)金屬材料所製成。
本發明更提供一種具電磁干擾屏蔽層的晶片封裝結構的製造方法，該製造方法包含下列步驟：步驟S1：提供一晶圓，該晶圓上設置多個形成陣列排列之晶片，各該晶片具有一表面，該表面上設有至少一晶墊(Die Pad)及至少一晶片保護層，其中該晶圓上的相鄰二該晶片之間具有一能分割各該晶片的切割道；步驟S2：在各該晶片之各該晶片保護層的一表面上對應覆蓋地設置至少一重佈線層(RDL，Redistribution Layer)，該重佈線層具有至少一導接線路以與該晶片的各該晶墊對應電性連結，且各該導接線路具有至少一銲墊(Pad)，各該銲墊外露於重佈線層的表面以對外電性連結；步驟S3：在該重佈線層的一表面上全面地覆設置一絕緣層，該絕緣層上具有至少一第一開口，以使各該導接線路上的各該銲墊藉能由各該第一開口以對外露出；步驟S4：在該絕緣層的各該第一開口的環周圍處形成一環周壁以包圍住各該第一開口，並使該絕緣層在該環周壁的外圍區域形成一凹下的平臺，其中該平臺的水平高度是低於該環周壁的水平高度；步驟S5：在該絕緣層的該平臺上覆蓋地形成一電磁干擾屏蔽層，該電磁干擾屏蔽層是由金屬材料所構成，其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣；及步驟S6：沿著該晶圓的各該切割道對該晶圓上的各該晶片進行分割，藉以形成多個晶片封裝結構。
在本發明一較佳實施例中，在步驟2時，進一步是先在各該晶片的各該晶片保護層的該表面上對應覆蓋地設置至少一第一介電層，各該第一介電層上形成有至少一第一凹槽，使各該晶墊能由各該第一凹槽對外露出；其中在各該第一介電層的一表面上對應覆蓋地設置至少一第二介電層，各該第二介電層上形成有至少一第二凹槽，各該第二凹槽與各該第一介電層的各該第一凹槽相通；其中將一金屬膏填入各該第一凹槽及各該第二凹槽之內，且該金屬膏的厚度高於各該第二介電層的一表面；其中將高於各該第二介電層的一表面的該金屬膏進行研磨並露出各該第二介電層的該表面，以使該金屬膏的表面與各該第二介電層的該表面齊平而構成各該導接線路；其中各該導接線路、各該第一介電層、及各該第二介電層即構成各該重佈線層。
在本發明一較佳實施例中，在步驟5時，進一步是先在該絕緣層的該平臺上填滿一金屬膏，且該金屬膏的厚度高於該環周壁的水平高度；其中將高於該環周壁的該金屬膏進行研磨並露出該環周壁的水平表面，以使該金屬膏的表面與該環周壁的水平表面齊平而構成該電磁干擾屏蔽層。
1:晶片封裝結構
10:晶片
11:表面
12:晶墊
13:晶片保護層
14:表面
20:重佈線層
201:表面
21:導接線路
21a:金屬膏
211:表面
212:銲墊
213:凸塊
22:第一介電層
221:第一凹槽
222:表面
23:第二介電層
231:第二凹槽
232:表面
30:絕緣層
31:第一開口
32:環周壁
33:平臺
40:電磁干擾屏蔽層
40a:金屬膏
41:表面
50:錫球
60:外護層
2:晶圓
2a:切割道
圖1為本發明的晶圓上設有多個晶片的側視剖面示意圖。
圖2為圖1的多個晶片完成分割的示意圖。
圖3為本發明的晶片封裝結構的側視剖面示意圖。
圖4為本發明的晶片的側視剖面示意圖。
圖5為圖4中的晶片上設有第一介電層的示意圖。
圖6為圖5中的第一介電層上設有第二介電層的示意圖。
圖7為圖6中的第一凹槽及第二凹槽之內填入金屬膏的示意圖。
圖8為圖7中的第一凹槽及第二凹槽之內構成導接線路的示意圖。
圖9為圖8中的導接線路上設有凸塊的示意圖。
圖10為圖9的重佈線層上設有絕緣層的示意圖。
圖11為圖10的絕緣層的平臺上填滿金屬膏的示意圖。
圖12為圖11的絕緣層的平臺上構成電磁干擾屏蔽層的示意圖。
配合圖示，將本發明的結構及其技術特徵詳述如後，其中各圖示只用以說明本發明的結構關係及相關功能，因此各圖示中各元件的尺寸並非依實際比例畫製且非用以限制本發明。
參考圖3，本發明提供一種具電磁干擾屏蔽層的晶片封裝結構1，該晶片封裝結構1包含一晶片10、一重佈線層(RDL，Redistribution Layer)20、一絕緣層30及一電磁干擾屏蔽層40。
該晶片10具有一表面11，該表面11上設有至少一晶墊(Die Pad)12及至少一晶片保護層13如圖4所示；其中該晶片10係由一晶圓2上所分割下來形成如圖1所示。
該重佈線層(RDL，Redistribution Layer)20是設在該晶片10的各該晶片保護層13的一表面14上，該重佈線層20具有至少一導接線路21以與該晶片10的各該晶墊12對應電性連結如圖8所示，且各該導接線路21具有至少一銲墊(Pad)212，各該銲墊212外露於重佈線層20的一表面201以對外電性連結如圖10所示；其中各該導接線路21進一步是由銀(Ag)膠材料所製成但不限制。
該絕緣層30是全面地覆設在該重佈線層20的該表面201上，該絕緣層30上具有至少一第一開口31，以使各該導接線路21上的各該銲墊212能藉由 各該第一開口31以對外露出如圖10所示；其中該絕緣層30是在各該第一開口31的環周圍處形成有一環周壁32以包圍住各該第一開口31，並使在該環周壁32的外圍區域形成一凹下的平臺33如圖10所示；其中該平臺33的水平高度是低於該環周壁32的水平高度如圖10所示。
該電磁干擾屏蔽層40是由金屬材料所構成，該電磁干擾屏蔽層40是覆蓋地設於該絕緣層30的該平臺33上供用以防止各該導接線路21及該晶片10受到電磁干擾如圖12所示；其中該電磁干擾屏蔽層40進一步是由銀(Ag)膠材料所製成但不限制；其中該電磁干擾屏蔽層40的水平高度進一步是不高過該絕緣層30的於該環周壁32的水平高度但不限制，即該電磁干擾屏蔽層40被該環周壁32隔絕於該環周壁32之外部，以使該電磁干擾屏蔽層40與各該銲墊212形成隔離並電性絕緣而不會對各該銲墊212產生干擾或影響。
其中，該電磁干擾屏蔽層40是藉由該絕緣層30的該環周壁32以與各該銲墊212隔離並電性絕緣如圖12所示。
參考圖1至3，該絕緣層30的各該第一開口31上進一步設有至少一錫球50但不限制，使各該導接線路21上的各該銲墊212能藉各該錫球50對外電性連結；其中各該錫球50是藉由該絕緣層30的該環周壁32以與該電磁干擾屏蔽層40隔離並電性絕緣。
參考圖3，該電磁干擾屏蔽層40的一表面41上進一步設有至少一外護層60但不限制，有助於增加對產品的保護；其中各該外護層60進一步是由鎳(Ni)或金(Au)金屬材料所製成但不限制，上述鎳(Ni)或金(Au)金屬材料有助於增進散熱的功效。
參考圖8，該重佈線層20進一步包含至少一第一介電層22及至少一第二介電層23但不限制；其中各該第一介電層22是覆設於該晶片10的各該晶片保護層13的一表面14上，且各該第一介電層22上形成有至少一第一凹槽221， 使各該晶墊12能由各該第一凹槽221對外露出如圖5所示；其中各該第二介電層23是覆設於各該第一介電層22的一表面222上，且各該第二介電層23上形成有至少一第二凹槽231，各該第二凹槽231與各該第一介電層22的各該第一凹槽221相通如圖6所示；其中各該導接線路21(如圖8所示)進一步是由一金屬膏21a平整地填滿在各該第一凹槽221及各該第二凹槽231內所構成(如圖7所示)，使各該晶墊12藉此能與各該導接線路21電性連結，藉由重佈線層之技藝有效地改善現有晶片產品中導接線路結構的厚度較厚或製程繁雜的問題，以符合現代經片導接線路結構越趨薄型的發展趨勢，有利於降低製造端成本。
參考圖9，各該導接線路21上進一步包含一凸塊213但不限制，以利於增進對各該導接線路21的結構保護或導電效能，該凸塊213是由鎳(Ni)或金(Au)金屬材料所製成但不限制。
參考圖1、2、4至8、10至12，本發明的該晶片封裝結構1更是由一種具電磁干擾屏蔽層的晶片封裝結構的製造方法所製成，該製造方法包含下列步驟：
步驟S1：提供一晶圓2，該晶圓2上設置多個形成陣列排列之晶片10(如圖1所示)，各該晶片10具有一表面11，該表面11上設有至少一晶墊(Die Pad)12及至少一晶片保護層13如圖4所示；其中該晶圓2上的相鄰二該晶片10之間具有一能分割各該晶片10的切割道2a如圖1所示。
步驟S2：在各該晶片10之各該晶片保護層13的一表面14上對應覆蓋地設置至少一重佈線層(RDL，Redistribution Layer)20，該重佈線層20具有至少一導接線路21以與該晶片10的各該晶墊12對應電性連結(如圖8所示)，且各該導接線路21具有至少一銲墊(Pad)212，各該銲墊212外露於重佈線層20的表面211以對外電性連結如圖10所示。
其中，進一步是先在各該晶片10的各該晶片保護層13的該表面14上對應覆蓋地設置至少一第一介電層22如圖5所示，各該第一介電層22上形成有至少一第一凹槽221，使各該晶墊12能由各該第一凹槽221對外露出如圖5所示；其中在各該第一介電層22的一表面222上對應覆蓋地設置至少一第二介電層23如圖6所示，各該第二介電層23上形成有至少一第二凹槽231，各該第二凹槽231與各該第一介電層22的各該第一凹槽221相通如圖6所示；其中將一金屬膏21a填入各該第一凹槽221及各該第二凹槽231之內，且該金屬膏21a的厚度高於各該第二介電層23的一表面232如圖7所示；其中將高於各該第二介電層23的該表面232的該金屬膏21a(如圖7所示)進行研磨並露出各該第二介電層23的該表面232，以使該金屬膏21a(如圖7所示)的表面與各該第二介電層23的該表面232齊平而構成各該導接線路21如圖8所示；其中各該導接線路21、各該第一介電層22、及各該第二介電層23即構成各該重佈線層20如圖8所示。
步驟S3：在該重佈線層20的一表面201上全面地覆設置一絕緣層30如圖10所示，該絕緣層30上具有至少一第一開口31，以使各該導接線路21上的各該銲墊212藉能由各該第一開口31以對外露出如圖10所示。
步驟S4：在該絕緣層30的各該第一開口31的環周圍處形成一環周壁32以包圍住各該第一開口31，並使該絕緣層30在該環周壁32的外圍區域形成一凹下的平臺33如圖10所示；其中該平臺33的水平高度是低於該環周壁32的水平高度如圖10所示。
步驟S5：在該絕緣層30的該平臺33上覆蓋地形成一電磁干擾屏蔽層40如圖12所示，該電磁干擾屏蔽層40是由金屬材料所構成；其中該電磁干擾屏蔽層40是藉由該絕緣層30的該環周壁32以與各該銲墊212隔離並電性絕緣如圖12所示。
其中，進一步是先在該絕緣層30的該平臺33上填滿一金屬膏40a但不限制如圖11所示，且該金屬膏40a的厚度高於該環周壁32的水平高度如圖11所示；其中將高於該環周壁32的該金屬膏40a(如圖11所示)進行研磨並露出該環周壁32的水平表面，以使該金屬膏40a(如圖11所示)的表面與該環周壁32的水平表面齊平而構成該電磁干擾屏蔽層40如圖12所示。
步驟S6：沿著該晶圓2的各該切割道2a對該晶圓2上的各該晶片10進行分割如圖1所示，藉以形成多個晶片封裝結構1如圖2所示。
本發明的該晶片封裝結構1與現有的晶片封裝結構相較，具有以下優點：本發明的該絕緣層30是在各該第一開口31的環周圍處形成有該環周壁32以包圍住各該第一開口31，並使在該環周壁32的外圍區域形成凹下的該平臺33，且該平臺33的水平高度是低於該環周壁32的水平高度；其中本發明的該電磁干擾屏蔽層40是由金屬材料所構成以利於增進產品的散熱功效，該電磁干擾屏蔽層40是覆蓋地設於該絕緣層30的該平臺33上供用以防止各該導接線路21及該晶片10受到電磁干擾；其中該電磁干擾屏蔽層40是藉由該絕緣層30的該環周壁32以與各該銲墊212隔離並電性絕緣，有效地解決電子產品中的晶片或內部線路因高溫及電磁干擾而導致產品短路或故障的問題，藉此提升產品的信賴度，以利於增進產品的市場競爭力。
而且，在現代各個領域都逐漸走向5G技術或未來6G技術的科技產品趨式，使得電子產品若要符合市場需求大部分都需要運用到晶片，因此，當本發明運用在交通或醫療領域時，電子產品中的晶片或內部線路所運作的電子系統即能保持正常運作，避免造成人身安全的危險。
以上該僅為本發明的優選實施例，對本發明而言僅是說明性的，而非限制性的；本領域普通技術人員理解，在本發明權利要求所限定的精神和 範圍內可對其進行許多改變，修改，甚至等效變更，但都將落入本發明的保護範圍內。
1:晶片封裝結構
10:晶片
12:晶墊
20:重佈線層
21:導接線路
212:銲墊
30:絕緣層
31:第一開口
32:環周壁
33:平臺
40:電磁干擾屏蔽層
50:錫球
2:晶圓
2a:切割道

Claims (11)

  1. 一種具電磁干擾屏蔽層的晶片封裝結構，其包含：一晶片，其具有一表面，該表面上設有至少一晶墊(Die Pad)及至少一晶片保護層；其中該晶片係由一晶圓上所分割下來形成；一重佈線層(RDL，Redistribution Layer)，其是設在該晶片的各該晶片保護層的一表面上，該重佈線層具有至少一導接線路以與該晶片的各該晶墊對應電性連結，且各該導接線路具有至少一銲墊(Pad)，各該銲墊外露於該重佈線層的一表面以對外電性連結；一絕緣層，其是全面地覆設在該重佈線層的該表面上，該絕緣層上具有至少一第一開口，以使各該導接線路上的各該銲墊能藉由各該第一開口以對外露出；其中該絕緣層是在各該第一開口的環周圍處形成有一環周壁以包圍住各該第一開口，並使在該環周壁的外圍區域形成一凹下的平臺；其中該平臺的水平高度是低於該環周壁的水平高度；及一電磁干擾屏蔽層，該電磁干擾屏蔽層是由金屬材料所構成，該電磁干擾屏蔽層是覆蓋地設於該絕緣層的該平臺上供用以防止各該導接線路及該晶片受到電磁干擾；其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣；其中該電磁干擾屏蔽層的水平高度更是不高過該絕緣層的於該環周壁的水平高度。
  2. 如請求項1所述之晶片封裝結構，其中該電磁干擾屏蔽層進一步是由銀(Ag)膠材料所製成。
  3. 如請求項1所述之晶片封裝結構，其中該絕緣層的各該第一開口上進一步設有至少一錫球，使各該導接線路上的各該銲墊能藉各該錫球對外電性連結；其中各該錫球是藉由該絕緣層的該環周壁以與該電磁干擾屏蔽層隔離並電性絕緣。
  4. 如請求項1所述之晶片封裝結構，其中該電磁干擾屏蔽層的一表面上進一步設有至少一外護層。
  5. 如請求項4所述之晶片封裝結構，其中各該外護層進一步是由鎳(Ni)或金(Au)金屬材料所製成。
  6. 如請求項1所述之晶片封裝結構，其中該重佈線層進一步包含至少一第一介電層及至少一第二介電層；其中各該第一介電層是覆設於該晶片的各該晶片保護層的一表面上，且各該第一介電層上形成有至少一第一凹槽，使各該晶墊能由各該第一凹槽對外露出；其中各該第二介電層是覆設於各該第一介電層的一表面上，且各該第二介電層上形成有至少一第二凹槽，各該第二凹槽與各該第一介電層的各該第一凹槽相通；其中各該導接線路進一步是由一金屬膏平整地填滿在各該第一凹槽及各該第二凹槽內所構成，使各該晶墊藉此能與各該導接線路電性連結。
  7. 如請求項1所述之晶片封裝結構，其中各該導接線路進一步是由銀(Ag)膠材料所製成。
  8. 如請求項1所述之晶片封裝結構，其中各該導接線路上進一步包含一凸塊，該凸塊是由鎳(Ni)或金(Au)金屬材料所製成。
  9. 一種具電磁干擾屏蔽層的晶片封裝結構的製造方法，其包含下列步驟： 步驟S1：提供一晶圓，該晶圓上設置多個形成陣列排列之晶片，各該晶片具有一表面，該表面上設有至少一晶墊(Die Pad)及至少一晶片保護層；其中該晶圓上的相鄰二該晶片之間具有一能分割各該晶片的切割道；步驟S2：在各該晶片之各該晶片保護層的一表面上對應覆蓋地設置至少一重佈線層(RDL，Redistribution Layer)，該重佈線層具有至少一導接線路以與該晶片的各該晶墊對應電性連結，且各該導接線路具有至少一銲墊(Pad)，各該銲墊外露於該重佈線層的表面以對外電性連結；步驟S3：在該重佈線層的一表面上全面地覆設置一絕緣層，該絕緣層上具有至少一第一開口，以使各該導接線路上的各該銲墊藉能由各該第一開口以對外露出；步驟S4：在該絕緣層的各該第一開口的環周圍處形成一環周壁以包圍住各該第一開口，並使該絕緣層在該環周壁的外圍區域形成一凹下的平臺；其中該平臺的水平高度是低於該環周壁的水平高度；步驟S5：在該絕緣層的該平臺上覆蓋地形成一電磁干擾屏蔽層，該電磁干擾屏蔽層是由金屬材料所構成；其中該電磁干擾屏蔽層是藉由該絕緣層的該環周壁以與各該銲墊隔離並電性絕緣；及步驟S6：沿著該晶圓的各該切割道對該晶圓上的各該晶片進行分割，藉以形成多個晶片封裝結構。
  10. 如請求項9所述之製造方法，其中在步驟2時，進一步是先在各該晶片的各該晶片保護層的該表面上對應覆蓋地設置至少一第一介電層，各該第一介電層上形成有至少一第一凹槽，使各該晶墊能由各該第一凹槽對外露出；其中在各該第一介電層的一表面上對應覆蓋地設置至少一第二介電層，各該第二介電層上形成有至少一第二凹槽，各該第二凹槽與各該第一介電層的各該第一凹槽相通；其中將一金屬膏填入各該第一凹槽及各該第二凹槽之內，且 該金屬膏的厚度高於各該第二介電層的一表面；其中將高於各該第二介電層的一表面的該金屬膏進行研磨並露出各該第二介電層的該表面，以使該金屬膏的表面與各該第二介電層的該表面齊平而構成各該導接線路；其中各該導接線路、各該第一介電層、及各該第二介電層即構成各該重佈線層。
  11. 如請求項9所述之製造方法，其中在步驟5時，進一步是先在該絕緣層的該平臺上填滿一金屬膏，且該金屬膏的厚度高於該環周壁的水平高度；其中將高於該環周壁的該金屬膏進行研磨並露出該環周壁的水平表面，以使該金屬膏的表面與該環周壁的水平表面齊平而構成該電磁干擾屏蔽層。
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US20100013102A1 (en) * 2008-07-15 2010-01-21 Stats Chippac, Ltd. Semiconductor Device and Method of Providing a Thermal Dissipation Path Through RDL and Conductive Via
TWM383199U (en) * 2009-09-17 2010-06-21 Mao Bang Electronic Co Ltd Chip stacking assembly
TW201532155A (zh) * 2014-02-11 2015-08-16 Dawning Leading Technology Inc 半導體封裝結構及其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100013102A1 (en) * 2008-07-15 2010-01-21 Stats Chippac, Ltd. Semiconductor Device and Method of Providing a Thermal Dissipation Path Through RDL and Conductive Via
TWM383199U (en) * 2009-09-17 2010-06-21 Mao Bang Electronic Co Ltd Chip stacking assembly
TW201532155A (zh) * 2014-02-11 2015-08-16 Dawning Leading Technology Inc 半導體封裝結構及其製造方法

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