TW201532155A - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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TW201532155A
TW201532155A TW103104391A TW103104391A TW201532155A TW 201532155 A TW201532155 A TW 201532155A TW 103104391 A TW103104391 A TW 103104391A TW 103104391 A TW103104391 A TW 103104391A TW 201532155 A TW201532155 A TW 201532155A
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layer
semiconductor package
redistribution circuit
package structure
dielectric layer
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TW103104391A
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TWI544555B (zh
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Yu-Shan Hu
Diann-Fang Lin
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Dawning Leading Technology Inc
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Abstract

本發明係為一半導體封裝結構及其製造方法，而該半導體封裝結構包含：一晶片、一介電層及複數個重分配電路層。晶片具有複數個連接墊；介電層設置於晶片上，且介電層中定義有複數個容置槽，該等連接墊分別從該等容置槽中暴露出；該等重分配電路層分別設置於該等容置槽內，並分別與該等連接墊電性連接。藉此，重分配電路層與介電層之間可具有較大的接觸面積。

Description

半導體封裝結構及其製造方法
本發明為一種半導體封裝結構以及其製造方法，特別是指一種晶片尺寸(Chip Scale Package,CSP)的半導體封裝結構及其製造方法。
隨著電子產品的微型化趨勢，半導體封裝結構的體積勢必需縮減，才能因應此趨勢。而目前的半導體封裝技術中，以晶片尺寸封裝之方式較能使半導體封裝結構滿足體積縮減之需求。
請參考中華民國專利證書號I251912號所揭露者，或是請參考第1圖所示的習知晶圓級晶片封裝結構1。該習知的晶圓級晶片封裝結構1大致包含一晶圓11、複數個鋁墊12、一介電層13及複數個重分配電路層14。該等鋁墊12設置於晶圓11上，而介電層13形成於晶圓11及鋁墊12上。介電層13中形成有複數個開口，以使鋁墊12暴露出。該等重分配電路層14則是堆疊於介電層13上，並分別與鋁墊12電性連接。
製造上述習知的半導體封裝結構時，往往需要使用到至少兩次對位(alignment)步驟，一次是在介電層13中形成開口時使用，而另一次是在形成重分配電路層14時使用。對位步驟的次數增加，會使得半導體封裝結構的整體製造時間增長、製造成本增加。
此外，習知的半導體封裝結構的重分配電路層14是堆疊在介 電層13上，使得重分配電路層14與介電層13之間只有一個平面相接觸。如此，重分配電路層14與介電層13之間的結合力會較差，使得重分配電路層14在後續的製程中，較容易從介電層13上剝離。
有鑑於此，提供一種可改善至少一種上述缺失的半導體封裝結構及其製造方法，乃為此業界亟待解決的問題。
本發明的一目的為提供一種半導體封裝結構及其製造方法，其中該半導體封裝結構可具有較大的重分配電路層與介電層之接觸面積。
為達上述目的，本發明所提供的半導體封裝結構之製造方法包含以下步驟：提供具有複數個連接墊之一晶片；形成一介電層於該晶片上，且該介電層覆蓋該等連接墊；移除部分的該介電層，以形成複數容置槽於該介電層中，該等連接墊分別從該等容置槽中暴露出；以及，形成複數個重分配電路層於該等容置槽內，該等重分配電路層分別與該等連接墊電性連接。
為達上述目的，本發明所提供的半導體封裝結構包含：一晶片、一介電層及複數個重分配電路層。晶片具有複數個連接墊。介電層設置於晶片上，且介電層中定義有複數個容置槽，該等連接墊分別從該等容置槽中暴露出。該等重分配電路層分別設置於該等容置槽中，並分別與該等連接墊電性連接。
為了讓上述的目的、技術特徵和優點能夠更為本領域之人士所知悉並應用，下文係以本發明之數個較佳實施例以及附圖進行詳細的說 明。
1‧‧‧晶圓級晶片封裝結構
11‧‧‧晶圓
12‧‧‧鋁墊
13‧‧‧介電層
14‧‧‧重分配電路層
2‧‧‧半導體封裝結構
21‧‧‧晶片
211‧‧‧上表面
212‧‧‧保護層
22‧‧‧連接墊
23‧‧‧介電層
231‧‧‧容置槽
2311‧‧‧貫穿部
2312‧‧‧非貫穿部
24‧‧‧重分配電路層
241‧‧‧金種層
242‧‧‧第一金屬層
25‧‧‧保護層
251‧‧‧凹槽
26‧‧‧凸塊
3‧‧‧半導體封裝結構
31‧‧‧晶片
32‧‧‧連接墊
33‧‧‧介電層
331‧‧‧容置槽
3311‧‧‧貫穿部
3312‧‧‧非貫穿部
34‧‧‧重分配電路層
35‧‧‧第二介電層
351‧‧‧第二容置槽
3511‧‧‧貫穿部
3512‧‧‧非貫穿部
36‧‧‧第二重分配電路層
37‧‧‧保護層
371‧‧‧凹槽
38‧‧‧凸塊
4‧‧‧半導體封裝結構
41‧‧‧晶片
411‧‧‧上表面
412‧‧‧保護層
42‧‧‧連接墊
43‧‧‧介電層
431‧‧‧容置槽
4311‧‧‧貫穿部
4312‧‧‧非貫穿部
44‧‧‧重分配電路層
441‧‧‧金種層
442‧‧‧第一金屬層
443‧‧‧第二金屬層
45‧‧‧保護層
451‧‧‧凹槽
46‧‧‧凸塊
47‧‧‧球下金屬層
S1至S6‧‧‧為步驟流程
第1圖為習知半導體封裝結構之示意圖；第2圖為本發明之半導體封裝結構之第一實施例之示意圖；第3圖為本發明之半導體封裝結構之第二實施例之示意圖。
第4A圖至第4J各為本發明之半導體封裝結構之製造方法之第一實施例之其中一步驟的示意圖；以及第5圖為本發明之半導體封裝結構之製造方法之第一實施例之流程圖。
本發明為一種半導體封裝結構及其製造方法，以下將先詳述本發明的半導體封裝結構。
請參考第2圖所示，為本發明的半導體封裝結構的第一實施例的示意圖。半導體封裝結構2包含：一晶片21、一介電層23、複數個重分配電路層24、一保護層25及複數個凸塊26。以下將依序說明各元件之內容。
晶片21為一已經歷過半導體製程而形成積體電路(圖未示)的晶片。晶片21具有複數個連接墊22(本實施例僅以二個為例)，而該等連接墊22形成於晶片21的上表面(或稱主動面)211上，且可為一鋁墊。晶片21還可具有一保護層212，保護層212也形成於晶片21的上表面211上，並覆蓋連接墊22的周緣。
為考量重分配電路層24之線路分配可能性，其重分配線路層24可不需受限於晶片21上表面的面積尺寸，其可視必要性延伸至晶片21上表面以外的區域(圖未示)。而在此一前提下，晶片21則須經由挑揀設備重新 將晶片21以擴散式排列產生一特定間隔，並在晶片21與晶片21間的間隔中再置入至少一填充材質(圖未示)，以構成一具有擴散式排列的再製晶圓(wafer form)或平板(panel form)，以滿足重分配電路層24之線路分配需求。
介電層23設置於晶片21上，且可覆蓋晶片21的保護層212。介電層23中定義有複數個容置槽231(可參考第4C圖所示，以更明顯觀察容置槽之形狀及位置)，而該等容置槽231各包含相連通的一貫穿部(through portion)2311及一非貫穿部(blind portion)2312。貫穿部2311及非貫穿部2312皆從介電層23的上表面向下凹陷而形成，而貫穿部2311進一步地貫穿至介電層23之下表面。
由於該等貫穿部2311貫穿介電層23，且分別位於該等連接墊22的上方，使得該等連接墊22可分別從該等容置槽231中暴露出。如此，若容置槽231中未被設置任何材料時，可從容置槽231中觀察到連接墊22。
該等重分配電路層24可分別設置該等容置槽231(貫穿部2311及非貫穿部2312)內，使得該等重分配電路層24陷入於介電層23中，被介電層23環繞、包圍。如此，除了重分配電路層24的上表面外，重分配電路層24的其它表面皆可與介電層23相接觸。此外，依據應用情形，重分配電路層24可填滿容置槽231，以使得重分配電路層24的上表面與介電層23的上表面為共面(如本實施例所示)；或者，重分配電路層可不填滿容置槽(圖未示)，或是填滿容置槽後，進一步突出容置槽外(圖未示)。
該等重分配電路層24設置該等容置槽231內時，該等重分配電路層24可分別與「暴露於容置槽231內的該等連接墊22」相接觸而電性連接。
該等重分配電路層24各可包含一金種層241(metal seed layer)和一第一金屬層242。金種層241接觸連接墊22及介電層23，而第一金屬層242形成於金種層241上，且較金種層241厚。於其它實施例(圖未示)中，重分配電路層也可只包含第一金屬層，此時第一金屬層會直接地接觸到連接墊及介電層。此外，重分配電路層可包含一第二金屬層形成於該等第一金屬層之上(圖未示)，以藉由不同的材料差異所產生的阻障特性來達到保護第一金屬層的效果，來避免因後續製程影響而可能造成的電性可靠度下降
保護層25(或可稱為防銲層(solder mask))設置於介電層23及該等重分配電路層24上，且保護層25中定義有複數個凹槽251(可參考4G圖所示，以更明顯觀察凹槽之形狀及位置)。該等凹槽251貫穿保護層25，且分別位於該等重分配電路層24的上方，使得該等重分配電路層24可分別從該等凹槽251中暴露出。另，該等凹槽251可分別橫向地偏離該等連接墊22，使得凹槽251並不是位連接墊22的正上方(意指兩者的中心並非在同一條鉛直線上)。
該等凸塊26分別設置於該等凹槽251中，且分別與「暴露於該等凹槽251中的該等重分配電路層24」相接觸而電性連接。由於凹槽251橫向地偏離連接墊22，故位於凹槽251中的凸塊26也會橫向地偏離連接墊22。如此，若凸塊26受到外力擠壓時，該外力不會直接地作用在連接墊22上，減小連接墊22損壞的機會。
在某些實施態樣中，半導體封裝結構2更可包含複數個球下金屬層(under bump metallization，圖未示)。該等球下金屬層分別設置於該等重分配電路層24與該等凸塊26之間，亦即該等球下金屬層分別設置於該 等凹槽251中，並分別與該等重分配電路層24接觸而電性連接，而該等凸塊26分別設置於該等球下金屬層上，然後再分別透過該等球下金屬層與該等重分配電路層24電性連接。
本實施例之半導體封裝結構2與習知的相較，半導體封裝結構2的重分配電路層24與介電層23之間的接觸(接合)面積較多，不再是只有一平面相接觸。如此，重分配電路層24與介電層23之間可具有較大之結合力，使得製造過程中，重分配電路層24不易從介電層23中剝離。
接著說明本發明的半導體封裝結構的其它較佳實施例。為了簡潔說明之目的，其他較佳實施例與第一較佳實施例相似之處，將不再敘述之。
請參考第3圖，為本發明的半導體封裝結構的第二實施例的示意圖。於第二實施例中，半導體封裝結構3同樣地包含一晶片31、一介電層33、複數個重分配電路層34、一保護層35及複數個凸塊36，而與前述半導體封裝結構2之差異在於：更包含一第二介電層35及複數個第二重分配電路層36。
詳言之，第二介電層35設置於該等重分配電路層34及該介電層33上，且第二介電墊層35中定義有複數個第二容置槽351。類似容置槽331，第二容置槽351也包含一貫穿部3511及一非貫穿部3512，使得該等重分配電路層34得以分別從該等第二容置槽351中暴露出。
該等第二重分配電路層36分別設置於該等第二容置槽351中，以被第二介電層35包圍；如此，第二重分配電路層36與第二介電層35之間的接觸面積可大幅增加。另，該等第二重分配電路層36分別與該等重 分配電路層34電性連接。
除了上述差異外，半導體封裝結構3的保護層37及凸塊38的位置也與半導體結構2的有所不同。
詳言之，保護層37是設置於第二介電層35及該等第二重分配電路層36上，且保護層37中也定義有複數個貫穿保護層37的凹槽371，以使得該等第二重分配電路層36可分別從該等凹槽371中暴露出。該等凸塊38分別設置於該等凹槽371中，並分別與「暴露於該等凹槽371中的該等第二重分配電路層36」相接觸而電性連接，使得凸塊38可間接地與重分配電路層34及連接墊32電性連接。
與第一實施例相似地，在某些實施態樣中，半導體封裝結構3更可包含複數個球下金屬層，設置於該等第二重分配電路層36與該等凸塊38之間。
由以上說明可知，本發明的半導體封裝結構不侷限於只包含一個「介電層及重分配電路層」之組合，可視應用情形而增設一個以上的「介電層及重分配電路層」之組合。此外，當「介電層及重分配電路層」之組合為多個時，並不侷限每個組合中的重分配電路層皆需陷入介電層中；換言之，只要其中一個「介電層及重分配電路層」之組合具有「重分配電路層陷入介電層中」之特徵時，即可視為落入本發明的保護範疇中。
以上為本發明的半導體封裝結構的較佳實施例之說明。接著說明本發明的半導體封裝結構之製造方法，該製造方法至少可製作出上述該等半導體封裝結構2及3。然而需說明的是，本發明的半導體封裝結構並不侷限由本發明的半導體封裝結構之製造方法製作。
請參閱第5圖所示，為本發明的半導體封裝結構之製造方法的第一較佳實施例的流程圖。並請參閱第4A圖至4H圖所示，各為第5圖的其中一個步驟的示意圖。
該製造方法可開始於步驟S1(如第4A圖所示)，也就是提供一晶片41。該晶片41可具有複數個連接墊42及一保護層412，且連接墊42及保護層412皆形成於晶片41的上表面411上，保護層412覆蓋連接墊42的周緣。接著，如步驟S2及第4B圖所示，形成一介電層43於晶片41上，並使介電層43覆蓋晶片41的保護層412以及連接墊42。
爾後，如步驟S3及第4C圖所示，移除部分的介電層43，以形成複數個容置槽431於介電層43中。所形成的容置槽431可包含一貫穿部4311及一非貫穿部4312，其中貫穿部4311位於連接墊42的上方，使得該等連接墊42可分別從該等容置槽431中暴露出。
介電層43的移除可藉由雷射加工、壓模或蝕刻等方式來達成，其中若藉由雷射(例如準分子雷射(excimer laser))加工時，介電層43的移除量可以較為精確地控制，使得所形成的容置槽431之尺寸可良好地控制，誤差可較小。也因為介電層43的移除量可較精確地控制，兩個容置槽431之間的距離可較小。
容置槽431形成後，接著可如步驟S4及第4F圖所示，形成複數個重分配電路層44於該等容置槽431內，且該等重分配電路層44分別與該等連接墊42相接觸而電性連接。重分配電路層44的形成方式有多種，本實施例是採用以下所述之方式。
首先，如步驟S41及第4D圖所示，藉由濺鍍或化鍍方式，形 成一金種層(metal seed layer)441於容置槽431中及介電層43上。然後，如步驟S42及第4E圖所示，藉由電鍍、化鍍或濺鍍的方式，形成一第一金屬層442於金種層441上。當第一金屬層442形成至具有一預期之厚度時，步驟S42即可停止，通常所形成的第一金屬層422之厚度會大於金種層441。本實施例中，第一金屬層422是形成至將容置槽431給填滿。金種層441與第一金屬層442的製造材料可為銅金屬或是其他導電性良好的金屬。
緊接著，如步驟S43及第4F圖所示，可利用回蝕(etch back)、研磨或雷射加工等方式，移除位於介電層43的上表面上的部分第一金屬層442及部分金種層441。如此，殘留在各容置槽431內的金屬層442及金種層441即可形成相互電性隔離的該等重分配電路層44。
此外，如第4I圖所示，該等重分配線路更可於上述步驟完成後，再針對該第一金屬層442施加一電鍍或化鍍以形成一第二金屬層443於該第一金屬層之上來達到一阻障的目的，以避免第一金屬層442因後續製程而可能產生之可靠度下降。該第二金屬層443可包含錫或鈦等相異於第一金屬層之材料。
須說明的是，除了上述步驟S41至S43外，重分配電路層44的形成方式還可藉由一印刷(例如網版印刷)方式來實行。採用印刷方式時，一金屬材料可直接地塗佈於該等容置槽431內，而形成該等重分配電路層44；介電層43上不會被塗佈到金屬材料，因此不用額外的步驟來移除介電層43上的金屬材料。採用印刷方式所形成的重分配電路層44可能會略向上突出容置槽431外，但不會影響到後續的製程。
重分配電路層44形成後，接著可如步驟S5及第4G圖所示， 形成一保護層45於該等重分配電路層44及介電層43上，並移除部分的保護層45，以形成複數個凹槽451於保護層45中。由於該等凹槽451貫穿保護層45且位於該等重分配電路層44的上方，該等重分配電路層44可分別從該等凹槽451中暴露出。
之後，可如步驟S6及第4H圖所示，設置複數個凸塊46於該等凹槽451中，並使該等凸塊46分別與「暴露於該等凹槽451中的該等重分配電路層44」相接觸而電性連接；如第4J圖所示，在步驟S6中更可在設置凸塊46前，先形成複數個球下金屬層47於該等凹槽451中，並使該等球下金屬層47接合該等重分配線路層44，爾後再將該等凸塊46形成於該等球下金屬層47之上，以空間上隔離凸塊46與重分配電路層44，但凸塊46可透過球下金屬層47電性連接至重分配線路層44。
步驟S6完成後，可進一步依序地執行一測試步驟及一切割步驟(圖未示)。詳言之，於測試步驟中，晶片、再製晶圓或平板內的積體電路會被測試是否有損壞或異常；於切割步驟中，晶片、再製晶圓或平板會被切割成多個獨立的部分，每個部分即可構成一個半導體封裝結構。
需說明的是，步驟S2至S4可重複執行數次，以在晶片上形成多個「介電層及重分配電路層」之組合。
綜合上述，本發明的半導體封裝結構及半導體封裝結構之製造方法可至少具有以下特點：
1、半導體封裝結構的重分配電路層部分地或全部地埋入於介電層中，使得重分配電路層與介電層之間有較多的接觸面積，增加了兩者之間的結合力。
2、由於重分配電路層埋設於介電層中，可降低整體封裝結構之厚度，或是在厚度不變的情況下，填入較厚的重分配電路層來增加導電性。
3、製造半導體封裝結構時，可藉由雷射加工來形成容置槽，以使得容置槽的尺寸可較為精準地控制，且使得兩個容置槽之間的間距可較小。如此，形成於容置槽的重分配電路層的尺寸也可較精準地控制，而兩個重分配電路層之間的距離也可較小。
4、製造半導體封裝結構時，可僅需於形成容置槽的步驟中，使用對位步驟來將雷射對準預期加工的介電層部位，而其它後續製程中可不使用到對位步驟，故整體製造時間及成本可大幅地減少。
5、在形成容置槽及重分配電路層的過程中，皆可不需使用到黃光製程。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
2‧‧‧半導體封裝結構
21‧‧‧晶片
211‧‧‧上表面
212‧‧‧保護層
22‧‧‧連接墊
23‧‧‧介電層
231‧‧‧容置槽
2311‧‧‧貫穿部
2312‧‧‧非貫穿部
24‧‧‧重分配電路層
241‧‧‧金種層
242‧‧‧金屬層
25‧‧‧保護層
251‧‧‧凹槽
26‧‧‧凸塊

Claims (19)

  1. 一種半導體封裝結構之製造方法，包含：提供一晶片，該晶片具有複數個連接墊；形成一介電層於該晶片上，且該介電層覆蓋該等連接墊；移除部分的該介電層，以形成複數容置槽於該介電層中，該等連接墊分別從該等容置槽中暴露出；以及形成複數個重分配電路層於該等容置槽內，該等重分配電路層分別與該等連接墊電性連接。
  2. 如請求項1所述的半導體封裝結構之製造方法，其中，「形成複數個重分配電路層於該等容置槽內」的該步驟中，更包含：形成一第一金屬層於該介電層上及該等容置槽中；以及移除位於該介電層上的該第一金屬層，以形成該等重分配電路層。
  3. 如請求項2所述的半導體封裝結構之製造方法，其中，「移除位於該介電層上的該第一金屬層」的該步驟中，更包含：移除位於該介電層上的該第一金屬層後，形成一第二金屬層於該第一金屬層之上，以形成該等重分配電路層。
  4. 如請求項2所述的半導體封裝結構之製造方法，其中，「形成一金屬層於該介電層上及該等容置槽中」的該步驟中，更包含：形成一金種層(metal seed layer)於該介電層上及該等容置槽中，該金種層之厚度小於該金屬層；以及可藉由包含電鍍、化鍍或濺鍍的方式，將該第一金屬層形成於該金種層上。
  5. 如請求項2所述的半導體封裝結構之製造方法，其中，位於該 介電層上的該第一金屬層的移除，可包含以研磨或蝕刻的方式來達成。
  6. 如請求項1所述的半導體封裝結構之製造方法，其中，該介電層的移除可藉由包含以雷射加工、壓模或蝕刻的方式來達成。
  7. 如請求項1所述的半導體封裝結構之製造方法，其中，「形成複數個重分配電路層於該等容置槽內」的該步驟中，更包含：塗佈一金屬材料於該等容置槽中，以形成該等重分配電路層。
  8. 如請求項1所述的半導體封裝結構之製造方法，更包含：形成一保護層於該介電層與該等重分配電路層上；以及移除部分的該保護層，以形成複數個凹槽於該保護層中，該等重分配電路層分別從該等凹槽中暴露出。
  9. 如請求項8所述的半導體封裝結構之製造方法，更包含：形成複數個球下金屬層於該等凹槽中，並使該等球下金屬層分別電性連接該等重分配電路層；以及設置複數個凸塊於該等球下金屬層上，並使該等凸塊分別透過該等球下金屬層電性連接該等重分配電路層。
  10. 一種半導體封裝結構，包含：一晶片，具有複數個連接墊；一介電層，設置於該晶片上，該介電層中定義有複數個容置槽，該等連接墊分別從該等容置槽中暴露出；以及複數個重分配電路層，分別設置於該等容置槽內，並分別與該等連接墊電性連接。
  11. 如請求項10所述的半導體封裝結構，其中，該等重分配電路層被該介電層包圍。
  12. 如請求項10所述的半導體封裝結構，其中，該等重分配電路層各包含一第一金屬層和一金種層，該第一金屬層形成於該金種層上。
  13. 如請求項12所述的半導體封裝結構，其中，該等重分配電路層更包括一第二金屬層，該第二金屬層形成於該第一金屬層上。
  14. 如請求項10所述的半導體封裝結構，更包含一保護層，設置於該介電層上，該保護層中定義有複數個凹槽，且該等重分配電路層分別從該等凹槽中暴露出。
  15. 如請求項14所述的半導體封裝結構，其中，該等凹槽分別偏離該等連接墊。
  16. 如請求項14所述的半導體封裝結構，更包含複數個球下金屬層及複數個凸塊，該等球下金屬層分別設置於該等凹槽中，而該等凸塊分別設置於該等球下金屬層之上，並透過該等球下金屬層與該等重分配電路層電性連接。
  17. 如請求項10所述的半導體封裝結構，更包含：一第二介電層，設置於該等重分配電路層及該介電層上，該第二介電層中定義有複數個第二容置槽，該等重分配電路層分別從該等第二容置槽中暴露出；以及複數個第二重分配電路層，分別設置於該等第二容置槽內，並與該等重分配電路層電性連接。
  18. 如請求項17所述的半導體封裝結構，更包含一保護層，形成於該第二介電層上，該保護層中定義有複數個凹槽，且該等第二重分配電路層分別從該等凹槽中暴露出。
  19. 如請求項18所述的半導體封裝結構，更包含複數個球下金屬層 及複數個凸塊，該等球下金屬層分別設置於該等凹槽中，而該等凸塊分別設置於該等球下金屬層之上，並透過該等球下金屬層與該第二重分配電路層電性相連。
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