TWI804243B - Pixel array - Google Patents
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本發明是有關於一種畫素陣列，且特別是有關於一種發光二極體畫素陣列。 The present invention relates to a pixel array, and in particular to a light-emitting diode pixel array.
因環保意識抬頭，節能省電、使用壽命、色彩飽和度及電源品質等訴求逐漸成為消費者考慮購買的因素，同時受到發光二極體(LED)晶片迅速發展與成本降低，驅使發光二極體成為未來照明與顯示器市場的發展主流。 Due to the rising awareness of environmental protection, demands for energy saving, power saving, service life, color saturation and power supply quality have gradually become factors that consumers consider purchasing. At the same time, the rapid development and cost reduction of light-emitting diode (LED) chips drive Become the mainstream of future lighting and display market development.
由於不同色彩發光二極體是使用不同的材料，亦即不同色彩發光二極體可能具有不同的發光效率曲線，因此要改善發光二極體面板的發光效率時，可能要基於發光二極體的發光效率對畫素電路進行調整。 Since different colors of light-emitting diodes use different materials, that is, different colors of light-emitting diodes may have different luminous efficiency curves, so when improving the luminous efficiency of light-emitting diode panels, it may be based on the The luminous efficiency adjusts the pixel circuit.
本發明提供一種畫素陣列，可使綠色發光二極體的發光效率向最大發光效率靠攏，以提高綠色畫素電路的發光效率。 The invention provides a pixel array, which can make the luminous efficiency of the green light-emitting diode approach to the maximum luminous efficiency, so as to improve the luminous efficiency of the green pixel circuit.
本發明的畫素陣列，包括多個紅色畫素、多個綠色畫素 以及多個藍色畫素。這些綠色畫素沿一第一方向排列以形成多個綠色畫素行，其中各個綠色畫素包括發光二極體、第一電晶體、第二電晶體、第三電晶體以及第四電晶體。發光二極體具有陽極及接收系統低電壓的陰極。第一電晶體具有接收第一資料信號的第一端、接收第一掃描信號的控制端及第二端。第二電晶體具有第一端、耦接第一電晶體的第二端的控制端及耦接發光二極體的陽極的第二端。第三電晶體具有接收系統高電壓的第一端、接收第一控制信號的控制端及耦接第二電晶體的第一端的第二端。第四電晶體具有耦接相鄰綠色畫素的發光二極體的陽極的第一端、耦接第三電晶體的控制端的控制端及耦接發光二極體的陽極的第二端。 The pixel array of the present invention includes a plurality of red pixels and a plurality of green pixels and multiple blue pixels. The green pixels are arranged along a first direction to form a plurality of rows of green pixels, wherein each green pixel includes a light emitting diode, a first transistor, a second transistor, a third transistor and a fourth transistor. A light-emitting diode has an anode and a cathode that receives the low voltage of the system. The first transistor has a first end for receiving the first data signal, a control end for receiving the first scanning signal, and a second end. The second transistor has a first terminal, a control terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode. The third transistor has a first end receiving the system high voltage, a control end receiving the first control signal, and a second end coupled to the first end of the second transistor. The fourth transistor has a first terminal coupled to the anode of the LED of the adjacent green pixel, a control terminal coupled to the control terminal of the third transistor, and a second terminal coupled to the anode of the LED.
基於上述，本發明實施例的畫素陣列，導通的第二電晶體、第三電晶體及第四電晶體並聯本級及上一級的綠色畫素的綠色發光二極體，以降低通過各個綠發光二極體的電流。藉此，使綠色發光二極體的發光效率向最大發光效率靠攏。 Based on the above, in the pixel array of the embodiment of the present invention, the turned-on second transistor, the third transistor, and the fourth transistor are connected in parallel to the green light-emitting diodes of the green pixels of the current stage and the upper stage, so as to reduce the green light-emitting diodes passing through each green pixel. LED current. Thereby, the luminous efficiency of the green light-emitting diode is approached to the maximum luminous efficiency.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.
BDX(n)~BDX(n+1):藍色資料信號 BDX(n)~BDX(n+1): blue data signal
C1:第一電容 C1: the first capacitor
CPC:補償電路 CPC: compensation circuit
D1:第一方向 D1: the first direction
D2:第二方向 D2: Second direction
EM(n-1)~EM(n+1):發光信號 EM(n-1)~EM(n+1): luminescent signal
GDX(n-1)~GDX(n+1):綠色資料信號 GDX(n-1)~GDX(n+1): green data signal
LED1、LED2:發光二極體 LED1, LED2: Light-emitting diodes
M1~M3:電晶體 M1~M3: Transistor
PAX1、PAX2、PAX3、PAX4:畫素陣列 PAX1, PAX2, PAX3, PAX4: pixel array
PXB(n-1)~PXB(n+1)、PXBa(n)~PXBa(n+1)、PXBb(n)~PXBb(n+1):藍色畫素 PXB(n-1)~PXB(n+1), PXBa(n)~PXBa(n+1), PXBb(n)~PXBb(n+1): blue pixels
PXG(n-1)~PXG(n+1)、PXGa(n-1)~PXGa(n+1)、PXGb(n-1)~PXGb(n+1)、PXGc(n-1)~PXGc(n+1):綠色畫素 PXG(n-1)~PXG(n+1), PXGa(n-1)~PXGa(n+1), PXGb(n-1)~PXGb(n+1), PXGc(n-1)~PXGc (n+1): green pixel
PXR(n-1)~PXR(n+1)、PXRa(n)~PXRa(n+1)、PXRb(n)~PXRb(n+1):紅色畫素 PXR(n-1)~PXR(n+1), PXRa(n)~PXRa(n+1), PXRb(n)~PXRb(n+1): red pixel
RDX(n)~RDX(n+1):紅色資料信號 RDX(n)~RDX(n+1): red data signal
SN(n-1)~SN(n+2):掃描信號 SN(n-1)~SN(n+2): Scan signal
T1:第一電晶體 T1: first transistor
T2:第二電晶體 T2: second transistor
T3:第三電晶體 T3: The third transistor
T4:第四電晶體 T4: The fourth transistor
T5:第五電晶體 T5: fifth transistor
T6:第六電晶體 T6: sixth transistor
VDD:系統高電壓 VDD: system high voltage
Vini:初始化電壓 Vini: initialization voltage
VSS:系統低電壓 VSS: System low voltage
圖1為依據本發明第一實施例的畫素陣列的電路示意圖。 FIG. 1 is a schematic circuit diagram of a pixel array according to a first embodiment of the present invention.
圖2為依據本發明第一實施例的畫素陣列的驅動波形示意 圖。 Fig. 2 is a schematic diagram of driving waveforms of a pixel array according to the first embodiment of the present invention picture.
圖3為依據本發明第一實施例的畫素陣列的顯示示意圖。 FIG. 3 is a schematic display diagram of a pixel array according to a first embodiment of the present invention.
圖4為依據本發明第二實施例的畫素陣列的電路示意圖。 FIG. 4 is a schematic circuit diagram of a pixel array according to a second embodiment of the present invention.
圖5為依據本發明第二實施例的畫素陣列的顯示示意圖。 FIG. 5 is a schematic display diagram of a pixel array according to a second embodiment of the present invention.
圖6為依據本發明第三實施例的畫素陣列的電路示意圖。 FIG. 6 is a schematic circuit diagram of a pixel array according to a third embodiment of the present invention.
圖7為依據本發明第四實施例的畫素陣列的電路示意圖。 FIG. 7 is a schematic circuit diagram of a pixel array according to a fourth embodiment of the present invention.
除非另有定義，本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地這樣定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.
應當理解，儘管術語”第一”、”第二”、”第三”等在本文中可以用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此，下面討論的”第一元件”、”部件”、”區域”、”層”或”部分”可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。 It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
這裡使用的術語僅僅是為了描述特定實施例的目的，而 不是限制性的。如本文所使用的，除非內容清楚地指示，否則單數形式”一”、”一個”和”該”旨在包括複數形式，包括”至少一個”。”或”表示”及/或”。如本文所使用的，術語”及/或”包括一個或多個相關所列項目的任何和所有組合。還應當理解，當在本說明書中使用時，術語”包括”及/或”包括”指定所述特徵、區域、整體、步驟、操作、元件的存在及/或部件，但不排除一個或多個其它特徵、區域整體、步驟、操作、元件、部件及/或其組合的存在或添加。 The terminology used herein is for the purpose of describing particular embodiments only and Not restrictive. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.
圖1為依據本發明第一實施例的畫素陣列的電路示意圖。請參照圖1，在本實施例中，畫素陣列PAX1包括多個紅色畫素(如PXR(n)~PXR(n+1))、多個綠色畫素(如PXG(n-1)~PXG(n+1))以及多個藍色畫素(如PXB(n)~PXB(n+1))，其中紅色畫素PXR(n)~PXR(n+1)、綠色畫素PXG(n-1)~PXG(n+1)以及藍色畫素PXB(n)~PXB(n+1)例如是以脈衝驅動方式(impulse driving mode)來驅動，其中n為一索引數。 FIG. 1 is a schematic circuit diagram of a pixel array according to a first embodiment of the present invention. Please refer to FIG. 1 , in this embodiment, the pixel array PAX1 includes a plurality of red pixels (such as PXR(n)~PXR(n+1)), a plurality of green pixels (such as PXG(n-1)~ PXG(n+1)) and multiple blue pixels (such as PXB(n)~PXB(n+1)), among which red pixels PXR(n)~PXR(n+1), green pixels PXG( n−1)˜PXG(n+1) and the blue pixels PXB(n)˜PXB(n+1) are driven by, for example, an impulse driving mode, wherein n is an index number.
在本實施例中，紅色畫素(如PXR(n)~PXR(n+1))沿第一方向D1(例如圖式的垂直方向)排列以形成多個紅色畫素行，綠色畫素(如(如PXG(n-1)~PXG(n+1))沿第一方向D1排列以形成多個綠色畫素行，並且這些藍色畫素(如PXG(n)~PXG(n+1))沿第一方向D1排列以形成多個藍色畫素行，其中紅色畫素行、綠色畫素行以及藍色畫素行可以沿著垂直第一方向D1的第二方向D2交替配置。 In this embodiment, the red pixels (such as PXR(n)~PXR(n+1)) are arranged along the first direction D1 (such as the vertical direction of the drawing) to form a plurality of red pixel rows, and the green pixels (such as (such as PXG(n-1)~PXG(n+1)) are arranged along the first direction D1 to form a plurality of green pixel rows, and these blue pixels (such as PXG(n)~PXG(n+1)) Arranged along the first direction D1 to form a plurality of blue pixel rows, wherein the red pixel rows, the green pixel rows and the blue pixel rows may be alternately arranged along the second direction D2 perpendicular to the first direction D1.
在本實施例中，各個綠色畫素(如PXG(n-1)~PXG(n+1)) 包括發光二極體LED1(在此為綠色發光二極體)、第一電晶體T1、第二電晶體T2、第三電晶體T3以及第四電晶體T4。發光二極體LED1具有陽極及接收系統低電壓VSS的陰極。第一電晶體T1具有接收第一資料信號(例如綠色資料信號GDX(n-1)~GDX(n+1))的一第一端、接收第一掃描信號(如SN(n-1)~SN(n+1))的控制端及第二端。第二電晶體T2具有第一端、耦接第一電晶體T1的第二端的控制端及耦接發光二極體LED1的陽極的第二端。 In this embodiment, each green pixel (such as PXG(n-1)~PXG(n+1)) It includes a light-emitting diode LED1 (here, a green light-emitting diode), a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 . The light emitting diode LED1 has an anode and a cathode receiving the system low voltage VSS. The first transistor T1 has a first terminal for receiving the first data signal (such as the green data signal GDX(n-1)~GDX(n+1)), and a first terminal for receiving the first scanning signal (such as SN(n-1)~ The control terminal and the second terminal of SN(n+1)). The second transistor T2 has a first terminal, a control terminal coupled to the second terminal of the first transistor T1 , and a second terminal coupled to the anode of the light emitting diode LED1 .
第三電晶體T3具有接收系統高電壓VDD的第一端、接收第一控制信號(例如發光信號EM(n-1)~EM(n+1))的一控制端及耦接第二電晶體T2的第一端的第二端。第四電晶體T4具有耦接垂直相鄰的綠色畫素(如PXG(n-1)~PXG(n+1))的發光二極體LED1的陽極的第一端、耦接第三電晶體T3的控制端的控制端及耦接發光二極體LED1的陽極的第二端。 The third transistor T3 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the first control signal (for example, light emitting signals EM(n-1)~EM(n+1)), and is coupled to the second transistor. The second end of the first end of T2. The fourth transistor T4 has a first end coupled to the anodes of the light-emitting diodes LED1 of vertically adjacent green pixels (such as PXG(n-1)~PXG(n+1)), and coupled to the third transistor The control end of the control end of T3 is coupled to the second end of the anode of the light-emitting diode LED1.
進一步來說，以綠色畫素PXG(n)為例，第一電晶體T1的第一端接收綠色資料信號GDX(n)，第一電晶體T1的控制端接收掃描信號SN(n)。並且，第三電晶體T3的控制端接收發光信號EM(n)。 Further, taking the green pixel PXG(n) as an example, the first terminal of the first transistor T1 receives the green data signal GDX(n), and the control terminal of the first transistor T1 receives the scan signal SN(n). Moreover, the control terminal of the third transistor T3 receives the light emitting signal EM(n).
圖2為依據本發明第一實施例的畫素陣列的驅動波形示意圖。請參照圖1及圖2，如圖2所示，掃描信號SN(n-1)~SN(n+1)為按時間而依序致能，亦即掃描信號SN(n-1)~SN(n+1)的致能準位期間為按時間而依序形成。並且，發光信號EM(n-1)~EM(n+1)同樣為按時間而依序致能，亦即發光信號EM(n-1)~EM(n+1)同樣為 按時間而依序形成。對綠色畫素PXG(n)而言，發光信號EM(n)的致能準位期間晚於掃描信號SN(n)的致能準位期間。 FIG. 2 is a schematic diagram of driving waveforms of the pixel array according to the first embodiment of the present invention. Please refer to Figure 1 and Figure 2, as shown in Figure 2, the scan signals SN(n-1)~SN(n+1) are enabled sequentially according to time, that is, the scan signals SN(n-1)~SN The enable level periods of (n+1) are sequentially formed in time. Moreover, the luminescence signals EM(n-1)~EM(n+1) are also enabled sequentially according to time, that is, the luminescence signals EM(n-1)~EM(n+1) are also Formed sequentially over time. For the green pixel PXG(n), the enable period of the light emission signal EM(n) is later than the enable period of the scan signal SN(n).
以綠色畫素PXG(n)的驅動為例，在掃描信號SN(n)致能時，綠色資料信號GDX(n)會進行寫入。接著，在發光信號EM(n)致能時，綠色畫素PXG(n)的第三電晶體T3、第四電晶體T4會導通，並且綠色畫素PXG(n)的第二電晶體T2的導通程度是反應綠色資料信號GDX(n)的電壓準位。此時，電流會自系統高電壓VDD開始，經由綠色畫素PXG(n)的第二電晶體T2、第三電晶體T3、發光二極體LED1，而流至系統低電壓VSS，並且也經由綠色畫素PXG(n)的第二電晶體T2、第三電晶體T3及第四電晶體T4、以及畫素PXG(n-1)的發光二極體LED1，而流至系統低電壓VSS。 Taking the driving of the green pixel PXG(n) as an example, when the scan signal SN(n) is enabled, the green data signal GDX(n) will be written. Then, when the light emitting signal EM(n) is enabled, the third transistor T3 and the fourth transistor T4 of the green pixel PXG(n) will be turned on, and the second transistor T2 of the green pixel PXG(n) will The conduction degree reflects the voltage level of the green data signal GDX(n). At this time, the current will start from the system high voltage VDD, flow to the system low voltage VSS through the second transistor T2, the third transistor T3, and the light-emitting diode LED1 of the green pixel PXG(n), and also pass through The second transistor T2 , the third transistor T3 and the fourth transistor T4 of the green pixel PXG(n), and the light-emitting diode LED1 of the pixel PXG(n−1) flow to the system low voltage VSS.
換言之，導通的第二電晶體T2、第三電晶體T3及第四電晶體T4並聯兩個綠色畫素PXG(n)及PXG(n-1)的發光二極體LED1。在本發明的實施例中，而紅色發光二極體及藍色發光二極體在所通過的電流愈大時，發光效率愈高。然而，綠發光二極體則不然，僅在特定電流時有最大發光效率，並且隨電流不斷增加，則發光效率愈低。因此，透過並聯兩個綠色畫素(如PXG(n-1)~PXG(n+1))的發光二極體LED1，可降低通過各個綠發光二極體的電流，以使綠色發光二極體的發光效率向最大發光效率靠攏。 In other words, the turned-on second transistor T2 , third transistor T3 and fourth transistor T4 are connected in parallel to the light-emitting diodes LED1 of the two green pixels PXG(n) and PXG(n−1). In the embodiment of the present invention, when the current passing through the red light emitting diode and the blue light emitting diode is larger, the luminous efficiency is higher. However, green light-emitting diodes are not the case. They only have a maximum luminous efficiency at a specific current, and as the current increases, the luminous efficiency becomes lower. Therefore, by connecting the light-emitting diode LED1 of two green pixels (such as PXG(n-1)~PXG(n+1)) in parallel, the current passing through each green light-emitting diode can be reduced, so that the green light-emitting diode The luminous efficiency of the body moves closer to the maximum luminous efficiency.
再看到圖1，在本實施例中，紅色畫素(如PXR(n)~PXR(n+1))及藍色畫素(如PXG(n)~PXG(n+1))的每一 者包括發光二極體LED2(在此為紅色發光二極體或藍色發光二極體)及電晶體M1~M3。發光二極體LED2的陰極接收系統低電壓VSS。電晶體M1具有接收資料信號(例如紅色資料信號RDX(n)~RDX(n+1)及藍色資料信號BDX(n)~BDX(n+1))的第一端、接收掃描信號(如SN(n)~SN(n+1))的控制端及第二端。電晶體M2具有第一端、耦接電晶體M1的第二端的控制端及耦接發光二極體LED2的陽極的第二端。電晶體M3具有接收系統高電壓VDD的第一端、接收發光信號(如EM(n)~EM(n+1))的控制端及耦接電晶體M2的第一端的第二端。 See Fig. 1 again, in this embodiment, each of the red pixel (such as PXR(n)~PXR(n+1)) and the blue pixel (such as PXG(n)~PXG(n+1)) one They include light-emitting diode LED2 (here, red light-emitting diode or blue light-emitting diode) and transistors M1-M3. The cathode of the light-emitting diode LED2 receives the system low voltage VSS. Transistor M1 has a first end for receiving data signals (such as red data signals RDX(n)~RDX(n+1) and blue data signals BDX(n)~BDX(n+1)), and receiving scanning signals (such as The control terminal and the second terminal of SN(n)~SN(n+1)). The transistor M2 has a first terminal, a control terminal coupled to the second terminal of the transistor M1 , and a second terminal coupled to the anode of the light emitting diode LED2 . The transistor M3 has a first end for receiving the system high voltage VDD, a control end for receiving light emitting signals (such as EM(n)˜EM(n+1)), and a second end coupled to the first end of the transistor M2.
圖3為依據本發明第一實施例的畫素陣列的顯示示意圖。請參照圖1至圖3，在本實施例中，紅色畫素(如PXR(n)~PXR(n+1))及藍色畫素(如PXG(n)~PXG(n+1))是逐個點亮(如斜線所示R及B)，但綠色畫素(如(如PXG(n-1)~PXG(n+1))是一次點亮兩個(如斜線所示G)，為了使亮點均勻，各個綠色畫素(如PXG(n-1)~PXG(n+1))可以沿著第二方向D2與相鄰的紅色畫素(如PXR(n)~PXR(n+1))及相鄰的藍色畫素(如PXG(n)~PXG(n+1))不對齊。換言之，沿著第二方向D2，各個綠色畫素(如PXG(n-1)~PXG(n+1))可以與兩個紅色畫素(如PXR(n)~PXR(n+1))及兩個藍色畫素(如PXG(n)~PXG(n+1))相對應。 FIG. 3 is a schematic display diagram of a pixel array according to a first embodiment of the present invention. Please refer to FIG. 1 to FIG. 3 , in this embodiment, red pixels (such as PXR(n)~PXR(n+1)) and blue pixels (such as PXG(n)~PXG(n+1)) It is lit up one by one (R and B as shown by the slash), but the green pixels (such as (such as PXG(n-1)~PXG(n+1)) light up two at a time (G as shown by the slash), In order to make the bright spots uniform, each green pixel (such as PXG(n-1)~PXG(n+1)) can communicate with adjacent red pixels (such as PXR(n)~PXR(n+) along the second direction D2 1)) and adjacent blue pixels (such as PXG(n)~PXG(n+1)) are not aligned. In other words, along the second direction D2, each green pixel (such as PXG(n-1)~ PXG(n+1)) can be compared with two red pixels (such as PXR(n)~PXR(n+1)) and two blue pixels (such as PXG(n)~PXG(n+1)) correspond.
圖4為依據本發明第二實施例的畫素陣列的電路示意圖。請參照圖1及圖3，畫素陣列PAX2大致相同於畫素陣列 PAX1，其不同之處畫素陣列PAX2的綠色畫素(如(如PXGa(n-1)~PXGa(n+1))更包括第五電晶體T5，其中相同或相似元件使用相同或相似標號。第五電晶體T5具有耦接垂直相鄰的綠色畫素(如PXG(n-1)~PXG(n+1))的發光二極體LED1的陽極的第一端、接收第二控制信號(例如發光信號EM(n-2)~EM(n))的控制端及耦接發光二極體LED1的陽極的第二端。 FIG. 4 is a schematic circuit diagram of a pixel array according to a second embodiment of the present invention. Please refer to Figure 1 and Figure 3, the pixel array PAX2 is roughly the same as the pixel array PAX1, the difference is that the green pixels of the pixel array PAX2 (such as (such as PXGa(n-1)~PXGa(n+1)) further include a fifth transistor T5, wherein the same or similar components use the same or similar labels The fifth transistor T5 has a first end coupled to the anode of the light-emitting diode LED1 of the vertically adjacent green pixels (such as PXG(n-1)~PXG(n+1)), and receives the second control signal (for example, the control end of the light emitting signal EM(n−2)˜EM(n)) and the second end coupled to the anode of the light emitting diode LED1.
進一步來說，以綠色畫素PXGa(n)為例，第一電晶體T1的第一端接收綠色資料信號GDX(n)，第一電晶體T1的控制端接收掃描信號SN(n)。第三電晶體T3的控制端接收發光信號EM(n)，並且第五電晶體T5的控制端接收發光信號EM(n-1)。請參照圖2及圖3，如圖2所示，對綠色畫素PXGa(n)而言，發光信號EM(n)的致能準位期間晚於掃描信號SN(n)的致能準位期間及發光信號EM(n-1)的致能準位期間。 Further, taking the green pixel PXGa(n) as an example, the first terminal of the first transistor T1 receives the green data signal GDX(n), and the control terminal of the first transistor T1 receives the scan signal SN(n). The control terminal of the third transistor T3 receives the light emitting signal EM(n), and the control terminal of the fifth transistor T5 receives the light emitting signal EM(n−1). Please refer to FIG. 2 and FIG. 3. As shown in FIG. 2, for the green pixel PXGa(n), the enable level period of the light emission signal EM(n) is later than the enable level period of the scan signal SN(n) period and the enable level period of the light emitting signal EM(n−1).
請參照圖2及圖4，以綠色畫素PXGa(n)的驅動為例，在掃描信號SN(n)致能時，綠色資料信號GDX(n)會進行寫入。接著，在發光信號EM(n)致能時，綠色畫素PXGa(n)的第三電晶體T3、第四電晶體T4會導通，綠色畫素PXGa(n+1)的第五電晶體T5會導通，並且綠色畫素PXGa(n)的第二電晶體T2的導通程度是反應綠色資料信號GDX(n)的電壓準位。此時，電流會自系統高電壓VDD開始，經由綠色畫素PXGa(n)的第二電晶體T2、第三電晶體T3、發光二極體LED1，而流至系統低電壓VSS；也經由綠色畫素PXGa(n)的第二電晶體T2、第三電晶體T3及第四電晶體T4、以 及畫素PXGa(n-1)的發光二極體LED1，而流至系統低電壓VSS；以及，更經由綠色畫素PXGa(n)的第二電晶體T2及第三電晶體T3、以及畫素PXGa(n+1)的第五電晶體T5及發光二極體LED1，而流至系統低電壓VSS。 Referring to FIG. 2 and FIG. 4 , taking the driving of the green pixel PXGa(n) as an example, when the scan signal SN(n) is enabled, the green data signal GDX(n) will be written. Next, when the light-emitting signal EM(n) is enabled, the third transistor T3 and the fourth transistor T4 of the green pixel PXGa(n) are turned on, and the fifth transistor T5 of the green pixel PXGa(n+1) is turned on, and the turn-on degree of the second transistor T2 of the green pixel PXGa(n) reflects the voltage level of the green data signal GDX(n). At this time, the current will start from the system high voltage VDD, and flow to the system low voltage VSS through the second transistor T2, the third transistor T3, and the light-emitting diode LED1 of the green pixel PXGa(n); The second transistor T2, the third transistor T3 and the fourth transistor T4 of the pixel PXGa(n), and And the light-emitting diode LED1 of the pixel PXGa (n-1), and flow to the system low voltage VSS; and, through the second transistor T2 and the third transistor T3 of the green pixel PXGa (n), and the picture The fifth transistor T5 of element PXGa(n+1) and the light-emitting diode LED1 flow to the system low voltage VSS.
換言之，導通的綠色畫素PXGa(n)的第二電晶體T2、第三電晶體T3及第四電晶體T4以及綠色畫素PXGa(n+1)的第五電晶體T5並聯三個綠色畫素PXGa(n-1)~PXGa(n+1)的發光二極體LED1，可降低通過各個綠發光二極體的電流，以使綠色發光二極體的發光效率向最大發光效率靠攏。 In other words, the second transistor T2, the third transistor T3, and the fourth transistor T4 of the turned-on green pixel PXGa(n) and the fifth transistor T5 of the green pixel PXGa(n+1) are connected in parallel to three green pixels. The PXGa(n-1)~PXGa(n+1) light-emitting diode LED1 can reduce the current passing through each green light-emitting diode, so that the luminous efficiency of the green light-emitting diode approaches the maximum luminous efficiency.
圖5為依據本發明第二實施例的畫素陣列的顯示示意圖。請參照圖2、圖4及圖5，在本實施例中，紅色畫素(如PXR(n)~PXR(n+1))及藍色畫素(如PXG(n)~PXG(n+1))是逐個點亮(如斜線所示R及B)，但綠色畫素(如(如PXGa(n-1)~PXGa(n+1))是一次點亮三個(如斜線所示G)，為了使亮點均勻，各個綠色畫素(如PXGa(n-1)~PXGa(n+1))可以沿著第二方向D2與相鄰的紅色畫素(如PXR(n)~PXR(n+1))及相鄰的藍色畫素(如PXG(n)~PXG(n+1))相互對齊。 FIG. 5 is a schematic display diagram of a pixel array according to a second embodiment of the present invention. Please refer to Fig. 2, Fig. 4 and Fig. 5, in the present embodiment, red pixel (such as PXR (n) ~ PXR (n+1)) and blue pixel (such as PXG (n) ~ PXG (n+1) 1)) is lit one by one (as shown by the slash R and B), but the green pixels (such as (such as PXGa(n-1)~PXGa(n+1)) are lit three at a time (as shown by the slash G), in order to make the bright spots uniform, each green pixel (such as PXGa(n-1)~PXGa(n+1)) can be connected with the adjacent red pixel (such as PXR(n)~PXR) along the second direction D2 (n+1)) and adjacent blue pixels (such as PXG(n)~PXG(n+1)) are aligned with each other.
圖6為依據本發明第三實施例的畫素陣列的電路示意圖。請參照圖1及圖4，畫素陣列PAX3大致相同於畫素陣列PAX1，其不同之處畫素陣列PAX3的紅色畫素(如PXRa(n)~PXRa(n+1))、綠色畫素(如PXGb(n-1)~PXGb(n+1))以及藍色畫素(如PXBa(n)~PXBa(n+1))更包括補償電路CPC，其 中相同或相似元件使用相同或相似標號。在本實施例中，綠色畫素(如PXGb(n-1)~PXGb(n+1))的補償電路CPC是耦接第二電晶體T2的控制端與第二端，以針對第二電晶體T2的臨界電壓作補償。紅色畫素(如PXRa(n)~PXRa(n+1))及藍色畫素(如PXBa(n)~PXBa(n+1))的補償電路CPC是耦接電晶體M2的控制端與第二端，以針對電晶體M2的臨界電壓作補償。 FIG. 6 is a schematic circuit diagram of a pixel array according to a third embodiment of the present invention. Please refer to Figure 1 and Figure 4, the pixel array PAX3 is roughly the same as the pixel array PAX1, the difference is that the red pixels (such as PXRa(n)~PXRa(n+1)) and the green pixels (such as PXGb(n-1)~PXGb(n+1)) and blue pixels (such as PXBa(n)~PXBa(n+1)) also include a compensation circuit CPC, which The same or similar reference numerals are used for the same or similar elements. In this embodiment, the compensation circuit CPC of the green pixels (such as PXGb(n-1)~PXGb(n+1)) is coupled to the control terminal and the second terminal of the second transistor T2, so as to control the second transistor T2 The critical voltage of crystal T2 is used for compensation. The compensation circuit CPC of red pixels (such as PXRa(n)~PXRa(n+1)) and blue pixels (such as PXBa(n)~PXBa(n+1)) is coupled to the control terminal of transistor M2 and The second terminal is used to compensate for the critical voltage of the transistor M2.
在本實施例中，以綠色畫素(如PXGb(n-1)~PXGb(n+1))的補償電路CPC為例，補償電路CPC包括第一電容C1以及第六電晶體T6。第一電容C1耦接於第二電晶體T2的控制端與第二端之間。第六電晶體T6具有耦接第二電晶體T2的第二端的第一端、接收掃描信號(如SN(n-1)~SN(n+1))的控制端及接收初始化電壓Vini的第二端。其中，初始化電壓Vini可針對第二電晶體T2(或電晶體M2)的臨界電壓來設定，以對第二電晶體T2(或電晶體M2)的臨界電壓作補償。 In this embodiment, taking the compensation circuit CPC of green pixels (such as PXGb(n−1)˜PXGb(n+1)) as an example, the compensation circuit CPC includes a first capacitor C1 and a sixth transistor T6. The first capacitor C1 is coupled between the control terminal and the second terminal of the second transistor T2. The sixth transistor T6 has a first end coupled to the second end of the second transistor T2, a control end for receiving scanning signals (such as SN(n-1)~SN(n+1)), and a first end for receiving the initialization voltage Vini. Two ends. Wherein, the initialization voltage Vini can be set according to the threshold voltage of the second transistor T2 (or the transistor M2 ), so as to compensate the threshold voltage of the second transistor T2 (or the transistor M2 ).
圖7為依據本發明第四實施例的畫素陣列的電路示意圖。請參照圖1及圖7，畫素陣列PAX4大致相同於畫素陣列PAX1，其不同之處在於畫素陣列PAX4的紅色畫素(如PXRb(n)~PXRb(n+1))、綠色畫素(如PXGc(n-1)~PXGc(n+1))以及藍色畫素(如PXBb(n)~PXBb(n+1))，其中相同或相似元件使用相同或相似標號。 FIG. 7 is a schematic circuit diagram of a pixel array according to a fourth embodiment of the present invention. Please refer to FIG. 1 and FIG. 7. The pixel array PAX4 is roughly the same as the pixel array PAX1. Pixels (such as PXGc(n-1)~PXGc(n+1)) and blue pixels (such as PXBb(n)~PXBb(n+1)), wherein the same or similar components use the same or similar labels.
參照圖2所示，發光信號EM(n-1)的波形實質上相同於掃描信號SN(n)，發光信號EM(n)的波形實質上相同於掃描信號 SN(n+1)，亦即發光信號(EM(n-1)~EM(n+1))實質上是可以掃描信號(如SN(n)~SN(n+2))取代。以綠色畫素PXGc(n)為例，第一電晶體T1的第一端接收綠色資料信號GDX(n)，第一電晶體T1的控制端接收掃描信號SN(n)。第三電晶體T3的控制端接收掃描信號SN(n+1)。 Referring to FIG. 2, the waveform of the light emitting signal EM(n-1) is substantially the same as the scanning signal SN(n), and the waveform of the light emitting signal EM(n) is substantially the same as the scanning signal SN(n+1), that is, luminescence signals (EM(n-1)~EM(n+1)) can be replaced by scanning signals (such as SN(n)~SN(n+2)). Taking the green pixel PXGc(n) as an example, the first terminal of the first transistor T1 receives the green data signal GDX(n), and the control terminal of the first transistor T1 receives the scan signal SN(n). The control terminal of the third transistor T3 receives the scan signal SN(n+1).
類似地，畫素陣列PAX2可以只採用掃描信號(如SN(n)~SN(n+2))。請參照圖4，以綠色畫素PXGa(n)為例，第一電晶體T1的第一端接收綠色資料信號GDX(n)，第一電晶體T1的控制端接收掃描信號SN(n)。第三電晶體T3的控制端接收的發光信號EM(n)可以掃描信號SN(n+1)替代，第五電晶體T5的控制端接收的發光信號EM(n-1)可以掃描信號SN(n)替代。 Similarly, the pixel array PAX2 can only use scan signals (such as SN(n)˜SN(n+2)). Referring to FIG. 4 , taking the green pixel PXGa(n) as an example, the first terminal of the first transistor T1 receives the green data signal GDX(n), and the control terminal of the first transistor T1 receives the scan signal SN(n). The light emitting signal EM(n) received by the control terminal of the third transistor T3 can be replaced by the scanning signal SN(n+1), and the light emitting signal EM(n-1) received by the control terminal of the fifth transistor T5 can be replaced by the scanning signal SN( n) Substitution.
綜上所述，本發明實施例的畫素陣列，導通的第二電晶體、第三電晶體及第四電晶體並聯本級及上一級的綠色畫素的綠色發光二極體，以降低通過各個綠發光二極體的電流。並且，導通的本級的第二電晶體、第三電晶體及第四電晶體及下一級的第五電晶體並聯本級、上一級及下一級的綠色畫素的綠色發光二極體，以進一步降低通過各個綠發光二極體的電流。藉此，使綠色發光二極體的發光效率向最大發光效率靠攏。 In summary, in the pixel array of the embodiment of the present invention, the turned-on second transistor, the third transistor, and the fourth transistor are connected in parallel with the green light-emitting diodes of the green pixels of the current stage and the previous stage, so as to reduce the The current of each green light-emitting diode. And, the second transistor, the third transistor and the fourth transistor of the turned-on current level and the fifth transistor of the next level are connected in parallel with the green light-emitting diodes of the green pixels of the current level, the upper level and the lower level, so as to The current through each green light-emitting diode is further reduced. Thereby, the luminous efficiency of the green light-emitting diode is approached to the maximum luminous efficiency.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.
BDX(n)~BDX(n+1):藍色資料信號 BDX(n)~BDX(n+1): blue data signal
D1:第一方向 D1: the first direction
D2:第二方向 D2: Second direction
EM(n-1)~EM(n+1):發光信號 EM(n-1)~EM(n+1): luminescent signal
GDX(n-1)~GDX(n+1):綠色資料信號 GDX(n-1)~GDX(n+1): green data signal
LED1、LED2:發光二極體 LED1, LED2: Light-emitting diodes
M1~M3:電晶體 M1~M3: Transistor
PAX1:畫素陣列 PAX1: pixel array
PXB(n)~PXB(n+1):藍色畫素 PXB(n)~PXB(n+1): blue pixel
PXG(n-1)~PXG(n+1):綠色畫素 PXG(n-1)~PXG(n+1): green pixel
PXR(n)~PXR(n+1):紅色畫素 PXR(n)~PXR(n+1): red pixel
RDX(n)~RDX(n+1):紅色資料信號 RDX(n)~RDX(n+1): red data signal
SN(n-1)~SN(n+1):掃描信號 SN(n-1)~SN(n+1): Scan signal
T1:第一電晶體 T1: first transistor
T2:第二電晶體 T2: second transistor
T3:第三電晶體 T3: The third transistor
T4:第四電晶體 T4: The fourth transistor
VDD:系統高電壓 VDD: system high voltage
VSS:系統低電壓 VSS: System low voltage
Claims (11)
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| CN202210397432.5A CN114822379B (en) | 2021-04-20 | 2022-04-15 | Pixel array |
| US17/724,495 US11514852B2 (en) | 2021-04-20 | 2022-04-20 | Pixel array |
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| US202163177345P | 2021-04-20 | 2021-04-20 | |
| US63/177,345 | 2021-04-20 |
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| TW111110687A TWI796177B (en) | 2021-04-20 | 2022-03-22 | Pixel array |
| TW111110664A TWI804243B (en) | 2021-04-20 | 2022-03-22 | Pixel array |
| TW111112306A TWI796188B (en) | 2021-04-20 | 2022-03-30 | Light emitting diode component and light emitting diode circuit |
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| JP2007529105A (en) * | 2003-07-16 | 2007-10-18 | 松下電器産業株式会社 | Semiconductor light emitting device, method of manufacturing the same, lighting device and display device |
| US9831387B2 (en) * | 2014-06-14 | 2017-11-28 | Hiphoton Co., Ltd. | Light engine array |
| FR3044467B1 (en) * | 2015-11-26 | 2018-08-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | LIGHT DALLE AND METHOD FOR MANUFACTURING SUCH LIGHT SLAB |
| US10453826B2 (en) * | 2016-06-03 | 2019-10-22 | X-Celeprint Limited | Voltage-balanced serial iLED pixel and display |
| CN106652902B (en) * | 2017-01-25 | 2019-01-22 | 上海天马有机发光显示技术有限公司 | Organic light emitting display panel and its driving method, organic light-emitting display device |
| CN108877644A (en) * | 2018-07-20 | 2018-11-23 | 京东方科技集团股份有限公司 | Array substrate and the method for repairing array substrate |
| TWI680448B (en) * | 2018-12-05 | 2019-12-21 | 友達光電股份有限公司 | Pixel circuit |
| CN109686314B (en) * | 2019-03-01 | 2021-01-29 | 京东方科技集团股份有限公司 | Pixel circuit, display substrate and display device |
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| TW200725518A (en) * | 2005-12-30 | 2007-07-01 | Lg Philips Lcd Co Ltd | Light emitting display and method of driving thereof |
| US9607546B2 (en) * | 2013-09-17 | 2017-03-28 | Samsung Display Co., Ltd. | Display panel and organic light emitting display device having the same |
| TW201721619A (en) * | 2015-12-07 | 2017-06-16 | 友達光電股份有限公司 | Plxel circuit and driving method thereof |
| TW201915997A (en) * | 2017-10-05 | 2019-04-16 | 友達光電股份有限公司 | Display device and method for controlling the same |
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| Publication number | Publication date |
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| TWI796188B (en) | 2023-03-11 |
| TWI796177B (en) | 2023-03-11 |
| TW202243283A (en) | 2022-11-01 |
| TW202242834A (en) | 2022-11-01 |
| TWI796970B (en) | 2023-03-21 |
| TW202242833A (en) | 2022-11-01 |
| TW202243033A (en) | 2022-11-01 |
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