TWI796970B

TWI796970B - Semiconductor device and display device

Info

Publication number: TWI796970B
Application number: TW111109651A
Authority: TW
Inventors: 謝嘉定; 黃建富; 葉政男; 李錫烈; 藍詠翔; 李俊雨; 蘇松宇; 王賢軍; 王雅榕; 林欣瑩; 林雨潔; 吳仰恩
Original assignee: 友達光電股份有限公司
Priority date: 2021-04-20
Filing date: 2022-03-16
Publication date: 2023-03-21
Also published as: TW202242833A; TWI796188B; TWI804243B; TW202243033A; TWI796177B; TW202242834A; TW202243283A

Abstract

The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting piece. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting piece is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.

Description

半導體裝置以及顯示裝置Semiconductor device and display device

本案是關於一種半導體裝置以及顯示裝置，特別是關於一種包含串聯耦接的發光二極體的半導體裝置以及顯示裝置。This application relates to a semiconductor device and a display device, in particular to a semiconductor device and a display device including serially coupled light-emitting diodes.

關於微發光二極體（micro light emitting diode，micro LED）顯示器，主要係將LED結構設計微小化，其尺寸僅在1~10μm等級左右；後將micro LED批量式轉移至電路基板上，再利用物理沈積製程進行基板的封裝，完成結構簡單的micro LED顯示器。micro LED顯示器具有高亮度而適合戶外應用，但其電力大多係由電池所提供，因此若欲延長micro LED顯示器的使用時間需要降低其功率消耗。Regarding micro light emitting diode (micro light emitting diode, micro LED) displays, the main purpose is to miniaturize the design of the LED structure, and its size is only about 1-10 μm; after that, the micro LEDs are transferred to the circuit substrate in batches for reuse The physical deposition process is used to package the substrate to complete the micro LED display with a simple structure. Micro LED displays have high brightness and are suitable for outdoor applications, but most of their power is provided by batteries. Therefore, if you want to extend the use time of micro LED displays, you need to reduce their power consumption.

本案的一實施例提供一種半導體裝置，包含緩衝層、第一子晶片及第二子晶片以及連接件。第一子晶片及第二子晶片分開設置於緩衝層上。第一子晶片及該第二子晶片中的每一者皆包含第一擴散層、主動層以及第二擴散層。第一擴散層、主動層及第二擴散層由上而下依序設置於緩衝層上，第一擴散層及緩衝層為第一類型磊晶層，第二擴散層為第二類型磊晶層。連接件用以將第一子晶片的第二擴散層電性耦接至第二子晶片的第一擴散層。An embodiment of the present application provides a semiconductor device, including a buffer layer, a first sub-chip, a second sub-chip, and a connecting piece. The first sub-chip and the second sub-chip are separately disposed on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer and a second diffusion layer. The first diffusion layer, the active layer and the second diffusion layer are sequentially arranged on the buffer layer from top to bottom, the first diffusion layer and the buffer layer are the first type epitaxial layer, and the second diffusion layer is the second type epitaxial layer . The connector is used for electrically coupling the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip.

本案的另一實施例提供一種顯示裝置，包含多個像素、第一參考電壓端、第二參考電壓端以及第三參考電壓端。像素中每一者包含複數組子像素。複數組子像素中的第一組子像素包含至少兩個第一發光元件。至少兩個第一發光元件彼此串聯耦接。第一參考電壓端用以提供第一參考電壓至像素。第二參考電壓端用以提供第二參考電壓至像素。第三參考電壓端用以提供第三參考電壓至像素。第一參考電壓、第二參考電壓及第三參考電壓三者彼此不同。第一組子像素中彼此串聯耦接的第一發光元件耦接於第一參考電壓端及第二參考電壓端之間，複數組子像素中的第二組子像素耦接第三參考電壓端。Another embodiment of the present application provides a display device including a plurality of pixels, a first reference voltage terminal, a second reference voltage terminal and a third reference voltage terminal. Each of the pixels includes a complex set of sub-pixels. The first group of sub-pixels in the plurality of groups of sub-pixels includes at least two first light-emitting elements. At least two first light emitting elements are coupled in series with each other. The first reference voltage terminal is used for providing the first reference voltage to the pixels. The second reference voltage terminal is used for providing a second reference voltage to the pixels. The third reference voltage terminal is used for providing a third reference voltage to the pixels. The first reference voltage, the second reference voltage and the third reference voltage are different from each other. The first light-emitting elements coupled in series with each other in the first group of sub-pixels are coupled between the first reference voltage terminal and the second reference voltage terminal, and the second group of sub-pixels in the plurality of sub-pixels are coupled to the third reference voltage terminal .

下列係舉實施例配合所附圖示做詳細說明，但所提供之實施例並非用以限制本揭露所涵蓋的範圍，而結構運作之描述非用以限制其執行順序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本揭露所涵蓋的範圍。另外，圖示僅以說明為目的，並未依照原尺寸作圖。為使便於理解，下述說明中相同元件或相似元件將以相同之符號標示來說明。The following is a detailed description of the embodiments in conjunction with the attached drawings, but the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structure and operation is not intended to limit the execution sequence. Any recombination of components Structures and devices with equivalent functions are all within the scope of this disclosure. In addition, the illustrations are for illustration purposes only and are not drawn in original size. To facilitate understanding, the same elements or similar elements will be described with the same symbols in the following description.

於本文中，除非內文對於冠詞有特別限定，否則『一』與『該』可泛指單一個或多個。此外，本文使用之『包含』、『包括』、『具有』、以及相似詞彙，係用以指明所記載的特徵、區域、整數、步驟、操作、元件及/或組件。In this article, "a" and "the" can generally refer to one or more, unless the context specifically restricts the article. In addition, "comprising", "comprising", "having" and similar words used herein are used to designate the recited features, regions, integers, steps, operations, elements and/or components.

於本文中，當一元件被描述為係『連接』、『耦接』或『電性連接』至另一元件時，該元件可為直接連接、直接耦接或直接電性連接至該另一元件，亦可為該二元件之間有一額外元件存在，而該元件間接連接、間接耦接或間接電性連接至該另一元件。此外，雖然本文中使用『第一』、『第二』、…等用語描述不同元件，該用語僅是用以區別以相同技術用語描述的元件或操作。In this document, when an element is described as being "connected", "coupled" or "electrically connected" to another element, the element may be directly connected, directly coupled or directly electrically connected to the other element. An element may also be an additional element existing between the two elements, and the element is indirectly connected, indirectly coupled, or indirectly electrically connected to the other element. In addition, although terms such as "first", "second", ..., etc. are used herein to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms.

本案的一實施例係關於一種顯示裝置。請參照第1圖。第1圖為根據本揭示一些實施例之顯示裝置100的局部示意圖。顯示裝置100包含多個像素110，像素110以陣列方式配置於顯示裝置100中，換言之像素110係以多行及多列的方式設置。此外，在第1圖的實施例中，同一列的像素110透過走線耦接至相同的電壓VDD、VSS，且電壓VDD具有相對高的電壓位準，電壓VSS具有相對低的電壓位準，惟此實施例僅為示例性質，在不同實施例中，可使用不同的走線設計（如下述第5A圖至第6B圖）來對像素110提供電壓。第1圖實施例中像素110的大小及數量亦為示意性質，而不代表像素110的實際大小及數量。An embodiment of the present application relates to a display device. Please refer to Figure 1. FIG. 1 is a partial schematic diagram of a display device 100 according to some embodiments of the present disclosure. The display device 100 includes a plurality of pixels 110 , and the pixels 110 are arranged in an array in the display device 100 , in other words, the pixels 110 are arranged in a plurality of rows and columns. In addition, in the embodiment in FIG. 1 , the pixels 110 in the same row are coupled to the same voltage VDD, VSS through wires, and the voltage VDD has a relatively high voltage level, and the voltage VSS has a relatively low voltage level, However, this embodiment is only exemplary, and in different embodiments, different wiring designs (such as the following FIGS. 5A to 6B ) can be used to supply voltage to the pixel 110 . The size and quantity of the pixels 110 in the embodiment in FIG. 1 are also schematic and do not represent the actual size and quantity of the pixels 110 .

如第1圖中左上角的像素110所示，每個像素110皆包含驅動電路120R、120G、120B以及發光二極體（light emitting diode，LED）DR1、DR2、DG、DB。驅動電路120R、120G、120B用以接收電壓VDD以驅動對應的發光二極體進行發光，詳細來說驅動電路120R、120G、120B的第一端用以接收電壓VDD，驅動電路120R的第二端耦接發光二極體DR1、DR2，驅動電路120G的第二端耦接發光二極體DG，驅動電路120B的第二端耦接發光二極體DB。發光二極體DR2、DG、DB的第二端用以接收電壓VSS。As shown by the pixel 110 at the upper left corner in FIG. 1 , each pixel 110 includes driving circuits 120R, 120G, 120B and light emitting diodes (light emitting diodes, LEDs) DR1 , DR2 , DG, DB. The driving circuits 120R, 120G, and 120B are used to receive the voltage VDD to drive the corresponding light-emitting diodes to emit light. Specifically, the first terminals of the driving circuits 120R, 120G, and 120B are used to receive the voltage VDD, and the second terminal of the driving circuit 120R The second end of the driving circuit 120G is coupled to the light emitting diode DG, and the second end of the driving circuit 120B is coupled to the light emitting diode DB. The second ends of the light emitting diodes DR2 , DG, DB are used to receive the voltage VSS.

如第1圖所示，驅動電路120R所耦接的發光二極體DR1、DR2可被視為第一組子像素，驅動電路120G所耦接的發光二極體DG可被視為第二組子像素，驅動電路120B所耦接的發光二極體DB可被視為第三組子像素。換言之，每個像素110皆包含三組子像素，每組子像素皆透過對應的驅動電路加以驅動而發光。在一些實施例中，第一組子像素包含紅光發光二極體而用以發出紅光，第二組子像素包含綠光發光二極體而用以發出綠光，第三組子像素包含藍光發光二極體而用以發出藍光。As shown in FIG. 1, the LEDs DR1 and DR2 coupled to the driving circuit 120R can be regarded as the first group of sub-pixels, and the LEDs DG coupled to the driving circuit 120G can be regarded as the second group. The sub-pixels, the LEDs DB coupled to the driving circuit 120B can be regarded as the third group of sub-pixels. In other words, each pixel 110 includes three groups of sub-pixels, and each group of sub-pixels is driven by a corresponding driving circuit to emit light. In some embodiments, the first group of sub-pixels includes red light-emitting diodes for emitting red light, the second group of sub-pixels includes green light-emitting diodes for emitting green light, and the third group of sub-pixels includes Blue light-emitting diodes are used to emit blue light.

在一些實施例中，顯示裝置100包含閘極驅動電路及源極驅動電路（未繪示於圖中），閘極驅動電路用以啟用並導通驅動電路120R、120G、120B，源極驅動電路用以提供電壓VDD至驅動電路120R、120G、120B，顯示裝置100因而可以透過閘極驅動電路決定各個像素110發光的時點，並透過源極驅動電路決定各個像素110發光的亮度。In some embodiments, the display device 100 includes a gate driving circuit and a source driving circuit (not shown in the figure), the gate driving circuit is used to enable and conduct the driving circuits 120R, 120G, 120B, and the source driving circuit is used for By providing the voltage VDD to the driving circuits 120R, 120G, and 120B, the display device 100 can determine the timing of each pixel 110 to emit light through the gate driving circuit, and determine the brightness of each pixel 110 through the source driving circuit.

值得注意的是，像素110中有一組子像素包含串聯耦接的兩個發光二極體。在第1圖所示的實施例中，第一組子像素包含串聯耦接的發光二極體DR1、DR2，不過本案之實施例並不限制於此，在不同的實施例中可以有多組子像素包含串聯耦接的發光二極體，且串聯耦接的發光二極體可以多於兩個。上述子像素中串聯耦接發光二極體的設計是為了降低顯示裝置100的功率消耗，以下透過第2A圖及第2B圖進一步說明。It should be noted that a group of sub-pixels in the pixel 110 includes two light-emitting diodes coupled in series. In the embodiment shown in FIG. 1 , the first group of sub-pixels includes light-emitting diodes DR1 and DR2 coupled in series, but the embodiment of this case is not limited thereto, and there may be multiple groups in different embodiments The sub-pixels include LEDs coupled in series, and there may be more than two LEDs coupled in series. The series connection of light-emitting diodes in the above-mentioned sub-pixels is designed to reduce the power consumption of the display device 100 , which will be further described below through FIG. 2A and FIG. 2B .

第2A圖及第2B圖為根據本案一些實施例之子像素顯示電路的電路示意圖。第2A圖的顯示電路並未採用串聯耦接發光二極體（顯示電路僅包含一個發光二極體D1），第2B圖的顯示電路採用串聯耦接發光二極體（顯示電路包含串聯耦接的發光二極體D1、D2），在此二實施例中皆透過電晶體T1來驅動一組子像素，且電晶體T1與子像素皆耦接於電壓VDD與電壓VSS之間。FIG. 2A and FIG. 2B are schematic circuit diagrams of sub-pixel display circuits according to some embodiments of the present invention. The display circuit in Figure 2A does not use series-coupled light-emitting diodes (the display circuit only includes one light-emitting diode D1), and the display circuit in Figure 2B uses series-coupled light-emitting diodes (the display circuit includes series-coupled In the two embodiments, a group of sub-pixels are driven by the transistor T1, and the transistor T1 and the sub-pixels are both coupled between the voltage VDD and the voltage VSS.

在第2A圖的顯示電路中，電晶體T1的第一端接收電壓VDD，電晶體T1的第二端耦接發光二極體D1，發光二極體D1的第二端耦接電壓VDD，流經電晶體T1及發光二極體D1的電流為電流I1。在第2B圖的顯示電路中，假設發光二極體D2與發光二極體D1為相同種類的發光二極體而具有相同的電阻及順向偏壓，由於串聯了兩個發光二極體D1、D2，第2B圖的子像素大約具有相較於第2A圖子像素兩倍的電阻，因此流經電晶體T1、發光二極體D1及發光二極體D2的電流I2其大小約為電流I1的二分之一（暫時忽略電晶體T1之電阻）。In the display circuit shown in Figure 2A, the first end of the transistor T1 receives the voltage VDD, the second end of the transistor T1 is coupled to the light-emitting diode D1, and the second end of the light-emitting diode D1 is coupled to the voltage VDD. The current passing through the transistor T1 and the light-emitting diode D1 is the current I1. In the display circuit shown in Figure 2B, assuming that the light-emitting diode D2 and the light-emitting diode D1 are the same type of light-emitting diode and have the same resistance and forward bias voltage, since two light-emitting diodes D1 are connected in series , D2, the sub-pixel in Figure 2B has about twice the resistance of the sub-pixel in Figure 2A, so the current I2 flowing through the transistor T1, the light-emitting diode D1 and the light-emitting diode D2 has a magnitude of approximately current One-half of I1 (temporarily ignore the resistance of transistor T1).

關於子像素（即發光二極體）的功率消耗，雖然電流I2為電流I1的二分之一，但第2B圖串聯耦接的發光二極體D1、D2其兩端的電壓差為第2A圖顯示電路中發光二極體D1其兩端電壓差的兩倍，因此在兩電路中發光二極體的功率消耗為相同（功率消耗為電流乘以電壓）。然而，關於電晶體T1的功率消耗，由於電流I2為電流I1的二分之一，第2B圖顯示電路中電晶體T1的功率消耗會小於第2A圖顯示電路中電晶體T1的功率消耗。此外，在第2A圖及第2B圖的兩電路中皆需要額外的電路（未繪示於圖中）來提供電壓至節點N1，節點N1的電壓將決定兩電路中的電流。由於電流I2為電流I1的二分之一，在第2B圖顯示電路中用以提供節點N1電壓的電路其功率消耗也會較第2A圖顯示電路的此等電路來的低。Regarding the power consumption of sub-pixels (ie, light-emitting diodes), although the current I2 is half of the current I1, the voltage difference between the light-emitting diodes D1 and D2 coupled in series in Figure 2B is as shown in Figure 2A The light-emitting diode D1 in the display circuit is twice the voltage difference between its two ends, so the power consumption of the light-emitting diode in the two circuits is the same (power consumption is current multiplied by voltage). However, regarding the power consumption of the transistor T1, since the current I2 is half of the current I1, the power consumption of the transistor T1 in the circuit shown in FIG. 2B is smaller than the power consumption of the transistor T1 in the circuit shown in FIG. 2A. In addition, in the two circuits of FIG. 2A and FIG. 2B , an additional circuit (not shown in the figure) is required to provide a voltage to the node N1, and the voltage of the node N1 will determine the current in the two circuits. Since the current I2 is one-half of the current I1, the power consumption of the circuit for supplying the node N1 voltage in the circuit shown in FIG. 2B is also lower than that in the circuit shown in FIG. 2A.

基於上述第2A圖及第2B圖實施例之比較，使用串聯耦接的多個發光二極體將有助於降低電路的功率消耗，因此本案之實施例（例如前述第1圖的顯示電路100）在每一像素中至少有一組子像素為串聯耦接的多個發光二極體，藉以提升顯示電路的功率效率。Based on the comparison of the embodiments in Figure 2A and Figure 2B above, the use of multiple light-emitting diodes coupled in series will help reduce the power consumption of the circuit, so the embodiments of this case (such as the display circuit 100 in the aforementioned Figure 1 ) In each pixel, at least one group of sub-pixels is a plurality of light-emitting diodes coupled in series, so as to improve the power efficiency of the display circuit.

本案的一實施例亦提出一種半導體結構，以將串聯耦接的多個發光二極體製作於同一個半導體結構上。請參照第3圖。第3圖為根據本揭示一些實施例之半導體裝置300的截面圖。半導體裝置300包含緩衝層330以及形成在緩衝層330上的兩個子晶片310、320。此兩個子晶片310、320可對應於第1圖實施例中串聯耦接的發光二極體DR1及發光二極體DR2。子晶片310與子晶片320係分開且獨立地設置在緩衝層330上。子晶片310由上至下依序包含第一擴散層312、主動層314以及第二擴散層316，子晶片320由上至下依序包含第一擴散層322、主動層324以及第二擴散層326。An embodiment of the present application also provides a semiconductor structure, so that a plurality of LEDs coupled in series are fabricated on the same semiconductor structure. Please refer to Figure 3. FIG. 3 is a cross-sectional view of a semiconductor device 300 according to some embodiments of the present disclosure. The semiconductor device 300 includes a buffer layer 330 and two sub-wafers 310 , 320 formed on the buffer layer 330 . The two sub-chips 310, 320 may correspond to the light-emitting diode DR1 and the light-emitting diode DR2 coupled in series in the embodiment of FIG. 1 . The sub-wafer 310 and the sub-wafer 320 are separated and independently disposed on the buffer layer 330 . The sub-chip 310 includes a first diffusion layer 312, an active layer 314, and a second diffusion layer 316 from top to bottom, and the sub-chip 320 includes a first diffusion layer 322, an active layer 324, and a second diffusion layer from top to bottom. 326.

在一些實施例中，子晶片310的第一擴散層312、子晶片320的第一擴散層322以及緩衝層330為相同類型的磊晶層，子晶片310的第二擴散層316以及子晶片320的第二擴散層326為另一類型的磊晶層。舉例而言，在第3圖的實施例中，第一擴散層312、第一擴散層322以及緩衝層330為包含P型摻雜物的P型磊晶層，第二擴散層316及第二擴散層326為包含N型摻雜物的N型磊晶層。In some embodiments, the first diffusion layer 312 of the sub-wafer 310, the first diffusion layer 322 of the sub-wafer 320, and the buffer layer 330 are the same type of epitaxial layer, and the second diffusion layer 316 of the sub-wafer 310 and the sub-wafer 320 The second diffusion layer 326 is another type of epitaxial layer. For example, in the embodiment of FIG. 3, the first diffusion layer 312, the first diffusion layer 322, and the buffer layer 330 are P-type epitaxial layers containing P-type dopants, and the second diffusion layer 316 and the second The diffusion layer 326 is an N-type epitaxial layer containing N-type dopants.

在一些實施例中，子晶片310的主動層314以及子晶片320的主動層324具有多重量子井（multiple quantum well，MQW）之結構，用以當電流流經時進行發光。In some embodiments, the active layer 314 of the sub-chip 310 and the active layer 324 of the sub-chip 320 have a multiple quantum well (MQW) structure for emitting light when current flows therethrough.

在第3圖的實施例中，半導體裝置300可更包含電極340、電極350以及連接件CON，其中電極340、電極350以及連接件CON為導體（例如金屬）而可用以傳輸電流。電極340設置於第一子晶片310的第一擴散層312上，且電極340用以接收相對高的電壓而作為半導體裝置300的陽極。連接件CON用以將第一子晶片310的第二擴散層316電性耦接至第二子晶片320的第一擴散層322。電極350用以將第二子晶片320的第二擴散層326與緩衝層330耦接，且電極350用以接收相對低的電壓而作為半導體裝置300的陰極。在一實施例中，半導體裝置300的多處具有隔離層INS，以確保電極340、電極350及連接件CON正確地耦接對應的結構並避免元件間產生錯誤的電性連接。In the embodiment shown in FIG. 3 , the semiconductor device 300 may further include an electrode 340 , an electrode 350 and a connector CON, wherein the electrode 340 , the electrode 350 and the connector CON are conductors (such as metal) for transmitting current. The electrode 340 is disposed on the first diffusion layer 312 of the first sub-wafer 310 , and the electrode 340 is used to receive a relatively high voltage as an anode of the semiconductor device 300 . The connector CON is used to electrically couple the second diffusion layer 316 of the first sub-chip 310 to the first diffusion layer 322 of the second sub-chip 320 . The electrode 350 is used to couple the second diffusion layer 326 of the second sub-chip 320 with the buffer layer 330 , and the electrode 350 is used to receive a relatively low voltage as a cathode of the semiconductor device 300 . In one embodiment, multiple places of the semiconductor device 300 have isolation layers INS to ensure that the electrodes 340 , the electrodes 350 and the connectors CON are correctly coupled to the corresponding structures and avoid incorrect electrical connections between elements.

操作上，當電極340接收相對高的電壓（例如第1圖實施例中的電壓VDD）而電極350接收相對低的電壓（例如第1圖實施例中的電壓VSS）時，子晶片310中將產生電流I31從P型的第一擴散層312流經主動層314再流向N型的第二擴散層316。接著，電流I32將從子晶片310的第二擴散層316透過連接件CON流向子晶片320的第一擴散層322。最後，子晶片320中將產生電流I33從P型的第一擴散層322流經主動層324再流向N型的第二擴散層326。由於電流I31、I33分別流經子晶片310的主動層314以及子晶片320的主動層324，子晶片310以及子晶片320將發光。第1圖實施例中串聯耦接的發光二極體DR1、DR2因而可採用如半導體結構300之結構，子晶片310、320分別對應發光二極體DR1、DR2，且子晶片310、320透過連接件CON來串聯耦接。Operationally, when the electrode 340 receives a relatively high voltage (such as the voltage VDD in the embodiment of FIG. 1 ) and the electrode 350 receives a relatively low voltage (such as the voltage VSS in the embodiment of FIG. 1 ), the daughter chip 310 will The generated current I31 flows from the P-type first diffusion layer 312 through the active layer 314 to the N-type second diffusion layer 316 . Then, the current I32 will flow from the second diffusion layer 316 of the sub-chip 310 to the first diffusion layer 322 of the sub-chip 320 through the connector CON. Finally, a current I33 will be generated in the daughter wafer 320 to flow from the P-type first diffusion layer 322 through the active layer 324 to the N-type second diffusion layer 326 . Since the currents I31 and I33 respectively flow through the active layer 314 of the sub-chip 310 and the active layer 324 of the sub-chip 320 , the sub-chip 310 and the sub-chip 320 will emit light. The light-emitting diodes DR1 and DR2 coupled in series in the embodiment of FIG. 1 can therefore adopt a structure such as the semiconductor structure 300. The sub-chips 310 and 320 correspond to the light-emitting diodes DR1 and DR2 respectively, and the sub-chips 310 and 320 are connected through parts CON to couple in series.

值得說明的是，經摻雜的緩衝層330（在第3圖實施例中緩衝層330包含P型摻雜物）可避免半導體裝置300中產生漏電流從子晶片310的第二擴散層316透過緩衝層330流向電極350，或有漏電流形成於子晶片320的第二擴散層326與緩衝層330之間。如前所述，第二擴散層316及第二擴散層326為N型磊晶層，而緩衝層330為P型磊晶層，因此第二擴散層316與緩衝層330的接觸面以及第二擴散層326與緩衝層330的接觸面皆將形成PN接面（PN junction）。基於PN接面在接收逆向偏壓（reverse bias）時將斷路的特性，第二擴散層316與緩衝層330的接觸面以及第二擴散層326與緩衝層330的接觸面皆可當作二極體。詳細來說，由於子晶片310透過電極340接收相對高的電壓，而緩衝層330透過電極350接收相對低的電壓，N型的第二擴散層316將具有較P型的緩衝層330更高的電壓，如此將形成PN接面的逆向偏壓，此時第二擴散層316與緩衝層330臨近其接觸面的區域將形成空乏區而僅有少數載子飄移，因此第二擴散層316與緩衝層330之間將形成斷路，而能確保不會有電流從第二擴散層316流向緩衝層330。此外，第二擴散層326與緩衝層330形成的PN接面由於兩者透過電極350而接收相同的電壓，因此兩者之間亦不會產生電流。在不同的例子中，緩衝層可能未經摻雜或僅有低摻雜，則緩衝層中即可能出現漏電流，而影響子晶片的發光效率。It is worth noting that the doped buffer layer 330 (the buffer layer 330 includes P-type dopants in the embodiment shown in FIG. The buffer layer 330 flows to the electrode 350 , or a leakage current is formed between the second diffusion layer 326 of the daughter chip 320 and the buffer layer 330 . As mentioned above, the second diffusion layer 316 and the second diffusion layer 326 are N-type epitaxial layers, and the buffer layer 330 is a P-type epitaxial layer, so the contact surface between the second diffusion layer 316 and the buffer layer 330 and the second Both the contact surfaces of the diffusion layer 326 and the buffer layer 330 will form a PN junction (PN junction). Based on the characteristic that the PN junction will be open when receiving reverse bias, the contact surface between the second diffusion layer 316 and the buffer layer 330 and the contact surface between the second diffusion layer 326 and the buffer layer 330 can be used as a diode body. In detail, since the daughter chip 310 receives a relatively high voltage through the electrode 340, and the buffer layer 330 receives a relatively low voltage through the electrode 350, the N-type second diffusion layer 316 will have a higher voltage than the P-type buffer layer 330. In this way, the reverse bias voltage of the PN junction will be formed. At this time, the region of the second diffusion layer 316 and the buffer layer 330 near the contact surface will form a depletion region and only a few carriers will drift. Therefore, the second diffusion layer 316 and the buffer layer An open circuit will be formed between the layers 330 to ensure that no current flows from the second diffusion layer 316 to the buffer layer 330 . In addition, since the PN junction formed by the second diffusion layer 326 and the buffer layer 330 receives the same voltage through the electrode 350 , no current will be generated between them. In different examples, the buffer layer may be undoped or only lightly doped, and leakage current may occur in the buffer layer, which affects the luminous efficiency of the sub-wafer.

在第3圖的實施例中，電極350延伸設置至第二子晶片320的第一擴散層322上，而與設置於第一子晶片310的第一擴散層312上的電極340具有實質上相同的高度，此實施例有利於進行半導體裝置300的巨量轉移。在一些實施例中，子晶片310及子晶片320之間的間隔大於或等於約1微米，且子晶片310及子晶片320的長度皆小於或等於約100微米。In the embodiment of FIG. 3 , the electrode 350 extends to the first diffusion layer 322 of the second sub-wafer 320 , and has substantially the same structure as the electrode 340 disposed on the first diffusion layer 312 of the first sub-wafer 310 . The height of this embodiment is favorable for mass transfer of the semiconductor device 300 . In some embodiments, the spacing between the sub-wafer 310 and the sub-wafer 320 is greater than or equal to about 1 micron, and the length of the sub-wafer 310 and the sub-wafer 320 is less than or equal to about 100 microns.

在一些實施例中，可以形成多於兩個的子晶片在同一個半導體裝置上，並透過多個連接件來將對應的兩個子晶片進行串聯耦接，例如在第3圖的半導體結構300中，於子晶片320的右側繼續向右設置具有類似的擴散層與主動層結構的子晶片並透過另一連接件CON加以連接，並將電極350改為設置於半導體結構300的最右側部分。In some embodiments, more than two sub-chips can be formed on the same semiconductor device, and the corresponding two sub-chips can be connected in series through a plurality of connectors, such as the semiconductor structure 300 in FIG. 3 In the process, a sub-chip with a similar diffusion layer and active layer structure is further disposed on the right side of the sub-chip 320 and connected through another connector CON, and the electrode 350 is changed to be disposed on the rightmost part of the semiconductor structure 300 .

請參照第4圖。第4圖為根據本揭示一些實施例之半導體裝置400的截面圖。半導體裝置400具有與半導體裝置300類似的結構，但半導體裝置400中的結構包含不同的摻雜物且其電極接收與第3圖實施例不同的電壓。如第4圖所示，半導體裝置400包含緩衝層430以及形成在緩衝層430上的兩個子晶片410、420。子晶片410包含第一擴散層412、主動層414以及第二擴散層416，子晶片420包含第一擴散層422、主動層424以及第二擴散層426。電極440設置於子晶片410的第一擴散層412上，連接件CON用以耦接子晶片410的第二擴散層416以及子晶片420的第一擴散層422。Please refer to Figure 4. FIG. 4 is a cross-sectional view of a semiconductor device 400 according to some embodiments of the present disclosure. Semiconductor device 400 has a similar structure to semiconductor device 300 , but the structure in semiconductor device 400 contains different dopants and its electrodes receive a different voltage than the embodiment of FIG. 3 . As shown in FIG. 4 , the semiconductor device 400 includes a buffer layer 430 and two sub-wafers 410 , 420 formed on the buffer layer 430 . The daughter chip 410 includes a first diffusion layer 412 , an active layer 414 and a second diffusion layer 416 , and the daughter chip 420 includes a first diffusion layer 422 , an active layer 424 and a second diffusion layer 426 . The electrode 440 is disposed on the first diffusion layer 412 of the sub-chip 410 , and the connector CON is used to couple the second diffusion layer 416 of the sub-chip 410 and the first diffusion layer 422 of the sub-chip 420 .

與第3圖實施例之半導體裝置300不同地，在半導體裝置400中子晶片410的第一擴散層412、子晶片420的第一擴散層422以及緩衝層430為包含N型摻雜物的N型磊晶層，子晶片410的第二擴散層416以及子晶片420的第二擴散層426為包含P型摻雜物的P型磊晶層。Different from the semiconductor device 300 of the embodiment in FIG. 3, in the semiconductor device 400, the first diffusion layer 412 of the sub-wafer 410, the first diffusion layer 422 of the sub-wafer 420, and the buffer layer 430 are N The second diffusion layer 416 of the sub-wafer 410 and the second diffusion layer 426 of the sub-wafer 420 are P-type epitaxial layers containing P-type dopants.

此外，電極440用以接收相對低的電壓（例如第1圖實施例中的電壓VSS），電極450用以接收相對高的電壓（例如第1圖實施例中的電壓VDD）。操作上，由於子晶片420的第二擴散層426透過電極450接收相對高的電壓，將形成電流I41從第二擴散層426流經主動層424再流向第一擴散層422。接著，電流I42將從子晶片420的第一擴散層422透過連接件CON流向子晶片410的第二擴散層416。最後，電流I43將從第二擴散層416流經主動層414再流向第一擴散層412。子晶片420以及子晶片410因此將發光。In addition, the electrode 440 is used to receive a relatively low voltage (such as the voltage VSS in the embodiment of FIG. 1 ), and the electrode 450 is used to receive a relatively high voltage (such as the voltage VDD in the embodiment of FIG. 1 ). In operation, since the second diffusion layer 426 of the daughter chip 420 receives a relatively high voltage through the electrode 450 , a current I41 will flow from the second diffusion layer 426 through the active layer 424 to the first diffusion layer 422 . Then, the current I42 will flow from the first diffusion layer 422 of the sub-chip 420 to the second diffusion layer 416 of the sub-chip 410 through the connector CON. Finally, the current I43 will flow from the second diffusion layer 416 through the active layer 414 to the first diffusion layer 412 . Daughter wafer 420 as well as daughter wafer 410 will thus emit light.

經摻雜的緩衝層430（在第4圖實施例中緩衝層430包含N型摻雜物）可避免半導體裝置400中產生漏電流。P型的第二擴散層416與N型的緩衝層430的接觸面以及P型的第二擴散層426與N型的緩衝層430的接觸面皆將形成PN接面，因此當緩衝層430具有相對於第二擴散層416或第二擴散層426更高的電壓時，PN接面為逆向偏壓，因此將形成斷路。換言之，由於緩衝層430透過電極450接收相對高的電壓，而子晶片410透過電極440接收相對低的電壓，第二擴散層416與緩衝層430形成的PN接面此時受到逆向偏壓，因此能確保不會有電流從緩衝層430流向第二擴散層416。此外，緩衝層430與第二擴散層426形成的PN接面由於兩者透過電極450而接收相同的電壓，因此兩者之間亦不會產生漏電流。The doped buffer layer 430 (in the embodiment of FIG. 4 , the buffer layer 430 includes N-type dopants) can prevent leakage current in the semiconductor device 400 . The contact surface between the P-type second diffusion layer 416 and the N-type buffer layer 430 and the contact surface between the P-type second diffusion layer 426 and the N-type buffer layer 430 will form a PN junction, so when the buffer layer 430 has At higher voltages relative to the second diffusion layer 416 or the second diffusion layer 426 , the PN junction is reverse biased and thus an open circuit will be formed. In other words, since the buffer layer 430 receives a relatively high voltage through the electrode 450 , and the daughter chip 410 receives a relatively low voltage through the electrode 440 , the PN junction formed by the second diffusion layer 416 and the buffer layer 430 is under reverse bias at this time, so It can ensure that no current flows from the buffer layer 430 to the second diffusion layer 416 . In addition, since the PN junction formed by the buffer layer 430 and the second diffusion layer 426 receives the same voltage through the electrode 450 , no leakage current will be generated between them.

在一些實施例中，可以形成多於兩個的子晶片在同一個半導體裝置上，並透過多個連接件來將對應的兩個子晶片進行串聯耦接，例如在第4圖的半導體結構400中，在子晶片410的左側繼續向左設置具有類似結構的子晶片並透過另一連接件CON加以連接，並將電極440改為設置於半導體結構400的最左側部分。In some embodiments, more than two sub-chips can be formed on the same semiconductor device, and the corresponding two sub-chips can be connected in series through a plurality of connectors, such as the semiconductor structure 400 in FIG. 4 In the process, a sub-chip with a similar structure is arranged on the left side of the sub-chip 410 to the left and is connected through another connector CON, and the electrode 440 is changed to be set on the leftmost part of the semiconductor structure 400 .

綜上所述，透過如第3圖及第4圖所示的半導體結構將可以實現第1圖顯示電路100中的串聯耦接的發光二極體，且如此結構能夠避免漏電流產生以確保發光二極體子晶片的發光效率。To sum up, through the semiconductor structure shown in FIG. 3 and FIG. 4, the series-coupled light-emitting diodes in the circuit 100 shown in FIG. 1 can be realized, and such a structure can avoid leakage current to ensure light emission. The luminous efficiency of the diode daughter chip.

請再參照第1圖。由於第1圖的像素110中第一組子像素的發光二極體DR1、DR2為串聯耦接，與發光二極體DG或發光二極體DB相比需要較大的電壓才能使其導通並發光，因此若對三組子像素皆提供相同的電壓VDD則可能造成額外的功率消耗。舉例來說，假設發光二極體DR1、DR2皆為紅光發光二極體且其順向偏壓為2.5伏特(V)，發光二極體DG、DB分別為綠光發光二極體及藍光發光二極體且其順向偏壓皆為3 V，若暫不考慮驅動電路120R、120G、120B所需的電壓，而以5V的電壓VDD來驅動三組子像素，雖可確保三組子像素中的發光二極體均能夠發光，但發光二極體DG、DB實質上僅需3V的電壓即可進行發光，因而產生多餘的功率消耗。基此，本案的一實施例亦提出包含三組以上電壓的顯示電路，以進一步改善顯示電路的功率效率。Please refer to Figure 1 again. Since the light-emitting diodes DR1 and DR2 of the first group of sub-pixels in the pixel 110 in FIG. Therefore, if the same voltage VDD is provided to all three groups of sub-pixels, additional power consumption may be caused. For example, assuming that the LEDs DR1 and DR2 are both red LEDs and their forward bias voltage is 2.5 volts (V), the LEDs DG and DB are green LEDs and blue LEDs respectively. The light-emitting diodes and their forward bias voltages are all 3 V. If the voltage required by the driving circuits 120R, 120G, and 120B is not considered for the time being, and the voltage VDD of 5V is used to drive the three groups of sub-pixels, although the three groups of sub-pixels can be guaranteed All the light emitting diodes in the pixel can emit light, but the light emitting diodes DG and DB only need a voltage of 3V to emit light substantially, thus generating redundant power consumption. Based on this, an embodiment of the present application also proposes a display circuit including more than three sets of voltages, so as to further improve the power efficiency of the display circuit.

請參照第5A圖，第5A圖為根據本揭示一些實施例之像素510A的示意圖。第1圖中的像素110可改採用像素510A之設計。如第5A圖所示，像素510A包含驅動電路120R、120G、120B以及三組子像素（即發光二極體DR1、DR2形成的第一組子像素、發光二極體DG形成的第二組子像素以及發光二極體DB形成的第三組子像素）。與第1圖實施例不同地，驅動電路120R的第一端接收電壓VDD2，驅動電路120G、120B的第一端接收電壓VDD1，電壓VDD2與電壓VDD1不同。Please refer to FIG. 5A , which is a schematic diagram of a pixel 510A according to some embodiments of the present disclosure. The pixel 110 in FIG. 1 can be changed to the design of the pixel 510A. As shown in FIG. 5A, the pixel 510A includes driving circuits 120R, 120G, and 120B and three groups of sub-pixels (that is, the first group of sub-pixels formed by light-emitting diodes DR1 and DR2, the second group of sub-pixels formed by light-emitting diodes DG pixel and the third group of sub-pixels formed by the light-emitting diode DB). Different from the embodiment in FIG. 1 , the first terminal of the driving circuit 120R receives the voltage VDD2 , the first terminals of the driving circuits 120G and 120B receive the voltage VDD1 , and the voltage VDD2 is different from the voltage VDD1 .

在一實施例中，發光二極體DR1、DR2皆為紅光發光二極體且其各自之順向偏壓皆為2.5 V，發光二極體DG、DB分別為綠光發光二極體及藍光發光二極體且其順向偏壓皆為3 V，因此電壓VDD1可具有較電壓VDD2小的電壓（例如電壓VDD2為5 V，電壓VSS為0 V，電壓VDD1為3 V），因而能夠使所有發光二極體發光並節省功率消耗。In one embodiment, the light-emitting diodes DR1 and DR2 are both red light-emitting diodes and their respective forward bias voltages are 2.5 V, and the light-emitting diodes DG and DB are green light-emitting diodes and The blue light-emitting diode and its forward bias voltage are all 3 V, so the voltage VDD1 can have a voltage smaller than the voltage VDD2 (for example, the voltage VDD2 is 5 V, the voltage VSS is 0 V, and the voltage VDD1 is 3 V), so it can Make all LEDs glow and save power consumption.

在一些實施例中，電壓VDD2是由顯示電路中的第一參考電壓端提供，電壓VSS是由顯示電路中的第二參考電壓端所提供，電壓VDD1是由顯示電路中的第三參考電壓端所提供，電壓VDD2、VDD1、VSS三者彼此不同。在第5A圖的實施例中，電壓VDD2、VDD1皆大於電壓VSS，電壓VDD2又大於電壓VDD1。此外，串聯耦接的發光二極體DR1、DR2耦接於第一參考電壓端及第二參考電壓端之間，發光二極體DG耦接於第三參考電壓端及第二參考電壓端之間。In some embodiments, the voltage VDD2 is provided by the first reference voltage terminal in the display circuit, the voltage VSS is provided by the second reference voltage terminal in the display circuit, and the voltage VDD1 is provided by the third reference voltage terminal in the display circuit Provided, the three voltages VDD2 , VDD1 , and VSS are different from each other. In the embodiment shown in FIG. 5A, the voltages VDD2 and VDD1 are both greater than the voltage VSS, and the voltage VDD2 is greater than the voltage VDD1. In addition, the light emitting diodes DR1 and DR2 coupled in series are coupled between the first reference voltage terminal and the second reference voltage terminal, and the light emitting diode DG is coupled between the third reference voltage terminal and the second reference voltage terminal. between.

在一些實施例中，第一組子像素除了發光二極體DR1、DR2外可包含更多個發光二極體。在不同的實施例中，像素510A的第一組子像素可僅包含一個紅光發光二極體，而第二組子像素或第三組子像素包含串聯耦接的多個綠光發光二極體或藍光發光二極體。In some embodiments, the first group of sub-pixels may include more light-emitting diodes besides the light-emitting diodes DR1, DR2. In different embodiments, the first group of sub-pixels of the pixel 510A may include only one red light-emitting diode, while the second group of sub-pixels or the third group of sub-pixels may include multiple green light-emitting diodes coupled in series. body or blue light emitting diode.

請參照第5B圖，第5B圖為根據本揭示一些實施例之像素510B的示意圖。第1圖中的像素110可改為採用像素510B之設計。像素510B具有與第1圖中像素110類似的結構，但與第1圖實施例不同地，發光二極體DR2的第二端接收電壓VSS2，發光二極體DG與發光二極體DB的第二端接收電壓VSS1，電壓VSS2與電壓VSS1不同。Please refer to FIG. 5B , which is a schematic diagram of a pixel 510B according to some embodiments of the present disclosure. The pixel 110 in FIG. 1 can be changed to adopt the design of the pixel 510B. The pixel 510B has a structure similar to that of the pixel 110 in Figure 1, but different from the embodiment in Figure 1, the second end of the light-emitting diode DR2 receives the voltage VSS2, and the second end of the light-emitting diode DG and the light-emitting diode DB The two terminals receive the voltage VSS1, and the voltage VSS2 is different from the voltage VSS1.

在一實施例中，發光二極體DR1、DR2皆為紅光發光二極體且其各自之順向偏壓皆為2.5 V，發光二極體DG、DB分別為綠光發光二極體及藍光發光二極體且其順向偏壓皆為3 V，電壓VDD為5 V，電壓VSS2為0 V，電壓VSS1為2 V。In one embodiment, the light-emitting diodes DR1 and DR2 are both red light-emitting diodes and their respective forward bias voltages are 2.5 V, and the light-emitting diodes DG and DB are green light-emitting diodes and The forward bias voltage of the blue light emitting diode is 3 V, the voltage VDD is 5 V, the voltage VSS2 is 0 V, and the voltage VSS1 is 2 V.

在一些實施例中，電壓VDD是由顯示電路中的第一參考電壓端提供，電壓VSS2是由顯示電路中的第二參考電壓端所提供，電壓VSS1是由顯示電路中的第三參考電壓端所提供，電壓VDD、VSS2、VSS1三者彼此不同。在第5B圖的實施例中，電壓VSS2、VSS1皆小於電壓VDD，電壓VSS2又小於電壓VSS1。此外，串聯耦接的發光二極體DR1、DR2耦接於第一參考電壓端及第二參考電壓端之間，發光二極體DG與發光二極體DB耦接於第一參考電壓端及第三參考電壓端之間。In some embodiments, the voltage VDD is provided by the first reference voltage terminal in the display circuit, the voltage VSS2 is provided by the second reference voltage terminal in the display circuit, and the voltage VSS1 is provided by the third reference voltage terminal in the display circuit It is provided that the three voltages VDD, VSS2 and VSS1 are different from each other. In the embodiment shown in FIG. 5B, the voltages VSS2 and VSS1 are both lower than the voltage VDD, and the voltage VSS2 is lower than the voltage VSS1. In addition, the serially coupled LEDs DR1 and DR2 are coupled between the first reference voltage terminal and the second reference voltage terminal, and the LED DG and LED DB are coupled between the first reference voltage terminal and the second reference voltage terminal. between the third reference voltage terminals.

在一些實施例中，當第5A圖的像素510A及第5B圖的像素510B中的發光二極體操作於發光期間而進行發光時，發光二極體的電流密度大於500毫安培/公分 ²(mA/cm ²)，以確保操作於高發光效率區間。 In some embodiments, when the light-emitting diodes in the pixel 510A of FIG. 5A and the pixel 510B of FIG. 5B operate to emit light during the light-emitting period, the current density of the light-emitting diodes is greater than 500 mA/cm ² ( mA/cm ² ) to ensure operation in the high luminous efficiency range.

在一些實施例中，像素中可包含多組子像素具有串聯耦接的發光二極體，以更佳地節省顯示電路的功率消耗。請參照第6A圖，第6A圖為根據本揭示一些實施例之像素610A的示意圖。像素610A具有與第5A圖中像素510A類似的結構，而同樣包含驅動電路120R、120G、120B來驅動對應的不同組子像素。與第5A圖中像素510A不同地，像素610A中的第三組子像素包含串聯耦接的發光二極體DB1、DB2，且驅動電路120B的第一端改為接收電壓VDD3。In some embodiments, a pixel may include multiple groups of sub-pixels having light-emitting diodes coupled in series, so as to better save power consumption of the display circuit. Please refer to FIG. 6A , which is a schematic diagram of a pixel 610A according to some embodiments of the present disclosure. The pixel 610A has a structure similar to that of the pixel 510A in FIG. 5A, and also includes driving circuits 120R, 120G, and 120B to drive corresponding different groups of sub-pixels. Different from the pixel 510A in FIG. 5A , the third group of sub-pixels in the pixel 610A includes LEDs DB1 and DB2 coupled in series, and the first terminal of the driving circuit 120B is changed to receive the voltage VDD3 .

在一實施例中，發光二極體DR1、DR2皆為紅光發光二極體且其各自之順向偏壓皆為2.5 V，發光二極體DG、DB分別為綠光發光二極體及藍光發光二極體且其順向偏壓皆為3 V，電壓VDD2為5 V，電壓VDD1為3 V，電壓VDD3為6 V，電壓VSS為0 V。換言之，針對不同組子像素提供不同的電壓，以避免額外的功率消耗。In one embodiment, the light-emitting diodes DR1 and DR2 are both red light-emitting diodes and their respective forward bias voltages are 2.5 V, and the light-emitting diodes DG and DB are green light-emitting diodes and The forward bias voltage of the blue light emitting diode is 3 V, the voltage VDD2 is 5 V, the voltage VDD1 is 3 V, the voltage VDD3 is 6 V, and the voltage VSS is 0 V. In other words, different voltages are provided for different groups of sub-pixels to avoid extra power consumption.

在一些實施例中，電壓VDD2是由顯示電路中的第一參考電壓端提供，電壓VSS是由顯示電路中的第二參考電壓端所提供，電壓VDD1是由顯示電路中的第三參考電壓端所提供，電壓VDD3是由顯示電路中的第四參考電壓端所提供，電壓VDD2、VDD1、VSS、VDD3彼此不同。In some embodiments, the voltage VDD2 is provided by the first reference voltage terminal in the display circuit, the voltage VSS is provided by the second reference voltage terminal in the display circuit, and the voltage VDD1 is provided by the third reference voltage terminal in the display circuit The voltage VDD3 is provided by the fourth reference voltage terminal in the display circuit, and the voltages VDD2, VDD1, VSS, and VDD3 are different from each other.

請參照第6B圖，第6B圖為根據本揭示一些實施例之像素610B的示意圖。像素610B具有與第5B圖中像素510B類似的結構，而同樣包含驅動電路120R、120G、120B來驅動對應的不同組子像素。與第5B圖中像素510B不同地，像素610B中的第三組子像素包含串聯耦接的發光二極體DB1、DB2，且發光二極體DB2的第二端接收電壓VSS3。Please refer to FIG. 6B , which is a schematic diagram of a pixel 610B according to some embodiments of the present disclosure. The pixel 610B has a structure similar to that of the pixel 510B in FIG. 5B, and also includes driving circuits 120R, 120G, and 120B to drive corresponding different groups of sub-pixels. Different from the pixel 510B in FIG. 5B , the third group of sub-pixels in the pixel 610B includes LEDs DB1 and DB2 coupled in series, and the second terminal of the LED DB2 receives the voltage VSS3 .

在一實施例中，發光二極體DR1、DR2皆為紅光發光二極體且其各自之順向偏壓皆為2.5 V，發光二極體DG、DB分別為綠光發光二極體及藍光發光二極體且其順向偏壓皆為3 V，電壓VDD為6 V，電壓VSS2為1 V，電壓VSS1為3 V，電壓VSS3為0 V。In one embodiment, the light-emitting diodes DR1 and DR2 are both red light-emitting diodes and their respective forward bias voltages are 2.5 V, and the light-emitting diodes DG and DB are green light-emitting diodes and The forward bias voltage of the blue light emitting diode is 3 V, the voltage VDD is 6 V, the voltage VSS2 is 1 V, the voltage VSS1 is 3 V, and the voltage VSS3 is 0 V.

在一些實施例中，電壓VDD是由顯示電路中的第一參考電壓端提供，電壓VSS2是由顯示電路中的第二參考電壓端所提供，電壓VSS1是由顯示電路中的第三參考電壓端所提供，電壓VSS3是由顯示電路中的第四參考電壓端所提供，電壓VDD、VSS2、VSS1、VSS3彼此不同。In some embodiments, the voltage VDD is provided by the first reference voltage terminal in the display circuit, the voltage VSS2 is provided by the second reference voltage terminal in the display circuit, and the voltage VSS1 is provided by the third reference voltage terminal in the display circuit The voltage VSS3 is provided by the fourth reference voltage terminal in the display circuit, and the voltages VDD, VSS2, VSS1, and VSS3 are different from each other.

在一些實施例中，第5A圖、第5B圖、第6A圖及第6B圖實施例中具有串聯耦接發光二極體的子像素可具有如第3圖或第4圖實施例之結構，將多個子晶片透過連接件串聯耦接而形成於同一個結構上，並藉由特定的層中摻雜來避免產生漏電流，以確保功率效率。In some embodiments, the sub-pixels with series-coupled light-emitting diodes in the embodiment of FIG. 5A, FIG. 5B, FIG. 6A and FIG. 6B may have the structure as the embodiment of FIG. 3 or FIG. 4, A plurality of subchips are connected in series through connectors to form on the same structure, and doping in specific layers avoids leakage current to ensure power efficiency.

綜上所述，第5A圖、第5B圖、第6A圖及第6B圖之實施例透過提供多組電壓來針對不同子像素提供不同大小的電壓，以進一步降低如第1圖顯示電路之功率消耗。To sum up, the embodiments in Fig. 5A, Fig. 5B, Fig. 6A and Fig. 6B provide voltages of different magnitudes for different sub-pixels by providing multiple sets of voltages to further reduce the power of the display circuit shown in Fig. 1 consume.

雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本發明。任何熟習此技藝之人，在不脫離本揭示內容之精神及範圍內，當可作各種更動及潤飾。本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。Although the present disclosure has been disclosed above in terms of implementation, it is not intended to limit the present invention. Any person skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of this disclosure. The scope of protection of the content of this disclosure should be defined by the scope of the appended patent application.

100:顯示裝置 110:像素 120R,120G,120B:驅動電路 DR1,DR2,DG,DB:發光二極體 VDD:電壓 VSS:電壓 T1:電晶體 N1:節點 D1:發光二極體 I1:電流 I2:電流 D2:發光二極體 300:半導體裝置 310:子晶片 312:第一擴散層 314:主動層 316:第二擴散層 320:子晶片 322:第一擴散層 324:主動層 326:第二擴散層 330:緩衝層 340:電極 350:電極 I31,I32,I33:電流 INS:隔離層 CON:連接件 400:半導體裝置 410:子晶片 412:第一擴散層 414:主動層 416:第二擴散層 420:子晶片 422:第一擴散層 424:主動層 426:第二擴散層 430:緩衝層 440:電極 450:電極 I41,I42,I43:電流 510A:像素 VDD2:電壓 VDD1:電壓 510B:像素 VSS1:電壓 VSS2:電壓 610A:像素 VDD3:電壓 610B:像素 VSS3:電壓 DB2:發光二極體 100: display device 110: pixels 120R, 120G, 120B: drive circuit DR1, DR2, DG, DB: LEDs VDD: Voltage VSS: Voltage T1: Transistor N1: node D1: light emitting diode I1: current I2: Current D2: light emitting diode 300: Semiconductor device 310: sub chip 312: first diffusion layer 314: active layer 316: second diffusion layer 320: sub chip 322: first diffusion layer 324: active layer 326: second diffusion layer 330: buffer layer 340: electrode 350: electrode I31, I32, I33: current INS: isolation layer CON: connector 400: Semiconductor device 410: sub chip 412: first diffusion layer 414: active layer 416: second diffusion layer 420: sub chip 422: The first diffusion layer 424: active layer 426: second diffusion layer 430: buffer layer 440: electrode 450: electrode I41, I42, I43: Current 510A: pixel VDD2: Voltage VDD1: Voltage 510B: pixel VSS1: Voltage VSS2: Voltage 610A: Pixel VDD3: Voltage 610B: pixel VSS3: Voltage DB2: light emitting diode

第1圖為根據本揭示一些實施例之顯示裝置的局部示意圖。第2A圖為根據本案一些實施例之子像素顯示電路的電路示意圖。第2B圖為根據本案一些實施例之子像素顯示電路的電路示意圖。第3圖為根據本揭示一些實施例之半導體裝置的截面圖。第4圖為根據本揭示一些實施例之半導體裝置的截面圖。第5A圖為根據本揭示一些實施例之像素的示意圖。第5B圖為根據本揭示一些實施例之像素的示意圖。第6A圖為根據本揭示一些實施例之像素的示意圖。第6B圖為根據本揭示一些實施例之像素的示意圖。 FIG. 1 is a partial schematic diagram of a display device according to some embodiments of the present disclosure. FIG. 2A is a schematic circuit diagram of a sub-pixel display circuit according to some embodiments of the present invention. FIG. 2B is a schematic circuit diagram of a sub-pixel display circuit according to some embodiments of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5A is a schematic diagram of a pixel according to some embodiments of the present disclosure. FIG. 5B is a schematic diagram of a pixel according to some embodiments of the present disclosure. FIG. 6A is a schematic diagram of a pixel according to some embodiments of the present disclosure. FIG. 6B is a schematic diagram of a pixel according to some embodiments of the present disclosure.

100:顯示裝置 100: display device

110:像素 110: pixels

120R,120G,120B:驅動電路 120R, 120G, 120B: drive circuit

DR1,DR2,DG,DB:發光二極體 DR1, DR2, DG, DB: LEDs

VDD:電壓 VDD: Voltage

VSS:電壓 VSS: voltage

Claims

一種半導體裝置，包含：一緩衝層；一第一子晶片及一第二子晶片，分開設置於該緩衝層上，該第一子晶片及該第二子晶片中的每一者皆包含：一第一擴散層；一主動層；以及一第二擴散層；其中，該第一擴散層、該主動層及該第二擴散層由上而下依序設置於該緩衝層上，該第一擴散層及該緩衝層為一第一類型磊晶層，該第二擴散層為一第二類型磊晶層；以及一連接件，用以將該第一子晶片的該第二擴散層電性耦接至該第二子晶片的該第一擴散層。 A semiconductor device comprising: a buffer layer; a first sub-chip and a second sub-chip separately disposed on the buffer layer, each of the first sub-chip and the second sub-chip includes: a a first diffusion layer; an active layer; and a second diffusion layer; wherein, the first diffusion layer, the active layer and the second diffusion layer are sequentially arranged on the buffer layer from top to bottom, and the first diffusion layer and the buffer layer are a first type epitaxial layer, the second diffusion layer is a second type epitaxial layer; connected to the first diffusion layer of the second sub-wafer.

如請求項1所述之半導體裝置，更包含：一第一電極，設置於該第一子晶片的該第一擴散層上且用以接收一第一參考電壓；以及一第二電極，用以將該第二子晶片的該第二擴散層與該緩衝層耦接，並接收一第二參考電壓。 The semiconductor device as claimed in claim 1, further comprising: a first electrode disposed on the first diffusion layer of the first sub-chip and used to receive a first reference voltage; and a second electrode used to The second diffusion layer of the second sub-chip is coupled to the buffer layer and receives a second reference voltage.

如請求項2所述之半導體裝置，其中：該第二電極延伸設置至該第二子晶片的該第一擴散層上，而與設置於該第一子晶片上的該第一電極具有實質上相同的高度。 The semiconductor device as claimed in claim 2, wherein: the second electrode is extended to the first diffusion layer of the second sub-wafer, and has substantially the same distance with the first electrode disposed on the first sub-wafer. same the height of.

如請求項2所述之半導體裝置，其中：該第一類型磊晶層為P型磊晶層，該第二類型磊晶層為N型磊晶層，該第一參考電壓大於該第二參考電壓；或者該第一類型磊晶層為N型磊晶層，該第二類型磊晶層為P型磊晶層，該第二參考電壓大於該第一參考電壓。 The semiconductor device according to claim 2, wherein: the first type epitaxial layer is a P-type epitaxial layer, the second type epitaxial layer is an N-type epitaxial layer, and the first reference voltage is greater than the second reference voltage; or the first type epitaxial layer is an N-type epitaxial layer, the second type epitaxial layer is a P-type epitaxial layer, and the second reference voltage is greater than the first reference voltage.

如請求項1所述之半導體裝置，其中：該第一子晶片及該第二子晶片之間的間隔大於或等於約1微米，且該第一子晶片及該第二子晶片中每一者的長度皆小於或等於約100微米。 The semiconductor device as claimed in claim 1, wherein: the interval between the first sub-chip and the second sub-chip is greater than or equal to about 1 micron, and each of the first sub-chip and the second sub-chip Each has a length less than or equal to about 100 microns.

一種顯示裝置，包含：多個像素，該等像素中每一者包含複數組子像素，該複數組子像素中的一第一組子像素包含：至少兩個第一發光元件，該至少兩個第一發光元件彼此串聯耦接；一第一參考電壓端，用以提供一第一參考電壓至該等像素；一第二參考電壓端，用以提供一第二參考電壓至該等像素；以及一第三參考電壓端，用以提供一第三參考電壓至該等像素；其中，該第一參考電壓、該第二參考電壓及該第三參考電壓三者彼此不同；其中，該第一組子像素中彼此串聯耦接的該等第一發光元件耦接於該第一參考電壓端及該第二參考電壓端之間，該複數組子像素中的一第二組子像素耦接該第三參考電壓端。 A display device, comprising: a plurality of pixels, each of which includes a plurality of sub-pixels, a first group of sub-pixels in the plurality of sub-pixels includes: at least two first light-emitting elements, the at least two The first light-emitting elements are coupled in series; a first reference voltage terminal is used to provide a first reference voltage to the pixels; a second reference voltage terminal is used to provide a second reference voltage to the pixels; and a third reference voltage terminal for providing a third reference voltage to the pixels; Wherein, the first reference voltage, the second reference voltage and the third reference voltage are different from each other; wherein, the first light-emitting elements connected in series in the first group of sub-pixels are coupled to the first Between the reference voltage terminal and the second reference voltage terminal, a second group of sub-pixels in the plurality of groups of sub-pixels is coupled to the third reference voltage terminal.

如請求項6所述之顯示裝置，其中：該第一參考電壓及該第三參考電壓皆大於該第二參考電壓；或者該第二參考電壓及該第三參考電壓皆小於該第一參考電壓。 The display device as described in Claim 6, wherein: both the first reference voltage and the third reference voltage are greater than the second reference voltage; or both the second reference voltage and the third reference voltage are lower than the first reference voltage .

如請求項6所述之顯示裝置，其中：當該等發光元件操作於一發光期間時，該等發光元件的電流密度大於500毫安培/公分²(mA/cm²)。 ^The display device according to claim 6, wherein: when the light-emitting elements operate in a light-emitting period, the current density of the light-emitting elements is greater than 500 mA/cm ² .

如請求項6所述之顯示裝置，更包含：一第四參考電壓端，用以提供一第四參考電壓至該等像素，該第四參考電壓不同於該第一參考電壓、該第二參考電壓及該第三參考電壓；其中，該複數組子像素中的一第三組子像素包含：兩個第二發光元件，該等第二發光元件彼此串聯耦接；其中，該第三組子像素耦接該第四參考電壓端。 The display device as described in Claim 6, further comprising: a fourth reference voltage terminal for providing a fourth reference voltage to the pixels, the fourth reference voltage being different from the first reference voltage, the second reference voltage voltage and the third reference voltage; wherein, a third group of sub-pixels in the plurality of groups of sub-pixels includes: two second light-emitting elements, and the second light-emitting elements are coupled in series; Wherein, the third group of sub-pixels is coupled to the fourth reference voltage terminal.

如請求項6所述之顯示裝置，其中：彼此串聯耦接的該等第一發光元件包含：一緩衝層；一第一子晶片及一第二子晶片，分開設置於該緩衝層上，該第一子晶片及該第二子晶片中的每一者皆包含：一第一擴散層；一主動層；以及一第二擴散層；其中，該第一擴散層、該主動層及該第二擴散層由上而下依序設置於該緩衝層上，該第一擴散層及該緩衝層為一第一類型磊晶層，該第二擴散層為一第二類型磊晶層；以及一連接件，用以將該第一子晶片的該第二擴散層電性耦接至該第二子晶片的該第一擴散層。 The display device as described in claim 6, wherein: the first light-emitting elements coupled in series with each other include: a buffer layer; a first sub-chip and a second sub-chip are separately arranged on the buffer layer, the Each of the first sub-chip and the second sub-chip includes: a first diffusion layer; an active layer; and a second diffusion layer; wherein, the first diffusion layer, the active layer and the second Diffusion layers are sequentially arranged on the buffer layer from top to bottom, the first diffusion layer and the buffer layer are a first type epitaxial layer, the second diffusion layer is a second type epitaxial layer; and a connection A component for electrically coupling the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip.