TWI802705B - 半導體裝置之製造方法 - Google Patents
半導體裝置之製造方法 Download PDFInfo
- Publication number
- TWI802705B TWI802705B TW108119284A TW108119284A TWI802705B TW I802705 B TWI802705 B TW I802705B TW 108119284 A TW108119284 A TW 108119284A TW 108119284 A TW108119284 A TW 108119284A TW I802705 B TWI802705 B TW I802705B
- Authority
- TW
- Taiwan
- Prior art keywords
- photoresist
- opening
- forming
- semiconductor device
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 122
- 230000004888 barrier function Effects 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000003848 UV Light-Curing Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 107
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 239000010936 titanium Substances 0.000 description 7
- 238000001723 curing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000008961 swelling Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000002815 nickel Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 150000003481 tantalum Chemical class 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
本發明係關於一種半導體裝置之製造方法,其包括:在半導體基板上形成包括Al之歐姆電極;形成覆蓋該歐姆電極之SiN膜;在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案;對該第一光阻劑進行紫外線固化;在經由該開口圖案露出之該SiN膜中形成開口並使該歐姆電極之表面在該開口內露出;在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層;在該開口圖案內形成第二光阻劑;對該第二光阻劑進行熱處理並利用該第二光阻劑將與該開口重疊之該障壁金屬層覆蓋;及使用該第二光阻劑對該障壁金屬層進行蝕刻。
Description
本發明係關於一種半導體裝置之製造方法。
自導電性及類似性質之觀點出發,半導體裝置之配線及歐姆電極有時使用鋁(Al)。例如,日本未審查專利公開案第H4-162531號揭示如下組態:將由具有Al膜或以Al為主成分之合金膜構成之第一層設置於半導體基板中之擴散層的表面上。
包括Al之配線及歐姆電極傾向於在製造半導體裝置時產生小凸起。例如,在包括Al之歐姆電極上的障壁金屬膜與覆蓋該膜之絕緣膜之間產生間隙時,在該間隙可能產生上述小凸起。此類小凸起之產生可能造成配線或電極之短路,此並非所期望的。
根據本發明之一態樣,提供一種半導體裝置之製造方法,其包括:在半導體基板上形成包括Al之歐姆電極;形成覆蓋該歐姆電極之SiN膜;在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案;對該第一光阻劑進行紫外線固化;在經由該開口圖案露出之該SiN膜中形成開口並使該歐姆電極之表面在該開口內露出;在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層;在該開口圖案內形成第二光阻劑;對該第二光阻劑進行熱處理並利用該第二光阻劑將與該開口重疊之該障壁金屬層覆蓋;及使用該第二光阻劑對該障壁金屬層進行蝕刻。
根據本發明之另一態樣,提供一種半導體裝置之製造方法,其包括:在半導體基板上形成半導體堆疊;在該半導體堆疊上形成包括Al之歐姆電極;形成覆蓋該歐姆電極之SiN膜;在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案;以第一溫度對該第一光阻劑進行第一熱處理;對該第一光阻劑進行紫外線固化;在該SiN膜中形成開口,以使得在該開口內部露出該歐姆電極之表面,該開口與該開口圖案重疊;在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層;在該開口圖案內形成第二光阻劑;以第二溫度對該第二光阻劑進行第二熱處理,以利用該第二光阻劑將該障壁金屬層中之一部分覆蓋,該障壁金屬層中之該部分與該開口重疊;以及使用該第二光阻劑對該障壁金屬層進行蝕刻,其中該第二溫度高於該第一溫度。
[本發明之實施例之說明]
首先,將列舉及描述本發明之實施例之細節。
本發明之實施例係一種半導體裝置之製造方法,其包括:在半導體基板上形成包括Al之歐姆電極;形成覆蓋該歐姆電極之SiN膜;在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案;對該第一光阻劑進行紫外線固化;在經由該開口圖案露出之該SiN膜中形成開口並使該歐姆電極之表面在該開口內露出;在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層;在該開口圖案內形成第二光阻劑;對該第二光阻劑進行熱處理並利用該第二光阻劑將與該開口重疊之該障壁金屬層覆蓋;及使用該第二光阻劑對該障壁金屬層進行蝕刻。
該製造方法可以在對第一光阻劑進行紫外線固化之前進一步包括對第一光阻劑進行熱處理。
障壁金屬層可以包括依次層疊之Ti層、TiWN層及TiW層。
SiN膜之厚度可以在30 nm至50 nm之範圍內。
第二光阻劑可以為紫外線抗蝕劑。對於第二光阻劑之熱處理可以在140℃或更高溫度下執行。
[本發明之詳細實施例]
以下,參照附圖,描述根據本發明之實施例之半導體裝置之製造方法的具體實例。本發明沒有限定為此等實例。本發明由申請專利範圍表明,且意圖包括與申請專利範圍等同之意思及範疇內之全部變更。在以下描述中,在附圖之描述中,對於同一要素,應用同一元件符號,且省略重複的描述。
圖1係示出利用根據實施例之製造方法製造之半導體裝置之剖視圖。如圖1所示,半導體裝置1例如係設置在基板2上之場效電晶體。基板2係晶體生長用之基板。基板2之實例包括諸如SiC基板及GaN基板之半導體基板、或者藍寶石(Al2
O3
)基板。在本實施例中,基板2係半導體基板。
半導體裝置1包括半導體堆疊11、絕緣膜12及21、源電極13、汲電極14、閘電極15及導電障壁層16及17。
半導體堆疊11係在基板2上進行磊晶生長之半導體層之層疊物。半導體堆疊11例如自基板2之表面依次包括緩衝層、通道層及障壁層。本實施例之半導體裝置1係高電子遷移率電晶體(HEMT)。藉由在通道層與障壁層之間的邊界表面之通道層側上產生二維電子氣體(2D EG),從而在通道層內形成通道區域。緩衝層為例如AlN層。通道層為例如GaN層。障壁層為例如AlGaN層。半導體堆疊11可以具有位於障壁層上之頂蓋層。頂蓋層為例如GaN層。
絕緣膜21係對半導體堆疊11之表面進行保護之鈍化膜,且設置在半導體堆疊11上。絕緣膜12係對源電極13、汲電極14及閘電極15進行保護之保護膜。在絕緣膜12中設有開口12a及12b。開口12a使源電極13之一部分露出,而開口12b使汲電極14之一部分露出。而且,在絕緣膜21中之與閘電極15對應之部位設有開口21a。閘電極15經由此開口21a與半導體堆疊11接觸。絕緣膜21係利用低壓CVD法形成之氮化矽(SiN)膜,而絕緣膜12係利用電漿CVD法形成之SiN膜。
源電極13及汲電極14各自與半導體堆疊11之障壁層接觸。源電極13及汲電極14係包括鋁(Al)之歐姆電極。源電極13及汲電極14係例如藉由將鉭(Ta)層、Al層及Ta層之分層結構在介於500℃至800℃範圍內之溫度下合金化來實現的。而且,可以使用鈦(Ti)層代替Ta層。此外,可以在上述分層結構上形成金(Au)層。源電極13及汲電極14之表面之一部分由絕緣膜12覆蓋。
閘電極15設置在源電極13與汲電極14之間。閘電極15例如包括與半導體堆疊11之頂蓋層進行肖特基接觸(Schottky-contact)之金屬,且例如具有鎳(Ni)層與金(Au)層之分層結構。在此情況下,Ni層與頂蓋層進行肖特基接觸。
導電障壁層16係保護源電極13之導電層,且設置於開口12a內。導電障壁層16具有例如彼此疊加之Ti層、TiWN層及TiW層。而且,導電障壁層17係保護汲電極14之導電層,且設置在開口12b內。導電障壁層16及17之配置彼此相同。
接下來,參照圖2A至圖5C,描述根據本實施例之半導體裝置之一部分之製造方法。圖2A至圖2C、圖3A至圖3C、圖4A、圖4B及圖5A至圖5C係說明根據本實施例之半導體裝置1之一部分之製造方法的圖。以下,詳細說明半導體裝置1中包括之作為歐姆電極之源電極13及設置在源電極13上之導電障壁層16的製造方法。
首先,如圖2A所示,在基板2上形成絕緣膜21。首先,利用金屬有機化學氣相沈積(MOCVD)在基板2上生長出半導體堆疊11。接下來,在半導體堆疊11上形成絕緣膜21。絕緣膜21係例如藉由低壓化學氣相沈積(LPCVD)法形成之SiN膜。LPCVD法係藉由降低沈積壓力並提高沈積溫度而形成緻密膜之方法。絕緣膜21之厚度例如在10 nm至30 nm範圍內。絕緣膜21之沈積溫度例如在800℃至900℃範圍內,且其沈積壓力例如在10 Pa至100 Pa範圍內。
接下來,如圖2B所示,在基板2上形成作為包括Al之歐姆電極之源電極13。首先,在絕緣膜21中形成開口21b。接下來,將具有依次層疊之Ta層、Al層及Ta層之源極金屬沈積在開口21b內。下側上之Ta層之厚度例如在5 nm至10 nm範圍內。Al層之厚度例如在200 nm至400 nm範圍內。上側上之Ta層之厚度例如在5 nm至10 nm範圍內。接下來,藉由將源極金屬加熱至在500℃至800℃範圍內的溫度來對源極金屬進行合金化,接著形成源電極13。在源電極13形成時也形成汲電極14(參照圖1)(未示出)。源極金屬使用例如抗蝕圖案(未示出),經由蒸鍍法及提離而形成。此抗蝕圖案也可以用於開口21b之形成。
接下來,如圖2C所示,形成將絕緣膜21及源電極13覆蓋之絕緣膜12。在本實施例中,絕緣膜12係藉由電漿CVD法形成之SiN膜。絕緣膜12之成膜溫度例如在300℃至320℃範圍內。絕緣膜12之厚度例如在30 nm至50 nm範圍內。
接下來,如圖3A所示,在絕緣膜12上形成具有與源電極13重疊之開口圖案31a之第一光阻劑31。首先,用第一光阻劑31塗佈絕緣膜12。接下來,對於第一光阻劑31執行光刻,接著在第一光阻劑31中形成開口圖案31a。開口圖案31a在第一光阻劑31中設置於與源電極13重疊之位置。絕緣膜12之一部分在開口圖案31a內露出。第一光阻劑31係例如紫外線抗蝕劑。第一光阻劑31之厚度例如在1 μm至2 μm範圍內。
接下來,對第一光阻劑31進行熱處理。例如以120℃或更高溫度將第一光阻劑31加熱(烘烤)。第一光阻劑31之流動性由於此烘烤而上升。由此,如圖3B所示,形成開口圖案31a之第一光阻劑31之端部變鈍。由於第一光阻劑31之表面張力,第一光阻劑31之向源電極13之上部流動受到妨礙。接下來,對第一光阻劑31進行紫外線固化。在此步驟中,對第一光阻劑31照射紫外線U。由此,第一光阻劑31固化,因此在第一光阻劑31中不太可能發生膨脹或類似問題。而且,開口圖案31a之形狀變化也不太可能發生。紫外線U係例如波長約365 nm之由汞燈得到之紫外線。
接下來,使用含氟氣體對於絕緣膜12之自第一光阻劑31露出之部分進行乾蝕刻。由此,如圖3C所示,源電極13之表面之一部分在開口12a內露出。具體而言,源電極13之頂面13a之與開口12a重疊之部分露出。乾蝕刻係例如反應性離子蝕刻(RIE)。作為含氟氣體,例如,至少一種係選自由SF6
、CF4
、CHF3
、C3
F6
及C2
F6
組成之群。可以採用電感耦合電漿(ICP)型RIE。
接下來,如圖4A所示,在第一光阻劑31上及經由絕緣膜12之開口12a露出之源電極13上形成障壁金屬層41。例如藉由濺射法,形成具有依次層疊之Ti層、TiWN層及TiW層之障壁金屬層41。障壁金屬層41之一部分在開口12a內與源電極13接觸。Ti層之厚度例如為5 nm。TiWN層之厚度例如為300 nm。TiW層之厚度例如為6 nm。障壁金屬層41沈積於平面時之厚度近似等於上述各層的厚度之和。然而,例如在障壁金屬層41中,在第一光阻劑31之側壁或絕緣膜12之開口12a的側壁中沈積之部分的厚度比上述厚度薄。在本實施例中,在障壁金屬層41中,位於第一光阻劑31之側壁上之部位之厚度為100 nm或更小。
接下來,如圖4B所示,在第一光阻劑31之開口圖案31a內形成第二光阻劑51。在障壁金屬層41之與開口12a重疊之部分41a上形成第二光阻劑51。如圖4B所示,障壁金屬層41中位於源電極13上之部分41a之一部分可以自第二光阻劑51露出。與第一光阻劑31類似,第二光阻劑51例如係紫外線抗蝕劑。第二光阻劑51之厚度例如在1 μm至2 μm範圍內。
接下來,如圖5A所示,對第二光阻劑51進行熱處理,且利用第二光阻劑51將與絕緣膜12之開口12a重疊之障壁金屬層41覆蓋。例如將第二光阻劑51加熱至140℃或更高溫度(在該溫度下烘烤)。自利用第二光阻劑51覆蓋障壁金屬層41中之與源電極13重疊之部分41a之觀點來看,烘烤溫度亦可以比第一光阻劑31之烘烤溫度高。由此,第二光阻劑51流動,且障壁金屬層41之部分41a由第二光阻劑51覆蓋。另一方面,第一光阻劑31不流動或基本上不流動。此外,第一光阻劑31中不太可能發生或基本上不發生膨脹或類似問題。此係因為,第一光阻劑31已經過烘烤,且利用紫外線U固化。
接下來,如圖5B所示,使用第二光阻劑51對障壁金屬層41進行蝕刻。使用含氟氣體對於障壁金屬層41之自第二光阻劑51露出之部分進行乾蝕刻。由此,形成將源電極13之頂面13a覆蓋並將經由絕緣膜12之開口12a露出之源電極13覆蓋的導電障壁層16。在此情況下,除去源電極13上障壁金屬層41之部分41a中的一部分,該部分位於第二光阻劑51之端部與絕緣膜12的開口12a的緣部之間,且由此露出源電極13之表面的一部分。該露出的表面具有與障壁金屬層41之厚度近似相等之寬度。由於障壁金屬層41中位於第一光阻劑31之側壁部分之一部分之厚度為100 nm或更小,因此其中此源電極13露出之間隙之寬度限於100 nm或更小。
接下來,如圖5C所示,將第一光阻劑31及第二光阻劑51除去。在障壁金屬層41之一部分殘存於第一光阻劑31上時,將該部分經由提離而能夠與第一光阻劑31一起除去。藉由執行上述步驟,形成源電極13及導電障壁層16。
經由以上步驟,形成本實施例之半導體裝置1。在形成半導體裝置1之後,可以形成用於覆蓋半導體裝置1之層間絕緣膜,可以形成將該層間絕緣膜貫通並使導電障壁層露出之通孔,且可以形成埋入至該通孔中之Au配線層。
根據以上描述之本實施例之半導體裝置1之製造方法,藉由執行上述步驟,利用流動之第二光阻劑51能夠將障壁金屬層41中之與開口12a重疊之部分41a覆蓋。接著,當將自第二光阻劑51露出之障壁金屬層41除去時,不僅能夠將作為包括Al之歐姆電極之源電極13的頂面13a覆蓋,而且能夠將絕緣膜12與導電障壁層16之間的間隙最小化至極小之寬度內。由此,即使當在半導體裝置1之製造方法期間在之後執行熱處理時,或者,當由於形成將半導體裝置1覆蓋之層間絕緣膜而對於源電極13產生應力時,亦能夠防止以源電極13中包括之Al為起因之小凸起的產生。
通常,當對於由金屬層覆蓋之光阻劑執行烘烤時,光阻劑膨脹而刺穿金屬層。然而,在本實施例中,首先將第一光阻劑31烘烤且利用紫外線U固化,隨後使第二光阻劑51經歷第二烘烤。因此,在第二烘烤期間,第一光阻劑31中不發生或基本上不發生膨脹。此適用於第二烘烤溫度比第一烘烤溫度高之情況。
根據本實施例之半導體裝置1之製造方法在對第一光阻劑31執行紫外線固化之前包括對第一光阻劑31進行熱處理之步驟。在此情況下,第一光阻劑31之角被修圓,因此,在如圖4A所示形成障壁金屬層41時,能夠將第一光阻劑31及絕緣膜12之側表面可靠地覆蓋。在未覆蓋側表面之狀態下進行如圖5A所示之障壁金屬層41之蝕刻時,使經由其露出源電極13之表面的間隙之寬度擴大。
在本實施例中,障壁金屬層41具有彼此疊加之Ti層、TiWN層及TiW層。在此情況下,導電障壁層16及17展現出有利的障壁效能。
根據本發明之半導體裝置之製造方法並不侷限於上述之實施例,且可對其進行各種改變。例如,實施例已關於其中本發明應用於HEMT之實例描述。但是,本發明之製造方法能夠應用於除HEMT以外的各種場效電晶體。相關申請案的交叉參考
本申請案主張2018年6月7月申請之日本申請案第JP2018-109653號之優先權,該申請案的全部內容以引用的方式併入本文中。
1‧‧‧半導體裝置
2‧‧‧基板
11‧‧‧半導體堆疊
12‧‧‧絕緣膜
12a‧‧‧開口
12b‧‧‧開口
13‧‧‧源電極
13a‧‧‧頂面
14‧‧‧汲電極
15‧‧‧閘電極
16‧‧‧導電障壁層
17‧‧‧導電障壁層
21‧‧‧絕緣膜
21a‧‧‧開口
21b‧‧‧開口
31‧‧‧第一光阻劑
31a‧‧‧開口圖案
41‧‧‧障壁金屬層
41a‧‧‧部分
51‧‧‧第二光阻劑
U‧‧‧紫外線
自以下參照附圖對本發明較佳實施例的詳細描述中,將更好地理解前述及其他目的、態樣及優點,在該等附圖中:
圖1係示出利用根據實施例之製造方法製造之半導體裝置之一實例的剖視圖;
圖2A至圖2C係說明根據實施例之半導體裝置之一部分之製造方法的圖;
圖3A至圖3C係說明根據實施例之半導體裝置之一部分之製造方法的圖;
圖4A及圖4B係說明根據實施例之半導體裝置之一部分之製造方法的圖;以及
圖5A至圖5C係說明根據實施例之半導體裝置之一部分之製造方法的圖。
2‧‧‧基板
11‧‧‧半導體堆疊
12‧‧‧絕緣膜
12a‧‧‧開口
13‧‧‧源電極
13a‧‧‧頂面
21‧‧‧絕緣膜
31‧‧‧第一光阻劑
31a‧‧‧開口圖案
41‧‧‧障壁金屬層
41a‧‧‧部分
51‧‧‧第二光阻劑
Claims (17)
- 一種半導體裝置之製造方法,其包含: 在半導體基板上形成包括Al之歐姆電極; 形成覆蓋該歐姆電極之SiN膜; 在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案; 對該第一光阻劑進行紫外線固化; 在經由該開口圖案露出之該SiN膜中形成開口並使該歐姆電極之表面在該開口內露出; 在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層; 在該開口圖案內形成第二光阻劑; 對該第二光阻劑進行熱處理並利用該第二光阻劑將與該開口重疊之該障壁金屬層覆蓋;及 使用該第二光阻劑對該障壁金屬層進行蝕刻。
- 如請求項1之半導體裝置之製造方法,其進一步包含: 在對該第一光阻劑進行紫外線固化之前對該第一光阻劑進行熱處理。
- 如請求項1之半導體裝置之製造方法, 其中該障壁金屬層包括依次層疊之Ti層、TiWN層及TiW層。
- 如請求項1之半導體裝置之製造方法, 其中該SiN膜之厚度在30 nm至50 nm之範圍內。
- 如請求項1之半導體裝置之製造方法, 其中該第二光阻劑為紫外線抗蝕劑,且 其中對於該第二光阻劑之該熱處理係在140℃或更高溫度下執行。
- 如請求項1之半導體裝置之製造方法,其進一步包含: 在該形成該歐姆電極之前在該半導體基板上形成半導體堆疊, 其中該歐姆電極與該半導體堆疊接觸。
- 如請求項6之半導體裝置之製造方法,其進一步包含: 在該形成該歐姆電極之前在該半導體堆疊上形成絕緣膜,該絕緣膜具有第二開口, 其中該歐姆電極係位於該第二開口之中。
- 如請求項7之半導體裝置之製造方法, 其中藉由低壓化學氣相沈積法來形成該絕緣膜。
- 如請求項1之半導體裝置之製造方法, 其中在該對該障壁金屬層進行蝕刻之後,形成在該開口之緣部與該第二光阻劑之端部之間的間隙,以及 其中該間隙之寬度係100 nm或更小。
- 一種半導體裝置之製造方法,其包含: 在半導體基板上形成半導體堆疊; 在該半導體堆疊上形成包括Al之歐姆電極; 形成覆蓋該歐姆電極之SiN膜; 在該SiN膜上形成第一光阻劑,該第一光阻劑具有與該歐姆電極重疊之開口圖案; 於第一溫度下對該第一光阻劑進行第一熱處理; 對該第一光阻劑進行紫外線固化; 在該SiN膜中形成開口,以使得在該開口內部露出該歐姆電極之表面,該開口與該開口圖案重疊; 在該第一光阻劑上及經由該開口露出之該歐姆電極上形成障壁金屬層; 在該開口圖案內形成第二光阻劑; 於第二溫度下對該第二光阻劑進行第二熱處理,以利用該第二光阻劑將該障壁金屬層中之一部分覆蓋,該障壁金屬層中之該部分與該開口重疊;以及 使用該第二光阻劑對該障壁金屬層進行蝕刻, 其中該第二溫度高於該第一溫度。
- 如請求項10之半導體裝置之製造方法, 其中在該對該第一光阻劑進行紫外線固化之後,進行該第一熱處理之執行。
- 如請求項10之半導體裝置之製造方法, 其中該障壁金屬層包括依次層疊之Ti層、TiWN層以及TiW層。
- 如請求項10之半導體裝置之製造方法, 其中該SiN膜之厚度係在30 nm至50 nm之範圍內。
- 如請求項10之半導體裝置之製造方法, 其中該第二光阻劑係紫外線抗蝕劑,且 其中該第二溫度係140℃或更高。
- 如請求項10之半導體裝置之製造方法,其進一步包含: 在該半導體堆疊上形成絕緣膜,該絕緣膜具有第二開口, 其中該歐姆電極係位於該第二開口之中。
- 如請求項15之半導體裝置之製造方法, 其中藉由低壓化學氣相沈積法來形成該絕緣膜。
- 如請求項10之半導體裝置之製造方法, 其中在該對該障壁金屬層進行蝕刻之後,形成在該開口之緣部與該第二光阻劑之端部之間的間隙,以及 其中該間隙之寬度係100 nm或更小。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018-109653 | 2018-06-07 | ||
JP2018109653A JP7019922B2 (ja) | 2018-06-07 | 2018-06-07 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202002023A TW202002023A (zh) | 2020-01-01 |
TWI802705B true TWI802705B (zh) | 2023-05-21 |
Family
ID=68763770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108119284A TWI802705B (zh) | 2018-06-07 | 2019-06-04 | 半導體裝置之製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US11011370B2 (zh) |
JP (1) | JP7019922B2 (zh) |
CN (1) | CN113506825A (zh) |
TW (1) | TWI802705B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7019922B2 (ja) * | 2018-06-07 | 2022-02-16 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW486740B (en) * | 2001-01-03 | 2002-05-11 | United Microelectronics Corp | Improved method for controlling critical dimension during high temperature photoresist reflow process by ultraviolet light irradiation |
US6699738B2 (en) * | 2001-11-15 | 2004-03-02 | Lg. Phillips Lcd Co., Ltd. | Semiconductor doping method and liquid crystal display device fabricating method using the same |
US6916720B2 (en) * | 1999-11-10 | 2005-07-12 | Hughes Electronics Corporation | Thin film devices and method for fabricating thin film devices |
US9640429B2 (en) * | 2012-10-29 | 2017-05-02 | Sumitomo Electric Device Innovations, Inc. | Method of fabricating semiconductor device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162531A (ja) | 1990-10-25 | 1992-06-08 | Iwatsu Electric Co Ltd | 半導体装置の製造方法 |
JP3516653B2 (ja) | 2000-12-15 | 2004-04-05 | シャープ株式会社 | 半導体装置の製造方法 |
JP4179769B2 (ja) * | 2001-10-12 | 2008-11-12 | シャープ株式会社 | 半導体装置の製造方法 |
US8907350B2 (en) * | 2010-04-28 | 2014-12-09 | Cree, Inc. | Semiconductor devices having improved adhesion and methods of fabricating the same |
JP5730511B2 (ja) * | 2010-07-29 | 2015-06-10 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
JP6052977B2 (ja) | 2012-10-29 | 2016-12-27 | 住友電工デバイス・イノベーション株式会社 | 半導体装置およびその製造方法 |
US9136234B2 (en) * | 2013-07-09 | 2015-09-15 | Globalfoundries Inc. | Semiconductor device with improved metal pillar configuration |
JP6420721B2 (ja) | 2014-07-09 | 2018-11-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6997002B2 (ja) * | 2018-02-19 | 2022-01-17 | 住友電気工業株式会社 | 半導体装置及びその製造方法 |
JP7019922B2 (ja) * | 2018-06-07 | 2022-02-16 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
-
2018
- 2018-06-07 JP JP2018109653A patent/JP7019922B2/ja active Active
-
2019
- 2019-06-04 TW TW108119284A patent/TWI802705B/zh active
- 2019-06-05 CN CN202110631068.XA patent/CN113506825A/zh active Pending
- 2019-06-06 US US16/433,883 patent/US11011370B2/en active Active
-
2021
- 2021-01-21 US US17/154,416 patent/US11476110B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6916720B2 (en) * | 1999-11-10 | 2005-07-12 | Hughes Electronics Corporation | Thin film devices and method for fabricating thin film devices |
TW486740B (en) * | 2001-01-03 | 2002-05-11 | United Microelectronics Corp | Improved method for controlling critical dimension during high temperature photoresist reflow process by ultraviolet light irradiation |
US6699738B2 (en) * | 2001-11-15 | 2004-03-02 | Lg. Phillips Lcd Co., Ltd. | Semiconductor doping method and liquid crystal display device fabricating method using the same |
US9640429B2 (en) * | 2012-10-29 | 2017-05-02 | Sumitomo Electric Device Innovations, Inc. | Method of fabricating semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2019212840A (ja) | 2019-12-12 |
US20190378708A1 (en) | 2019-12-12 |
TW202002023A (zh) | 2020-01-01 |
JP7019922B2 (ja) | 2022-02-16 |
CN110581064A (zh) | 2019-12-17 |
US11011370B2 (en) | 2021-05-18 |
US11476110B2 (en) | 2022-10-18 |
US20210143002A1 (en) | 2021-05-13 |
CN113506825A (zh) | 2021-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI608568B (zh) | 半導體元件與其製作方法 | |
CN103579328B (zh) | 高电子迁移率晶体管及其制造方法 | |
JP5531434B2 (ja) | 化合物半導体装置及びその製造方法 | |
US20210043724A1 (en) | Semiconductor devices and methods for fabricating the same | |
TWI680503B (zh) | 氮化鎵高電子移動率電晶體的閘極結構的製造方法 | |
US20160013305A1 (en) | Nitride semiconductor device and method for manufacturing nitride semiconductor device | |
JP2014199864A (ja) | 半導体装置及びその製造方法 | |
TW202017038A (zh) | 半導體裝置之製造方法 | |
TWI776061B (zh) | 半導體裝置之製造方法 | |
US9640429B2 (en) | Method of fabricating semiconductor device | |
US9281370B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
TWI802705B (zh) | 半導體裝置之製造方法 | |
KR102261740B1 (ko) | 고주파 소자 및 이의 제조 방법 | |
TW202022951A (zh) | 半導體裝置及其製造方法 | |
TWI686873B (zh) | 半導體裝置及其製造方法 | |
JP6888224B2 (ja) | 半導体装置の製造方法 | |
JP6984456B2 (ja) | 電界効果トランジスタの製造方法 | |
CN110581064B (zh) | 半导体装置的制造方法 | |
US10199467B2 (en) | Semiconductor device having plated metal in electrode and process to form the same | |
US20180277434A1 (en) | Process of forming ohmic electrode on nitride semiconductor material | |
JP7484479B2 (ja) | 半導体装置の製造方法 | |
JP6048732B2 (ja) | 半導体装置およびその製造方法 | |
JP7215800B2 (ja) | 半導体装置の製造方法および半導体装置 | |
US10790397B2 (en) | Semiconductor device and method for manufacturing the same |