TWI794996B - Apparatus and system for debugging solid state disk devices - Google Patents
Apparatus and system for debugging solid state disk devices Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
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Abstract
Description
本發明涉及儲存裝置,尤指一種為固態硬碟裝置除錯的裝置及系統。 The invention relates to a storage device, in particular to a device and system for debugging a solid-state hard disk device.
目前使用市售的內電路仿真器(in-circuit emulator,ICE)來搜集固態硬碟(solid state disk,SSD)裝置運行時的韌體狀態,會遭遇到以下的問題:內電路仿真器無法被控制來滿足所有的應用環境,舉例來說,當內電路仿真器停止時會執行一些固定的操作,例如,停止固態硬碟產品中的中央處理器等,導致主機端無法接著存取固態硬碟產品中的資料。目前的內電路仿真器在需要改變位址才能讀取硬體寄存器時,例如,當工程師在韌體卡住時還希望存取硬體寄存器去知道NAND閃存的狀態時,回應的速度很慢。此外,內電路仿真器非常昂貴,並且除錯成本需要進一步降低。因此,本發明提出一種為固態硬碟裝置除錯的裝置及系統,用於解決如上所述的問題。 At present, using a commercially available in-circuit emulator (ICE) to collect the firmware status of a solid state disk (SSD) during operation will encounter the following problem: the in-circuit emulator cannot be accessed Control to meet all application environments, for example, when the in-circuit emulator stops, it will perform some fixed operations, such as stopping the central processing unit in the solid-state hard disk product, so that the host cannot continue to access the solid-state hard disk information in the product. The current in-circuit emulator needs to change the address to read the hardware register, for example, when the engineer wants to access the hardware register to know the state of the NAND flash memory when the firmware is stuck, the response speed is very slow. In addition, in-circuit emulators are very expensive, and debugging costs need to be further reduced. Therefore, the present invention proposes a device and system for debugging solid-state hard disk devices to solve the above-mentioned problems.
有鑑於此,如何減輕或消除上述相關領域的缺失,實為有待解決的問題。 In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem to be solved.
本說明書涉及一種為固態硬碟裝置除錯的裝置的實施例,包含:聯合測試工作群組附加板;以及樹莓派。樹莓派包含通用輸入輸出介面,耦接聯合測試工作群組附加板;以及處理單元,耦接通用輸入輸出介面。處理單元用於通過通用輸入輸出介面模擬多個聯合測試工作群組命令給固態硬碟裝置,以從固態硬碟裝置轉儲固態硬碟裝置運行時產生的資料。 This specification relates to an embodiment of a device for debugging a solid-state hard disk device, including: an additional board for a joint test workgroup; and a Raspberry Pi. The Raspberry Pi includes a general-purpose input-output interface coupled to the additional board of the joint test workgroup; and a processing unit coupled to the general-purpose input-output interface. The processing unit is used for simulating a plurality of joint test working group commands to the solid state hard disk device through the general input and output interface, so as to dump data generated during the operation of the solid state hard disk device from the solid state hard disk device.
本說明書另涉及一種為固態硬碟裝置除錯的系統的實施例,包含如上所述的為固態硬碟裝置除錯的裝置。 The present specification further relates to an embodiment of a system for debugging a solid-state hard disk device, including the above-mentioned device for debugging a solid-state hard disk device.
上述實施例的優點之一,使用如上所述的裝置可降低除錯固態硬碟裝置所需的成本。 As one of the advantages of the above-mentioned embodiments, using the above-mentioned device can reduce the cost required for debugging the solid-state hard disk device.
本發明的其他優點將搭配以下的說明和圖式進行更詳細的解說。 Other advantages of the present invention will be explained in more detail with the following description and drawings.
10:除錯系統 10: Debugging system
110:除錯裝置 110: Debugging device
112:樹莓派 112: Raspberry Pi
114:JTAG附加板 114: JTAG additional board
120:固態硬碟裝置 120: Solid state hard disk device
121:快閃控制器 121: Flash controller
122:輔助寄存器 122: auxiliary register
123:JTAG介面 123: JTAG interface
124:UART介面 124: UART interface
125:處理單元 125: processing unit
126:記憶體 126: memory
127:裝置介面 127: Device interface
128:閃存模組 128:Flash memory module
129:主機介面 129: host interface
130:個人電腦 130: personal computer
132:裝置介面 132: Device interface
140:JTAG連接裝置 140: JTAG connection device
150:UART錄製裝置 150: UART recording device
160:電源 160: power supply
210:處理單元 210: processing unit
222:AHB/ASB 222:AHB/ASB
224:APB 224:APB
230:記憶體控制器 230: memory controller
232:SRAM 232: SRAM
234:DRAM 234:DRAM
236:閃存 236: flash memory
260:GPIO介面 260: GPIO interface
270:USB介面 270:USB interface
280:Wi-Fi模組 280: Wi-Fi module
290:藍牙模組 290:Bluetooth module
S510~S595:方法步驟 S510~S595: method steps
710:20接腳連接器 710: 20 pin connector
730:10接腳連接器 730:10 pin connector
S910~S970:方法步驟 S910~S970: method steps
圖1為依據本發明實施例的除錯系統的方塊圖。 FIG. 1 is a block diagram of a debugging system according to an embodiment of the invention.
圖2為依據本發明實施例的樹莓派的系統架構圖。 FIG. 2 is a system architecture diagram of a Raspberry Pi according to an embodiment of the present invention.
圖3為依據本發明實施例的Argonaut精簡指令集電腦核心(Argonaut Reduced Instruction Set Computer Core,ARC)輔助寄存器集的示意圖。 FIG. 3 is a schematic diagram of an auxiliary register set of an Argonaut Reduced Instruction Set Computer Core (ARC) according to an embodiment of the present invention.
圖4為依據本發明實施例的Argonaut精簡指令集電腦機器(Argonaut RISC Machine,ARM)輔助控制寄存器和二級輔助控制寄存器的位元分配示意圖。 FIG. 4 is a schematic diagram of bit allocation of an Argonaut RISC Machine (ARM) auxiliary control register and a secondary auxiliary control register according to an embodiment of the present invention.
圖5為依據本發明實施例的由除錯應用程式實施的固態硬碟裝置除錯的方法流程圖。 FIG. 5 is a flowchart of a method for debugging a solid-state hard disk device implemented by a debugging application program according to an embodiment of the present invention.
圖6為依據本發明實施例的樹莓派的通用輸入輸出(General-Purpose Input/Output,GPIO)介面的接腳示意圖。 FIG. 6 is a schematic diagram of pins of a General-Purpose Input/Output (GPIO) interface of a Raspberry Pi according to an embodiment of the present invention.
圖7為依據本發明實施例的聯合測試工作群組(Joint Test Action Group,JTAG)連接裝置中的JTAG 20接腳轉10接腳的示意圖。 FIG. 7 is a schematic diagram of converting JTAG 20 pins to 10 pins in a Joint Test Action Group (JTAG) connection device according to an embodiment of the present invention.
圖8為依據本發明實施例的樹莓派的GPIO介面的接腳圖。 FIG. 8 is a pin diagram of the GPIO interface of the Raspberry Pi according to an embodiment of the present invention.
圖9為依據本發明實施例的由執行時程式庫中的函數所實施的固態硬碟裝置除錯的方法流程圖。 FIG. 9 is a flow chart of a method for debugging a solid-state hard disk device implemented by a function in a runtime library according to an embodiment of the present invention.
以下說明為完成發明的較佳實現方式,其目的在於描述本發明的基本精神,但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。 The following description is a preferred implementation mode of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. For the actual content of the invention, reference must be made to the scope of the claims that follow.
必須了解的是,使用於本說明書中的“包含”、“包括”等詞,用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件,但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件,或以上的任意組合。 It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, components and/or components, but do not exclude the possibility of adding More technical characteristics, numerical values, method steps, operation processes, components, components, or any combination of the above.
於權利要求中使用如“第一”、“第二”、“第三”等詞是用於修飾權利要求中的元件,並非用於表示之間具有優先順序,前置關係,或者是一個元件先於另一個元件,或者是執行方法步驟時的時間先後順序,僅用於區別具有相同名字的元件。 Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a priority order, a pre-relationship, or an element An element preceding another element, or a chronological order in performing method steps, is only used to distinguish elements with the same name.
必須了解的是,當元件描述為“連接”或“耦接”至另一元件時,可以是直接連結、或耦接至其他元件,可能出現中間元件。相反地,當元件描述為“直接連接”或“直接耦接”至另一元件時,其中不存在任何中間元件。使用來描述元件之間關係的其他語詞也可類似方式解讀,例如“介於”相對於“直接介於”,或者是“鄰接”相對於“直接鄰接”等等。 It must be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements may be interpreted in a similar fashion, eg, "between" versus "directly between," or "adjacent" versus "directly adjacent," and so forth.
參考圖1所示的除錯系統方塊圖。除錯系統10包含除錯裝置110、固態硬碟裝置120、個人電腦130、聯合測試工作群組(Joint Test Action Group,JTAG)連接裝置140、通用非同步收發器(Universal Asynchronous Receiver/Transmitter,UART)錄製裝置150和電源160。個人電腦130上設置固態硬碟裝置120。除錯裝置110從電源160獲取電力,並且供電給個人電腦130、JTAG連接裝置140和UART錄製裝置150。個人電腦130供電給固態硬碟裝置120。
Refer to the block diagram of the debugging system shown in Figure 1. The
固態硬碟裝置120為待除錯的裝置,至少包含閃存控制器121和閃存模組128。閃存模組128提供大量的儲存空間,通常是數百個千兆位元組(Gigabytes),甚至是數個兆兆位元組(Terabytes),用於儲存大量的使用者資料,例如高解析度圖片、影片等。閃存控制器121包含主機介面129,用於連接上個人電腦130以獲取電力。主機介面129可以通用序列匯流排(Universal Serial Bus,USB)、先進
技術附著(advanced technology attachment,ATA)、序列先進技術附著(serial advanced technology attachment,SATA)、快速周邊元件互聯(peripheral component interconnect express,PCI-E)、通用快閃記憶儲存(Universal Flash Storage UFS)、嵌入式多媒體卡(Embedded Multi-Media Card,eMMC)等通訊協定和個人電腦130中的裝置介面132溝通。閃存控制器121還包含處理單元125,通過匯流排架構和主機介面121、輔助寄存器(auxiliary register,AUX)122、JTAG介面123、UART介面124、記憶體126、裝置介面127彼此連接以傳送和接收命令、控制訊號、訊息、資料等。處理單元125可使用多種方式實施,如使用通用硬體(例如,單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行韌體(firmware)指令過程中存取輔助寄存器122和記憶體126,用於讀取和儲存執行過程中使用到的變數、資料表、資料、訊息等。例如,處理單元125可以是Argonaut精簡指令集電腦核心(Argonaut Reduced Instruction Set Computer,RISC Core,簡稱為ARC)、Argonaut精簡指令集電腦機器(Argonaut RISC Machine,簡稱為ARM)等。輔助寄存器122和記憶體126中儲存的內容是除錯時的重要參考依據。在一些實施例中,記憶體126可為靜態隨機存取記憶體(Static Random Access Memory,SRAM)。在另一些實施例中,記憶體126可包含靜態隨機存取記憶體和動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)。裝置介面127可使用雙倍資料率(Double Data Rate DDR)通訊協定彼此溝通,例如,開放NAND快閃(Open NAND Flash Interface ONFI)、雙倍資料率開關(DDR Toggle)或其他通訊協定和閃存模組128溝通,用於讀取、寫入或者抹除資料。固態硬碟裝置120通過JTAG介面連接上JTAG連接裝置140,並且通過UART介面124連接上UART錄製裝置150。
The solid
輔助寄存器122可服從ARC、ARM或其他的規範。例如,圖3顯示從2008年四月發表的ARCompact TM Instruction Set Architecture:Programmer’s Reference的第45至46頁摘錄出的輔助寄存器集的摘要。圖4中的A部分顯示從2010至2011年發表的Cortex TM -R5 and Cortex-R5F revision:r1p1,Technical Reference Manual的第4-41頁摘錄出的位元分配。圖4中的B部分顯示從2010至2011年發表的Cortex TM -R5 and Cortex-R5F revision:r1p1,Technical Reference Manual的第4-45頁摘錄出的二級輔助控制寄存器的位元分配。
本發明實施例使用除錯裝置110、JTAG連接裝置140和UART錄製裝置150來取代市售的內電路仿真器(in-circuit emulator,ICE),用於避免使用ICE來除錯固態硬碟裝置120中的硬體和軟體所產生的技術問題。此外,除錯裝置110、JTAG連接裝置140和UART錄製裝置150的成本也低於使用ICE除錯的成本。
The embodiment of the present invention uses the
除錯裝置110為整個除錯系統10的核心,包含樹莓派(raspberry Pi)112和JTAG附加板(add-on board)114。樹莓派112是基於Linux作業系統的單晶片電腦。除錯應用程式執行於樹莓派112,並且待除錯的韌體執行於固態硬碟裝置120。樹莓派112於執行除錯應用程式時通過通用輸入輸出(General-Purpose Input/Output,GPIO)介面將電源160饋入個人電腦130以啟動個人電腦130,使得固態硬碟裝置120也跟著啟動,接著,依據驅動電源發光二極體(Light-Emitting Diode,LED)的訊號判斷個人電腦130是否啟動成功。因為JTAG介面可使用一般的IO訊號驅動,樹莓派112於執行除錯應用程式時通過內建的GPIO介面模擬JTAG的行為,用於從固態硬碟裝置120獲取所需的資訊,存取速度可高於4Mbps。JTAG的通訊協定可參考2001年6月14准許的IEEE Standard Test Access Port and Boundary-Scan Architecture。樹莓派112於執行除錯應用程式時通過內建的GPIO介面和JTAG連接裝置140強迫固態硬碟裝置120進入唯
讀記憶體(Read-Only Memory,ROM)模式。當固態硬碟裝置120進入ROM模式時,處理單元125從ROM(未顯示在圖1當中)載入和執行程式碼,用於執行系統開機的操作,例如各種的硬體測試等。樹莓派112於執行除錯應用程式時通過內建的USB介面和UART錄製裝置150從固態硬碟裝置120搜集UART資料、訊號和訊息等。工程師可操作樹莓派112來對固態硬碟裝置120的硬體和/或固態硬碟裝置120中執行的韌體進行除錯。舉例來說,樹莓派112可裝配Wi-Fi或藍牙模組,工程師通過與樹莓派112中的Wi-Fi或藍牙模組建立遠端連線,控制整個除錯裝置110。
The
參考圖2的樹莓派112的系統架構。處理單元210可為ARM架構的處理器,並且在執行除錯應用程式的指令時,完成如下所述的功能。工具開發人員可使用Python來撰寫除錯應用程式。樹莓派112包含可以組合使用的不同類型的匯流排:先進高效匯流排/先進系統匯流排(Advanced High-performance Bus/Advanced System Bus,AHB/ASB)222;以及先進周邊匯流排(Advanced Peripheral Bus,APB)224。AHB/ASB 222和APB 224之間以橋接器(bridge)220連接。AHB/ASB 222用於滿足處理單元210通過記憶體控制器230和SRAM 232、DRAM 234或者閃存(flash memory)236之間高速頻寬要求。APB 224適用於低功耗的周邊設備,例如GPIO介面260、USB介面270、Wi-Fi模組280、藍牙模組290等。處理單元210可通過GPIO介面260模擬JTAG的行為,並且通過USB介面270接收UART資料、訊號和訊息等。處理單元210可經由Wi-Fi模組280或藍牙模組290從遠端接收除錯請求,並且載入並執行除錯應用程式來回應除錯請求。
Refer to the system architecture of the
本發明實施例提出一種固態硬碟裝置的除錯方法,由處理單元210載入並執行除錯應用程式的程式碼時實施。參考圖5,詳細說明如下:
An embodiment of the present invention proposes a debugging method for a solid-state hard disk device, which is implemented when the
步驟S510:通過GPIO介面260模擬JTAG命令以讀取固態硬碟裝置
120中的快閃控制器121的處理單元125的識別碼(identifier,ID),例如ARCID、ARM ID等。舉例來說,可從固態硬碟裝置120中的輔助寄存器122的指定位址讀取處理單元125的識別碼。在一些實施例中,ARC ID記錄在圖3中的第四個雙位元組的第0至7個位元”ARCVER[7:0]”。
Step S510: Simulate the JTAG command through the
步驟S520:判斷識別碼是否正確。當識別碼正確時,流程繼續進行步驟S530的處理。否則,流程繼續進行步驟S525的處理。這個步驟可用以確認除錯裝置110是否正確地連接上固態硬碟裝置120。如果處理單元210無法從固態硬碟裝置120讀取到關於快閃控制器121的處理單元125的識別碼,則代表除錯裝置110沒有正確地連接上固態硬碟裝置120。
Step S520: Determine whether the identification code is correct. When the identification code is correct, the process proceeds to step S530. Otherwise, the process proceeds to step S525. This step can be used to confirm whether the
步驟S525:除錯應用程式回覆錯誤訊息給啟動除錯應用程式的上層。上層可據以驅動顯示器以顯示錯誤訊息,或者將錯誤訊息儲存在閃存236,用於讓工程師知道在除錯的過程中發生了錯誤。
Step S525: The debugging application program returns an error message to the upper layer that activates the debugging application program. The upper layer can drive the display to display the error message, or store the error message in the
步驟S530:通過GPIO介面260模擬JTAG命令以停止固態硬碟裝置120中的快閃控制器121的處理單元125的運行。舉例來說,可修改固態硬碟裝置120中的輔助寄存器122的指定位址的值以停止處理單元125。在一些實施例中,可將圖3中的第五個雙位元組的第1個位元”FH”設為”1”以停止處理單元125。
Step S530 : Stop the operation of the
步驟S540:通過GPIO介面260模擬JTAG命令以讓固態硬碟裝置120離開休眠模式(sleep mode)。舉例來說,可修改固態硬碟裝置120中的輔助寄存器122的指定位址的值以讓固態硬碟裝置120離開休眠模式。在一些實施例中,可將圖3中的第五個雙位元組的第23個位元”ZZ”設為”0”以讓固態硬碟裝置120離開休眠模式。
Step S540 : Simulate the JTAG command through the
步驟S550:通過GPIO介面260模擬JTAG命令以讀取固態硬碟裝置120的系統內編程碼(in-system programming,ISP code)。舉例來說,系統內編程碼可儲存於閃存模組128中的指定位址,除錯應用
程式可發出JTAG命令以從閃存模組128的指定位址讀取指定長度的資料(也就是系統內編程碼)。系統內編程碼包含用於執行從主機發出的主機命令,例如主機讀取、寫入、抹除命令等,或者執行背景操作,例如垃圾回收(garbage collection,GC)、損耗磨平(wear leveling,WL)、讀取再生(read reclaim)、讀取刷新(read refresh)等程序。主機命令為由標準制定組織所規範命令,例如通用快閃記憶儲存(Universal Flash Storage,UFS)、快速非揮發性記憶體(Non-Volatile Memory Express,NVMe)、開放通道固態硬碟(Open-channel Solid State Disk,SSD)等。
Step S550 : read the in-system programming (ISP code) of the solid
步驟S560:計算系統內編程碼的校驗和(checksum)。除錯應用程式可使用特定的演算法來計算校驗和,例如MD5、SHA1、SHA256、SHA512等。 Step S560: Calculate the checksum of the programming code in the system. Debugging applications can use specific algorithms to calculate checksums, such as MD5, SHA1, SHA256, SHA512, etc.
步驟S570:判斷校驗和是否正確。當校驗和正確時,流程繼續進行步驟S580的處理。否則,流程繼續進行步驟S525的處理。在一些實施例中,由於固態硬碟裝置120的閃存控制器121的製造廠商可能因應不同類型的NAND快閃記憶體,提供不同版本的系統內編程碼。樹莓派112中的閃存236可預先儲存相應於多個系統內編程碼版本的校驗和。除錯應用程式可將步驟S560中產生的校驗和比對閃存236中儲存的校驗和。如果步驟S560中產生的校驗和相符於閃存236中儲存的多個校驗和中之一者時,判定校驗和正確(也就是固態硬碟裝置120的閃存控制器121中執行的系統內編程碼可以辨認為特定系統內編程碼版本)。反之,判定校驗和不正確(也就是固態硬碟裝置120的閃存控制器121中執行的系統內編程碼不正確或者不能辨認)。這個步驟除了可以用來判斷校驗和是否正確外,還可以知道閃存控制器121中執行的系統內編程碼的版本。在這裡需要注意的是,不同的系統內編程碼的版本擁有不同的記憶體配置邏輯,用於儲存執行時的變數、資料表、即將寫入閃存模組128的資料、從閃
存模組128讀出的資料等。也就是說,除錯應用程式需要先知道記憶體配置邏輯,接著才能夠依據記憶體配置邏輯從固態硬碟裝置120中的記憶體126(包含SRAM、DRAM)的正確位址轉儲(dump)所需的資料。
Step S570: Determine whether the checksum is correct. When the checksum is correct, the process continues to step S580. Otherwise, the process proceeds to step S525. In some embodiments, because the manufacturer of the flash memory controller 121 of the solid-state
步驟S580:通過GPIO介面260模擬JTAG命令以讀取固態硬碟裝置120的SRAM中的資料。舉例來說,開機期間或者是正常操作期間產生的韌體資料可儲存於SRAM中的指定位址,除錯應用程式可發出多個JTAG命令給固態硬碟裝置120,每個JTAG命令請求從SRAM的指定位址讀取指定長度的資料(也就是韌體資料)。在一些實施例中,樹莓派112中的閃存236可儲存一份文件,包含多筆紀錄。每筆紀錄包含開始位址和長度的資訊。除錯應用程式可依據文件中的每一筆紀錄發出JTAG命令給固態硬碟裝置120以從SRAM的指定位址讀取指定長度的資料。
Step S580 : Simulate the JTAG command through the
步驟S590:在記憶體126中有配備DRAM的實施例中,通過GPIO介面260模擬JTAG命令以讀取固態硬碟裝置120的DRAM中的資料。舉例來說,開機期間或者是正常操作期間產生的韌體資料可儲存於DRAM中的指定位址,除錯應用程式可發出多個JTAG命令給固態硬碟裝置120,每個JTAG命令請求從DRAM的指定位址讀取指定長度的資料(也就是韌體資料)。在一些實施例中,樹莓派112中的閃存236可儲存一份文件,包含多筆紀錄。每筆紀錄包含開始位址和長度的資訊。除錯應用程式可依據文件中的每一筆紀錄發出JTAG命令給固態硬碟裝置120以從DRAM的指定位址讀取指定長度的資料。
Step S590 : In the embodiment in which the
步驟S595:通過GPIO介面260模擬JTAG命令以回復固態硬碟裝置120中的快閃控制器121的處理單元125。舉例來說,可修改固態硬碟裝置120中的輔助寄存器122的指定位址的值以回復處理單元125。在一些實施例中,可將圖3中的第五個雙位元組的第1個位元”FH”設
為”0”以回復處理單元125。
Step S595 : Simulate the JTAG command through the
以下顯示除錯應用程式的虛擬碼: The following shows the dummy code for the debugger application:
通過如上所述由除錯應用程式所實施的固態硬碟裝置的除錯方法,可較內電路仿真器具有彈性,以解決除錯時遭遇到的問題。例如,在固態硬碟裝置的韌體運行卡住時可以快速存取硬體寄存器以獲取NAND閃存的狀態等。 Through the debugging method of the solid state hard disk device implemented by the debugging application program as described above, it can be more flexible than the internal circuit emulator, so as to solve the problems encountered during debugging. For example, when the firmware of the solid-state hard disk device is stuck, the hardware register can be quickly accessed to obtain the status of the NAND flash memory.
參考圖1和圖2。UART錄製裝置150包含USB介面、UART介面、控制器和記憶體。UART錄製裝置150的USB介面連接樹莓派112的USB介面,以及UART錄製裝置150的UART介面連接固態硬碟裝置120的UART介面124。UART錄製裝置150經由其UART介面從固態硬碟裝置120接收日誌資訊(log information),包含資料、訊息和/或訊號等,並且將日誌資訊經由其USB介面傳送給樹莓派112。UART錄製裝置150還可包含非揮發性儲存單元,用於儲存從固態硬碟裝置120接收的日誌資訊。USB介面中的使用到的每個埠可經由電壓/電平轉換器(level shifter)連接到UART介面上的指定埠,電壓/電平轉換器用於將從USB介面的輸入信號從一個電壓域調整到UART介面的電壓域,或者將從UART介面的輸入信號從一個電壓域調整到USB介面的電壓域。
Refer to Figure 1 and Figure 2. The
參考圖6,樹莓派112可經由GPIO介面260的40個接腳連接上JTAG附加板114。JTAG附加板114負責在樹莓派112和JTAG連接裝置140之間傳遞訊號,以及在樹莓派112和個人電腦130之間傳遞訊號。JTAG附加板114包含GPIO介面和type-C介面,GPIO介面連接樹莓派112和個人電腦130,而type-C介面連接JTAG連接裝置140。GPIO介
面中的使用到的每個埠可經由電壓/電平轉換器連接到type-C介面上的指定埠,電壓/電平轉換器用於將從GPIO介面的輸入信號從一個電壓域調整到type-C介面的電壓域,或者將從type-C介面的輸入信號從一個電壓域調整到GPIO介面的電壓域。
Referring to FIG. 6 , the
JTAG連接裝置140可視為一個JTAG轉接器(JTAG adaptor),可以是20接腳轉10接腳、20接腳轉8接腳等,負責將樹莓派112經由JTAG附加板114模擬的JTAG命令、資料傳送給固態硬碟裝置120,以及將固態硬碟裝置120輸出的資料經由JTAG附加板114傳送給樹莓派112。JTAG連接裝置140包含type-C介面、JTAG介面、控制器和記憶體。JTAG連接裝置140的type-C介面可連接JTAG附加板114的type-C介面,以及JTAG連接裝置140的JTAG介面連接固態硬碟裝置120的JTAG介面123。在這裡需要注意的是,由於固態硬碟裝置120需要在試驗艙(test chamber)在高溫的環境下進行測試,將JTAG連接裝置140獨立出來,而不是讓JTAG連接裝置140整合到JTAG附加板114上,能夠讓固態硬碟裝置120和JTAG連接裝置140一起放置到試驗艙中進行除錯的操作。參考圖7的20接腳轉10接腳的範例,包含用於連接JTAG附加板114的20接腳連接器(20-pin connector)710,以及用於連接JTAG介面123的10接腳連接器(10-pin connector)730。舉例來說,連接器710的第9個腳位從JTAG附加板114饋入測試時鐘(test clock,TCLK)訊號,連接器730的第4個腳位則輸出時鐘訊號給JTAG介面123。連接器710的第7個腳位從JTAG附加板114輸入測試模式選擇輸入(test mode select input,TMS)訊號,連接器730的第2個腳位則輸出測試模式選擇輸入訊號給JTAG介面123。連接器710的第5個腳位從JTAG附加板114輸入測試資料輸入(test data input,TDI)訊號,連接器730的第8個腳位則輸出測試資料輸入訊號給JTAG介面123。連接器730的第6個腳位從JTAG介面123輸入測試資料輸出(test data output,TDO)訊號,
連接器710的第13個腳位則輸出測試資料輸出訊號給JTAG附加板114。連接器710的第3個腳位從JTAG附加板114輸入測試重置輸入(test reset input,TRST)訊號,連接器730的第10個腳位則輸出測試重置輸入訊號給JTAG介面123。連接器710的以上所述每個腳位可經由電壓/電平轉換器連接到連接器730的的指定腳位,電壓/電平轉換器用於將type-C介面的輸入信號從一個電壓域調整到JTAG介面的電壓域,或者將JTAG介面的輸入信號從一個電壓域調整到type-C介面的電壓域。
The
JTAG附加板114上可設置連接電源的三個繼電器(power relay)。參考圖8的GPIO介面260的範例接腳圖(pin-out diagram),腳位GPIO12、GPIO18和GPIO23用於分別控制JTAG附加板114上設置的三個繼電器(power relay)以驅動繼電器來饋入電源160至個人電腦130。腳位GPIO17連接到個人電腦130中的驅動LED的訊號線,用於偵測個人電腦130是否正確啟動。腳位GPIO16連接到固態硬碟裝置120的特定腳位,用於驅動固態硬碟裝置120進入ROM模式。腳位GPIO22連接到固態硬碟裝置120的SATA介面的特定腳位,用於驅動固態硬碟裝置120進入或離開休眠模式(sleep mode)。在這裡需要注意的是,通過SATA介面進入的休眠模式會切斷固態硬碟裝置120中大部分元件(包含處理單元125)的供電以節省電力。換句話說,當通過SATA介面進入休眠模式時,固態硬碟裝置120中的處理單元125並不會執行任何操作。如上所述的除錯應用程式於發出JTAG命令時所離開的休眠模式,不同於通過SATA介面進入的休眠模式。腳位GPIO11、GPIO5、GPIO6、GPIO13、GPIO19和GPIO26通過用JTAG附加板114和JTAG連接裝置140連接固態硬碟裝置120中的JTAG介面123,用於讓樹莓派112中的處理單元210在執行除錯應用程式時模擬JTAG行為,通過這些腳位發送JTAG命令給固態硬碟裝置120,以及從固態硬碟裝置120獲取系統內編程碼、韌體資料
等。例如,腳位GPIO5可用來傳送JTAG TDI訊號給固態硬碟裝置120,腳位GPIO6可用來從固態硬碟裝置120接收JTAG TDO訊號。關於JTAG行為的模擬細節,可參考2001年6月14准許的IEEE Standard Test Access Port and Boundary-Scan Architecture。
Three power relays connected to the power supply can be provided on the JTAG add-on
參考圖2。樹莓派112是一種低成本的個人電腦,因此沒有實作低延遲周邊埠(low latency peripheral port,LLPP)的技術,其使用專屬的路徑來存取GPIO介面。當上層的除錯應用程式欲通過GPIO介面260發出JTAG命令來存取固態硬碟裝置120中的周邊寄存器122或記憶體126中的內容時,下層的GPIO驅動程式可依序通過AHB/ASB 222和APB 224發出硬體指令和參數給GPIO介面260,用於寫入(或稱為設定)GPIO介面260中相應於特定接腳的寄存器以完成JTAG命令的模擬。然而,由於硬體的限制,一些硬體指令可能會延遲到達APB 224。當兩個用於寫入GPIO介面260中的相同寄存器的硬體指令在非常短的時間區間先後到達APB控制器時,APB控制器可能會誤判成錯誤的硬體指令而捨棄其中的一個不執行,造成部分的系統內編程碼、韌體資料等無法從固態硬碟裝置120讀取回來。
Refer to Figure 2. The
為了解決如上所述的問題,本發明實施例修改運行期函式庫(runtime library)中的函數,此函數用於驅動GPIO介面260以完成操作,讓除錯應用程式可以呼叫此函數以完成如上所述的功能,例如發出JTAG命令來讀取固態硬碟裝置120中的快閃控制器121的處理單元125的識別碼、停止固態硬碟裝置120中的快閃控制器121的處理單元125、讓固態硬碟裝置120離開休眠模式、讀取固態硬碟裝置120的閃存模組128中儲存的系統內編程碼、讀取固態硬碟裝置120的SRAM、DRAM中的資料等。運行期函式庫是一種被編譯器(compiler)用來實現程式語言的內建函數集合,以提供該程式語言執行時支援的一種特殊的電腦程式函式庫。參考圖9,詳細說明如下:
In order to solve the above problems, the embodiment of the present invention modifies the function in the runtime library (runtime library), this function is used to drive the
步驟S910:從除錯應用程式接收驅動GPIO介面的請求,包含完成特定JTAG命令所需的參數。例如,相應於圖5的步驟S510,參考圖3,請求中的參數包含讀取輔助寄存器122中的第四個雙位元組的第0至7個位元的資訊。相應於圖5的步驟S530,參考圖3,請求中的參數包含將輔助寄存器122中的第五個雙位元組的第1個位元設為”1”的資訊。相應於圖5的步驟S540,參考圖3,請求中的參數包含將輔助寄存器122中的第五個雙位元組的第23個位元設定為”0”的資訊。相應於圖5的步驟S550,請求中的參數包含從閃存模組128的指定位址讀取指定長度的資料的資訊。相應於圖5的步驟S580,請求中的參數包含從SRAM的指定位址讀取指定長度的資料的資訊。相應於圖5的步驟S590,請求中的參數包含從DRAM的指定位址讀取指定長度的資料的資訊。
Step S910: Receive a request to drive the GPIO interface from the debugging application program, including parameters required to complete a specific JTAG command. For example, corresponding to step S510 of FIG. 5 , referring to FIG. 3 , the parameters in the request include information on reading
步驟S930:依據請求中攜帶的參數發出硬體指令給GPIO介面260以設定相應於TDI的GPIO接腳的寄存器,用於模擬特定JTAG的命令。
Step S930 : Send a hardware command to the
步驟S950:發出硬體指令給GPIO介面260以讀取相應於TDI的GPIO接腳的寄存器的值。由於這個步驟的操作,在依據兩個請求所產生的設定相應於TDI的GPIO接腳的寄存器的硬體指令之間,***一個讀取相應於TDI的GPIO接腳的寄存器值的硬體指令,可避免APB控制器將兩個在非常短的時間區間先後到達的設定相應於TDI的GPIO接腳的寄存器的硬體指令誤判成錯誤的硬體指令。在這裡需要注意的是,這個步驟也可執行於步驟S910和S930之間,本發明並不因此局限。
Step S950 : Send a hardware command to the
步驟S970:回覆驅動完成的訊息給除錯應用程式。 Step S970: Reply a message of completion of driving to the debugging application program.
樹莓派112的處理單元210可週期性地執行程式庫中的另一個函數,用於週期性地驅動GPIO介面260,用於讀取相應於TDO的GPIO接腳的寄存器的值。讀取的值為之前通過相應於TDI的GPIO接腳所發出的模擬JTAG命令的執行結果,由固態硬碟裝置120產生並回覆,可
包含例如輔助寄存器122的設定成功或失敗的訊息、從閃存模組128讀取的系統內編程碼、從SRAM或DRAM讀取的韌體資料等等。
The
本發明所述的方法中的全部或部分步驟可以計算機指令實現,例如特定硬體的驅動程式、韌體程式或軟體程式等。此外,也可實現於其他類型程式。所屬技術領域人員可將本發明實施例的方法撰寫成計算機指令,為求簡潔不再加以描述。依據本發明實施例方法實施的計算機指令可儲存於適當的電腦可讀取媒體,例如DVD、CD-ROM、USB碟、硬碟,亦可置於可通過網路(例如,網際網路,或其他適當載具)存取的網路伺服器。 All or part of the steps in the method of the present invention can be implemented by computer instructions, such as specific hardware drivers, firmware programs or software programs. In addition, it can also be implemented in other types of programs. Those skilled in the art can write the methods of the embodiments of the present invention into computer instructions, and the description is omitted for the sake of brevity. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed through a network (for example, the Internet, or other suitable means of access to the web server.
雖然圖1和圖2中包含了以上描述的元件,但不排除在不違反發明的精神下,使用更多其他的附加元件,已達成更佳的技術效果。此外,雖然圖5和圖9的流程圖採用指定的順序來執行,但是在不違反發明精神的情況下,熟習此技藝人士可以在達到相同效果的前提下,修改這些步驟間的順序,所以,本發明並不侷限於僅使用如上所述的順序。此外,熟習此技藝人士亦可以將若干步驟整合為一個步驟,或者是除了這些步驟外,循序或平行地執行更多步驟,本發明亦不因此而侷限。 Although the elements described above are included in FIG. 1 and FIG. 2 , it is not excluded to use more other additional elements to achieve better technical effects without violating the spirit of the invention. In addition, although the flow charts in FIG. 5 and FIG. 9 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, The invention is not limited to using only the sequence described above. In addition, those skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereby.
雖然本發明使用以上實施例進行說明,但需要注意的是,這些描述並非用以限縮本發明。相反地,此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以,申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。 Although the present invention is described using the above examples, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.
10:除錯系統 10: Debugging system
110:除錯裝置 110: Debugging device
112:樹莓派 112: Raspberry Pi
114:JTAG附加板 114: JTAG additional board
120:固態硬碟裝置 120: Solid state hard disk device
121:快閃控制器 121: Flash controller
122:輔助寄存器 122: auxiliary register
123:JTAG介面 123: JTAG interface
124:UART介面 124: UART interface
125:處理單元 125: processing unit
126:記憶體 126: memory
127:裝置介面 127: Device interface
128:閃存模組 128:Flash memory module
129:主機介面 129: host interface
130:個人電腦 130: personal computer
132:裝置介面 132: Device interface
140:JTAG連接裝置 140: JTAG connection device
150:UART錄製裝置 150: UART recording device
160:電源 160: power supply
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