CN114265786A

CN114265786A - Automatic testing method and device, computer equipment and readable storage medium

Info

Publication number: CN114265786A
Application number: CN202111672172.XA
Authority: CN
Inventors: 柏颖; 欧国东; 高金培; 马玲芝; 李晨; 吴轲
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-01

Abstract

The application provides an automatic testing method and device, computer equipment and a readable storage medium. The method comprises the following steps: after receiving a simulation starting instruction initiated by a user, the computer equipment executes a first connection function of the test script to trigger the hardware simulation accelerator to execute a first connection command, so that the communication connection between the computer equipment and the hardware simulation accelerator is realized; and after the hardware simulation accelerator executes the first connection command, the computer equipment executes the configuration function of the test script so as to configure the function to be tested of the chip to be tested based on the configuration procedure corresponding to the configuration function. The test script outputs the configuration instruction corresponding to each configuration procedure and automatically configures the next configuration procedure when the previous configuration procedure is completed, so that the manual intervention of the hardware simulation accelerator in the configuration process is reduced and the configuration efficiency is improved.

Description

Automatic testing method and device, computer equipment and readable storage medium

Technical Field

The present application relates to the field of hardware simulation technologies, and in particular, to an automated testing method and apparatus, a computer device, and a readable storage medium.

Background

With the rapid development of integrated circuit technology, the design scale of microprocessors is gradually increased, the design complexity is increasingly increased, and higher requirements are put forward for verification technology. The verification technology mainly comprises software simulation verification, FPGA (Field Programmable Gate Array) prototype system verification and hardware simulation accelerator verification. Software simulation verification technology can verify modules in a microprocessor, but the requirement of large-scale verification at a system level on simulation speed is difficult to meet. The FPGA prototype verification can improve higher simulation speed, but is limited by the capacity of the FPGA, one microprocessor needs to be divided into a plurality of FPGAs, so that the problem of logic division is introduced, the technical difficulty and the time cost are high, and meanwhile, the problems of I/O (Input/Output) bottleneck, inconvenience in debugging and the like also exist.

The hardware simulation accelerator is a main means of the current microprocessor system level verification, effectively makes up the defects of software simulation verification and FPGA prototype verification, and has the following advantages: the user can conveniently establish a hardware model of the chip at the early stage of design; the chip software can be conveniently debugged and designed by a user at the early stage of design; can be repeatedly used for many times; the built-in logic analyzer can be conveniently used for debugging the circuit; there are rich reusable standard bus models such as PCI (Peripheral Component Interconnect), Ethernet (Ethernet), etc.

However, the hardware simulation accelerator needs to be manually configured by a tester in the configuration process before testing, and the method needs to consume a large amount of manpower, thereby greatly reducing the configuration efficiency.

Disclosure of Invention

An object of the embodiments of the present application is to provide an automated testing method, an automated testing apparatus, a computer device, and a readable storage medium, which can reduce manual intervention and improve configuration efficiency.

The invention is realized by the following steps:

in a first aspect, an embodiment of the present application provides an automated testing method, which is applied to a computer device, where the computer device is used for being physically connected to a hardware simulation accelerator, and the hardware simulation accelerator runs a file related to a chip to be tested to test a function to be tested of the chip to be tested; the method comprises the following steps: after receiving a simulation starting instruction initiated by a user, the computer equipment executes a first connection function of a test script to trigger the hardware simulation accelerator to execute a first connection command, so that the communication connection between the computer equipment and the hardware simulation accelerator is realized; after the hardware simulation accelerator executes the first connection command, the computer equipment executes a configuration function of the test script so as to configure a function to be tested of the chip to be tested based on a configuration procedure corresponding to the configuration function; when the configuration function of the test script is executed, the test script outputs a configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically carried out.

In the embodiment of the application, after receiving a simulation starting instruction initiated by a user, the computer device may automatically execute the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command, so that the computer device and the hardware simulation accelerator establish a communication connection. By the method, interaction between the computer equipment and the hardware simulation accelerator can be realized, and further the subsequent computer equipment can complete configuration of the hardware simulation accelerator through the configuration function of the test script. In addition, because the test script outputs the configuration instruction corresponding to each configuration procedure and automatically configures the next configuration procedure when the previous configuration procedure is completed, the manual intervention of the hardware simulation accelerator in the configuration process is reduced by the mode, and the configuration efficiency is improved.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the hardware simulation accelerator further runs a serial port model; the executing the configuration function of the test script comprises: the computer equipment outputs a first configuration instruction corresponding to a first configuration procedure to the serial port model through the test script so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator in a force mode; the first arrangement step is any one of the arrangement steps; the computer equipment receives actual characters output by the serial port model in a display cache mode, wherein the actual characters are characters which are generated when the hardware simulation accelerator executes the first configuration instruction and are captured by a debugging script language supported by the hardware simulation accelerator; the computer equipment compares a preset expected finished character with the actual character through a comparison instruction in the configuration function so as to determine whether the first configuration procedure is finished; and when the computer equipment determines that the first configuration procedure is finished and the first configuration procedure is not the last configuration procedure, outputting a second configuration instruction corresponding to a second configuration procedure to the serial port model through the test script, wherein the second configuration procedure is the next configuration procedure of the first configuration procedure.

In the embodiment of the application, the traditional serial port chip is replaced by the serial port model, so that the configuration difficulty of the hardware simulation accelerator in a hardware environment can be reduced. And the serial port model sends the output actual characters to the computer equipment in a display cache mode, so that a user can visually see the process of each configuration stage, the problem analysis is facilitated for the user, and the test efficiency under a complex scene is greatly improved. In addition, the computer equipment can compare the preset expected completion character with the actual character output by the serial port model through the comparison instruction in the configuration function, and further determine whether to output the configuration instruction corresponding to the next configuration procedure to the serial port model according to the comparison result, so that the automatic triggering of the next configuration procedure is realized through the mode, and further the automation of the whole configuration process of the test script is realized.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the actual character is successfully recognized and identified through the serial port model before being output through the display cache manner.

In the embodiment of the application, the serial port model is further used for recognizing the characters before the actual characters are output. The serial port model can be output only under the condition that the characters can be successfully identified, the accuracy and the reliability of the serial port model in application can be guaranteed through the method, and the problem that the serial port model still outputs the characters under the condition that the characters are lost so as to cause follow-up comparison errors is avoided.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the configuration procedure includes uboot boot, operating system boot, driver loading of the function to be tested, and parameter configuration of the function to be tested.

In this embodiment of the application, the configuration process may include uboot boot, operating system boot, driver loading of the function to be tested, and parameter configuration of the function to be tested, so as to implement full-stage automatic configuration.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the computer device is further configured to connect to another computer device, the network card connected to the hardware simulation accelerator is connected to the other computer device through a network cable, and after it is determined that the configuration procedure of the function to be tested of the chip to be tested is completed, the method further includes: and the computer equipment executes the second connection function of the test script to realize that the computer equipment automatically remotely logs in the hardware simulation accelerator and tests the function to be tested by running a test program.

In the embodiment of the application, when the network card connected to the hardware simulation accelerator is connected to other computer equipment through the optical fiber, and the computer equipment connected to the other computer equipment determines that the configuration process of the function to be tested is configured, the second connection function of the test script can be automatically executed, so that the computer equipment can automatically log in the hardware simulation accelerator in a remote mode, and simultaneously the function to be tested is tested through the test program.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the test script is an expect script, and the executing, by the computer device, the second connection function of the test script includes: the computer equipment connects an SSH port of the computer equipment with a network configured by the hardware simulation accelerator through a spawn command in the expect script; wherein the spawn command is provided with an address of the network.

In the embodiment of the application, the spawn command in the expect script is modified and carries the address of the network, so that the SSH port of the computer device is connected with the network configured by the hardware emulation accelerator. Furthermore, because the spawn command has a function of starting a new process, the method can meet the requirement of simultaneously starting test connections between a plurality of computer devices and the hardware simulation accelerator, and further can simultaneously test a plurality of functions to be tested of the chip to be tested.

With reference to the technical solution provided by the first aspect, in some possible implementation manners, the computer device is further configured to connect with the other computer device in a way of access without secret.

In the embodiment of the application, because the computer device can be connected with other computer devices in a way of secret-less access, different computer devices can realize quick access with the hardware simulation accelerator and perform testing.

In a second aspect, an embodiment of the present application provides an automated testing apparatus, which is applied to a computer device, where the computer device is used for being physically connected to a hardware simulation accelerator, and the hardware simulation accelerator runs a file related to a chip to be tested, so as to test a function to be tested of the chip to be tested; the device comprises: the starting module is used for receiving a starting simulation instruction initiated by a user; the first connection module is used for executing a first connection function of a test script after the start module receives a start simulation instruction initiated by a user, so as to trigger the hardware simulation accelerator to execute a first connection command, and realize the communication connection between the computer equipment and the hardware simulation accelerator; the configuration module is used for executing the configuration function of the test script after the hardware simulation accelerator executes the first connection command so as to configure the function to be tested of the chip to be tested based on the configuration procedure corresponding to the configuration function; when the configuration function of the test script is executed, the test script outputs a configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically carried out.

In a third aspect, an embodiment of the present application provides a computer device, including: a processor and a memory, the processor and the memory connected; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform a method as provided in the above-described first aspect embodiment and/or in combination with some possible implementations of the above-described first aspect embodiment.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, performs the method as set forth in the above first aspect embodiment and/or in combination with some possible implementations of the above first aspect embodiment.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a block diagram of an automated testing system according to an embodiment of the present disclosure.

Fig. 2 is a block diagram of a computer device according to an embodiment of the present disclosure.

Fig. 3 is a block diagram of another automated test system according to an embodiment of the present disclosure.

Fig. 4 is a flowchart illustrating steps of an automated testing method according to an embodiment of the present disclosure.

Fig. 5 is a flowchart illustrating another exemplary automated testing process according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a test performed by multiple computer devices according to an embodiment of the present application.

Fig. 7 is a block diagram of an automated testing apparatus according to an embodiment of the present disclosure.

Icon: 10-an automated test system; 100-a computer device; 110-a processor; 120-a memory; 200-a hardware emulation accelerator; 300-an automated testing device; 310-a start-up module; 320-a first connection module; 330-configuration module.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

To facilitate understanding of the present application, the following technical terms are explained:

test scripts, i.e., computer readable instructions that automatically execute a test procedure (or portion thereof). The test scripts can be created (recorded) or automatically generated using a test automation tool, or can be implemented using programming language programming, or can be implemented by combining the first three approaches. In the present application, the test script may include three processes, which are respectively: the computer equipment is connected with the hardware simulation accelerator, the function to be tested of the chip to be tested is configured, and the computer equipment can automatically log in the hardware simulation accelerator remotely. The present application will focus on how to implement a hardware-based simulation accelerator simulation test based on a test script in the following.

The inventor of the application finds in practice that in the simulation test based on the hardware simulation accelerator, when a tester inputs one command, the tester needs to wait for the command to respond to the completion and then input other commands. This approach can waste time waiting for the tester. And after the driver loading is completed, if the tester delays due to other things, the hardware simulation accelerator does not complete the configuration all the time. In order to solve the technical problem, embodiments of the present application provide an automated testing system, method, and apparatus.

Specifically, referring to fig. 1, an automated test system 10 is provided according to an embodiment of the present disclosure. The automated test system 10 includes: computer device 100 and hardware emulation accelerator 200.

Wherein computer device 100 is physically connected to hardware emulation accelerator 200.

In the embodiment of the present application, the computer device 100 and the hardware simulation accelerator 200 are physically connected through an optical fiber.

In the automatic testing process of the automatic testing system 10, the hardware simulation accelerator 200 runs a file related to the chip to be tested, so as to simulate the related functions of the chip to be tested. The computer device 100 is configured with a test script, and after the computer device 100 establishes a communication connection with the hardware simulation accelerator 200, the computer device 100 is configured to execute a configuration function of the test script, so that the hardware simulation accelerator 200 automatically configures a function to be tested of a chip to be tested based on a configuration procedure corresponding to the configuration function.

Referring to fig. 2, fig. 2 is a schematic block diagram of a computer device 100 applying an automated testing method and apparatus according to an embodiment of the present disclosure. In the embodiment of the present application, the Computer device 100 may be a terminal or a server, and the terminal may be, but is not limited to, a PC (Personal Computer), a notebook Computer, and the like. The server may be, but is not limited to, a web server, a database server, a cloud server, or a server assembly composed of a plurality of sub-servers, etc. Of course, the above-mentioned devices are only used to facilitate understanding of the embodiments of the present application, and should not be taken as limiting the embodiments.

Structurally, computer device 100 may include a processor 110 and a memory 120.

The processor 110 and the memory 120 are electrically connected directly or indirectly to enable data transmission or interaction, for example, the components may be electrically connected to each other via one or more communication buses or signal lines. The automated testing equipment includes at least one software module stored in the form of software or Firmware (Firmware) in the memory 120 or solidified in an Operating System (OS) of the computer device 100. The processor 110 is used for executing executable modules stored in the memory 120, such as software functional modules and computer programs included in the automatic testing apparatus, so as to implement the automatic testing method. The processor 110 may execute the computer program upon receiving the execution instruction.

The processor 110 may be an integrated circuit chip having signal processing capabilities. The Processor 110 may also be a general-purpose Processor, for example, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a discrete gate or transistor logic device, or a discrete hardware component, which may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application. Further, a general purpose processor may be a microprocessor or any conventional processor or the like.

The Memory 120 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), and an electrically Erasable Programmable Read-Only Memory (EEPROM). The memory 120 is used for storing a program, and the processor 110 executes the program after receiving the execution instruction.

It should be noted that the structure shown in fig. 2 is only an illustration, and the computer device 100 provided in the embodiment of the present application may also have fewer or more components than those shown in fig. 2, or have a different configuration than that shown in fig. 2. Further, the components shown in fig. 2 may be implemented by software, hardware, or a combination thereof.

In the embodiment of the present application, the number of the computer devices 100 may be one or more. When the number of the computer devices 100 is plural, a plurality of computer devices 100 are communicatively connected.

Alternatively, when the number of the computer devices 100 is plural, the plural computer devices 100 may be connected to each other in a manner of secret-less access.

The hardware emulation accelerator 200 is explained below. In the embodiment of the present application, a file related to a chip to be tested runs in the hardware simulation accelerator 200.

Illustratively, the entire verification environment is compiled and loaded into the hardware simulation accelerator 200, so that the hardware simulation accelerator 200 simulates the relevant functions of the chip to be tested. The verification environment includes an RTL (Register Transfer Level) code and a testbench (test platform) code of the chip to be tested. The above-described loading is equivalent to distributing the computational effort of a large IC (Integrated Circuit) design to the various units in the hardware simulation accelerator 200.

The RTL code and the testbench code of the chip to be tested are files related to the chip to be tested.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating a possible hardware connection relationship before testing. Specifically, the hardware simulation accelerator 200 is physically connected to the plurality of computer devices 100 (computer device a, computer device B, and computer device C) through an optical fiber, and the plurality of computer devices 100 are connected to each other in a way of secret-less access. Hardware emulation accelerator 200 may support, but is not limited to, an ethernet interface, a SATA (Serial Advanced Technology Attachment) interface, a USB (Universal Serial Bus) interface, a PCIE (Peripheral Component Interconnect Express) interface, and a display interface.

The above-described interfaces can be divided into two categories. The first type of interface requires a motherboard (motherboard), such as a USB interface or a PCIE interface, during connection test. The second type of interface does not need to use a motherboard, such as an ethernet interface, a SATA interface, and a display interface, during connection test.

For the first type of interface, during testing, the connection relationship may be: the first type interface of the hardware simulation accelerator 200 is connected to one end of an optical fiber, and the other end of the optical fiber is connected to a speed reduction bridge (speedbridge) corresponding to the interface through a tpod (a type of hardware connector). The speed reducing bridge is inserted into the motherboard to supply power, and meanwhile, the other slot on the motherboard is inserted with the corresponding peripheral card.

It should be noted that, for the test of the high-speed peripheral, since the speed of the high-speed peripheral is very high in the real system, for example, the transmission rate of PCIE4.0 is 16GT/s (unit: precursor transmission/second), while when the test is performed on the hardware emulation accelerator 200, the speed is very slow, and the speed on the real board is about 2000 times faster than that on the hardware emulation accelerator 200. Thus, for testing of high-speed peripherals, the speed is reduced by the speed reduction bridge to match the speed of the hardware simulation accelerator 200.

Illustratively, when the first type of interface is a USB interface, the USB interface is connected to one end of an optical fiber, and the other end of the optical fiber is connected to a corresponding speed-down bridge of the USB interface through tpod. The speed reducing bridge is inserted into the motherboard for power supply, and the other slot on the motherboard is inserted with a corresponding peripheral card, such as a USB flash disk (short for USB flash disk) and a mouse.

When the first type of interface is a PCIE interface, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the PCIE interface through tpod. The speed reducing bridge is inserted on a motherboard to supply power, and meanwhile, another slot on the motherboard is inserted with a corresponding peripheral card, such as SATA, SSD (Solid State Disk or Solid State Drive), NIO (Non-blocking IO), or a network card. The network card may be a gigabit network card or a gigabit network card, and the present application is not limited thereto. When the network card is a gigabit network card, the gigabit network card is connected to the computer device 100 through a gigabit network cable; when the network card is a gigabit network card, the gigabit network card is connected to the computer device 100 through a gigabit network cable.

For the second type of interface, during testing, the connection relationship may be: the second type interface of the hardware simulation accelerator 200 is connected to the corresponding speed-down bridge of the interface through an optical fiber line, and a power box (chasis) is used for supplying power to the speed-down bridge, and the speed-down bridge is also connected to the computer device 100 through an optical fiber. Meanwhile, the speed reduction bridge is physically connected with the peripheral.

Illustratively, when the first type of interface is an ethernet interface, the ethernet interface of the hardware emulation accelerator 200 is connected to a speed-down bridge corresponding to the ethernet interface through an optical fiber line, and a power box is used to supply power to the speed-down bridge, and the speed-down bridge is further connected to the computer device 100 through an optical fiber. Meanwhile, the speed reduction bridge is physically connected with the network cable. The network cable is also physically connected to the computer device 100. The network cable may be a gigabit network cable or a gigabit network cable, and the present application is not limited thereto.

When the first type of interface is an SATA interface, the SATA interface of the hardware emulation accelerator 200 is connected to a speed-down bridge corresponding to the SATA interface through an optical fiber line, and a power box is used to supply power to the speed-down bridge, and the speed-down bridge is further connected to the computer device 100 through an optical fiber. Meanwhile, the speed reduction bridge is physically connected with the SATA or the SSD.

In addition, when the first type of interface is a display interface, the display interface is directly connected with a PC through a network cable.

It should be noted that, please refer to the prior art for the connection mode of each interface of the hardware simulation accelerator 200 during the simulation process, which is not described herein in detail.

The following describes an automated testing method provided in an embodiment of the present application. Referring to fig. 4, fig. 4 is a flowchart of steps of an automatic testing method provided in the embodiment of the present application, where the method may be applied to the automatic testing system 10 shown in fig. 1, where the automatic testing system 10 completes building of a hardware environment according to the connection relationship shown in fig. 3 (which type of interface is required to be tested, and then establishes a corresponding hardware connection relationship). It should be noted that, the automated testing method provided in the embodiment of the present application is not limited by the sequence shown in fig. 4 and the following, and the method includes: step S101-step S104.

Step S101: the computer device 100 receives a user initiated start-up emulation instruction.

When a user needs to test a function to be tested of a chip to be tested, the chip to be tested can be simulated through the hardware simulation accelerator 200. If the hardware simulation accelerator 200 is configured with a file related to the chip to be tested, the hardware simulation accelerator 200 can simulate the related function of the chip to be tested. And then, the user connects the corresponding interface according to the function to be tested. If a user needs to test the connection function of the USB interface of the chip to be tested, the USB interface is connected with one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the USB interface through the tpod. The speed reducing bridge is inserted in the motherboard to supply power, and the other slot on the motherboard is inserted in the USB flash disk.

For another example, when a user needs to test the network card function of the chip to be tested, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed-down bridge corresponding to the PCIE interface through the tpod. The speed reduction bridge is inserted into the motherboard to supply power, and simultaneously, the gigabit network card is inserted into the other slot on the motherboard.

For another example, when a user needs to test the SATA function of the chip to be tested, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the PCIE interface through the tpod. The speed reducing bridge is inserted in the motherboard to supply power, and the SATA is inserted in the other slot of the motherboard.

After the user has set up the above hardware environment, a start simulation instruction may be initiated to the computer device 100. For example, a user may click a button that initiates a simulation on a test interface displayed by computer device 100.

The user may be a tester performing automated testing.

Step S102: after receiving a user-initiated start simulation instruction, the computer device 100 executes a first connection function of the test script to trigger the hardware simulation accelerator 200 to execute a first connection command.

After the computer device 100 receives a user-initiated simulation starting instruction, the first connection function in the test script is executed, so that the hardware simulation accelerator 200 is triggered to execute the first connection command through the first connection function.

In one possible implementation, the test script may be an expect script. Of course, in other embodiments, the test script may be written in other languages as long as the script can implement automatic human-computer interaction, such as shell, python, ruby, and the like.

Step S103: hardware simulation accelerator 200 executes the first connection command to enable communication connection of computer device 100 with hardware simulation accelerator 200.

The communication connection between the computer device 100 and the hardware emulation accelerator 200 can be made by a first connection command of the hardware emulation accelerator 200 itself.

In this embodiment, the first connection command executed by the hardware emulation accelerator 200 may be its xecl command. Of course, in other embodiments, other connection commands supported by hardware emulation accelerator 200 that enable the above-described communication connection may also be implemented.

Step S104: after the hardware simulation accelerator 200 executes the first connection command, the computer device 100 executes the configuration function of the test script to configure the function to be tested of the chip to be tested based on the configuration procedure corresponding to the configuration function.

After the hardware simulation accelerator 200 executes the first connection command to realize the communication connection with the hardware simulation accelerator 200, the computer device 100 executes the configuration function of the test script, and then configures the function to be tested of the chip to be tested based on the configuration procedure corresponding to the configuration function. When executing the configuration function of the test script, the computer device 100 outputs a configuration instruction corresponding to each configuration process, and automatically performs configuration of the next configuration process when the previous configuration process is completed.

For example, after the computer device 100 establishes a communication connection with the hardware simulation accelerator 200, a first configuration procedure in the configuration function of the test script is executed, that is, the computer device 100 outputs a configuration instruction corresponding to the first configuration procedure to the hardware simulation accelerator 200. Hardware simulation accelerator 200 is configured based on a first configuration pass. When the computer device 100 determines that the first configuration procedure of the hardware simulation accelerator 200 is completed, the second configuration procedure in the configuration function of the test script is executed, that is, the computer device 100 outputs an instruction corresponding to the second configuration procedure to the hardware simulation accelerator 200. Hardware simulation accelerator 200 is configured based on the second configuration pass. And so on until the computer device 100 has performed all configuration procedures in the configuration function of the test script.

The configuration process may specifically include boot of a boot loader, boot of an operating system (os), driver loading of the function to be tested, and parameter configuration of the function to be tested.

The uboot guidance is a first configuration procedure, the operating system guidance is a second configuration procedure, the drive loading of the function to be tested is a third configuration procedure, and the parameter configuration of the function to be tested is a fourth configuration procedure.

Illustratively, when the function to be tested is a network card function, the third configuration process is the drive loading of the network card, and the fourth configuration process is the configuration of an IP (Internet Protocol) address.

When the function to be tested is the function of connecting the PCIE interface with the SATA, the third configuration procedure is the installation of the SATA drive, and the fourth configuration procedure is the mount operation of the SATA, namely mounting.

Therefore, in the embodiment of the application, when the configuration process includes uboot boot, operating system boot, driver loading of the function to be tested, and parameter configuration of the function to be tested, full-stage automatic configuration can be realized.

In summary, in the embodiment of the present application, after receiving the simulation starting instruction initiated by the user, the computer device 100 may automatically execute the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command, so that the computer device 100 establishes a communication connection with the hardware simulation accelerator 200. By the method, interaction between the computer device 100 and the hardware simulation accelerator 200 can be realized, and further, the subsequent computer device can complete configuration of the hardware simulation accelerator 200 through the configuration function of the test script. In addition, because the test script outputs the configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically performed, the manual intervention of the hardware simulation accelerator 200 in the configuration process is reduced through the above method, and the configuration efficiency is improved.

In one embodiment, hardware simulation accelerator 200 also runs a serial port model. The serial port model can be understood as an abstracted model based on the characteristics of the serial port chip. The serial port model has the following characteristics: firstly, serial port chips are simulated (the functions of the serial port chips and the serial port chips are completely equivalent); secondly, the input value and the output value of the serial port model and the serial port chip are the same.

In the embodiment of the present application, the serial port model is configured to input a force mode using the hardware simulation accelerator 200, and output a display cache (display) mode using a debugging script language supported by the hardware simulation accelerator 200.

The debugging script Language supported by the hardware simulation accelerator 200 may be a State Description Language (SDL).

Referring to fig. 5, the interaction process between the computer device 100 and the hardware simulation accelerator 200 when executing the configuration function of the test script specifically includes: step S201-step S205.

Step S201: the computer device 100 outputs a first configuration instruction corresponding to the first configuration procedure to the serial port model through the test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator 200 in a force manner; the first arrangement step is any one of the arrangement steps.

Step S202: after receiving the first configuration instruction, the serial port model run by the hardware simulation accelerator 200 inputs the first configuration instruction into the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 executes the first configuration instruction for configuration.

Step S203: the serial port model run by the hardware simulation accelerator 200 captures actual characters generated when the first configuration instruction is executed through a debugging script language supported by the hardware simulation accelerator 200, and outputs the actual characters to the computer device through a display cache mode.

Step S204: the computer device 100 compares the preset expected finished character with the actual character through the comparison instruction in the configuration function to determine whether the first configuration process is finished.

In this embodiment, the test script is preset with expected completion characters corresponding to each configuration process. When the computer device 100 receives the actual character output by the serial port model operated by the hardware simulation accelerator 200, the actual character is compared with the expected completion character corresponding to the current configuration procedure. If the current configuration procedure is the first configuration procedure, the computer equipment compares the actual character with the expected finished character corresponding to the first configuration procedure through the comparison instruction in the configuration function. And if the actual character is the same as the expected finished character corresponding to the first configuration process, determining whether the first configuration process is the last configuration process. If the first allocation procedure is not the last allocation procedure, step S205 is executed. If the first configuration process is the last configuration process, the automated configuration of the hardware simulation accelerator 200 is completed.

If the actual character is different from the expected completion character corresponding to the first configuration procedure, it is determined that the first configuration procedure is not completed, and at this time, the hardware simulation accelerator 200 continues to wait for the actual character output next time, or the user is notified to switch to the manual configuration mode, so that the user performs manual configuration.

Step S205: when the computer device 100 determines that the first configuration procedure is completed, a second configuration instruction corresponding to a second configuration procedure is output to the serial port model through the test script, wherein the second configuration procedure is the next configuration procedure of the first configuration procedure.

When the computer device 100 determines that the first configuration procedure is completed and the first configuration procedure is not the last configuration procedure, a second configuration instruction corresponding to the second configuration procedure is automatically output to the serial port model through the test script, and the second configuration procedure is the next configuration procedure of the first configuration procedure. After receiving the second configuration instruction, the serial port model run by the hardware simulation accelerator 200 inputs the second configuration instruction into the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 executes the second configuration instruction for configuration. Then, the serial port model run by the hardware simulation accelerator 200 captures an actual character generated when the second configuration instruction is executed through the debugging script language supported by the hardware simulation accelerator 200, and outputs the latest actual character to the computer device 100 in a display cache manner. The computer device 100 compares the latest actual character with the expected finished character corresponding to the second configuration process through the comparison instruction in the configuration function. If the latest actual character is the same as the expected finished character corresponding to the second configuration process, determining whether the second configuration process is the last configuration process. And if the second configuration procedure is not the last configuration procedure, outputting a third configuration instruction corresponding to the third configuration procedure to the serial port model through the test script, wherein the third configuration procedure is the next configuration procedure of the second configuration procedure, and so on. If the second configuration process is the last configuration process, the automated configuration of the hardware simulation accelerator 200 is completed.

Illustratively, when the function to be tested is a network card function, the process specifically includes: the computer device 100 outputs a uboot through the test script to guide the corresponding configuration instruction to the serial port model. After receiving the configuration instruction, the serial port model run by the hardware simulation accelerator 200 inputs the configuration instruction into the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 performs uboot guidance. Then, the serial port model run by the hardware simulation accelerator 200 captures an actual character generated when the configuration instruction is executed through a debugging script language supported by the hardware simulation accelerator 200, and outputs the actual character to the computer device 100 in a display cache manner. The computer device 100 compares the preset expected completion character with the actual character through the comparison instruction in the configuration function to determine whether the uboot guidance is completed. When determining that the uboot guidance is completed, the computer device 100 outputs a configuration instruction corresponding to the guidance of the operating system to the serial port model through the test script, and after the serial port model operated by the hardware simulation accelerator 200 receives the configuration instruction, the configuration instruction is input into the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 performs the guidance of the operating system. Then, the serial port model run by the hardware simulation accelerator 200 captures an actual character generated when the configuration instruction is executed through a debugging script language supported by the hardware simulation accelerator 200, and outputs the actual character to the computer device 100 in a display cache manner. The computer device 100 compares the preset expected completion character with the actual character through the comparison instruction in the configuration function to determine whether the booting of the operating system is completed. When the computer device 100 determines that the booting of the operating system is completed, the test script outputs a network card driver to load a corresponding configuration instruction to the serial port model, and after the serial port model operated by the hardware simulation accelerator 200 receives the configuration instruction, the configuration instruction is input to the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 loads the network card driver. Then, the serial port model run by the hardware simulation accelerator 200 captures an actual character generated when the configuration instruction is executed through a debugging script language supported by the hardware simulation accelerator 200, and outputs the actual character to the computer device 100 in a display cache manner. The computer device 100 compares the preset expected completion character with the actual character through the comparison instruction in the configuration function to determine whether the network card driver loading is completed. When the computer device 100 determines that the loading of the network card driver is completed, the configuration instruction corresponding to the configuration of the IP address is output to the serial port model through the test script, and after the serial port model operated by the hardware simulation accelerator 200 receives the configuration instruction, the configuration instruction is input to the hardware simulation accelerator 200 in a force manner, so that the hardware simulation accelerator 200 performs the configuration of the IP address (where, the IP address is configured to be in the same network segment as the connected computer device). Then, the serial port model run by the hardware simulation accelerator 200 captures an actual character generated when the configuration instruction is executed through a debugging script language supported by the hardware simulation accelerator 200, and outputs the actual character to the computer device 100 in a display cache manner. The computer device 100 compares the preset expected completion character with the actual character through the comparison instruction in the configuration function to determine whether the configuration of the IP address is completed. When the configuration of the IP address is completed, the automatic configuration of the hardware simulation accelerator 200 when the function to be tested is the network card function is completed.

Therefore, in the embodiment of the present application, the configuration difficulty of the hardware simulation accelerator 200 in the hardware environment can be reduced by replacing the conventional serial port chip with the serial port model. And the serial port model sends the output actual characters to the computer equipment 100 in a display cache mode, so that a user can visually see the process of each configuration stage, the problem analysis is facilitated for the user, and the test efficiency in a complex scene is greatly improved. In addition, the computer device 100 may compare the preset expected completion character with the actual character output by the serial port model through the comparison instruction in the configuration function, and then determine whether to output the configuration instruction corresponding to the next configuration procedure to the serial port model according to the comparison result, so as to implement automatic triggering of the next configuration procedure, and further implement automation of the whole configuration process of the test script.

Optionally, the actual character is successfully recognized through recognition of the serial port model before being output through a display cache mode.

That is, a function for preventing character loss can be added in the serial port model. Take the debug script language supported by hardware emulation accelerator 200 as SDL for example. After the serial port model captures the characters, the SDL load function in the SDL is utilized, when the characters are not output, whether the characters are identified by the SDL tool or not is detected through the load function, and if the characters are identified, the characters are output. Otherwise, the serial port model will automatically re-input the previously input character into the SDL, so as to ensure that the character can be recognized after the load, thereby ensuring that the input character can be correctly output.

Therefore, in the embodiment of the application, the serial port model is further used for recognizing the characters before the actual characters are output. The serial port model can be output only under the condition that the characters can be successfully identified, the accuracy and the reliability of the serial port model in application can be guaranteed through the method, and the problem that the serial port model still outputs the characters under the condition that the characters are lost so as to cause follow-up comparison errors is avoided.

In addition, the hardware simulation accelerator 200 may also implement instruction input and actual character output through a conventional serial port chip, which is not limited in this application.

After the automatic configuration of the hardware simulation accelerator 200 is completed, the function to be tested of the chip to be tested can be tested.

In some embodiments, if it is determined that the previous configuration process is completed and the previous configuration process is the last process in the configuration processes, the test on the function to be tested may be automatically triggered, or a manual trigger mode may be switched to, and the user performs a manual test on the function to be tested.

The following will describe an implementation manner of performing an automated test by taking a case of automatically triggering a test on a function to be tested as an example.

In an embodiment, with continuing reference to fig. 3, the computer device 100 is further configured to connect to another computer device 100, the network card connected to the hardware simulation accelerator 200 is connected to the other computer device 100 through a network cable, and after it is determined that the configuration procedure of the function to be tested of the chip to be tested is completed, the method further includes: the computer device 100 executes the second connection function of the test script to enable the computer device 100 to automatically remotely log into the hardware simulation accelerator 200 and test the function to be tested by running the test program.

Specifically, the computer device 100 executes the second connection function of the test script after determining that the last configuration procedure of the function to be tested of the chip to be tested is completed. A configured network is connected through an SSH (Secure Shell protocol) port of the computer device 100, and then enters the hardware simulation accelerator 200 through a test script, so as to run a test program to test a function to be tested.

It can be seen that, in the embodiment of the present application, when the network card connected to the hardware simulation accelerator 200 is connected to the other computer device 100 through the optical fiber, and the computer device 100 connected to the other computer device 100 determines that the configuration procedure of the function to be tested is configured, the second connection function of the test script may be automatically executed, so that the computer device 100 automatically logs in to the hardware simulation accelerator in a remote manner, and simultaneously tests the function to be tested through the test program.

In this embodiment of the present application, the test script may be an expect script, and the computer device 100 executes a second connection function of the test script, including: the computer apparatus 100 connects the SSH port of the computer apparatus 100 with the network configured by the hardware emulation accelerator 200 by the spawn command in the expect script. Wherein, the spawn command is provided with the address of the network.

In the embodiment of the application, the spawn command in the expect script is modified and carries the address of the network, so as to connect the SSH port of the computer device 100 with the network configured by the hardware simulation accelerator 200. Further, since the spawn command has a function of starting a new process, it can satisfy the requirement of simultaneously starting test connections between a plurality of computer devices 100 and the hardware simulation accelerator 200, and further can simultaneously test a plurality of functions to be tested of the chip to be tested.

Taking the network card testing process as an example: when the network card has successfully loaded the driver and has configured the IP address, the computer apparatus 100 executes the second connection function of the test script. The computer apparatus 100 connects to the network through a spawn command in an expect script, which may be spawn sh-c "SSH-t server1 telnet $ IP _ ADDR", over a network configured over an SSH (Secure Shell protocol) connection of the computer apparatus 100. Finally, the test script enters the hardware simulation accelerator 200, and then a network card test program is run for testing. The network card test program may be a network performance test program.

Taking the function test flow of the PCIE interface connection SATA as an example: when the SATA driver has been successfully loaded and mount the mount successfully, and then the SATA driver is connected to the network through SSH (Secure Shell protocol) of the computer apparatus 100, the computer apparatus 100 connects to the network through a spawn command in the expect script, which may be spawn sh-c "SSH-t server1 telnet IP _ ADDR" as in the network card test procedure. Finally, the hardware simulation accelerator 200 is entered through the test script, and the SATA test program is run for testing. The SATA test program may be a disk performance test program.

In addition, when there are a plurality of computer apparatuses 100, only one of the computer apparatuses 100 needs to be connected to the network. Because the computer devices 100 are interconnected, testing can be performed on multiple computer devices 100 simultaneously. Of course, any one of the computer apparatuses 100 may be selected to perform the test of the function to be tested. As shown in fig. 6, after the computer device a is connected to the configured network, the computer device a may establish two test connections with the hardware simulation accelerator 200 to perform the network card test and the SATA test, and at this time, the computer device B may also establish a test connection with the hardware simulation accelerator 200 to perform the USB test.

In one embodiment, the computer device 100 is also configured to connect to other computer devices 100 via a secure access. For example, in fig. 3, a secret-less access is available between the computer device a and the computer device B, a secret-less access is available between the computer device a and the computer device C, and a secret-less access is available between the computer device B and the computer device C.

In the embodiment of the present application, since the computer device 100 can be connected with other computer devices 100 in a way of being without secret access, different computer devices 100 can realize quick access with the hardware simulation accelerator 200 and perform testing.

Referring to fig. 7, based on the same inventive concept, an embodiment of the present application further provides an automatic testing apparatus 300, which is applied to a computer device 100, where the computer device 100 is used to be physically connected to a hardware simulation accelerator 200, and the hardware simulation accelerator 200 runs a file related to a chip to be tested to test a function of the chip to be tested; the automated testing apparatus 300 includes:

the starting module 310 is configured to receive a user-initiated simulation starting instruction.

The first connection module 320 is configured to execute a first connection function of a test script after the start module receives a start simulation instruction initiated by a user, so as to trigger the hardware simulation accelerator to execute a first connection command, thereby implementing communication connection between the computer device and the hardware simulation accelerator;

a configuration module 330, configured to execute a configuration function of the test script after the hardware simulation accelerator executes the first connection command, so as to configure a function to be tested of the chip to be tested based on a configuration procedure corresponding to the configuration function; when the configuration function of the test script is executed, the test script outputs a configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically carried out.

Optionally, the hardware simulation accelerator further runs a serial port model; the configuration module 330 is specifically configured to output a first configuration instruction corresponding to a first configuration procedure to the serial port model through the test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator in a force manner; the first arrangement step is any one of the arrangement steps; receiving actual characters output by the serial port model in a display cache mode, wherein the actual characters are characters which are generated when the hardware simulation accelerator executes the first configuration instruction and are captured by a debugging script language supported by the hardware simulation accelerator; comparing a preset expected finished character with the actual character through a comparison instruction in the configuration function to determine whether the first configuration procedure is finished or not; and when the first configuration procedure is determined to be completed and is not the last configuration procedure, outputting a second configuration instruction corresponding to a second configuration procedure to the serial port model through the test script, wherein the second configuration procedure is the next configuration procedure of the first configuration procedure.

Optionally, the configuration procedure in the configuration module 330 includes uboot boot, operating system boot, driver loading of the function to be tested, and parameter configuration of the function to be tested.

Optionally, the computer device is further configured to be connected to another computer device, the network card connected to the hardware simulation accelerator is connected to the other computer device through a network cable, and the automatic testing apparatus 300 further includes: a second connection module;

and the second connection module is used for executing the second connection function of the test script after the configuration procedure of the function to be tested of the chip to be tested is determined to be configured, so that the computer equipment can automatically log in the hardware simulation accelerator remotely, and the function to be tested can be tested by running a test program.

Optionally, the test script is an expect script. The second connection module is specifically configured to connect, through a spawn command in the expect script, an SSH port of the computer device with a network configured by the hardware simulation accelerator; wherein the spawn command is provided with an address of the network.

It should be noted that, as those skilled in the art can clearly understand, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

Based on the same inventive concept, embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the computer program performs the methods provided in the above embodiments.

The storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An automatic test method is characterized by being applied to computer equipment, wherein the computer equipment is used for being physically connected with a hardware simulation accelerator, and the hardware simulation accelerator runs a file related to a chip to be tested so as to test the function to be tested of the chip to be tested; the method comprises the following steps:

after receiving a simulation starting instruction initiated by a user, the computer equipment executes a first connection function of a test script to trigger the hardware simulation accelerator to execute a first connection command, so that the communication connection between the computer equipment and the hardware simulation accelerator is realized;

after the hardware simulation accelerator executes the first connection command, the computer equipment executes a configuration function of the test script so as to configure a function to be tested of the chip to be tested based on a configuration procedure corresponding to the configuration function;

when the configuration function of the test script is executed, the test script outputs a configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically carried out.

2. The method of claim 1, wherein the hardware simulation accelerator is further run with a serial port model; the executing the configuration function of the test script comprises:

the computer equipment outputs a first configuration instruction corresponding to a first configuration procedure to the serial port model through the test script so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator in a force mode; the first arrangement step is any one of the arrangement steps;

the computer equipment receives actual characters output by the serial port model in a display cache mode, wherein the actual characters are characters which are generated when the hardware simulation accelerator executes the first configuration instruction and are captured by a debugging script language supported by the hardware simulation accelerator;

the computer equipment compares a preset expected finished character with the actual character through a comparison instruction in the configuration function so as to determine whether the first configuration procedure is finished;

and when the computer equipment determines that the first configuration procedure is finished and the first configuration procedure is not the last configuration procedure, outputting a second configuration instruction corresponding to a second configuration procedure to the serial port model through the test script, wherein the second configuration procedure is the next configuration procedure of the first configuration procedure.

3. The method of claim 2, wherein the actual character is successfully recognized and recognized through the serial port model before being output through the display buffer mode.

4. The method of claim 1, wherein the configuration process comprises uboot boot, operating system boot, driver loading of the function under test, and parameter configuration of the function under test.

5. The method according to any one of claims 1 to 4, wherein the computer device is further configured to connect to another computer device, the network card connected to the hardware simulation accelerator is connected to the other computer device through a network cable, and after it is determined that the configuration procedure of the function to be tested of the chip to be tested has been completed, the method further includes:

and the computer equipment executes the second connection function of the test script to realize that the computer equipment automatically remotely logs in the hardware simulation accelerator and tests the function to be tested by running a test program.

6. The method of claim 5, wherein the test script is an expect script, and wherein the computer device performs a second connection function of the test script, comprising:

the computer equipment connects an SSH port of the computer equipment with a network configured by the hardware simulation accelerator through a spawn command in the expect script; wherein the spawn command is provided with an address of the network.

7. The method of claim 5, wherein the computer device is further configured to connect with the other computer device in a manner that is not cryptographically accessible.

8. An automatic testing device is applied to computer equipment, the computer equipment is used for being physically connected with a hardware simulation accelerator, and the hardware simulation accelerator runs a file related to a chip to be tested so as to test the function to be tested of the chip to be tested; the device comprises:

the starting module is used for receiving a starting simulation instruction initiated by a user;

the first connection module is used for executing a first connection function of a test script after the start module receives a start simulation instruction initiated by a user, so as to trigger the hardware simulation accelerator to execute a first connection command, and realize the communication connection between the computer equipment and the hardware simulation accelerator;

the configuration module is used for executing the configuration function of the test script after the hardware simulation accelerator executes the first connection command so as to configure the function to be tested of the chip to be tested based on the configuration procedure corresponding to the configuration function; when the configuration function of the test script is executed, the test script outputs a configuration instruction corresponding to each configuration procedure, and when the previous configuration procedure is completed, the configuration of the next configuration procedure is automatically carried out.

9. A computer device, comprising: a processor and a memory, the processor and the memory connected;

the memory is used for storing programs;

the processor is configured to execute a program stored in the memory to perform the method of any of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored which, when executed by a computer, performs the method of any one of claims 1-7.