TWI794647B - 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置 - Google Patents

一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置 Download PDF

Info

Publication number
TWI794647B
TWI794647B TW109132386A TW109132386A TWI794647B TW I794647 B TWI794647 B TW I794647B TW 109132386 A TW109132386 A TW 109132386A TW 109132386 A TW109132386 A TW 109132386A TW I794647 B TWI794647 B TW I794647B
Authority
TW
Taiwan
Prior art keywords
igbt
bipolar transistor
gate bipolar
insulated gate
super junction
Prior art date
Application number
TW109132386A
Other languages
English (en)
Other versions
TW202113983A (zh
Inventor
馬督兒 博德
管靈鵬
卡爾提克 帕德瑪納罕
徐範錫
Original Assignee
加拿大商萬國半導體國際有限合夥公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 加拿大商萬國半導體國際有限合夥公司 filed Critical 加拿大商萬國半導體國際有限合夥公司
Publication of TW202113983A publication Critical patent/TW202113983A/zh
Application granted granted Critical
Publication of TWI794647B publication Critical patent/TWI794647B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664Vertical bipolar transistor in combination with diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一種改良絕緣閘極雙極性電晶體(IGBT)的輕負載效率裝置包括一個絕緣閘極雙極性電晶體(IGBT)和超級接面金氧半場效電晶體(超級接面MOSFET),其中絕緣閘極雙極性電晶體和超接合面金屬氧化物半導體場效電晶體是電耦合的,還可選擇結構耦合的。

Description

一種改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝 置
本創作涉及電晶體領域,尤其是一種改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置。
各種現代應用都使用電子開關來執行不同的操作功能。雖然有許多不同類型的電子開關,包括繼電器,電晶體和真空管等。但是目前,電子電路中仍然主要使用固態電晶體。電晶體主要分為以下兩大類型:絕緣閘極雙極性電晶體(IGBT)和金屬-氧化物半導體場效電晶體(MOSFET)。
與MOSFET相比,IGBT具有優良的高電流電導特性。MOSFET的“接通”狀態電導率在標準溫度下是線性的,可以利用RDSon,建模成為一個電阻器。另一方面,IGBT的電導率在標準溫度下是非線性的,可以更好地建模為二極體。另外,IGBT與MOSFET相比,在處理較高的電流密度時表現更加出色,與超級接面金氧半場效電晶體(超級接面MOSFET)相比,具有極其簡單的/較低成本的製程技術。因此,IGBT因其具有相對低的電阻和相對低的成本,是理想的高電流應用。
儘管IGBT擁有許多優於MOSFET的優良特性,但是也存在一些明顯的不足。其中一個不足就是IGBT在低電流下具有一個“接通”狀態電壓閾值Vth, 並且只有當電壓超過閾值之後,才會開始傳導。這就意味著對於低安培和電壓應用來說,傳統的IGBT與MOSFET相比,具有相當高的導電損耗,在非零電壓下的“接通”狀態中,而沒有任何處於它們的輸出特性的二極體拐點。IGBT的另一個不足是由於它的結構,它無法在反向電流方向傳導電流,而MOSFET具有一個內置的體二極體,可以反轉電流方向傳導。
為了克服這個問題,二極體可以放置在反平行於IGBT的地方,這通常稱為整流二極體。整流二極體解決了反向電流方向傳導的問題,但是無法解決電壓閾值的問題。因此,它有利於配置IGBT封裝,IGBT封裝可以在低安培下傳導,並具有良好的反向電流傳導特性。
正是在這一前提下,本創作提出了各種實施例做為新的技術方案以解決現存的技術問題。
本創作公開了一種改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,包括:一個絕緣閘極雙極性電晶體,具有一個摻雜立柱在本體區下方,摻雜立柱延伸到絕緣閘極雙極性電晶體的漂流區中;以及一個超級接面金氧半場效電晶體(即超級接面MOSFET),其中絕緣閘極雙極性電晶體的射極和超級接面MOSFET的源極導電耦合,絕緣閘極雙極性電晶體的集極和超級接面MOSFET的汲極導電耦合,絕緣柵雙極電晶體的閘極和超級接面MOSFET的閘極導電耦合。
其中,超級接面MOSFET的體二極體和絕緣閘極雙極性電晶體是反並聯的。
其中,絕緣閘極雙極性電晶體和超級接面MOSFET都位於同一個電路板上。
其中,絕緣閘極雙極性電晶體和超級接面MOSFET位於同一個基板中。
其中,絕緣閘極雙極性電晶體和超級接面MOSFET位於同一個積體電路封裝中。
其中,在“接通”狀態下,當電流小於一額定電流時,大部分的電荷都流經超級接面金屬-氧化物半導體場效電晶體。
其中,在“接通”狀態下,當電流大於一額定電流時,大部分的電荷都流經絕緣閘極雙極性電晶體。
其中,絕緣閘極雙極性電晶體為一個平面柵絕緣閘極雙極性電晶體。
其中,配置絕緣閘極雙極性電晶體和超級接面MOSFET,使其具有閘極源極電壓閾值在彼此的±2伏特以內。
其中,超級接面MOSFET穿插在基板中的絕緣閘極雙極性電晶體之間。
其中,絕緣閘極雙極性電晶體與超級接面MOSFET共用一個漂流區,並且其中共用的漂流區對於絕緣閘極雙極性電晶體和超級接面MOSFET來說處於相同的摻雜濃度。
其中,有多個本體區和摻雜立柱,其中多個摻雜立柱延伸在漂流區中,並且其中本體區和摻雜立柱具有相同的導電類型。
101:射極金屬
102:遮罩溝槽電介質
103:遮罩溝槽電極
104:重摻雜射極區
105:本體區
106:重摻雜區
107:輕摻雜漂流區
108:平面閘極絕緣層
109:閘極電極層
110:遮罩溝槽電極
111:電介質
112:緩衝區
113:輕摻雜層
114:重摻雜層
115:集極
201:IGBT
202:二極體
301:IGBT
302:超級接面MOSFET
303:節點
304:節點
305:節點
401:IGBT
402:超級接面MOSFET
403:外延層
404:閘極絕緣物
405:閘極電極
406:漂流區
407:源極區
408:本體區
409:摻雜立柱
410:重摻雜底層
411:基板接頭
412:輕摻雜外延漂流區
413:重摻雜緩衝區
414:輕摻雜層
415:底層
416:重摻雜區
417:接觸金屬
418:遮罩溝槽電介質
419:遮罩溝槽電極
420:本體區
421:射極區
422:閘極電極
423:絕緣層
424:電介質
425:遮罩溝槽電極
501:底層
502:超級接面MOSFET基板區
601:IGBT部分
602:超級接面部分
603:接觸金屬層
604:射極層
605:本體區
606:摻雜立柱
607:漂流區
608:閘極絕緣層
609:閘極電極
610:注入區
611:輕摻雜層
612:底層
613:基板接觸層
701:IGBT
702:超級接面MOSFET
703:射極接觸金屬層
704:源極接觸金屬層
705:閘極電極引線
706:射極接觸引線
707:集極接觸引線
708:漂流區
709:外延/漂流區
710:汲極接頭
711:集極接頭
712:基板層
714:超級接面MOSFET部分
715:IGBT部分
716:緩衝物
717:輕摻雜區
718:注入層
801:IGBT曲線
802:超級接面MOSFET曲線
803:超級接面MOSFET曲線
804:IGBT曲線
805:超級接面MOSFET曲線
806:超級接面MOSFET曲線
901:曲線
902:曲線
903:曲線
904:曲線
圖1為沒有整流二極體的原有技術的IGBT的示意圖。
圖2為在IGBT中加置整流二極體的一種原有技術的一個示例的電路圖。
圖3為本創作的其中一個實施例中,一種耦合超級接面MOSFET及IGBT的電路圖。
圖4為本創作的其中一個實施例中,一種在結構上耦合了超級接面MOSFET及GBT的側視圖。
圖5為本創作的其中一個實施例中,一種在結構上耦合了超級接面MOSFET的一種IGBT的仰視圖。
圖6為本創作的其中一個實施例中,在同一個基板上結構耦合了超級接面MOSFET並且具有很深的超級接面類似的摻雜立柱的IGBT的側視圖。
圖7為本創作的的其中一個實施例中,IGBT射極和集極分別導電耦合到超級結MOSFET的源極和汲極上的IGBT側視圖。
圖8A為本創作中,在25℃下,電流與電壓的關係曲線圖。
圖8B為本創作中,在125℃下,電流與電壓的關係曲線圖。
圖9A為本創作中,在25℃下,電流與電壓的關係曲線圖。
圖9B為本發明中,在125℃下,電流與電壓的關係曲線圖。
下面將結合本創作實施例中的附圖,對本創作實施例中的技術方案進行清楚、完整地描述;需要說明的是,本實施例以本技術方案為前提,給出了詳細的實施方式和具體的操作過程,顯然,所描述的實施例僅僅是本創作一部分實施例,而不是全部的實施例,故本創作的保護範圍並不限於本實施例。基於本創作中的實施例,本領域普通技術人員在沒有做出創造性勞動前提下所獲得的所有其他實施例,都屬於本創作保護的範圍。
另外,文中所述的濃度、數量及其他數值數據可以在一定範圍內。 應理解的是,這種範圍格式的使用僅僅是為了方便和簡潔,而且應靈活解釋, 在以下具體實施例的說明中,第一導電類型通常為N型,第二導電類型通常為P型。然而,要注意的是基本上類似的元件都可以用類似的製程技術進行製作,但是導電類型可能與所述類型相反。確切地說,本創作的各個方面包括所述的實施例,其中用P代替N,反之亦然。
絕緣閘極雙極性電晶體(以下簡稱IGBT)通常具有優於金屬氧化物半導體場效電晶體(以下簡稱MOSFET)的高安培導電性能。IGBT的製備方式通常與MOSFET類似,但是除此之外,IGBT還可以擁有一個額外的摻雜層。因此,MOSFET可以具有一種N-摻雜層、P-摻雜層、N-摻雜層的摻雜結構。IGBT將具有P、N、P、N或N、P、N、P的摻雜結構。
如圖1所示,圖1表示一種習知技術的IGBT的層結構。IGBT具有第一導電類型的輕摻雜漂流區107(例如N-摻雜)。根據所需的擊穿電壓值,該輕摻雜漂流區107的摻雜濃度可以在1e13cm-3至5e14cm-3之間。輕摻雜漂流區107的較低的摻雜濃度會産生較高的擊穿電壓。一個第一導電類型的較重摻雜的緩衝區112,在該輕摻雜漂流區107下方。緩衝區112的摻雜濃度可以在1e15cm-3至5e16cm-3之間。任一種導電類型的輕摻雜層113來自於初始的基板材料,位於緩衝區112下方。輕摻雜層113的摻雜濃度通常在1e15cm-3以下。第二導電類型的重摻雜層114位於輕摻雜層113下方。重摻雜層114構成IGBT的集極115,可以在外延生長過程中,從背部或正面注入。其摻雜濃度在1e17cm-3至1e19cm-3之間。集極115接觸金屬層形成在集極115的底部。
輕摻雜漂流區107的上方是第一導電類型的重摻雜區106。本體區105位於重摻雜區106上方。本體區105可以摻雜第二導電類型。本體區105可以具 有1e17cm-3至1e18cm-3之間的摻雜濃度。本體區105具有一個第一導電類型的重摻雜發射區,位於重摻雜射極區104上方。源極區的摻雜濃度可以在2e19cm-3左右以上。
遮罩溝槽可以形成在基板中,終止在輕摻雜漂流區107的深度。遮罩溝槽內,襯入電介質111(例如一個氧化層)。遮罩溝槽電極110放置在電介質上方,並且處於射極電壓。例如,遮罩溝槽電極可以是一個多晶矽層。平面閘極由一個平面閘極絕緣層108(例如一個閘極氧化層)和一個閘極電極層109構成,形成在遮罩溝槽電極110上方,並且延伸到射極區上方。閘極電極層109形成在閘極絕緣層上方,更多平面閘極絕緣層108形成在閘極電極附近,使閘極電極層109與射極金屬101絕緣。僅作為示例,但不作為局限,可以用一個多晶矽層製備閘極電極層。
如1圖所示,不是所有的遮罩溝槽電極都被平面閘極覆蓋。閘極氧化層和閘極電極不會覆蓋遮罩溝槽電介質102以及遮罩溝槽電極103。遮罩溝槽用作補償N+區,並且保持很高的擊穿電壓。
如圖2所示,IGBT 201以及二極體202的電路圖。由於IGBT 201的結構以及反轉偏壓,使得反向電流不會流經IGBT 201。配置IGBT 201,使得當閘極G上加載的電壓高於閘極-射極電壓閾值(Vge(th))時,電流從集極C流至射極E。加載到集極的反向偏壓不會産生流經IGBT 201的電流。為了克服這個問題,之前的IGBT電路設計了一個二極體202,反並聯於IGBT 201。根據本創作,反並聯是指元件為並聯,但是配置成當集極上加載反向偏壓時會導電。參見圖2,二極體202的陽極連接到IGBT 201的集極,二極體的陰極連接到IGBT 201的射極。
依據本創作,利用超級接面MOSFET 302與IGBT 301並聯,而不是與整流二極體並聯,來改良設計。
如圖3所示,本創作的一個實施例二,其中IGBT 301結構上連接到超級接面MOSFET 302。另外,通過共用同一個接觸層,IGBT 301導電耦合到超級接面MOSFET 302上。IGBT 301表示為一個N-通道的IGBT,超級接面MOSFET表示為一個N-通道的超級接面MOSFET。IGBT 301的閘極G以及超級接面MOSFET 302的閘極G,導電耦合到節點303處上。IGBT 301和超級接面MOSFET連接在一起,IGBT301的VGE(th)以及超級接面MOSFET的VGS(th)應在類似的範圍內,例如各自的±2伏特以內。由於閘極的導電耦合,以及IGBT 301和超級接面MOSFET 302類似的啟動閾值,當IGBT 301上加載了足夠的電壓將元件置於“接通”狀態時,超級接面MOSFET302應也處於“接通”狀態。IGBT 301的集極C以及超級接面MOSFET 302的汲極D也可以導電耦合於節點304處。IGBT 301的射極E以及超級接面MOSFET 302的源極S,也可以導電耦合於節點305處。用於此目的的超級接面MOSFET 302,包括一個快恢復二極體,可以利用電子輻射等方法,減小超級接面MOSFET 302的少數載流子壽命來製作快恢復二極體。
另外,當如上所述配置超級接面MOSFET 302時,超級接面MOSFET302的快恢復二極體與IGBT 301反並聯。因此,當反向偏壓和反向電流模式下運行時,超級接面MOSFET 302的快恢復二極體可以作為IGBT 301的整流二極體。
上文所述的導電耦合是指在允許電子從一個元件流動至另一個元件的兩個元件之間的電路連接。電路連接可以通過導線、金屬引線、導電凝膠、金屬化玻璃、金屬化塑膠等類似的任意導電材料進行連接。結構耦合是指兩個元 件相互貼合,或者貼合到同一結構或表面上,其中貼合可以是具可撓曲性或剛性連接。結構或表面可以是本領域中習知的任意表面,例如但不僅限於PCB、積體電路封裝、金屬表面、塑膠表面、木制表面或其他類似物。
如圖4所示,本創作的另一個實施例三,其中IGBT 401和超級接面MOSFET 402通過相同的基板、外延層和接觸層結構耦合。基板和外延層包括IGBT 401和超級接面MOSFET 402。另外,兩個開關共同使用一個接觸金屬417以及一個基板接頭411。通過共用一個接觸金屬417和一個基板接頭411,IGBT 401和超級接面MOSFET 402電耦合在一起。超級接面MOSFET 402的接觸金屬417為源極金屬接頭,與源極區407電連接在一起。源極區407可以用第一導電類型摻雜,並位於外延層403的表面上。第二導電類型的本體區408形成在外延層403的較深處,在源極區407下方。第二導電類型的摻雜立柱409位於外延層403中本體區408的下方。源極區407和本體區408的摻雜濃度範圍如上所述。作為示例,但不作為局限,源極摻雜濃度可以在2e19級別上,本體摻雜濃度可以在1-5e17級別上。通過調節本體劑量和閘極氧化物厚度,可以改變Vth
如圖4所示,第一導電類型的漂流區406可以位於外延層403中,在第二導電類型的兩個摻雜立柱409之間。在漂流區上方可以是閘極絕緣物404,作為示例,但不作為局限,閘極絕緣物可以是一個氧化層。閘極電極405位於閘極絕緣物404上方,通過閘極絕緣物保護它不受接觸金屬417影響。作為示例,但不作為局限,閘極電極405可以是一個多晶矽層。當閘極電極405上加載的電壓處於或高於電壓閾值(Vgs(th))時,在重摻雜底層410處流至汲極的電流(對於一個N-通道MOSFET來說)將垂直傳導,流經漂流區406、本體區408以及源極區407,流至接觸金屬417。設計漂流區406和摻雜立柱409的尺寸和摻雜 濃度,使得它們與鄰近立柱在水平方向上保持電荷平衡。摻雜立柱409和漂流區406的濃度可以高於典型電晶體的漂流區濃度,從而在接通狀態下,傳導較低的“接通”電阻。另外,應為超級接面MOSFET 402選擇合適的VGS(th),使得它等於IGBT 401的電壓閾值(VGE(th))或在電壓閾值(VGE(th))±2伏特以內。
在漂流區406下方,是一個第一導電類型的重摻雜底層410。最終,與重摻雜底層410導電接觸的是超級接面MOSFET的基板接頭411或汲極接頭。重摻雜底層410可以用作為元件的汲極,電流從基板接頭411流經重摻雜底層410,最終流至接觸金屬417。
IGBT 401是由與超級接面MOSFET 402相同的基板和外延層403製成的。一個遮罩溝槽可以將IGBT 401與超級接面MOSFET 402分開。遮罩溝槽內,襯入遮罩溝槽電介質418,如上所述,遮罩溝槽電介質418可以由一個氧化層構成,但不作為局限。遮罩溝槽電極419可以放置在遮罩溝槽電介質418上方,並通過電介質與外延層403和基板絕緣。遮罩溝槽電極419可以由導電材料,例如,多晶矽,但不作為局限製成。
IGBT 401具有一個第一導電類型的輕摻雜外延漂流區412。該區域的摻雜濃度可以低於超級接面MOSFET 402的摻雜濃度。第一導電類型的重摻雜緩衝區413形成在輕摻雜外延漂流區412下方。在重摻雜緩衝區413下方的是任意導電類型的輕摻雜層414,以及底部第二導電類型的注入底層415構成IGBT 401的集極。基板接頭411形成在注入底層415的底部。基板接頭411可以是一個金屬層,該金屬層可以由放置在背面的銅、鋁或金製成。
在輕摻雜外延漂流區412上方,是一個第一導電類型的重摻雜區416。本體區420位於重摻雜區上方。本體區420可以摻雜第二導電類型。本體區420具有重摻雜區,第一導電類型的射極區421形成在它上方。
遮罩溝槽可以形成在基板中,並終止在輕摻雜外延漂流區412的深度。遮罩溝槽內,可以襯入電介質424。遮罩溝槽電極425放置在電介質424的上方,可以處於射極電壓下。由閘極上的絕緣層423和閘極電極422構成的閘極,形成在遮罩電極上方,並延伸到射極區上方。閘極電極422形成在閘極上的絕緣層423上方,更多絕緣層423形成在閘極電極周圍,使閘極電極422與接觸金屬417絕緣。
與超級接面MOSFET 402類似,配置IGBT 401的VGE(th)在超級接面MOSFET的VGS(th)的±2伏特以內。注入底層415用作IGBT 401的集極,並且當閘極電極422加載電壓時,基板接頭411的電流垂直流經注入底層415以及外延層403,到射極區421,最終流至接觸金屬417。
如圖5所示,本創作的另一個可選實施例四,具有IGBT和超級接面MOSFET的元件的底視圖,並通過共用背部金屬和外延層的方式結構耦合。在所述的實施例四中,顯示了晶片的背部IGBT和超級接面MOSFET的元件的區域。在IGBT部分,所示區域為集極,並且處於超級接面MOSFET中,該區域為汲極。大部分的基板空間被IGBT的第二導電類型的注入底層501占據。第一導電類型的超級接面MOSFET基板區502有規律地穿插其中。在所示的實施例四中,超級接面MOSFET為圓形區域,被IGBT隔開。
如圖6所示,本創作的另一個可選實施例五。在該可選實施例五中,IGBT部分601中省去了遮罩溝槽,超級接面類似的摻雜立柱606位於本體區605 下方,並延伸到漂流區607中。超級接面類似的摻雜立柱606可以為第二導電類型,作為本體區605。在圖6所示的可選實施例五中,與圖4所示的實施例三的IGBT相比,實施例五中的外延/漂流區的第一導電類型的相對摻雜濃度較大。另外,漂流區607一直延伸到緩衝注入區610中。在緩衝注入區610下方的是任意導電類型的輕摻雜層611,第二導電類型的注入底層612構成IGBT集極。
如圖6所示,IGBT部分601還包括一個形成在外延層上的閘極絕緣層608。閘極絕緣層608保護閘極電極609,不受流經外延層和接觸金屬層603的電流影響。例如,但不作為局限,閘極絕緣層可以是一個氧化矽層。閘極電極609形成在閘極絕緣層608的表面上,絕緣層包圍著閘極電極,使閘極電極與金屬接觸層603電絕緣。例如,但不作為局限,閘極電極可以是一個多晶矽層。當閘極電極上加載電壓等於或超過VGE(th)時,來自基板接觸層613的電流,流經形成在注入區610、漂流區607、本體區605、射極層604的一個垂直通道,流至接觸金屬層603。
如圖4及圖6所示,超級接面部分602與圖4所示的超級接面MOSFET 402部分基本保持不變。要注意的是,在本實施例中,超級接面部分602以及IGBT部分601共用一個漂流區607。超級接面部分602以及IGBT部分601共用的外延/漂流區可以具有相同的摻雜濃度。
如圖7所示,依據本創作的另一個可選實施例六;此時,IGBT 701和超級接面MOSFET 702是物理隔離的,但是通過閘極電極和接頭之間的電連接實現結構耦合。如圖7所示,IGBT 701和超級接面MOSFET 702的結構與圖4所示的結構類似。但與圖4和圖6所示的實施例不同,IGBT 701具有一個單獨的射極接觸金屬層703、漂流區708、緩衝物716、任意導電類型的輕摻雜區717, 以及第二導電類型的注入層718,第二導電類型的注入層718構成IGBT集極和集極接頭711。與之類似,超級接面MOSFET 702包括一個單獨的源極接觸金屬層704、外延/漂流區709、基板層712以及汲極接頭710。
如圖7所示的兩部分的運行方式與上述實施例類似,這是因為超級接面MOSFET部分714的閘極電極電耦合到IGBT部分715的閘極電極,通過閘極電極引線705。另外,在一些實施例中,IGBT 701的射極接觸金屬層703,通過射極接觸引線706電耦合到源極接觸金屬層704。與之類似,IGBT 701的集極接觸層711,通過集極接觸引線707,電耦合到汲極接觸層710。兩個元件部分的這種電耦合區域,允許它們在沒有共用的公共基板或外延層的情況下,共同運行。確切地說,IGBT部分715和超級接面MOSFET部分714的閘極電極的電耦合,意味著在運行時,具有接近的閘極電壓閾值的IGBT 701和超級接面MOSFET 702,當切換至“接通”狀態時,將在同步方式下運行。另外,IGBT 701和超級接面MOSFET 702,可以通過例如,但不作為局限,在相同的積體電路封裝中、相同的印刷電路板上或連接到相同的基板上等方式,實現結構耦合。
功能:如圖8A-8B所示,依據本創作的各個方面,在25℃處,IGBT的功能結構耦合到超級接面MOSFET曲線803上;在125℃處,IGBT的功能結構耦合到超級接面MOSFET曲線806上;顯示結構耦合到超級接面MOSFET元件的IGBT的功能。而且也表示出了一個單獨的IGBT曲線801功能和一個單獨的超級接面MOSFET曲線802。圖8A和圖8B表示不同元件的電流和電壓之間的關係。如上所述,在25℃處,單獨的IGBT曲線801具有類似電壓閾值的二極體,其中流經元件的電流直到25℃處的電壓為~0.6伏特時才會升高。在125℃處, 單獨的IGBT曲線804表示,流經單獨的IGBT的電流直到~0.45伏特時才會升高。另一方面,在25℃處,單獨的超級接面MOSFET曲線802表示流經元件的電流從0伏特開始線性升高。與125℃處類似,超級接面MOSFET曲線805表示流經單獨的超級接面元件的電流具有線性特徵,並且比25℃處的曲線更加平坦。另一方面,在電壓閾值之後,在25℃ 801和125℃ 804處的單獨的IGBT元件具有非線性特徵。這種特徵可以理解為絕大部分流經超級接面MOSFET的電流都低於0.6-1安培,並且由於IGBT在電流高於0.6-1安培時的非線性特徵,絕大部分的電流都流經元件的IGBT部分。
IGBT結構耦合並電耦合到超級接面MOSFET曲線803上,表示單獨的IGBT和單獨的超級接面MOSFET的特徵。如圖8A-8B所示,該元件在低壓(25℃處0.6伏特以下以及125℃處0.4伏特以下)下具有線性特徵。在較高的電壓下,該元件的電流和電壓之間具有非線性關係,這種超級接面MOSFET曲線的非線性關係從25℃持續到125℃因此,這些曲線清楚地表明由於在>0伏特時元件就開始傳導電流,因此IGBT結構耦合和電耦合到超級接面MOSFET解決了原有技術IGBT元件中的電壓閾值問題。該元件還保持了IGBT的正向特性,其原因是在電壓閾值之後,元件具有明顯的非線性IGBT特徵。
如圖9A和9B所示,依據本創作,IGBT的反向電流和反向偏壓功能結構耦合並電耦合到超級接面MOSFET上,在25℃(曲線901)和125℃(曲線903)電流與電壓的關係曲線圖,以顯示結構耦合到超級接面MOSFET元件的IGBT反向電流反向偏壓方向的功能。電流和電壓曲線還表示普通的IGBT與反並聯快速恢復二極體共同封裝的元件在25℃(曲線902)和125℃(曲線904)。該圖表示對於低電壓下的普通IGBT(曲線902)來說,沒有電流流經元件。該 曲線圖表示在反向偏壓和反向電流方向下,耦合超級接面MOSFET的IGBT元件的電導由元件的超級接面MOSFET部分的體二極體上的電導控制。超級接面MOSFET的體二極體可以被認為是用作元件的整流二極體。因此,該元件還滿足了單獨的IGBT元件中對整流二極體的需求,與共同封裝的FRD相比,具有更低的導電損耗。
儘管本發明關於某些較佳的版本已經做了詳細的敘述,但是仍可能存在其他版本。因此,本發明的範圍不應由上述說明決定,與之相反,本發明的範圍應參照所附的發明專利申請範圍及其全部等效內容。任何可選實施例(無論首選與否),都可與其他任何可選實施例(無論首選與否)組合。以上是對本創作的較佳實施進行了具體說明,但本創作創造並不限於所述實施例,熟悉本領域的技術人員在不違背本創作精神的前提下還可做出種種的等同變形或替換,這些等同的變形或替換均包含在本申請權利要求所限定的範圍。
301:IGBT
302:超級接面MOSFET
303:節點
304:節點
305:節點

Claims (12)

  1. 一種改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,包括:一個絕緣閘極雙極性電晶體,具有一個摻雜立柱在本體區下方,摻雜立柱延伸到絕緣閘極雙極性電晶體的漂流區中,所述漂流區具有第一導電類型,還具有與所述第一導電類型相反的第二導電類型的注入底層,在所述漂流區和所述注入底層之間的第一導電類型的緩衝注入區,以及位於所述緩衝注入區與所述注入底層之間的第一導電類型或第二導電類型的輕摻雜層,其中所述摻雜立柱不延伸至緩衝注入區;以及一個超級接面MOSFET,其中絕緣閘極雙極性電晶體的射極和超級接面MOSFET的源極導電耦合,絕緣閘極雙極性電晶體的集極和超級接面MOSFET的汲極導電耦合,絕緣閘極雙極性電晶體的閘極和超級接面MOSFET的閘極導電耦合。
  2. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中超級接面MOSFET的體二極體和絕緣閘極雙極性電晶體是反並聯的。
  3. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中絕緣閘極雙極性電晶體和超級接面MOSFET都位於同一個電路板上。
  4. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中絕緣閘極雙極性電晶體和超級接面MOSFET位於同一個基板中。
  5. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中絕緣閘極雙極性電晶體和超級接面MOSFET位於同一個積體電路封裝中。
  6. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中在“接通”狀態下,當電流小於一額定電流時,大部分的電荷都流經超級接面MOSFET。
  7. 如請求項1和6所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中在“接通”狀態下,當電流大於一額定電流時,大部分的電荷都流經絕緣閘極雙極性電晶體。
  8. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中絕緣閘極雙極性電晶體為一個平面柵絕緣閘極雙極性電晶體。
  9. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中配置絕緣閘極雙極性電晶體和超級接面MOSFET,使其具有閘極源極電壓閾值在彼此的±2伏特以內。
  10. 如請求項4所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中超級接面MOSFET穿插在基板中的絕緣閘極雙極性電晶體之間。
  11. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中絕緣閘極雙極性電晶體與超級接面MOSFET共用一個漂流區,並且其中共用的漂流區對於絕緣閘極雙極性電晶體和超級接面MOSFET來說處於相同的摻雜濃度。
  12. 如請求項1所述之改良絕緣閘極雙極性電晶體(IGBT)輕負載效率的裝置,其中有多個本體區和摻雜立柱,其中多個摻雜立柱延伸在漂流區中,並且其中本體區和摻雜立柱具有相同的導電類型。
TW109132386A 2019-09-27 2020-09-18 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置 TWI794647B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/585,388 2019-09-27
US16/585,388 US11342410B2 (en) 2019-09-27 2019-09-27 Improving IGBT light load efficiency

Publications (2)

Publication Number Publication Date
TW202113983A TW202113983A (zh) 2021-04-01
TWI794647B true TWI794647B (zh) 2023-03-01

Family

ID=75119598

Family Applications (2)

Application Number Title Priority Date Filing Date
TW109132386A TWI794647B (zh) 2019-09-27 2020-09-18 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置
TW112102201A TWI827449B (zh) 2019-09-27 2020-09-18 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW112102201A TWI827449B (zh) 2019-09-27 2020-09-18 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置

Country Status (2)

Country Link
US (2) US11342410B2 (zh)
TW (2) TWI794647B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061003A1 (en) * 2013-08-29 2015-03-05 Infineon Technologies Ag Power Semiconductor Package
CN204332965U (zh) * 2014-12-04 2015-05-13 国家电网公司 一种平面栅igbt
US20160111419A1 (en) * 2014-10-15 2016-04-21 Fuji Electric Co., Ltd. Semiconductor device
US20180269871A1 (en) * 2017-03-16 2018-09-20 Infineon Technologies Austria Ag Transistor device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005052733B3 (de) 2005-11-04 2007-05-03 Infineon Technologies Ag Vertikales Halbleiterbauelement
CN101079576B (zh) 2006-05-24 2010-04-07 昂宝电子(上海)有限公司 用于提供对电源调节器的开关的***
US7670908B2 (en) 2007-01-22 2010-03-02 Alpha & Omega Semiconductor, Ltd. Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling
US7951676B2 (en) 2008-08-29 2011-05-31 Infineon Technologies Ag Semiconductor device and method for the production of a semiconductor device
US8896131B2 (en) 2011-02-03 2014-11-25 Alpha And Omega Semiconductor Incorporated Cascode scheme for improved device switching behavior
JP5333485B2 (ja) 2011-03-04 2013-11-06 株式会社デンソー 電力変換装置
JP5749580B2 (ja) 2011-06-16 2015-07-15 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP5447603B2 (ja) 2011-08-27 2014-03-19 株式会社デンソー 電力変換装置
US8569780B2 (en) 2011-09-27 2013-10-29 Force Mos Technology Co., Ltd. Semiconductor power device with embedded diodes and resistors using reduced mask processes
US9013848B2 (en) 2012-09-27 2015-04-21 Alpha And Omega Semiconductor Incorporated Active clamp protection circuit for power semiconductor device for high frequency switching
TWI520337B (zh) 2012-12-19 2016-02-01 財團法人工業技術研究院 階梯溝渠式金氧半場效電晶體及其製造方法
WO2016063681A1 (ja) * 2014-10-24 2016-04-28 富士電機株式会社 半導体装置
WO2016063683A1 (ja) * 2014-10-24 2016-04-28 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6402591B2 (ja) 2014-10-31 2018-10-10 富士電機株式会社 半導体装置
JP6652802B2 (ja) * 2015-09-15 2020-02-26 ローム株式会社 半導体装置、および当該半導体装置を備えるインバータ装置
JP6693131B2 (ja) 2016-01-12 2020-05-13 富士電機株式会社 半導体装置
WO2018012122A1 (ja) 2016-07-11 2018-01-18 富士電機株式会社 半導体装置及び振動抑制装置
JP7290973B2 (ja) * 2019-03-27 2023-06-14 ローム株式会社 半導体装置
US10931276B1 (en) 2019-09-27 2021-02-23 Alpha And Omega Semiconductor (Cayman) Ltd. Combined IGBT and superjunction MOSFET device with tuned switching speed

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150061003A1 (en) * 2013-08-29 2015-03-05 Infineon Technologies Ag Power Semiconductor Package
US20160111419A1 (en) * 2014-10-15 2016-04-21 Fuji Electric Co., Ltd. Semiconductor device
CN204332965U (zh) * 2014-12-04 2015-05-13 国家电网公司 一种平面栅igbt
US20180269871A1 (en) * 2017-03-16 2018-09-20 Infineon Technologies Austria Ag Transistor device

Also Published As

Publication number Publication date
TW202320341A (zh) 2023-05-16
US11756993B2 (en) 2023-09-12
CN112582395A (zh) 2021-03-30
US20210098569A1 (en) 2021-04-01
TW202113983A (zh) 2021-04-01
US20220262898A1 (en) 2022-08-18
US11342410B2 (en) 2022-05-24
TWI827449B (zh) 2023-12-21

Similar Documents

Publication Publication Date Title
US9299695B2 (en) Semiconductor device
KR100474214B1 (ko) 실리콘 카바이드 수평 채널이 버퍼된 게이트 반도체 소자
US20130320354A1 (en) Semiconductor Device Including a Normally-Off Transistor and Transistor Cells of a Normally-On GaN HEMT
CN107026207B (zh) 包括横向晶体管的半导体器件
US8124983B2 (en) Power transistor
JP2009065026A (ja) 電気回路のスイッチング装置
US11398769B2 (en) Semiconductor device comprising switching elements and capacitors
JP2012146977A (ja) ダイオードを含む半導体装置
WO2019085850A1 (zh) Igbt功率器件
KR20180068179A (ko) 반도체 소자 및 그 제조 방법
US9018633B2 (en) Semiconductor device
CN105702719B (zh) 具有改进稳定性的功率半导体器件及其生产方法
US11444193B2 (en) Silicon carbide semiconductor device
TW201824539A (zh) 高電壓積體電路的高電壓終端結構
US11482615B2 (en) Super-junction power MOSFET device with improved ruggedness, and method of manufacturing
US11094691B2 (en) Semiconductor device
US10931276B1 (en) Combined IGBT and superjunction MOSFET device with tuned switching speed
US11069769B2 (en) Semiconductor device
TWI794647B (zh) 一種改良絕緣閘極雙極性電晶體(igbt)輕負載效率的裝置
US20230049852A1 (en) Transistor and semiconductor device
KR101836258B1 (ko) 반도체 소자 및 그 제조 방법
CN112582395B (zh) 改良igbt的轻负荷效率
CN112582394B (zh) 开关速度可调的igbt与超结mosfet组合器件
TWI839573B (zh) 開關速度可調的igbt與超級結mosfet組合器件
JP2020013959A (ja) 半導体装置