TWI779560B - 具有多個電壓供應源的半導體封裝結構及其製備方法 - Google Patents

具有多個電壓供應源的半導體封裝結構及其製備方法 Download PDF

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TWI779560B
TWI779560B TW110113609A TW110113609A TWI779560B TW I779560 B TWI779560 B TW I779560B TW 110113609 A TW110113609 A TW 110113609A TW 110113609 A TW110113609 A TW 110113609A TW I779560 B TWI779560 B TW I779560B
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die
substrate
additional
device die
packaging substrate
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TW110113609A
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TW202143407A (zh
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楊吳德
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體封裝結構及其製備方法。該半導體封裝結構具有一封裝基底、一下元件晶粒、一上元件晶粒以及一額外封裝基底。該下元件晶粒貼合在該封裝基底上。該上元件晶粒貼合到該下元件晶粒上，而其主動側係背對該下元件晶粒。多個晶粒輸入/輸出位在該上元件晶粒之該主動側的一第一部分係電性連接到該封裝基底。該額外封裝基底係貼合到該上元件晶粒的該主動側，且電性連接到該封裝基底以及該上元件晶粒之該等晶粒輸入/輸出的一第二部分。

Description

具有多個電壓供應源的半導體封裝結構及其製備方法
本申請案主張2020年5月5日申請之美國正式申請案第16/867,202號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝結構及其製備方法。特別是有關於一種多晶粒半導體封裝結構及其製備方法。
由於各種電子元件的積體密度的不斷改善，所以半導體產業經歷了持續的增長。此等改善主要係來自最小特徵尺寸的不斷減小，從而允許將更多元件整合到一給定的晶片面積中。
因為積體元件所佔據的體積基本上在半導體晶圓的表面上，所以這些整合的改善本質上是二維的(2D)。雖然微影技術的顯著改善已導致在二維積體電路形成中的顯著改進，但是其可在二維所達到的密度仍是有實體上的限制。當二維的縮放(scaling)仍是一些新設計的一選項，但採用利用z方向的三維(3D)封裝組合已成為業界研究的重點。在一個三維封裝結構中，多個半導體晶粒可相互堆疊在其上。結果，一上半導體晶粒與該三維封裝結構的多個輸入/輸出(I/Os)之間的一訊號路徑，係較長於 在一下半導體晶粒與該等輸入/輸出之間的一訊號路徑，因此可延遲位在上半導體晶粒之訊號傳輸時間。此外，由於相對較長之訊號路徑的較大阻抗(impedance)，所以可增加在最上面的上半導體晶粒與該等輸入/輸出之間的訊號損耗(signal loss)。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底；一下元件晶粒，貼合在該封裝基底上；一上元件晶粒，貼合在該下元件晶粒上，其中該上元件晶粒的一主動側係背對該封裝基底，該上元件晶粒的一後側係面朝該封裝基底，該上元件晶粒包括多個晶粒輸入/輸出，該等晶粒輸入/輸出位在該主動側處，且該等晶粒輸入/輸出的一第一部分係電性連接到該封裝基底；以及一額外封裝基底，貼合到該上元件晶粒的該主動側上，其中該額外封裝基底係電性連接到該上元件晶粒之該等晶粒輸入/輸出的一第二部分，並電性連接到該封裝基底。
在本揭露的一些實施例中，該額外封裝基底藉由多個第一接合線而電性連接到該等晶粒輸入/輸出的該第二部分，且該額外封裝基底藉由多個第二接合線而電性連接到該封裝基底。
在本揭露的一些實施例中，該額外封裝基底具有一開口以及一本體部，該本體部側向圍繞該開口設置。
在本揭露的一些實施例中，該等輸入/輸出的該第二部分與該開口重疊，且該等第一接合線從該額外封裝基底的一上表面經由該額外 封裝基底的該開口而延伸到該等晶粒輸入/輸出的該第二部分。
在本揭露的一些實施例中，該等第二接合線從該額外封裝基底之一上表面的一周圍區延伸到該封裝基底。
在本揭露的一些實施例中，該等晶粒輸入/輸出的一第一部分至少部分係位在該額外封裝基底的一跨度(span)外側。
在本揭露的一些實施例中，該等晶粒輸入/輸出的該第一部分藉由多個第三接合線而電性連接到該封裝基底。
在本揭露的一些實施例中，該半導體封裝結構還包括一第一黏貼材料以及一第二黏貼材料，該第一黏貼材料設置在該下元件晶粒與該上元件晶粒之間，該第二黏貼材料設置在該上元件晶粒與該額外封裝基底之間。
在本揭露的一些實施例中，該第二黏貼材料具有一開口以及一本體部，該本體部側向圍繞該額外封裝基底的該開口設置，而該第二黏貼材料的該開口與該等晶粒輸入/輸出的該第二部分重疊。
在本揭露的一些實施例中，該額外封裝基底經配置以提供一電源電壓(power voltage)以及一參考電壓給該上元件晶粒，而該封裝基底經配置以提供多個命令給在該上元件晶粒中的一積體電路。
在本揭露的一些實施例中，該半導體封裝結構還包括一囊封體(encapsulant)，設置在該封裝基底上，並囊封該下元件晶粒、該上元件晶粒以及該額外封裝基底。
在本揭露的一些實施例中，該半導體封裝結構還包括多個封裝輸入/輸出，設置在該封裝基底背對該下元件晶粒的一表面處。
本揭露之另一實施例提供一種半導體封裝結構。該半導體 封裝結構包括一第一封裝基底；一第一元件晶粒，接合到該第一封裝基底上，並具有一第一主動側以及一第一後側，該第一主動側面朝該第一封裝基底，該第一後側背對該第一主動側；一第二元件晶粒，貼合在該第一元件晶粒上，並具有一第二主動側以及一第二後側，該第二主動側背對該第一元件晶粒，該第二後側面朝該第一元件晶粒；一第二封裝基底，貼合在該第二元件晶粒的該第二主動側上，其中該第二元件晶粒位在該第二主動側處的多個晶粒輸入/輸出電性連接到該第一封裝基底與該第二封裝基底；以及一囊封體，設置在該第一封裝基底上，並囊封該第一元件晶粒、該第二元件晶粒以及該第二封裝基底。
在本揭露的一些實施例中，該第二封裝基底包括：多個積層介電層與多個導電層，沿著一垂直方向交錯堆疊設置；多個接合墊，設置在最上面之該導電層的多個開口中；以及多個佈線結構，連接除了最上面的該導電層之外的該等導電層到該等接合墊。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該製備方法包括接合一下元件晶粒到一封裝基底上；貼合一上元件晶粒到該下元件晶粒上；貼合一額外封裝基底到該上元件晶粒上；建立該額外封裝基底與該上元件晶粒之間的電性連接、該額外封裝基底與該封裝基底之間的電性連接，以及該上元件晶粒與該封裝基底之間的電性連接；以及囊封該下元件晶粒、該上元件晶粒以及該額外封裝基底，其係藉由一囊封體進行囊封。
在本揭露的一些實施例中，該下元件晶粒經由一覆晶方式(flip chip manner)而接合到該封裝基底上。
在本揭露的一些實施例中，該半導體封裝結構的製備方法 還包括：在該下元件晶粒接合到該封裝基底上之前，形成多個電連接件在該下元件晶粒的一主動側上，其中在該下元件晶粒接合到該封裝基底上之後，該等電連接件連接在該下元件晶粒的該主動側與該封裝基底之間。
在本揭露的一些實施例中，該半導體封裝結構的製備方法還包括：在該上元件晶粒貼合到該下元件晶粒上之前，提供一第一黏貼材料在該下元件晶粒上。
在本揭露的一些實施例中，該半導體封裝結構的製備方法還包括：在該額外封裝基底貼合到該上元件晶粒之前，提供一第二黏貼材料在該上元件晶粒上。
在本揭露的一些實施例中，藉由形成從該額外封裝基底延伸到該上元件晶粒的多個接合線、從該額外封裝基底延伸到該封裝基底的多個接合線以及從該上元件晶粒延伸到該封裝基底的多個電線，以建立電性連接。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:半導體封裝結構
20:半導體封裝結構
30:半導體封裝結構
40:半導體封裝結構
40a:半導體封裝結構
100:下元件晶粒
102:晶粒輸入/輸出
110:上元件晶粒
112:晶粒輸入/輸出
120:封裝基底
122:介電核心層
124:積層介電層
126:導電圖案
128:佈線結構
130:額外封裝基底
132:積層介電層
134:導電圖案
136:佈線結構
138:接合墊
140:囊封體
AM1:黏貼材料
AM2:黏貼材料
AM3:黏貼材料
AP1:導電墊
AP2:導電墊
AS1:主動側
AS2:主動側
BS1:後側
BS2:後側
BW1:接合線
BW2:接合線
BW3:接合線
BW4:接合線
CL1:導電線
CL2:導電線
CP1:導電柱
EC1:電連接件
EC2:封裝輸入/輸出
M10:方法
RD1:重分布結構
RD2:重分布結構
RP1:重分布墊
RP2:重分布墊
S11:步驟
S13:步驟
S15:步驟
S17:步驟
S19:步驟
S21:步驟
S23:步驟
S25:步驟
S27:步驟
S29:步驟
SJ1:焊料接頭
W:開口
W134:開口
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1A為依據本揭露一些實施例一種半導體封裝結構的剖視示意圖。
圖1B為如圖1A所示在該半導體裝結構中之一下元件晶粒的一主動側的平面示意圖。
圖1C為如圖1A所示之該半導體封裝結構的平面示意圖。
圖1D為如圖1A所示在該半導體裝結構中之一上元件晶粒的一主動側的平面示意圖。
圖2為如圖1所示的該半導體封裝結構之製備方法的流程示意圖。
圖3A到圖31為在如圖2所示之該半導體封裝結構的製備流程期間在不同階段之結構的剖視示意圖。
圖4為依據本揭露一些實施例之一種半導體封裝結構的平面示意圖。
圖5為依據本揭露一些實施例之一種半導體封裝結構的剖視示意圖。
圖6A為依據本揭露一些實施例之一種半導體封裝結構的剖視示意圖。
圖6B為如圖6A所示在該半導體封裝結構中一下元件晶粒之一主動側的平面示意圖。
圖7A為依據本揭露一些實施例之一種半導體封裝結構的剖視示意圖。
圖7B為如圖7A所示在該半導體封裝結構中一下元件晶粒之一主動側的平面示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneatb)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的 (upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1A為依據本揭露一些實施例一種半導體封裝結構10的剖視示意圖。圖1B為如圖1A所示在該半導體裝結構10中之一下元件晶粒100的一主動側AS1的平面示意圖。
請參考圖1A，在一些實施例中，半導體封裝結構10為一雙晶粒半導體封裝結構。在這些實施例中，半導體封裝結構10可具有一下元件晶粒100以及一上元件晶粒110，上元件晶粒110位在下元件晶粒100上。下元件晶粒100接合到一封裝基底120上，且上元件晶粒110可經由一黏貼材料AM1而貼合在下元件晶粒100上。在一些實施例中，下元件晶粒100的一主動側AS1面朝封裝基底120，同時下元件晶粒100的一後側BS1背對封裝基底120。另一方面，上元件晶粒110的一主動側AS2背對下元件晶粒100，同時上元件晶粒110的一後側BS2面朝下元件晶粒100。在這些實施例中，黏貼材料AM1佈設在下元件晶粒100的後側BS1與上元件晶粒110的後側BS2之間。此外，黏貼材料AM1可覆蓋下元件晶粒100之大致整體背側BS1以及上元件晶粒110之大致整體背側BS2，且黏貼材料AM1的一側壁可大致與下元件晶粒100與上元件晶粒110的側壁為共面，或者是從下元件晶粒100與上元件晶粒110的側壁側向突伸。或者是，黏貼材料AM1的側壁可從下元件晶粒100與上元件晶粒110的側壁側向凹陷，並可不覆蓋下元件晶粒100之後側BS1與上元件晶粒110之後側BS2的周圍 區。在一些實施例中，黏貼材料AM1由一聚合物材料所組成，例如環氧樹脂(epoxy)。
一元件晶粒100/110的主動側AS1/AS2可表示成其上設置有多個晶粒輸入/輸出102/112的一側。在一些實施例中，下元件晶粒100的該等晶粒輸入/輸出102包括多個導電墊AP1，上元件晶粒110的該等晶粒輸入/輸出112包括多個導電墊AP2。導電墊AP1/AP2電性連接到在元件晶粒100/110中的一積體電路。舉例來說，積體電路包括多個主動元件及/或多個被動元件(圖未示)，並包括多個內連接(圖未示)，其係用於佈線該等主動元件及/或該等被動元件。導電墊AP1/AP2可經由該等內連接而連接到該等主動/被動元件。在一些實施例中，下元件晶粒100與上元件晶粒110為記憶體晶粒，例如動態隨機存取記憶體(DRAM)晶粒。在這些實施例中，在每一下元件晶粒100與上元件晶粒110中的積體電路可包括多個記憶體胞的一陣列，而每一記憶體胞具有至少一存取電晶體以及至少一儲存電容器。此外，就電路與尺寸而言，上元件晶粒110可大致相同於下元件晶粒100。或者是，就電路、尺寸或其他特性而言，上元件晶粒110與下元件晶粒100可相互不同。
在那些實施例中，在下元件晶粒100的主動側AS1面朝封裝基底120的情況下，下元件晶粒100經由多個電連接件EC1而接合到封裝基底120。該等電連接件EC1連接下元件晶粒100的該等晶粒輸入/輸出102到封裝基底120。在一些實施例中，該等電連接件EC1分別包括一導電柱CP1以及一焊料接頭SJ1。導電柱CP1的一端子(terminal)連接到其中一晶粒輸入/輸出102，且導電柱CP1的另一端子經由焊料接頭SJ1而連接到封裝基底120。如圖1A所示，每一導電柱CP1垂直延伸在其中一焊料接頭 SJ1與其中一晶粒輸入/輸出102之間。在一些實施例中，該等導電柱CP1的一材料可包含金屬(意即銅或銅合金)，同時該等焊料接頭SJ1可由一焊錫材料(solder material)所製。此外，該等電連接件EC1可具有一高度，係在30μm到150μm範圍之間。然而，所屬技術領域中具有通常知識者可依據設計所需，而選擇該等電連接件EC1的其他適合的材料及/或改良該等電連接件EC1的尺寸，本揭露並不以此為限。
在一些實施例中，封裝基底120為具有一介電核心層(dielectric core layer)122的一封裝基底。在這些實施例中，封裝基底120包括介電核心層122，並包括多個積層介電層(built-up dielectric layers)124以及多個導電圖案126的多層，而多個導電圖案126的該等層交錯地形成在介電核心層122的相對側處。如圖1A所示，該等積層介電層124與該等導電圖案126的該等層可交錯地堆疊在介電核心層122的一上側以及一下側。該等導電圖案126的該等層可包括至少一層接地面(ground plane)、至少一層電源面(power plane)以及至少一訊號面(signal plane)。舉例來說，二訊號面跨設在一接地面與一電源面之間。此外，封裝基底120還可包括多個佈線結構(routing structures)128，用於佈線多個嵌入層(embedded layers)與該等導電圖案126的最下面一層到封裝基底120的一上表面，以及用於佈線該等嵌入層與該等導電圖案126之最上面一層到封裝基底120的一下表面。一些電連接件EC1接合在該等導電圖案126之最上面一層上(意即接地面)，而其他電連接件EC1則維持在該等佈線結構128的最上面部分上，且經由該等佈線結構128而佈線到該等導電圖案126的該等嵌入層。該等佈線結構128可具有多個導電跡線(conductive traces)、多個導電通孔(conductive vias)以及多個穿孔(through vias)。該等導電跡 線分別延伸在其中一積層介電層124的一表面上，或者是在介電核心層122的一表面上。該等導電通孔分別穿過一或多個積層介電層124，並電性連接到一或多個導電跡線及/或該等導電圖案126的其中一層。此外，該等穿孔穿經介電核心層122，並經配置以建立該等佈線結構128位在接電核心層122之相對側之部分之間的電性連接。在一些實施例中，多個封裝輸入/輸出EC2形成在封裝基底120的一下側。一些封裝輸入/輸出EC2接觸該等導電圖案126之最下面一層，同時其他的封裝輸入/輸出EC2接觸該等佈線結構128之該等最下面部分。在一些實施例中，該等封裝輸入/輸出EC2可為球狀柵格陣列(ball grid array，BGA)球、受控塌陷晶片連接(controlled-collapse-chip-connection，C4)凸塊或其類似物。
請參考圖1A及圖1B，在一些實施例中，下元件晶粒100該等晶粒輸入/輸出102還包括多個重分布結構RD1。在多個導電墊AP1形成在下元件晶粒100之主動側AS1的一中心區內的實施例中，一些導電墊AP1藉由該等重分布結構RD1而佈線到主動側AS1的一周圍區。在此方法中，下元件晶粒100的該等晶粒輸入/輸出102可分佈在主動側AS1的中心區與周圍區內。舉個例子，該等導電墊AP1可配置在中心區中的二行(columns)中，且在每一行中的該等導電墊AP1交錯地連接到延伸至周圍區的重分布結構RD1。然而，所屬技術領域中具有通常知識者可依據設計所需，改良該等導電墊AP1與該等重分布結構RD1的架構，且下元件晶粒100的該等晶粒輸入/輸出102可分佈在下元件晶粒100之主動側AS1的中心區與周圍區內。在一些實施例中，該等重分布結構RD1分別具有一導電線CL1以及一重分布墊RP1。應當理解，在圖1A中僅顯示出該等重分布結構RD1的該等重分布墊RP1，從圖1A中省略該等導電線CL1。另一方面，該 等導電線CL1與該等重分布墊RP1均顯示在圖1B中。導電線CL1從其中一導電墊AP1延伸到其中一重分布墊RP1。在一些實施例中，導電線CL1從暴露在主動側AS1處之對應的導電墊AP1的一表面延伸，並側向接觸對應的重分布墊RP1。導電線CL1可形成為一直線。或者是，導電線CL1可具有沿著其延伸方向的至少一轉折(turn)。此外，該等電連接件EC1可形成在該等重分布墊RP1上，且該等導電墊AP1並未連接到該等重分布結構RD1。在這些實施例中，在一些導電墊AP1從主動側AS1的中心區佈線到主動側AS1的周圍區的情況下，該等電連接件EC1與主動側AS1的中心區及周圍區重疊。
請參考圖1A，在一些實施例中，半導體封裝結構10還包括一額外封裝基底130。當上元件晶粒110的主動側AS2背對下元件晶粒100的這些實施例中，額外封裝基底130設置在上元件晶粒110上。在額外封裝基底130中的多個電子元件(意即如將要描述的多個導電圖案134)電性連接到上元件晶粒110的一些導電墊AP2，且當作是額外電壓供應源給上元件晶粒110。在一些實施例中，額外封裝基底110經由一黏貼材料AM2而貼合在上元件晶粒110上。此外，在該等導電墊AP2位在上元件晶粒110之主動側AS2的一中心區內的該等實施例中，額外封裝基底130具有一開口W，係與至少一些導電墊AP2重疊。應當理解，雖然在圖1A中所描述的額外封裝基底130係具有二分開的子部分，但這些子部分相互連接，且側向圍繞開口W設置。類似於額外封裝基底130，黏貼材料AM2的一本體部可側向圍繞黏貼材料AM2的一開口，且此開口與額外封裝基底130的開口W重疊。雖然描述黏貼材料AM2的內側壁與外側壁係與額外封裝基底130的內側壁與外側壁為共面，但黏貼材料AM2的內側壁與外側壁可從額外封 裝基底130的內側壁與外側壁交錯凹陷或突伸。
在一些實施例中，額外封裝基底130為一無核心(core-less)封裝基底。在這些實施例中，額外封裝基底130包括多個積層介電層132以及多個導電圖案134的多層。該等積層介電層132與該等到電圖案134的該等層係沿一垂直方向而交錯堆疊。在額外封裝基底130具有開口W的那些實施例中，開口W係穿經該等積層介電層132以及該等導電圖案134的該等層。該等導電圖案132的該等層可包括至少一層接地面以及至少一層電源面。舉例來說，該等導電圖案132的該等層具有一單一接地面以及多個電源面(意即三個電源面)，而該等電源面係舖設在接地面下方。此外，額外封裝基底130可包括多個佈線結構136以及多個接合墊138。該等接合墊138可與最上面的該等導電圖案134的該等層(意即接地面)一起設置在最上面的積層介電層132上。此外，該等接合墊138可位在該等導電圖案134之最上面一層的多個開口W134中，且與該等導電圖案134之最上面一層的一本體部分開設置。位在該等導電圖案134之最上面一層下方的一些該等導電圖案134的該等層(意即該等電源面)，係藉由該等佈線結構136而佈線到該等接合墊138。在一些實施例中，該等佈線結構136具有多個導電通孔，每一個導電通孔係穿經一或多個積層介電層132。位在該等導電圖案134之最上面一層的該等導電圖案134的該等層以及位在該等導電圖案134之最下面一層的該等導電圖案134的該等層，係可在該等佈線結構136經過處為非連續的。
依據如上所述的該等實施例，封裝基底120為具有介電核心層122的一封裝基底，且額外封裝基底130為一無核心封裝基底。然而，在其他實施例中，封裝基底120與額外封裝基底130均為一無核心封 裝基底。在其他的實施例中，封裝基底120與額外封裝基底130均為具有一介電核心層的封裝基底。或者是，封裝基底120為一無核心封裝基底，同時額外封裝基底130為具有一介電核心層的封裝基底。由硬質材料所製之具有一介電核心層的封裝基底，係可改善機構強度，同時無核心封裝基底可具有例如重量輕以及z方向高度低的優點。所屬技術領域中具有通常知識者可依據製程所需而選擇對於封裝基底120以及額外封裝基底130之適合的基底型態，本揭露並不以此為限。
請參考圖1A及圖1C，在一些實施例中，額外封裝基底130的一本體部係側向圍繞額外封裝基底130的開口W設置。在這些實施例中，額外封裝基底130的本體部具有一外邊緣以及一內邊緣，外邊緣係界定出額外封裝基底130的一外邊界，而內邊緣係界定出開口W的一輪廓(contour)。該等導電圖案134之最上面一層的該等開口W134可分別接近額外封裝基底130的外邊緣或內邊緣設置。舉例來說，如圖1C所示，一些開口W134係接近額外封裝基底130的外邊緣設置，同時其他開口W134係接近額外封裝基底130的內邊緣設置。此外，一或多個接合墊138係形成在每一開口W134。在一個以上之接合墊138中的該等開口W134可具有一覆蓋區(footprint area)，係大於在單一個接合墊138中之開口W134的一覆蓋區。
在一些實施例中，該等導電圖案134的最上面一層以及一些接合墊138係藉由多個接合線BW1而電性連接到上元件晶粒110的該等導電墊AP2，而所述上元件晶粒110的該等導電墊AP2係與開口W重疊。此外，該等導電圖案134的最上面一層與其他的接合墊138係藉由多個接合線BW2而電性連接到封裝基底120。在一些實施例中，該等接合線BW1 從該等接合墊138以及該等導電圖案134之最上面一層(意即接地面)接近額外封裝基底130之內邊緣處(意即開口W的輪廓)的一部份，而延伸到上元件晶粒110的該等導電墊AP2。在另一方面，該等接合線BW2係從該等接合墊138以及該等導電圖案134之最上面一層接近額外封裝基底130之外邊緣處的一部份，而延伸到該等導電圖案126之最上面一層以及該等佈線結構128之最上面的部分。在此方法中，該等接合線BW1與額外封裝基底130的一內周圍區連接，同時該等接合線BW2與額外封裝基底130的一外周圍區連接。在一些實施例中，多個電源電壓(意即直流電壓)以及一參考電壓可藉由在額外封裝基底130中的電源面以及接地面，並經由該等接合線BW1而提供到上元件晶粒110，且在額外封裝基底130的電源面以及接地面係藉由該等接合線BW2而電性耦接到封裝基底120的電源面與接地面。此外，由於從額外封裝基底130到上元件晶粒110的一垂直距離係較短於從額外封裝基底130到封裝基底120的一垂直距離，所以連接在額外封裝基底130與上元件晶粒110之間的該等接合線BW1可具有一長度，係較短於連接在額外封裝基底130與封裝基底120之間的該等接合線BW2之一長度。
請參考圖1C及圖1D，在一些實施例中，上元件晶粒110的該等晶粒輸入/輸出112還包括多個重分布結構RD2。在該等導電墊AP2形成在上元件晶粒110之主動側AS2的一中心區內的該等實施例中，一些導電墊AP2係藉由該等重分布結構RD2而佈線到主動側AS2的一周圍區。在此方法中，上元件晶粒110的該等晶粒輸入/輸出112可同時分布在主動側AS2之中心區與周圍區。舉例來說，未藉由該等重分布結構RD2佈線的該等導電墊AP2係可與額外封裝基底130的開口W重疊，並藉由該等接合線 BW1(如圖1C所示)而連接到額外封裝基底130。在另一方面，藉由該等重分布結構RD2佈線的該等導電墊AP2，可被額外封裝基底130的本體部(如圖1A所示)所覆蓋。在一些實施例中，上元件晶粒110的一覆蓋區係較大於額外封裝基底130的一覆蓋區，以使位在上元件晶粒110之周圍區的該等重分布結構RD2可至少部分位在額外封裝基底130的外側，因此可用於建立在上元件晶粒110與封裝基底120之間的電性連接。舉個例子，該等導電墊AP2可配置成在中心區內的多個行。該等導電墊AP2遠離主動側AS2之周圍區的該等行可不藉由該等重分布結構RD2佈線，同時該等導電墊AP2接近主動側AS2之周圍區的該等行可藉由該等重分布結構RD2而佈線到周圍區。然而，所屬技術領域中具有通常知識者可依據設計所需而改良該等導電墊AP2與該等重分布結構RD2的架構，本揭露並不以此為限。
在一些實施例中，該等重分布結構RD2分別具有一導電線CL2以及一重分布墊RP2。應當理解，在圖1A中僅描述該等重分布結構RD2的該等重分布墊RP2，且在圖1A中係省略該等導電線CL2。此外，由於該等導電線CL2係被額外封裝基底130的本體部所覆蓋，所以在圖1C中並未顯示該等導電線CL2。在另一方面，在圖1D中均顯示出該等導電線CL2與該等重分布墊RP2。該等導電線CL2係從其中一導電墊AP2延伸到其中一重分布墊RP2。在一些實施例中，導電線CL2係從相對應之導電墊AP2暴露在主動側AS2處的一表面延伸，且側向接觸相對應的重分布墊RP2。導電線CL2可形成如一直線。或者是，導電線CL2可具有沿著其延伸方向的至少一轉折(turn)。
在一些實施例中，位在上元件晶粒110之周圍區內的重分布結構RD2，係藉由多個接合線BW3而連接到封裝基底120。為了建立在 上元件晶粒110與封裝基底120之間的電性連接，該等接合線BW3可分別從其中一重分布墊RP2延伸到封裝基底120之該等佈線結構128的一最上面部分。在一些實施例中，用於控制在上元件晶粒110中之積體電路的多個命令，係可經由該等接合線BW3而提供到上元件晶粒110。由於在上元件晶粒110與封裝基底120之間的一垂直距離，係較短於在額外封裝基底130與封裝基底120之間的一垂直距離，所以連接在上元件晶粒130與封裝基底120之間的該等接合線BW3可具有一長度，係較短於連接在額外封裝基底130與封裝基底120之間的該等接合線BW2。此外，該等接合線BW3的長度可較短於、相同於或是較長於該等接合線BW1。
請參考圖1A，在一些實施例中，半導體封裝結構10還包括一囊封體(encapsulant)140。囊封體140係囊封設置在封裝基底120上的多個元件。換言之，下元件晶粒100、上元件晶粒110、額外封裝基底130以及該等電連接件EC1、該等接合線BW1、BW2、BW3與黏貼材料AM1、AM2，係均被囊封體140所囊封。在一些實施例中，囊封體140的一側壁係大致與封裝基底120的一側壁為共面。囊封體140包含一模製化合物(molding compound)，例如環氧樹脂(epoxy resin)。在一些實施例中，囊封體140還包括多個填充粒子(圖未示)，係分散在模製化合物中。該等填充粒子可由一非有機材料(意即矽石(silica))所製，並經配置以改良囊封體140的一材料特性(意即熱膨脹係數(CTE))。
如上所述，依據本揭露的一些實施例的半導體封裝結構10係為一雙晶粒半導體封裝，並具有封裝基底120、接合在封裝基底120上的下元件晶粒100、貼合到下元件晶粒100上的上元件晶粒110以及貼合到上元件晶粒110上的額外封裝基底130。藉由設置額外封裝基底130，可提 供額外的電源面與額外的接地面給上元件晶粒110。相較於形成在封裝基底120中的電源面以及接地面，在額外封裝基底130中的這些額外的電源面與接地面係接近上元件晶粒110。因此，可藉由具有較低損耗之額外封裝基底130而提供電源及參考電壓給上元件晶粒110。據此，可改善上元件晶粒110的效能。
圖2為如圖1所示的該半導體封裝結構10之製備方法M10的流程示意圖。圖3A到圖3I為在如圖2所示之該半導體封裝結構10的製備流程期間在不同階段之結構的剖視示意圖。
請參考圖2及圖3A，執行步驟S11，並提供封裝基底120。在封裝基底120為具有一介電核心層(意即介電核心層122)之封裝基底的這些實施例中，多個積層介電層124以及多個導電圖案126的多層形成在介電核心層122的相對側。此外，該等佈線結構128的該等導電通孔與該等導電跡線係該等導電圖案126的該等層一起形成，且該等佈線結構128的該等穿孔(through vias)可形成在介電核心層122中。在一些實施例中，形成每一積層介電層124的方法包括一疊層製程(lamination process)，且形成該等導電圖案126之每一層的方法包括一微影製程以及一鍍覆製程或一沉積製程。此外，在一些實施例中，該等佈線結構128的該等穿孔之形成方法包括藉由一鑽孔(drilling)製程(例如一雷射鑽孔製程)以形成多個透孔(through holes)在介電核心層122中，且充填一導電材料進入這些透孔中，以藉由一鍍覆製程或一沉積製程而形成該等穿孔。在封裝基底120為一無核心封裝基底的那些實施例中，如此封裝基底的形成方法可類似於如參考圖3F所描述之額外封裝基底130的形成方法。
請參考圖2及圖3B，執行步驟S13，且下元件晶粒100接合 到封裝基底120上。在一些實施例中，下元件晶粒100經由一覆晶方式(flip chip manner)而接合到封裝基底120上。在這些實施例中，多個電連接件EC1可預先形成在下元件晶粒100的該等晶粒輸入/輸出102上，且下元件晶粒100係經由該等電連接件EC1而接合到封裝基底120上。在下元件晶粒100接合到封裝基底120上之後，該等電連接件EC1可接觸在封裝基底120中之該等導電圖案126的最上面一層以及該等佈線結構128的最上面部分，並可建立在下元件晶粒100與該等導電圖案126之間的電性連接。在一些實施例中，一取放(pick and place)製程係用於貼合下元件晶粒100到封裝基底120。此外，可接著執行一熱處理以接合下元件晶粒100到封裝基底120。
請參考圖2及圖3C，執行步驟S15，且黏貼材料AM1係提供在下元件晶粒100的後側BS1上。如參考圖1A所述，黏貼材料AM1可大致覆蓋整個後側BS1。在一些實施例中，形成黏貼材料AM1的方法包括一點膠製程(dispensing process)。
請參考圖2及圖3D，執行步驟S17，且上元件晶粒110貼合到黏貼材料AM1上。一旦上元件晶粒110貼合到黏貼材料AM1上，上元件晶粒110的後側BS2係接觸黏貼材料AM1，同時目前係暴露上元件晶粒110的主動側AS2。在一些實施例中，一取放製程係用於貼合上元件晶粒110在黏貼材料AM1上。此外，在一些實施例中，在上元件晶粒110貼合之後，係執行一熱處理，以固化黏貼材料AM1。
請參考圖2及圖3E，執行步驟S19，且黏貼材料AM2係提供在上元件晶粒110上。黏貼材料AM2形成在上元件晶粒110的主動側AS2，以使黏貼材料AM2覆蓋上元件晶粒110的至少一些晶粒輸入/輸出 112。在貼合在黏貼材料AM2上之額外封裝基底130具有位在額外封裝基底130之一中心區內的開口W的那些實施例中(如圖1C及圖3E所示)，黏貼材料AM2可具有一開口，係對準開口W。在這些實施例中，該等晶粒輸入/輸出112的一些導電墊AP2可暴露在黏貼材料AM2的開口中，同時黏貼材料AM2的一本體部係覆蓋其他的導電墊AP2。此外，在一些實施例中，該等晶粒輸入/輸出112的該等重分布墊RP2可分別部分或完全位在黏貼材料AM2的外側。在一些實施例中，形成黏貼材料AM2的方法包括一點膠製程。
請參考圖2及圖3F，執行步驟S21，且額外封裝基底130係提供且貼合在黏貼材料AM2上。在額外封裝基底130為一無核心封裝基底的那些實施例中，形成額外封裝基底130的方法包括交錯形成多個積層介電層132以及多個導電圖案134的多層在一載體(carrier)(圖未示)上。形成每一積層介電層132的方法可包括一疊層製程(lamination process)。此外，形成該等導電圖案134的每一層之方法可包括一微影製程以及一不鍍覆製程或一沉積製程。在一些實施例中，多個佈線結構136係與位在該等導電圖案134的最上面一層與最下面一層之間該等導電圖案134之一些層一起形成，且多個接合墊138係與該等導電圖案134的最上面一層一起形成。該等積層介電層132可由一聚合物材料所組成，同時該等導電圖案134、該等佈線結構136以及該等接合墊138可由一金屬材料所組成。在形成該等積層介電層132、該等導電圖案134、該等佈線結構136以及該等接合墊138之後，係移除載體，且餘留的結構係形成額外封裝基底130。或者是，額外封裝基底130為具有一介電核心層的封裝基底，且形成如此封裝基底的方法可類似於形成如參考圖3A所描述的封裝基底120之方法。在 額外封裝基底130貼合之後，額外封裝基底130的一下表面係接觸黏貼材料AM2的一上表面，且暴露該等導電圖案134的最上面一層以及該等接合墊138。在一些實施例中，再額外封裝基底130貼合之後，額外封裝基底130具有開口W，且額外封裝基底130的開口W可大致對準黏貼材料AM2的開口。一取放製程可用於貼合額外封裝基底130到黏貼材料AM2上。此外，在一些實施例中，在額外封裝基底130貼合之後，係執行一熱處理，以固化黏貼材料AM2。
請參考圖2及圖3G，執行步驟S23，以使額外封裝基底130電性連接到上元件晶粒110與封裝基底120，且上元件晶粒110電性連接到封裝基底120。在一些實施例中，額外封裝基底130藉由該等接合線BW1、BW2而分別電性連接到上元件晶粒110與封裝基底120。此外，在一些實施例中，上元件晶粒110藉由該等接合線BW3而電性連接到封裝基底120。該等接合線BW1可與上元件晶粒100的該等導電墊AP2連接，而該等導電墊AP2係暴露在額外封裝基底130之開口W中，同時該等接合線BW3可連接到上元件晶粒110的該等重分布墊RP2，而該等重分布墊RP2係至少部分位在額外封裝基底之跨度(span)外側。在一些實施例中，該等接合線BW1、BW2、BW3可分別藉由使用一線接合製程所形成，而線接合製程係包括一固相焊接步驟(solid phase welding step)。由於該等接合線BW3從一相對低高度延伸，所以該等接合線BW3的形成可先於該等接合線BW1、BW2。然而，所屬技術領域中具有通常知識者可依據製程需要而調整形成接合線BW1、BW2、BW3之製程的順序，本揭露並不以此為限。
請參考圖2及圖3H，執行步驟S25，且囊封體140係囊封設 置在封裝基底120上的多個元件。換言之，囊封體140係囊封下元件晶粒100、上元件晶粒110、額外封裝基底130以及該等電連接件EC1與該等接合線BW1、BW2、BW3。在一些實施例中，轉移模製(transfer-molding)製程、壓縮模製(compression-molding)製程或其他可行的模製製程係可用於形成囊封體140。此外，在一些實施例中，可對形成的囊封體140進行一平坦化製程(意即化學機械研磨製程)，以使囊封體140可具有一大致平坦上表面。
請參考圖2及圖3I，執行步驟S27，且多個封裝輸入/輸出EC2形成在封裝基底120背對下元件晶粒100之一側處。在該等封裝輸入/輸出EC2為BGA球的那些實施例中，形成該等封裝輸入/輸出EC2的方法可包括一植球製程(ball placement process)或一球安裝製程(ball mount process)。
請參考圖2、圖3I及圖1A，執行步驟S29，且對如圖3I所示的結構進行一單體化製程(singulation process)。在圖1A中係描述其中一單體化結構。在一些實施例中，單體化製程可包括一鋸刀切割製程(blade sawing process)、一電漿切割(plasma dicing)製程或其類似製程。在上述的該等實施例中，該等封裝輸入/輸出EC2的形成係先於單體化製程。然而，單體化製程可緊隨在該等封裝輸入/輸出EC2的形成之後。本揭露並未限制這兩步驟的順序。
至此，係依據該等實施例而形成半導體封裝結構10。還可對半導體封裝結構10進行其他封裝製程或測試程序。
圖4為依據本揭露一些實施例之一種半導體封裝結構20的平面示意圖。半導體封裝結構20係類似於如參考圖1A所描述的半導體封 裝結構10，且將僅討論其間的差異，而相同或類似的部分則不再重複。
請參考圖4，在一些實施例中，上元件晶粒110的該等導電墊AP2設置在上元件晶粒110之主動側AS2的一周圍區內，且額外封裝基底130可不具有如參考圖1A及圖1C所描述的開口W。在這些實施例中，上元件晶粒110的該等晶粒輸入/輸出112可不包括如參考圖1D所描述的該等重分布結構RD2。此外，每一導電墊AP2部分或完全位在額外封裝基底130之一跨度外側，且經由該等接合線BW1、BW3而分別電性連接到額外封裝基底130與封裝基底120。該等接合線BW1從該等接合墊138與該等導電圖案134的最上面一層延伸到一些導電墊AP2，以使電源電壓與參考電壓可從在額外封裝基底130中的電源面與接地面而提供到上元件晶粒110。此外，該等接合線BW3係從一些接合墊AP2延伸到在封裝基底120中之該等佈線結構128的最上面的部分，以使驅動在上元件晶粒110中之積體電路的多個命令，可從封裝基底120傳輸到上元件晶粒110。所屬技術領域中具有通常知識者可依據設計所需而改良該等導電墊AP2、該等接合墊138以及該等佈線結構128之最上面部分的架構，本揭露並不以此為限。
圖5為依據本揭露一些實施例之一種半導體封裝結構30的剖視示意圖。半導體封裝結構30係類似於如參考圖1A所描述的半導體封裝結構10，且將僅討論其間的差異，而相同或類似的部分則不再重複。
請參考圖5，在一些實施例中，下元件晶粒100的後側BS1面朝封裝基底120，同時下元件晶粒100的主動側AS1背對封裝基底120。在這些實施例中，黏貼材料AM1可覆蓋位在下元件晶粒100之主動側AS1處的該等晶粒輸入/輸出102。此外，該等晶粒輸入/輸出102的該等重分布 墊RP1可藉由多個接合線BW4而電性連接到封裝基底120。該等接合線BW4可從該等重分布墊RP1延伸到該等導電圖案124的最上面一層以及該等佈線結構128的一些最上面部分。再者，該等接合線BW4可部分嵌入在黏貼材料AM1中。形成該等接合線BW4的方法可類似於形成該等接合線BW1、BW2、BW3的方法，而在黏貼材料AM1提供在下元件晶粒100上之前，即可形成該等接合線BW4。
圖6A為依據本揭露一些實施例之一種半導體封裝結構40的剖視示意圖。圖6B為如圖6A所示在該半導體封裝結構40中一下元件晶粒100之一主動側AS1的平面示意圖。半導體封裝結構40係類似於如參考圖1A所描述的半導體封裝結構10，且將僅討論其間的差異，而相同或類似的部分則不再重複。
請參考圖6A及圖6B，在一些實施例中，係省略如參考圖1A及圖1B所描述的該等重分布結構RD1。在這些實施例中，下元件晶粒100的該等晶粒輸入/輸出102可僅包括該等導電墊AP1。此外，一黏貼材料AM3可設置在下元件晶粒100與封裝基底120之間。黏貼材料AM3可不覆蓋下元件晶粒100的整個主動側AS1。在該等導電墊AP1形成在主動側AS1之一中心區內的那些實施例中，黏貼材料AM3可具有二分開的子部分，且該等導電墊AP1可位在黏貼材料AM3的這些子部分之間的一空間內。關於半導體封裝結構40的一製造程序，在下元件晶粒100貼合到封裝基底120上之前，黏貼材料AM3可點膠(dispensed)在封裝基底120上，且在下元件晶粒100貼合之後，可執行一熱處理，以固化黏貼材料AM3。
圖7A為依據本揭露一些實施例之一種半導體封裝結構40a的剖視示意圖。圖7B為如圖7A所示在該半導體封裝結構40a中一下元件晶 粒100之一主動側AS1的平面示意圖。半導體封裝結構40a係類似於如參考圖6A所描述的半導體封裝結構40，且將僅討論其間的差異，而相同或類似的部分則不再重複。
請參考圖7A及圖7B，在該等導電墊AP1形成在下元件晶粒100之主動側AS1的一周圍區內的該等實施例中，該等導電墊AP1可位在黏貼材料AM3的相對側處。此外，黏貼材料AM3可形成一連續伸展圖案，而不是形成如具有多個分開的子部份。
如上，依據本揭露之該等實施例的半導體封裝結構具有一額外封裝基底，係貼合到上元件晶粒上。而額外封裝基底係經配置以提供電源面及接地面給上元件晶粒。相較於位在封裝基底中的電源面及接地面，其中下元件晶粒與上元件晶粒係貼合在該封裝基底上，在額外封裝基底中的這些電源面及接地面係更接近上元件晶粒。因此，電源電壓及參考電壓可藉由具有較少損耗之額外封裝基底而提供到上元件晶粒。據此，可改善上元件晶粒的性能。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一封裝基底；一下元件晶粒，貼合在該封裝基底上；一上元件晶粒，貼合在該下元件晶粒上，其中該上元件晶粒的一主動側背對該封裝基底方向，該上元件晶粒的一後側面朝該封裝基底，該上元件晶粒包括多個晶粒輸入/輸出，該等晶粒輸入/輸出位在該主動側處，且該等晶粒輸入/輸出的一第一部分電性連接到該封裝基底；以及一額外封裝基底，貼合到該上元件晶粒的該主動側上，其中該額外封裝基底電性連接到該上元件晶粒之該等晶粒輸入/輸出的一第二部分，並電性連接到該封裝基底。
本揭露之另一實施例提供一種半導體封裝結構。該半導體 封裝結構包括一第一封裝基底；一第一元件晶粒，接合到該第一封裝基底上，並具有一第一主動側以及一第一後側，該第一主動側面朝該第一封裝基底，該第一後側背對該第一主動側；一第二元件晶粒，貼合在該第一元件晶粒上，並具有一第二主動側以及一第二後側，該第二主動側背對該第一元件晶粒，該第二後側面朝該第一元件晶粒；一第二封裝基底，貼合在該第二元件晶粒的該第二主動側上，其中該第二元件晶粒位在該第二主動側處的多個晶粒輸入/輸出電性連接到該第一封裝基底與該第二封裝基底；以及一囊封體，設置在該第一封裝基底上，並囊封該第一元件晶粒、該第二元件晶粒以及該第二封裝基底。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該製備方法包括接合一下元件晶粒到一封裝基底上；貼合一上元件晶粒到該下元件晶粒上；貼合一額外封裝基底到該上元件晶粒上；建立該額外封裝基底與該上元件晶粒之間的電性連接、該額外封裝基底與該封裝基底之間的電性連接，以及該上元件晶粒與該封裝基底之間的電性連接；以及囊封該下元件晶粒、該上元件晶粒以及該額外封裝基底，其係藉由一囊封體進行囊封。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應 實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體封裝結構
100:下元件晶粒
102:晶粒輸入/輸出
110:上元件晶粒
112:晶粒輸入/輸出
120:封裝基底
122:介電核心層
124:積層介電層
126:導電圖案
128:佈線結構
130:額外封裝基底
132:積層介電層
134:導電圖案
136:佈線結構
138:接合墊
140:囊封體
AM1:黏貼材料
AM2:黏貼材料
AP1:導電墊
AP2:導電墊
AS1:主動側
AS2:主動側
BS1:後側
BS2:後側
BW1:接合線
BW2:接合線
BW3:接合線
CP1:導電柱
EC1:電連接件
EC2:封裝輸入/輸出
RP1:重分布墊
RP2:重分布墊
SJ1:焊料接頭
W:開口
W134:開口

Claims (16)

  1. 一種半導體封裝結構，包括：一封裝基底；一下元件晶粒，貼合在該封裝基底上；一上元件晶粒，貼合在該下元件晶粒上，其中該上元件晶粒的一主動側係背對該封裝基底，該上元件晶粒的一後側係面朝該封裝基底，該上元件晶粒包括多個晶粒輸入/輸出，該等晶粒輸入/輸出係位在該主動側處，且該等晶粒輸入/輸出的一第一部分係電性連接到該封裝基底；以及一額外封裝基底，貼合到該上元件晶粒的該主動側上，其中該額外封裝基底係電性連接到該上元件晶粒之該等晶粒輸入/輸出的一第二部分，並電性連接到該封裝基底；其中該額外封裝基底具有一基底開口以及一本體部，該本體部側向圍繞該基底開口設置。
  2. 如請求項1所述之半導體封裝結構，其中該額外封裝基底藉由多個第一接合線而電性連接到該等晶粒輸入/輸出的該第二部分，且該額外封裝基底藉由多個第二接合線而電性連接到該封裝基底。
  3. 如請求項3所述之半導體封裝結構，其中該等輸入/輸出的該第二部分與該開口重疊，且該等第一接合線從該額外封裝基底的一上表面經由該額外封裝基底的該開口而延伸到該等晶粒輸入/輸出的該第二部分。
  4. 如請求項2所述之半導體封裝結構，其中該等第二接合線從該額外封裝基底之一上表面的一周圍區延伸到該封裝基底。
  5. 如請求項1所述之半導體封裝結構，其中該等晶粒輸入/輸出的一第一部分至少部分位在該額外封裝基底的一跨度外側。
  6. 如請求項1所述之半導體封裝結構，其中該等晶粒輸入/輸出的該第一部分藉由多個第三接合線而電性連接到該封裝基底。
  7. 如請求項1所述之半導體封裝結構，還包括一第一黏貼材料以及一第二黏貼材料，該第一黏貼材料設置在該下元件晶粒與該上元件晶粒之間，該第二黏貼材料設置在該上元件晶粒與該額外封裝基底之間。
  8. 如請求項7所述之半導體封裝結構，其中該第二黏貼材料具有一材料開口以及一本體部，該本體部側向圍繞該額外封裝基底的該基底開口設置，而該第二黏貼材料的該材料開口與該等晶粒輸入/輸出的該第二部分重疊。
  9. 如請求項1所述之半導體封裝結構，其中該額外封裝基底經配置以提供一電源電壓以及一參考電壓給該上元件晶粒，而該封裝基底經配置以提供多個命令給在該上元件晶粒中的一積體電路。
  10. 如請求項1所述之半導體封裝結構，還包括一囊封體，設置在該封裝基底上，並囊封該下元件晶粒、該上元件晶粒以及該額外封裝基底。
  11. 如請求項1所述之半導體封裝結構，還包括多個封裝輸入/輸出，設置在該封裝基底背對該下元件晶粒的一表面處。
  12. 一種半導體封裝結構的製備方法，包括：接合一下元件晶粒到一封裝基底上；貼合一上元件晶粒到該下元件晶粒上；貼合一額外封裝基底到該上元件晶粒上；建立該額外封裝基底與該上元件晶粒之間的電性連接、該額外封裝基底與該封裝基底之間的電性連接，以及該上元件晶粒與該封裝基底之間的電性連接；囊封該下元件晶粒、該上元件晶粒以及該額外封裝基底，其係藉由一囊封體進行囊封；以及在該額外封裝基底貼合到該上元件晶粒之前，提供一第二黏貼材料在該上元件晶粒上。
  13. 如請求項12所述之半導體封裝結構的製備方法，其中該下元件晶粒經由一覆晶方式而接合到該封裝基底上。
  14. 如請求項13所述之半導體封裝結構的製備方法，還包括：在該下元件晶粒接合到該封裝基底上之前，形成多個電連接件在該下元件晶粒的一 主動側上，其中在該下元件晶粒接合到該封裝基底上之後，該等電連接件連接在該下元件晶粒的該主動側與該封裝基底之間。
  15. 如請求項12所述之半導體封裝結構的製備方法，還包括：在該上元件晶粒貼合到該下元件晶粒上之前，提供一第一黏貼材料在該下元件晶粒上。
  16. 如請求項12所述之半導體封裝結構的製備方法，其中藉由形成從該額外封裝基底延伸到該上元件晶粒的多個接合線、從該額外封裝基底延伸到該封裝基底的多個接合線以及從該上元件晶粒延伸到該封裝基底的多個電線，以建立電性連接。
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