TWI769022B - 接合元件及其製備方法 - Google Patents

接合元件及其製備方法 Download PDF

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TWI769022B
TWI769022B TW110127041A TW110127041A TWI769022B TW I769022 B TWI769022 B TW I769022B TW 110127041 A TW110127041 A TW 110127041A TW 110127041 A TW110127041 A TW 110127041A TW I769022 B TWI769022 B TW I769022B
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Taiwan
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layer
passivation layer
bonding element
connection bump
substrate
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TW110127041A
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English (en)
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TW202305957A (zh
Inventor
胡瀚文
劉德民
蔡逸杰
陳冠能
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國立陽明交通大學
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Priority to TW110127041A priority Critical patent/TWI769022B/zh
Priority to US17/477,996 priority patent/US11621241B2/en
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Publication of TWI769022B publication Critical patent/TWI769022B/zh
Publication of TW202305957A publication Critical patent/TW202305957A/zh

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Piezo-Electric Transducers For Audible Bands (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露提供一種接合元件及其製備方法，其中，製備方法包含以下步 驟：提供一承載基板；形成一第一金屬層於承載基板上；形成一第一絕緣層於第一金屬層上，其中第一絕緣層包含一第一穿孔；形成一第一鈍化層及一第一導電層於第一穿孔中，其中第一穿孔中的第一鈍化層與第一導電層形成一第一連接凸塊；形成一第一基板於第一連接凸塊及第一絕緣層上；移除承載基板及第一金屬層，形成一第一子接合元件；以及以第一連接凸塊的第一鈍化層的表面，將第一子接合元件與一第二子接合元件進行一對接製程，形成接合元件。

Description

接合元件及其製備方法
本揭露提供一種接合元件及其製備方法，尤指一種可提高接合可靠度、簡化製程或降低成本之接合元件及其製備方法。
隨著科技發展及因應消費者需求，現今電子產品大多朝向高整合度方向發展，即單一電子裝置中可具有多種功能。而愈多功能的電子產品伴隨著所需晶片數量愈多，以及晶片I/O數愈高等。
然而，於一般傳統接合製程中，受限於器件表面平整度之限制，多採用焊材或凸塊等元件進行接合，在接點密度上受到限制。若要提升接點密度，則須於接合前進行平坦化等製程，導致成本提高。此外，傳統接合製程中的高溫也容易造成器件損傷，降低製程良率。
因此，目前亟需提供一種接合元件的製備方法及接合元件，以改善傳統接合技術之缺點。
於本揭露中，除了特別指明者之外，具備「一」元件不限於具備單一的該元件，而可具備一或更多的該元件。再者，說明書與申請專利範圍中所使用的序數例如「第一」及「第二」等之用詞，以修飾權利要求之元件，其本身並不意含或代表該請求元件有任何之前的序數，也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。
於本揭露中，「包含」、「含有」、「具有」等詞為開放式詞語，因此其應被解釋為「含有但不限定為...」之意。因此，當本揭露的描述中使用術語「包含」、「含有」及/或「具有」時，其指定了相應的特徵、區域、步驟、操作及/或構件的存在，但不排除一個或多個相應的特徵、區域、步驟、操作及/或構件的存在。
除非另外定義，本揭露中使用的全部用語(包含技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是這些用語，例如在通常使用的字典中定義的用語，應被解讀成具有一與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在此特別定義。
此外，於本揭露中可能使用相對性的用語，例如「下方」或「底部」及「上方」或「頂部」，以描述圖式的一個元件對於另一元件的相對關係。能理解的是，如果將圖式的裝置翻轉使其上下顛倒，則所敘述在「下方」側的元件將會成為在「上方」側的元件。當相應的構件(例如膜層或區域)被稱為「在另一個構件上」時，它可以直接在另一個構件上，或者兩者之間可存在有其他構件。另一方面，當構件被稱為「直接在另一個構件上」時，則兩者之間不存 在任何構件。另外，當一構件被稱為「在另一個構件上」時，兩者在俯視方向上有上下關係，而此構件可在另一個構件的上方或下方，而此上下關係取決於裝置的取向(orientation)。
於本揭露中，長度與寬度的量測方式可以是採用光學顯微鏡量測而得，厚度則可以由電子顯微鏡中的剖面影像量測而得，但不本揭露並不局限於此。此外，用語「範圍為第一數值至第二數值」、「範圍介於第一數值至第二數值之間」表示所述範圍包含第一數值、第二數值以及它們之間的其它數值。
本揭露提供一種接合元件之製備方法，包含以下步驟：提供一承載基板；形成一第一金屬層於該承載基板上；形成一第一絕緣層於該第一金屬層上，其中該第一絕緣層包含一第一穿孔；形成一第一鈍化層於該第一穿孔中；形成一第一導電層於該第一鈍化層上，其中該第一絕緣層的該第一穿孔中的該第一鈍化層與該第一導電層形成一第一連接凸塊；形成一第一基板於該第一連接凸塊及該第一絕緣層上；移除該承載基板及該第一金屬層，以顯露出該第一連接凸塊的該第一鈍化層的一表面及該第一絕緣層的一表面，形成一第一子接合元件；以及以該第一連接凸塊的該第一鈍化層的該表面，將該第一子接合元件與一第二子接合元件進行一對接製程，形成該接合元件。
於本揭露中，承載基板和第一基板的材料並無特殊限制，例如可為石英基板、玻璃基板、晶圓、藍寶石基板、軟硬混合板或其他硬質基板。或者，承載基板和第一基板也可為可撓性基板或薄膜，其材料可包含聚碳酸酯(PC)、聚醯亞胺(PI)、聚丙烯(PP)、聚對苯二甲酸乙酯(PET)、或其他塑膠材料，但本揭露並不局限於此。於本揭露中，可使用相同或不相同材料來分別製備承載基板和第一基板。此外，於本揭露之一實施態樣中，承載基板與第一金屬層 間可更包含一離型層，可利於後續移除承載基板之步驟。在此，離型層可為黏著劑、環氧樹脂、晶粒附接膜(Die Attach Film,DAF)、或其類似物，但本揭露並不局限於此。
於本揭露中，第一金屬層的材料並無特別限制，例如可包含銅(Cu)、鎳(Ni)、鈦(Ti)、鉻(Cr)、其合金、或其組合，但本揭露並不局限於此。第一金屬層可由單層或多層金屬材料所構成，例如於本揭露之一態樣中，第一金屬層可由Ti/Cu多層金屬材料所構成。
於本揭露中，第一絕緣層的材料可為聚醯亞胺(PI)、感光型聚醯亞胺(Photosensitive PI；PSPI)、環氧樹脂、聚苯並噁唑(Polybenzoxazole,PBO)、苯並環丁烯(Benzocyclobutene,ECB)、氮化矽、氧化矽、氮氧化矽、碳氮化矽、光阻、聚合物、或其組合，但本揭露並不局限於此。於本揭露之一態樣中，可藉由微影製程於第一絕緣層上形成第一穿孔，但本揭露並不局限於此。於本揭露中，第一鈍化層和第一導電層可形成於第一絕緣層的第一穿孔中，換句話說，第一絕緣層可包覆第一鈍化層及第一導電層，因此，可提升第一連接凸塊的可靠度，進而可改善後續接合元件的可靠度。於本揭露中，第一導電層和/或第一鈍化層可更形成於第一穿孔的一側壁上，更具體地，當第一鈍化層形成於第一穿孔中，且第一導電層形成於第一穿孔的側壁上時，第一導電層可直接與第一穿孔的側壁接觸；當第一鈍化層和第一導電層形成於第一穿孔的側壁上時，第一鈍化層可直接與第一穿孔的側壁接觸。
於本揭露中，第一鈍化層的材料可包含至少一選自由金(Au)、銀(Ag)、Cu、鈀(Pd)、鉑(Pt)、釕(Ru)、鋁(Al)、鈷(Co)、Ni、Ti、鉬(Mo)、錳(Mn)及鋅(Zn)所組成的群組。第一鈍化層的材料可為單一金屬材料、其合金、或其組 合，其中合金的具體例子可包含康銅、錳銅等，但本揭露並不局限於此。此外，在上述金屬材料中，可包含沿任何晶軸方向排列的金屬材料，例如可為沿[111]、[100]、[311]、或[220]晶軸方向排列的金屬材料，但本揭露並不局限於此。第一鈍化層的厚度可為1nm至300nm，例如可為1nm至200nm、1nm至150nm、1nm至100nm、1nm至80nm、1nm至50nm、1nm至30nm、3nm至80nm、3nm至50nm、5nm至50nm、或5nm至30nm，但本揭露並不局限於此。
於本揭露中，第一鈍化層可保護第一導電層，避免第一導電層於對接製程中氧化，可提升接合元件的可靠度、或改善接合效果。此外，第一鈍化層可降低對接製程的接合溫度，可用於降低製備成本、或改善製程良率。於本揭露之一態樣中，第一鈍化層的材料可包含Au，但本揭露並不局限於此。於本揭露之另一態樣中，第一鈍化層的材料可包含Ag，但本揭露並不局限於此。
於本揭露中，第一導電層的材料可包含Cu，但本揭露並不局限於此。第一導電層的厚度並無特別限制，可視欲接合的器件而調整。於本揭露中，可使用濺鍍、電鍍、化學鍍(chemical plating)、化學氣相沉積等方法、或其組合，來分別形成第一金屬層、第一鈍化層和第一導電層。此外，可使用相同或不相同的方法來製備所述第一金屬層、第一鈍化層和第一導電層。
於本揭露中，移除第一承載基板及第一金屬層的方法並無特別限制，可使用本領域已知的工藝進行移除步驟。於本揭露之一態樣中，可藉由蝕刻法來移除第一金屬層，所述蝕刻法包含濕蝕刻、乾蝕刻、或其組合，但本揭露並不局限於此。
於本揭露中，對接製程的溫度可為室溫至250℃，例如可為室溫至200℃、室溫至180℃、室溫至150℃、室溫至120℃、室溫至100℃、50℃至200 ℃、80℃至200℃、80℃至180℃、或50℃至150℃，但本揭露並不局限於此。此外，對接製程的時間可為大於或等於10秒，例如可為10秒至90分鐘、10秒至80分鐘、10秒至60分鐘、10秒至300秒、10分鐘至60分鐘，但本揭露並不局限於此，可視欲接合的器件而調整，例如當器件為晶片級時，對接製程的時間可為15秒至180秒；當器件為晶圓級時，對接製程的時間可為15分鐘至50分鐘，但本揭露並不局限於此。
於本揭露之一態樣中，於形成該第一導電層於該第一鈍化層上之步驟前，更包含一步驟：形成一潤濕層於該第一鈍化層上。更具體地，潤濕層可更設置於該第一絕緣層的該第一穿孔中，且該潤濕層位於該第一鈍化層與該第一導電層之間。
於本揭露中，潤濕層可進一步降低對接製程的溫度，可降低成本、或改善高溫導致的器件損傷等缺點。於本揭露中，潤濕層的材料可為任何可提供潤濕效果的材料，例如可包含至少一選自由Ti、Cr、Ni、Co、鉭(Ta)、其合金及其組合所組成的群組。在上述金屬材料中，可包含沿任何晶軸方向排列的金屬材料，例如可為沿[111]、[100]、[311]、或[220]晶軸方向排列的金屬材料，但本揭露並不局限於此。此外，可使用與第一金屬層或第一鈍化層相似的方法來製備潤濕層，在此不再贅述。潤濕層的厚度可為0.1nm至50nm，例如可為0.5nm至30nm、0.5nm至15nm、0.5nm至10nm、1nm至50nm、1nm至30nm、1nm至10nm、1nm至8nm、或1nm至5nm，但本揭露並不局限於此。
於本揭露之一態樣中，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，可更包含：形成一第二金屬層於該第一連接凸塊及該 第一絕緣層上。在此，第二金屬層的材料及製備方法與第一金屬層相似，在此不再贅述。此外，第二金屬層可與第一連接凸塊接觸，以提供電性連接。
於本揭露中，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，該第一連接凸塊的該第一導電層的表面具有一第一粗糙度。更具體地，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，可更包含一步驟：蝕刻該第一鈍化層及該第一導電層，以形成該第一連接凸塊。因此，所述「第一粗糙度」是指第一穿孔中的第一導電層的上表面(即遠離承載基板的表面)的粗糙度，更具體地，是指蝕刻第一鈍化層及第一導體層後的第一導體層的表面的粗糙度。
於移除該承載基板及該第一金屬層之步驟後，所顯露的該第一連接凸塊的該第一鈍化層的該表面(即遠離第一基板的表面)具有一第二粗糙度，且所述第一粗糙度不等於第二粗糙度，更具體地，該第一粗糙度可大於該第二粗糙度。因此，當以第一連接凸塊的第一鈍化層的該表面，將第一子接合元件與第二子接合元件進行對接製程時，不需再經過平坦化等其他製程，可降低生產成本、或實現高接點密度的效果。
於本揭露之另一實施態樣中，於形成該第一連接凸塊之步驟後，可更包含：形成一絕緣層於該第一連接凸塊上，其中該絕緣層包含一穿孔；以及形成一第三連接凸塊於該穿孔中，其中，該第三連接凸塊包含一潤濕層及一導電層，該潤濕層位於該第一連接凸塊與該導電層之間，且該潤濕層與該第一導電層接觸。因此，第一子接合元件可更包含第三連接凸塊，且第一連接凸塊與第三連接凸塊可電性連接，可提供信號或電傳導。此外，可視接合元件需要 設置一或多個第三連接凸塊，所形成之接合元件可應用於重布線路層薄膜堆疊、2.5D封裝等，但本揭露並不局限於此。
於本揭露中，第二子接合元件可包含：一第二基板；一第二絕緣層，設於該第二基板上且包含一第二穿孔；以及一第二連接凸塊，設於該第二穿孔中且包含一第二鈍化層及一第二導電層，其中該第二導電層設於該第二鈍化層與該第二基板間。因此，當該第一子接合元件與該第二子接合元件進行對接製程時，該第一連接凸塊的該第一鈍化層可與該第二連接凸塊的該第二鈍化層連接，該第一子接合元件的該第一絕緣層可與該第二子接合元件的該第二絕緣層連接。於本揭露之一態樣中，當該第一子接合元件與該第二子接合元件進行對接製程時，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接可形成一接點，其中，該接點更包含一連接層，該連接層形成於該第一鈍化層與該第二鈍化層之間。於本揭露中，可以第一子接合元件的第一連接凸塊的第一鈍化層與第二子接合元件的第二連接凸塊的第二鈍化層直接進行對接製程，不需要進行額外的微影製程等其他步驟，可簡化製程步驟或降低成本。
於本揭露中，連接層可包含一第一金屬。由於第一導電層或第二導電層的材料可透過第一鈍化層、第二鈍化層或潤濕層擴散至連接層中，因此，連接層可包含第一導電層或第二導電層所包含的金屬。於本揭露之一態樣中，第一導電層或第二導電層的材料可包含Cu，因此，連接層包含的第一金屬可為Cu。
於本揭露之一態樣中，潤濕層的材料也可擴散至連接層中，因此，連接層可更包含一第二金屬，該第二金屬可包含潤濕層所包含的材料，更具體地，第二金屬可包含至少一選自由Ti、Cr、Ni、Co、及Ta所組成的群組。 於本揭露之一態樣中，所形成的連接層可包含第一金屬及第二金屬，與包含第一金屬的連接層相比，可表現出更好的接合效果。
於本揭露中，第二子接合元件的製備方法及材料可與第一子接合元件相似，在此不再贅述，但本揭露並不局限於此。此外，由於第二連接凸塊設於第二絕緣層的第二穿孔中，換句話說，第二絕緣層可包圍第二連接凸塊，因此，可提升第二連接凸塊的可靠度，進而可改善後續接合元件的可靠度。
經由上述製備方法所形成的接合元件可包含：一第一子接合元件，包含：一第一基板；一第一絕緣層，設於該第一基板上且包含一第一穿孔；以及一第一連接凸塊，設於該第一穿孔中且包含一第一鈍化層及一第一導電層，其中該第一導電層設於該第一鈍化層與該第一基板間；以及一第二子接合元件，包含：一第二基板；一第二絕緣層，設於該第二基板上且包含一第二穿孔；以及一第二連接凸塊，設於該第二穿孔中且包含一第二鈍化層及一第二導電層，其中該第二導電層設於該第二鈍化層與該第二基板間；其中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接，該第一子接合元件的該第一絕緣層與該第二子接合元件的該第二絕緣層連接。
於本揭露中，由於第一連接凸塊是設於第一絕緣層的第一穿孔中，換句話說，第一絕緣層可包圍第一連接凸塊，因此，可提升第一子接合元件的可靠度，進而可改善後續接合元件的可靠度。相似地，由於第二連接凸塊是設於第二絕緣層的第二穿孔中，換句話說，第二絕緣層可包圍第二連接凸塊，因此，可提升第二子接合元件的可靠度，進而可改善後續接合元件的可靠度。
於本揭露之一態樣中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接可形成一接點，該接點更包含一連接層，且該連 接層形成於該第一鈍化層與該第二鈍化層之間。因此，第一子接合元件與第二子接合元件可藉由連接層彼此接合，可改善第一子接合元件與第二子接合元件的接合效果，提升接合元件的可靠度、或提高接點密度。
於本揭露中，在接合元件的一剖面中，該第一連接凸塊具有一第一表面及一第二表面，該第一表面朝向該第一基板且與該第二表面相對，且該第一表面的寬度大於該第二表面的寬度。而該第二連接凸塊具有一第三表面及一第四表面，該第三表面朝向該第二基板且與該第四表面相對，且該第三表面的寬度大於該第四表面的寬度。
於本揭露之一態樣中，該第一子接合元件可更包含一潤濕層，設於該第一鈍化層上，且該潤濕層位於該第一鈍化層與該第一導電層之間。而該第二子接合元件可更包含另一潤濕層層，設於該第二鈍化層上，且該另一潤濕層位於該第二鈍化層與該第二導電層之間。在此，另一潤濕層的材料可與潤濕層相似，在此不再贅述。此外，潤濕層的材料與另一潤濕層的材料可為相同或不相同。
於本揭露中，該連接層可包含一第一金屬，該第一金屬可為該第一導電層或該第二導電層所包含的金屬。於本揭露之一態樣中，第一導電層或第二導電層的材料可包含Cu，因此，第一金屬可為Cu。此外，於本揭露之一態樣中，該連接層可更包含一第二金屬，該第二金屬可為潤濕層或另一潤濕層所包含的金屬，更具體地，該第二金屬可包含至少一選自由Ti、Cr、Ni、Co、及Ta所組成的群組。
於本揭露之另一實施態樣中，第一子接合元件可更包含：一絕緣層，設置於該第一連接凸塊上且包含一穿孔；以及一第三連接凸塊，設置於該 穿孔中且包含一潤濕層及一導電層，其中該潤濕層設於該第一連接凸塊與該導電層之間，且該潤濕層與該第一導電層接觸。因此，第一連接凸塊與第三連接凸塊可電性連接，可提供信號或電傳導，所形成之接合元件可應用於重布線路層薄膜堆疊、2.5D封裝等，但本揭露並不局限於此。相似地，第二子接合元件也可視需要包含第三連接凸塊，在此不再贅述。
綜上所述，本揭露提供一種新穎的接合元件的製備方法，可在不需要額外的平坦化、或微影製程等其他步驟下，實現改善的接合效果。此外，本揭露所提供之製備方法可降低對接製程的溫度，達到降低成本、或改善製程良率的效果。而由此製備的接合元件可具有改善的可靠度、或改善的接點密度。
1:第一絕緣層
11:第一穿孔
111:側壁
12、13:表面
1’:第二絕緣層
11’:第二穿孔
2:第一鈍化層
21:表面
2’:第二鈍化層
21’:表面
3、3’、8:潤濕層
4:第一導電層
41:表面
4’:第二導電層
5:第二金屬層
5’:第三金屬層
6:第一基板
6’:第二基板
7:絕緣層
71:穿孔
9:導電層
100:承載基板
200:第一金屬層
300:光阻
CB1:第一連接凸塊
CB2:第二連接凸塊
CB3:第三連接凸塊
CL:連接層
SBE1:第一子接合元件
SBE2:第二子接合元件
BE:接合元件
S1:第一表面
S2:第二表面
S3:第三表面
S4:第四表面
W1、W2、W3、W4:寬度
圖1A至1H為本揭露之一實施例之接合元件之製備方法之示意圖。
圖2A為本揭露之實施例1之一實施態樣之接合元件之剖面圖。
圖2B為本揭露之實施例1之另一實施態樣之接合元件之剖面圖。
圖3A至圖3C為本揭露之另一實施例之接合元件之製備方法之部分示意圖。
圖4A為本揭露之實施例2之一實施態樣之接合元件之剖面圖。
圖4B為本揭露之實施例2另一實施態樣之接合元件之剖面圖
圖5為本揭露之又一實施例之接合元件之製備方法之部分示意圖。
以下係藉由特定的具體實施例說明本揭露之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本揭露之其他優點與功效。本揭露亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可針對不同觀點與應用，在不悖離本創作之精神下進行各種修飾與變更。
須說明的是，下文中不同實施例所提供的技術方案可相互替換、組合或混合使用，以在未違反本揭露精神的情況下構成另一實施例。
實施例1
圖1A至1H為本揭露之一實施例之接合元件之製備方法之示意圖。圖2A和圖2B為本揭露之實施例1之接合元件之剖面圖。
如圖1A所示，提供一承載基板100。形成一第一金屬層200於承載基板100上。接著，如圖1B所示，形成一第一絕緣層1於第一金屬層200上，其中，第一絕緣層1藉由微影製程形成一第一穿孔11。而後，如圖1C所示，形成一第一鈍化層2於第一絕緣層1上及第一穿孔11中；以及形成一潤濕層3於第一鈍化層2上及第一穿孔11中。更具體地，第一鈍化層2及第一潤濕層3可形成於第一穿孔11的側壁111上，其中，第一鈍化層2可與第一穿孔11的側壁111接觸。
接著，以微影製程形成一圖案化光阻300於潤濕層3上，其中，圖案化光阻300不設置於第一穿孔11內，如圖1D所示。而後，於潤濕層3上電鍍銅形成一第一導電層4，更具體地，第一導電層4是形成於第一穿孔11中的潤濕層3上。
接著，以蝕刻法將部分第一導電層4、第一鈍化層2、潤濕層3及光阻300移除，以顯露第一絕緣層1的一表面12，如圖1E所示。在此，第一絕緣層1的表面12是指第一絕緣層1遠離承載基板100的表面。其中，第一絕緣層1的 第一穿孔11中的第一鈍化層2、潤濕層3與第一導電層4形成一第一連接凸塊CB1，第一連接凸塊CB1的第一導電層4的表面41具有一第一粗糙度。在此，第一導電層4的表面41是指第一導電層4遠離承載基板100的表面。
而後，如圖1F所示，形成一第二金屬層5以及一第一基板6於第一連接凸塊CB1及第一絕緣層1上。更具體地，係先形成一第二金屬層5於第一連接凸塊CB1及第一絕緣層1上，再形成第一基板6於第二金屬層5上。
接著，分別移除承載基板100及第一金屬層200，以顯露出第一連接凸塊CB1的第一鈍化層2的一表面21及第一絕緣層1的一表面13，形成一第一子接合元件SBE1，如圖1G所示。因此，第一子接合元件SBE1包含一第一基板6；一第一絕緣層1，設於第一基板6上且包含一第一穿孔11；以及一第一連接凸塊CB1，設於第一穿孔11中且包含一第一鈍化層2及一第一導電層4，其中第一導電層4設於第一鈍化層2與第一基板6間。於此態樣中，第一子接合元件SBE1更包含一第二金屬層5，設置於第一連接凸塊CB1及第一絕緣層1上；第一連接凸塊CB1更包含一潤濕層3，設於第一鈍化層2及第一導電層4之間。
在此，第一鈍化層2的表面21是指第一鈍化層2遠離第一基板6的表面；第一絕緣層1的表面13是指第一絕緣層1遠離第一基板6的表面。其中，第一鈍化層2的表面21具有一第二粗糙度，且第一粗糙度大於該第二粗糙度。由於第二粗糙度較小，將有利於以第一連接凸塊CB1的第一鈍化層2的表面21進行後續對接製程。
而後，如圖1H所示，以第一連接凸塊CB1的第一鈍化層2的表面21，將第一子接合元件SBE1與一第二子接合元件SBE2進行一對接製程，形成接合元件BE，如圖2A或圖2B所示。在此，可以上述製備第一子接合元件SBE1相 同之方法來製備第二子接合元件SBE2，因此，第二子接合元件SBE2包含一第二基板6’；一第二絕緣層1’，設於第二基板6’上且包含一第二穿孔11’；以及一第二連接凸塊CB2，設於第二穿孔11’中且包含一第二鈍化層2’及一第二導電層4’，其中第二導電層4’設於第二鈍化層2’與第二基板6’間。於此態樣中，第二子接合元件SBE2更包含一第三金屬層5’，設置於第二連接凸塊CB2及第二絕緣層1’上；第二連接凸塊CB2更包含一潤濕層3’，設於第二鈍化層2’與第二導電層4’之間。此外，第一子接合元件SBE1是以第一連接凸塊CB1的第一鈍化層2的表面21與第二子接合元件SBE2對接；相似地，第二子接合元件SBE2是以第二連接凸塊CB2的第二鈍化層2’的表面21’與第一子接合元件SBE1對接。
如圖1H所示，於剖面圖中，第一連接凸塊CB1具有一第一表面S1及一第二表面S2，第一表面S1朝向第一基板6且與第二表面S2相對，換句話說，第一表面S1靠近第一基板6，且第二表面S2遠離第一基板6。其中，第一表面S1的寬度W1大於第二表面S2的寬度W2。相似地，於剖面圖中，第二連接凸塊CB2具有一第三表面S3及一第四表面S4，第三表面S3朝向第二基板6’且與第四表面S4相對，換句話說，第三表面S3靠近第二基板6’，且第四表面S4遠離第二基板6’。其中，第三表面S3的寬度W3大於第四表面S4的寬度W4。
於本實施例之一態樣中，當第一子接合元件SBE1與第二子接合元件SBE2對接後，如圖2A所示，第一連接凸塊CB1的第一鈍化層2與第二連接凸塊CB2的第二鈍化層2’連接而形成一接點，第一子接合元件SBE1的第一絕緣層1與第二子接合元件SBE2的第二絕緣層1’連接，且接點更包含一連接層CL，其中連接層CL形成於第一鈍化層2與第二鈍化層2’之間。因此，如圖2A所示，接合元件BE包含：一第一子接合元件SBE1，包含：一第一基板6；一第一絕緣層1，設於 第一基板6上且包含一第一穿孔11；以及一第一連接凸塊CB1，設於第一穿孔11中且包含一第一鈍化層2及一第一導電層4，其中第一導電層4設於第一鈍化層2與第一基板6間；以及一第二子接合元件SBE2，包含：一第二基板6’；一第二絕緣層1’，設於第二基板6’上且包含一第二穿孔11’；以及一第二連接凸塊CB2，設於第二穿孔11’中且包含一第二鈍化層2’及一第二導電層4’，其中第二導電層4’設於第二鈍化層2’與第二基板6’間；其中，第一連接凸塊CB1的第一鈍化層2與第二連接凸塊CB2的第二鈍化層2’連接而形成一接點，第一子接合元件SBE1的第一絕緣層1與第二子接合元件SBE2的第二絕緣層1’連接，且接點更包含一連接層CL，連接層CL形成於第一鈍化層2與該第二鈍化層2’之間。於此態樣中，第一連接凸塊CB1更包含一潤濕層3，設置於第一鈍化層2與第一導電層4之間；第二連接凸塊CB2更包含一潤濕層3’，設置於第二鈍化層2’與第二導電層4’之間。
由於第一導電層4的材料可透過第一鈍化層2或潤濕層3擴散至連接層CL中；相似地，第二導電層4’的材料可透過第二鈍化層2’或潤濕層3’擴散至連接層CL中，因此，連接層CL可包含第一導電層4或第二導電層4’所包含的金屬。此外，潤濕層3/3’的材料也可擴散至連接層CL中，因此，連接層CL可更包含潤濕層3/3’所包含的材料。
於圖2A中，第一子接合元件SBE1與第二子接合元件SBE2大致上是對準的，換句話說，在接合元件BE的第一基板6的俯視方向上，第一連接凸塊CB1的第二表面S2會與第二連接凸塊CB2的第四表面S4大致上重疊。在此，所述「大致上重疊」是指第一連接凸塊CB1的第二表面S2與第二連接凸塊CB1的第四表面S4的重疊面積大於或等於90%。然而，雖然圖未示，於本實施例的其他態樣中，第一連接凸塊CB1的第二表面S2可與第二連接凸塊CB2的第四表面S4不完全 重疊，只要能達到電性連接的目的即可。在此，所述「不完全重疊」是指第一連接凸塊CB1的第二表面S2與第二連接凸塊CB1的第四表面S4的重疊面積小於90%，例如重疊面積可大於等於50%，且小於90%，但並不局限於此。因此，第一連接凸塊CB1的部分第一鈍化層2也可與第二子接合元件SBE2的部分第二絕緣層1’連接，相似地，第二連接凸塊CB2的部分第二鈍化層2’也可與第一子接合元件SBE1的部分第一絕緣層1連接。
圖2B為本實施例之另一實施態樣之接合元件之剖面圖。其中，圖2B之接合元件與圖2A相似，除了以下差異。
於本實施例之另一態樣中，當第一子接合元件SBE1與第二子接合元件SBE2對接後，如圖2B所示，第一連接凸塊CB1的第一鈍化層2與第二連接凸塊CB2的第二鈍化層2’連接，第一子接合元件SBE1的第一絕緣層1與第二子接合元件SBE2的第二絕緣層1’連接。更具體地，第一連接凸塊CB1的第一鈍化層2會與第二連接凸塊CB2的第二鈍化層2’直接接觸。
此外，於圖2B中的第一子接合元件SBE1與第二子接合元件SBE2大致上是對準的，換句話說，在接合元件BE的第一基板6的俯視方向上，第一連接凸塊CB1的第二表面S2會與第二連接凸塊CB2的第四表面S4大致上重疊。然而，雖然圖未示，於本實施例的其他態樣中，第一連接凸塊CB1的第二表面S2可與第二連接凸塊CB2的第四表面S4不完全重疊，只要能達到電性連接的目的即可。因此，第一連接凸塊CB1的部分第一鈍化層2也可與第二子接合元件SBE2的部分第二絕緣層1’連接，相似地，第二連接凸塊CB2的部分第二鈍化層2’也可與第一子接合元件SBE1的部分第一絕緣層1連接。
實施例2
圖3A至圖3C為本揭露之另一實施例之接合元件之製備方法之部分示意圖。圖4A和圖4B為本揭露之實施例2之接合元件之剖面圖。其中，圖3A至圖3C的製備方法與圖1A至圖1C相似，除了以下差異。
如圖3A所示，提供一承載基板100。形成一第一金屬層200於承載基板100上。形成一第一絕緣層1於第一金屬層200上，其中，第一絕緣層1藉由微影製程形成一第一穿孔11。接著，如圖3B所示，以化學鍍製程形成一第一鈍化層2於第一穿孔11中。而後，如圖3C所示，形成一潤濕層3於第一絕緣層1和第一鈍化層2上以及第一穿孔11中。更具體地，由於第一鈍化層2是以化學鍍製程形成，因此，第一鈍化層2可不形成於第一絕緣層1上，且後續形成的潤濕層3可直接與第一穿孔11的側壁111接觸。
接著，後續製備方法與實施例1相似，更具體地，後續製備方法可如圖1D至1H所示，依序形成第一導電層4、第二金屬層5及第一基板6，並移除承載基板100及第一金屬層200後，形成第一子接合元件SBE1。而後，以第一連接凸塊CB1的第一鈍化層2的表面21，將第一子接合元件SBE1與一第二子接合元件SBE2進行一對接製程，形成接合元件BE，如圖4A或圖4B所示。在此，可以上述製備第一子接合元件SBE1相同之方法來製備第二子接合元件SBE2，因此，第二子接合元件SBE2的第二鈍化層2’可不形成於第二絕緣層1’上，且潤濕層3’可直接與第二穿孔11’的側壁接觸。
因此，於本實施例中，所形成的接合元件BE如圖4A所示。其中，圖4A的接合元件BE與圖2A相似，除了以下差異。
如圖4A所示，當第一子接合元件SBE1與第二子接合元件SBE2對接後，第一連接凸塊CB1的第一鈍化層2與第二連接凸塊CB2的第二鈍化層2’連 接而形成一接點，第一子接合元件SBE1的第一絕緣層1與第二子接合元件SBE2的第二絕緣層1’連接，且接點更包含一連接層CL，其中連接層CL形成於第一鈍化層2與第二鈍化層2’之間。與圖4A的接合元件BE不同的是，圖4A的接合元件BE的第一鈍化層2可不形成於第一絕緣層1上，且潤濕層3可直接與第一穿孔11的側壁111接觸。相似地，第二鈍化層2’可不形成於第二絕緣層1’上，且潤濕層3’可直接與第二穿孔11’的側壁接觸。
於圖4A中，第一子接合元件SBE1與第二子接合元件SBE2大致上是對準的，換句話說，在接合元件BE的第一基板6的俯視方向上，第一連接凸塊CB1的第二表面S2會與第二連接凸塊CB2的第四表面S4大致上重疊。雖然圖未示，於本實施例的其他態樣中，第一連接凸塊CB1的第二表面S2可與第二連接凸塊CB2的第四表面S4不完全重疊，只要能達到電性連接的目的即可。因此，第一連接凸塊CB1的部分第一鈍化層2也可與第二子接合元件SBE2的部分第二絕緣層1’連接，相似地，第二連接凸塊CB2的部分第二鈍化層2’也可與第一子接合元件SBE1的部分第一絕緣層1連接。
圖4B為本實施例之另一實施態樣之接合元件之剖面圖。其中，圖4B之接合元件與圖4A相似，除了以下差異。
於本實施例之另一態樣中，當第一子接合元件SBE1與第二子接合元件SBE2對接後，如圖4B所示，第一連接凸塊CB1的第一鈍化層2與第二連接凸塊CB2的第二鈍化層2’連接，第一子接合元件SBE1的第一絕緣層1與第二子接合元件SBE2的第二絕緣層1’連接。更具體地，第一連接凸塊CB1的第一鈍化層2會與第二連接凸塊CB2的第二鈍化層2’直接接觸。
此外，於圖4B中，第一子接合元件SBE1與第二子接合元件SBE2大致上是對準的，換句話說，在接合元件BE的第一基板6的俯視方向上，第一連接凸塊CB1的第二表面S2會與第二連接凸塊CB2的第四表面S4大致上重疊。雖然圖未示，於本實施例的其他態樣中，第一連接凸塊CB1的第二表面S2可與第二連接凸塊CB2的第四表面S4不完全重疊，只要能達到電性連接的目的即可。因此，第一連接凸塊CB1的部分第一鈍化層2也可與第二子接合元件SBE2的部分第二絕緣層1’連接，相似地，第二連接凸塊CB2的部分第二鈍化層2’也可與第一子接合元件SBE1的部分第一絕緣層1連接。
圖5為本揭露之又一實施例之接合元件之製備方法之部分示意圖。其中，圖5之示意圖與圖1E相似，除了以下差異。
如圖5所示，於形成第一連接凸塊CB1之步驟後，可更包含：形成一絕緣層7於第一連接凸塊CB1上，其中絕緣層7包含一穿孔71；以及形成一第三連接凸塊CB3於穿孔71中，其中，第三連接凸塊CB3包含一潤濕層8及一導電層9，潤濕層8位於第一連接凸塊CB1與導電層9之間，且潤濕層8與第一導電層4接觸。因此，由此形成的第一子接合元件可更包含第三連接凸塊CB3，且第一連接凸塊CB1與第三連接凸塊CB3可電性連接，以提供信號或電傳導。此外，如圖5所示，第一子接合元件可包含複數個絕緣層7及第三連接凸塊CB3，以形成多層薄膜堆疊。此外，雖然圖未示，第三連接凸塊CB3也可選擇性的更包含一鈍化層，且潤濕層8位於鈍化層與導電層9之間。相似地，雖然圖未示，但第二子接合元件也可包含一或多個絕緣層7及一或多個第三連接凸塊CB3，以形成多層薄膜堆疊。此外，雖然圖未示，於本揭露的其他實施態樣中，也可以實施例2的方法先 形成第一連接凸塊；再形成絕緣層7於該第一連接凸塊上，其中，絕緣層7包含穿孔71；以及形成一第三連接凸塊CB3於穿孔71中。
實驗例1
使用實施例1的方法製備實驗例1的接合元件，實驗例1的接合元件BE可如圖2A所示，其中，第一鈍化層2和第二鈍化層2’為Au，厚度為8nm。潤濕層3和3’為Cr，厚度為2nm。第一導電層4和第二導電層4’為Cu，厚度為400nm，第一絕緣層1和第二絕緣層1’為PI。以歐傑電子能譜法(Auger electron spectroscopy,AES)分析，發現連接層CL包含Cr和Cu。此外，在對接製程的溫度為100℃，對接製程的時間為15分鐘；以及對接製程的溫度為70℃，對接製程的時間為180秒的情況下皆可獲得具有改善接合效果的結合元件BE。
實驗例2
使用實施例1的方法製備實驗例2的接合元件，實驗例2的接合元件BE可如圖2A所示，其中，第一鈍化層2和第二鈍化層2’為Ag，厚度為10nm。潤濕層3和3’為Ti，厚度為2nm。第一導電層4和第二導電層4’為Cu，厚度為780nm，第一絕緣層1和第二絕緣層1’為二氧化矽(SiO2)。以AES分析，發現連接層CL包含Cu。對接製程的溫度為80℃至150℃，對接製程的時間為3分鐘，可獲得具有改善接合效果的結合元件BE。
實驗例3
使用實施例1的方法製備實驗例3的接合元件，實驗例3的接合元件BE可如圖2B所示，其中，第一鈍化層2和第二鈍化層2’為Au，厚度為80nm。潤濕層3和3’為Cr，厚度為25nm。第一導電層4和第二導電層4’為Cu，厚度為 300nm，第一絕緣層1和第二絕緣層1’為SiO2。對接製程的溫度為100℃，對接製程的時間為30分鐘，可獲得具有改善接合效果的結合元件BE。
實驗例4
使用實施例2的方法製備實驗例4的接合元件，實驗例4的接合元件BE與圖4A所示相似，但本實驗例中不含潤濕層3和3’，其中，第一鈍化層2和第二鈍化層2’為Au，厚度為10nm。第一導電層4和第二導電層4’為Cu，厚度為800nm，第一絕緣層1和第二絕緣層1’為PI。對接製程的溫度為150℃，對接製程的時間為15min，可獲得具有改善接合效果的結合元件BE。
以上的具體實施例應被解釋為僅僅是說明性的，而不以任何方式限制本公開的其餘部分，且不同實施例間的特徵，只要不互相衝突均可混合搭配使用。
1:第一絕緣層
11:第一穿孔
1’:第二絕緣層
11’:第二穿孔
2:第一鈍化層
21:表面
2’:第二鈍化層
21’:表面
3、3’:潤濕層
4:第一導電層
41:表面
4’:第二導電層
5:第二金屬層
5’:第三金屬層
6:第一基板
6’:第二基板
CB1:第一連接凸塊
CB2:第二連接凸塊
SBE1:第一子接合元件
SBE2:第二子接合元件
S1:第一表面
S2:第二表面
S3:第三表面
S4:第四表面
W1、W2、W3、W4:寬度

Claims (20)

  1. 一種接合元件之製備方法，包含以下步驟：提供一承載基板；形成一第一金屬層於該承載基板上；形成一第一絕緣層於該第一金屬層上，其中該第一絕緣層包含一第一穿孔；形成一第一鈍化層於該第一穿孔中；形成一第一導電層於該第一鈍化層上，其中該第一絕緣層的該第一穿孔中的該第一鈍化層與該第一導電層形成一第一連接凸塊；形成一第一基板於該第一連接凸塊及該第一絕緣層上；移除該承載基板及該第一金屬層，以顯露出該第一連接凸塊的該第一鈍化層的一表面及該第一絕緣層的一表面，形成一第一子接合元件；以及以該第一連接凸塊的該第一鈍化層的該表面，將該第一子接合元件與一第二子接合元件進行一對接製程，形成該接合元件。
  2. 如請求項1所述之製備方法，其中，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，更包含一步驟：蝕刻該第一鈍化層及該第一導電層，以形成該第一連接凸塊。
  3. 如請求項1所述之製備方法，其中，於形成該第一導電層於該第一鈍化層上之步驟前，更包含一步驟：形成一潤濕層於該第一鈍化層上。
  4. 如請求項3所述之製備方法，其中，該潤濕層更設置於該第一絕緣層的該第一穿孔中，且該潤濕層位於該第一鈍化層與該第一導電層之間。
  5. 如請求項1所述之製備方法，其中，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，更包含：形成一第二金屬層於該第一連接凸塊及該第一絕緣層上。
  6. 如請求項1所述之製備方法，其中，於形成該第一基板於該第一連接凸塊及該第一絕緣層上之步驟前，該第一連接凸塊的該第一導電層的表面具有一第一粗糙度，於移除該承載基板及該第一金屬層之步驟後，所顯露的該第一連接凸塊的該第一鈍化層的該表面具有一第二粗糙度，且該第一粗糙度大於該第二粗糙度。
  7. 如請求項1所述之製備方法，其中，該對接製程的溫度為室溫至250℃。
  8. 如請求項1所述之製備方法，其中，該第二子接合元件包含：一第二基板；一第二絕緣層，設於該第二基板上且包含一第二穿孔；以及一第二連接凸塊，設於該第二穿孔中且包含一第二鈍化層及一第二導電層，其中該第二導電層設於該第二鈍化層與該第二基板間。
  9. 如請求項8所述之製備方法，其中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接，該第一子接合元件的該第一絕緣層與該第二子接合元件的該第二絕緣層連接。
  10. 如請求項8所述之製備方法，其中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接而形成一接點，該第一子接合元件的該第一絕緣層與該第二子接合元件的該第二絕緣層連接，且該接點更包含一連接層，該連接層形成於該第一鈍化層與該第二鈍化層之間。
  11. 如請求項10所述之製備方法，其中，該連接層包含一第一金屬，該第一金屬為該第一導電層或該第二導電層所包含的金屬。
  12. 如請求項11所述之製備方法，其中，該連接層更包含一第二金屬，該第二金屬包含至少一選自由Ti、Cr、Ni、Co、及Ta所組成的群組。
  13. 如請求項1所述之製備方法，其中，於一剖面中，該第一連接凸塊具有一第一表面及一第二表面，該第一表面朝向該第一基板且與該第二表面相對，且該第一表面的寬度大於該第二表面的寬度。
  14. 如請求項8所述之製備方法，其中，於一剖面中，該第二連接凸塊具有一第三表面及一第四表面，該第三表面朝向該第二基板且與該第四表面相對，且該第三表面的寬度大於該第四表面的寬度。
  15. 一種接合元件，包含：一第一子接合元件，包含：一第一基板；一第一絕緣層，設於該第一基板上且包含一第一穿孔；以及一第一連接凸塊，設於該第一穿孔中且包含一第一鈍化層及一第一導電層，其中該第一導電層設於該第一鈍化層與該第一基板間，該第一鈍化層與該第一穿孔的一側壁接觸；以及一第二子接合元件，包含：一第二基板；一第二絕緣層，設於該第二基板上且包含一第二穿孔；以及一第二連接凸塊，設於該第二穿孔中且包含一第二鈍化層及一第二導電層，其中該第二導電層設於該第二鈍化層與該第二基板間，該第二鈍化層與該第二穿孔的另一側壁接觸； 其中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接，該第一子接合元件的該第一絕緣層與該第二子接合元件的該第二絕緣層連接。
  16. 如請求項15所述之接合元件，其中，該第一連接凸塊的該第一鈍化層與該第二連接凸塊的該第二鈍化層連接而形成一接點，該接點更包含一連接層，且該連接層形成於該第一鈍化層與該第二鈍化層之間。
  17. 如請求項16所述之接合元件，其中，該連接層包含一第一金屬，該第一金屬為該第一導電層或該第二導電層所包含的金屬。
  18. 如請求項17所述之接合元件，其中，該連接層更包含一第二金屬，該第二金屬包含至少一選自由Ti、Cr、Ni、Co、及Ta所組成的群組。
  19. 如請求項15所述之接合元件，其中，於一剖面中，該第一連接凸塊具有一第一表面及一第二表面，該第一表面朝向該第一基板且與該第二表面相對，且該第一表面的寬度大於該第二表面的寬度。
  20. 如請求項15所述之接合元件，其中，於一剖面中，該第二連接凸塊具有一第三表面及一第四表面，該第三表面朝向該第二基板且與該第四表面相對，且該第三表面的寬度大於該第四表面的寬度。
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