TWI767890B - Fan-out semiconductor package and manufacturing method thereof - Google Patents

Fan-out semiconductor package and manufacturing method thereof Download PDF

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TWI767890B
TWI767890B TW105132678A TW105132678A TWI767890B TW I767890 B TWI767890 B TW I767890B TW 105132678 A TW105132678 A TW 105132678A TW 105132678 A TW105132678 A TW 105132678A TW I767890 B TWI767890 B TW I767890B
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layer
redistribution layer
fan
connection member
redistribution
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TW105132678A
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TW201724414A (en
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李斗煥
吳暻燮
金宗立
金亨俊
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南韓商三星電子股份有限公司
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    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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Abstract

A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.

Description

扇出型半導體封裝及其製造方法Fan-out semiconductor package and method of making the same [相關申請案的交叉參考] [Cross-reference to related applications]

本申請案主張於2015年10月13日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0143009號的優先權、於2016年2月24日在韓國智慧財產局提出申請的韓國專利申請案第10-2016-0021767號的優先權、以及於2016年8月24日在韓國智慧財產局提出申請的韓國專利申請案第10-2016-0107634號的優先權，所述各韓國專利申請案的揭露內容全文併入本案供參考。 This application claims the priority of Korean Patent Application No. 10-2015-0143009 filed with the Korea Intellectual Property Office on October 13, 2015, and the Korean Patent Application No. Priority of Patent Application No. 10-2016-0021767 and Korean Patent Application No. 10-2016-0107634 filed with the Korean Intellectual Property Office on August 24, 2016, each of the Korean Patents The full disclosure of the application is incorporated into this case for reference.

本發明是有關於一種半導體封裝，舉例而言，一種扇出型半導體封裝及其製造方法，在所述扇出型半導體封裝中，連接端子可在其中安置有半導體晶片的區之外延伸。 The present invention relates to a semiconductor package, for example, a fan-out type semiconductor package in which connection terminals may extend beyond a region in which a semiconductor die is placed, and a method of manufacturing the same.

目前，與半導體晶片相關聯的技術發展中的顯著趨勢是減小組件的尺寸。因此，在封裝技術的領域中，隨著對小尺寸半導體晶片等的需求的增加，已經需要實作在包括多個引腳的同時具有壓縮的尺寸的半導體封裝。 Currently, a significant trend in technological development associated with semiconductor wafers is to reduce the size of components. Therefore, in the field of packaging technology, with the increasing demand for small-sized semiconductor wafers and the like, there has been a need to implement a semiconductor package having a compressed size while including a plurality of pins.

為滿足上述技術要求所建議的一種封裝技術為扇出型半 導體封裝。此類扇出半導體封裝可藉由對位於其中安置有半導體晶片的區之外的連接端子進行重佈線而有助於實作大量引腳且具有壓縮的尺寸。 A proposed packaging technology to meet the above technical requirements is the fan-out half conductor package. Such fan-out semiconductor packages can facilitate the implementation of a large number of pins and have compact dimensions by rerouting connection terminals outside the area in which the semiconductor die is disposed.

本發明的態樣可提供一種扇出型半導體封裝及其高效製造方法，所述扇出型半導體封裝能夠解決在將其上形成有重佈線層的第一連接構件引入至半導體晶片的包封區時因重佈線層的厚度而產生的第二連接構件的絕緣距離不均勻問題。 Aspects of the present invention can provide a fan-out semiconductor package that can solve the problem of introducing a first connection member having a redistribution layer formed thereon to an encapsulation region of a semiconductor wafer and an efficient method of manufacturing the same. At the same time, due to the thickness of the redistribution layer, the insulation distance of the second connection member is not uniform.

本發明中所建議的一種解決方法是將與第二連接構件接觸的重佈線層嵌置於第一連接構件中。 One solution proposed in the present invention is to embed the redistribution layer in contact with the second connecting member in the first connecting member.

根據本發明的態樣，一種扇出型半導體封裝可包括：第一連接構件，具有貫穿孔；半導體晶片，安置於所述第一連接構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊；包封體，至少局部地包封所述第一連接構件及所述半導體晶片的所述非主動表面；以及第二連接構件，安置於所述第一連接構件及所述半導體晶片的所述主動表面上，且包括電性連接至所述連接墊的重佈線層，其中所述第一連接構件包括第一絕緣層、在與所述第二連接構件接觸的同時嵌置於所述第一絕緣層中的第一重佈線層、以及安置於所述第一絕緣層的與其中嵌置有所述第一重佈線層的一側相對的另一側上的第二重佈線層，所述第一重佈線層及所述第二重佈線層電性連接至所述連接墊。 According to an aspect of the present invention, a fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor die disposed in the through hole of the first connection member and having an active surface and a connection with the an inactive surface opposite an active surface on which connection pads are disposed; an encapsulant at least partially encapsulating the first connection member and the inactive surface of the semiconductor wafer; and a second connection a member disposed on the first connection member and the active surface of the semiconductor wafer, and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, A first redistribution layer embedded in the first insulating layer while being in contact with the second connection member, and a first redistribution layer disposed in the first insulating layer with the first redistribution layer embedded therein The second redistribution layer on one side opposite to the other side, the first redistribution layer and the second redistribution layer are electrically connected to the connection pads.

根據本發明的另一態樣，一種扇出型半導體封裝的製造方法可包括：製備載體膜；在所述載體膜上形成第一連接構件；移除所述載體膜；形成穿透過所述第一連接構件的貫穿孔；在所述貫穿孔中安置半導體晶片，所述半導體晶片具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊；使用包封體至少局部地包封所述第一連接構件及所述半導體晶片的所述非主動表面；以及在所述第一連接構件及所述半導體晶片的所述主動表面上形成第二連接構件，所述第二連接構件包括電性連接至所述連接墊的重佈線層，其中形成所述第一連接構件包括：在所述載體膜上形成第一重佈線層，在所述載體膜上形成用於嵌置所述第一重佈線層的第一絕緣層，以及在所述第一絕緣層的與其中嵌置有所述第一重佈線層的一側相對的另一側上形成第二重佈線層，所述第一重佈線層及所述第二重佈線層電性連接至所述連接墊。 According to another aspect of the present invention, a method of manufacturing a fan-out semiconductor package may include: preparing a carrier film; forming a first connection member on the carrier film; removing the carrier film; A through hole for a connecting member; a semiconductor wafer is placed in the through hole, the semiconductor wafer has an active surface and a non-active surface opposite the active surface, and connection pads are placed on the active surface; using an encapsulation a body at least partially encapsulating the first connection member and the inactive surface of the semiconductor wafer; and forming a second connection member on the first connection member and the active surface of the semiconductor wafer, the The second connection member includes a redistribution layer electrically connected to the connection pad, wherein forming the first connection member includes: forming a first redistribution layer on the carrier film, forming a redistribution layer on the carrier film A second redistribution layer is formed on the first insulating layer in which the first redistribution layer is embedded, and on the other side of the first insulating layer opposite to the side in which the first redistribution layer is embedded. A wiring layer, the first redistribution layer and the second redistribution layer are electrically connected to the connection pads.

根據本發明的另一態樣，一種扇出型半導體封裝可包括：半導體晶片，具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊；一或多個連接單元，圍繞所述半導體晶片安置；以及連接構件，安置於所述連接單元及所述半導體晶片上，其中所述連接單元包括第一絕緣層、在與所述連接構件接觸的同時嵌置於所述第一絕緣層中的第一重佈線層、以及安置於所述第一絕緣層的與其中嵌置有所述第一重佈線層的一側相對的另一側上的第二重佈線層，且所述連接構件包括 絕緣層及安置於所述絕緣層上的重佈線層，所述連接單元的所述第一重佈線層及所述第二重佈線層以及所述連接構件的所述重佈線層電性連接至所述半導體晶片的所述連接墊。 According to another aspect of the present invention, a fan-out semiconductor package may include: a semiconductor die having an active surface and a non-active surface opposite the active surface, with connection pads disposed on the active surface; one or more a connecting unit disposed around the semiconductor wafer; and a connecting member disposed on the connecting unit and the semiconductor wafer, wherein the connecting unit includes a first insulating layer and is embedded while being in contact with the connecting member a first redistribution layer in the first insulating layer, and a second redistribution layer disposed on the other side of the first insulating layer opposite to the side in which the first redistribution layer is embedded a wiring layer, and the connecting member includes An insulating layer and a redistribution layer disposed on the insulating layer, the first redistribution layer and the second redistribution layer of the connection unit and the redistribution layer of the connecting member are electrically connected to the connection pads of the semiconductor wafer.

100:半導體封裝 100: Semiconductor Packaging

100A、200A:封裝 100A, 200A: Package

100B、100C、100D、100E、100F、100G、100H、200B、200C、200D、200E、200F、200G、2100:扇出型半導體封裝 100B, 100C, 100D, 100E, 100F, 100G, 100H, 200B, 200C, 200D, 200E, 200F, 200G, 2100: Fan-Out Semiconductor Packages

110、210、210':第一連接構件 110, 210, 210': the first connecting member

110A、110B、110C、110D、110E:連接單元 110A, 110B, 110C, 110D, 110E: connection unit

110H、210H、210H':貫穿孔 110H, 210H, 210H': through hole

111a:第一絕緣層 111a: first insulating layer

111a-1、111a-2:第一絕緣層 111a-1, 111a-2: first insulating layer

111b:第二絕緣層 111b: second insulating layer

111b-1、111b-2:第二絕緣層 111b-1, 111b-2: second insulating layer

111c:第三絕緣層 111c: Third insulating layer

112a、112b、112c、112d、212a、212b:重佈線層 112a, 112b, 112c, 112d, 212a, 212b: redistribution layers

112a-1、112a-2:第一重佈線層 112a-1, 112a-2: first redistribution layer

112b-1、112b-2:第二重佈線層 112b-1, 112b-2: Second redistribution layer

112c-1、112c-2:第三重佈線層 112c-1, 112c-2: The third redistribution layer

114、214:金屬層 114, 214: Metal layer

120、220、220'、2120、2220:半導體晶片 120, 220, 220', 2120, 2220: Semiconductor wafers

121、221、221'、1101、2121、2221:主體 121, 221, 221', 1101, 2121, 2221: main body

122、222、222'、2122、2222:連接墊 122, 222, 222', 2122, 2222: Connection pads

123、223、223'、2223:保護膜 123, 223, 223', 2223: protective film

124、224:第一被動組件 124, 224: The first passive component

126、226:第二被動組件 126, 226: Second passive component

130、230、230'、2130:包封體 130, 230, 230', 2130: Encapsulation

131、151、231、231'、251、251'、2251:開口 131, 151, 231, 231', 251, 251', 2251: Opening

140、240、240':第二連接構件 140, 240, 240': the second connecting member

141a、141b、211、211'、241a、241a'、241b、241b'、2141、2241:絕緣層 141a, 141b, 211, 211', 241a, 241a', 241b, 241b', 2141, 2241: insulating layer

142a、142b、182、212a'、212b'、242a、242a'、242b、242b'、282、2142:重佈線層 142a, 142b, 182, 212a', 212b', 242a, 242a', 242b, 242b', 282, 2142: Redistribution layers

113a、113b、143a、143b、183、213、213'、243a、243a'、243b、243b'、283、2143、2243:介層窗 113a, 113b, 143a, 143b, 183, 213, 213', 243a, 243a', 243b, 243b', 283, 2143, 2243: Vias

150、180、250、250'、280、2150、2250:保護層 150, 180, 250, 250', 280, 2150, 2250: protective layer

160、184、260、260'、284、2160、2260:凸塊下金屬層 160, 184, 260, 260', 284, 2160, 2260: Under-bump metal layer

170、185、270、270'、285:連接端子 170, 185, 270, 270', 285: Connection terminals

181、186、281、286:表面安裝組件 181, 186, 281, 286: Surface Mount Components

187、287:記憶體晶片封裝 187, 287: Memory chip packaging

301:載體膜 301: carrier film

302、303:金屬膜 302, 303: Metal film

304:乾膜 304: Dry Film

305:黏合膜 305: Adhesive film

1000:電子裝置 1000: Electronics

1010、1110、2500:主板 1010, 1110, 2500: Motherboard

1020:晶片相關組件 1020: Wafer Related Components

1030:網路相關組件 1030: Network related components

1040:其他組件 1040: Other Components

1050、1130:照相機 1050, 1130: Camera

1060:天線 1060: Antenna

1070:顯示器 1070: Monitor

1080:電池 1080: Battery

1090:訊號線 1090: Signal line

1100:智慧型電話 1100: Smartphone

1120:組件 1120: Components

2140、2240:連接構件 2140, 2240: Connecting components

2170、2270:焊料球 2170, 2270: Solder balls

2200:扇入型半導體封裝 2200: Fan-In Semiconductor Packaging

2242:配線圖案 2242: Wiring pattern

2243h:介層窗孔 2243h: via hole

2280:底部填充樹脂 2280: Underfill resin

2290:模製材料 2290: Molding Materials

2301、2302:插板基板 2301, 2302: Board substrate

H:台階部分 H: Step part

I-I'、II-II'、III-III'、IV-IV'、V-V'、VI-VI'、VII-VII':線 I-I', II-II', III-III', IV-IV', V-V', VI-VI', VII-VII': line

結合附圖閱讀以下詳細說明，將更加清晰地理解本發明的上述及其他態樣、特徵及優點，在附圖中：圖1是示意性地說明電子裝置系統的實例的方塊圖。 The above and other aspects, features and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram schematically illustrating an example of an electronic device system.

圖2是示意性地說明電子裝置的實例的立體圖。 FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

圖3A及圖3B是示意性地說明扇入型半導體封裝在被封裝之前及被封裝之後的狀態的剖視圖。 3A and 3B are cross-sectional views schematically illustrating states of a fan-in type semiconductor package before and after being packaged.

圖4是示意性地說明扇入型半導體封裝的封裝製程的剖視圖。 4 is a cross-sectional view schematically illustrating a packaging process of a fan-in type semiconductor package.

圖5是示意性地說明其中扇入型半導體封裝安裝於插板(interposer)基板上且最終安裝於電子裝置的主板上的情形的剖視圖。 5 is a cross-sectional view schematically illustrating a situation in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

圖6是示意性地說明其中扇入型半導體封裝嵌置於插板基板中且最終安裝於電子裝置的主板上的情形的剖視圖。 6 is a cross-sectional view schematically illustrating a situation in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

圖7是示意性地說明扇出型半導體封裝的剖視圖。 7 is a cross-sectional view schematically illustrating a fan-out semiconductor package.

圖8是示意性地說明其中扇出型半導體封裝安裝於電子裝置的主板上的狀態的剖視圖。 8 is a cross-sectional view schematically illustrating a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

圖9是示意性地說明扇出型半導體封裝的實例的剖視圖。 9 is a cross-sectional view schematically illustrating an example of a fan-out type semiconductor package.

圖10是沿圖9所示的線I-I'截取的扇出型半導體封裝的剖切平面圖。 FIG. 10 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line II′ shown in FIG. 9 .

圖11A至圖11D是示意性地說明形成於圖9所示扇出型半導體封裝的第一連接構件中的介層窗的各種形狀的剖視圖。 11A to 11D are cross-sectional views schematically illustrating various shapes of vias formed in the first connection member of the fan-out type semiconductor package shown in FIG. 9 .

圖12A至圖12D說明圖9所示扇出型半導體封裝的示意性製造製程的實例。 12A-12D illustrate an example of a schematic fabrication process for the fan-out semiconductor package shown in FIG. 9 .

圖13是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 13 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖14是沿圖13所示的線II-II'截取的扇出型半導體封裝的剖切平面圖。 FIG. 14 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line II-II' shown in FIG. 13 .

圖15是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 15 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖16是沿圖15所示的線III-III'截取的扇出型半導體封裝的剖切平面圖。 FIG. 16 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line III-III' shown in FIG. 15 .

圖17是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 17 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖18是沿圖17所示的線IV-IV'截取的扇出型半導體封裝的剖切平面圖。 FIG. 18 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line IV-IV' shown in FIG. 17 .

圖19是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 19 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖20是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 20 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖21是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 21 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖22是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 22 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖23是示意性地說明扇出型半導體封裝的另一實例的剖視圖。 23 is a cross-sectional view schematically illustrating another example of a fan-out type semiconductor package.

圖24是沿圖23所示的線V-V'截取的扇出型半導體封裝的剖切平面圖。 FIG. 24 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line V-V' shown in FIG. 23 .

圖25A至圖25D是示意性地說明形成於圖23所示扇出型半導體封裝的第一連接構件中的介層窗的各種形狀的剖視圖。 25A to 25D are cross-sectional views schematically illustrating various shapes of vias formed in the first connection member of the fan-out semiconductor package shown in FIG. 23 .

圖26A至圖26D說明圖23所示扇出型半導體封裝的示意性製造製程的實例。 26A-26D illustrate an example of a schematic fabrication process for the fan-out semiconductor package shown in FIG. 23 .

圖27是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 27 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖28是沿圖27所示的線VI-VI'截取的扇出型半導體封裝的剖切平面圖。 FIG. 28 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line VI-VI' shown in FIG. 27 .

圖29是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 29 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖30是沿圖29所示的線VII-VII'截取的扇出型半導體封裝的剖切平面圖。 FIG. 30 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line VII-VII' shown in FIG. 29 .

圖31是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 31 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖32是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 32 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖33是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 33 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖34是示意性地說明其中第二連接構件的絕緣距離不均勻的扇出型半導體封裝的實例的剖視圖。 34 is a cross-sectional view schematically illustrating an example of a fan-out type semiconductor package in which the insulating distance of the second connection member is not uniform.

在下文中，將參照附圖闡述本發明。為提供更加清晰的說明，可誇大或減小圖式中所示組件的形狀及尺寸。 Hereinafter, the present invention will be explained with reference to the accompanying drawings. The shapes and sizes of components shown in the drawings may be exaggerated or reduced to provide greater clarity.

本發明中所使用的用語「實例」或「經修改實例」並非意指同一示例性實施例，而是為強調及闡述不同的獨有特徵而提供。然而，以上所建議的實例或經修改實例亦可被實作成與其他實例或經修改實例的特徵組合。舉例而言，儘管未在另一實例中闡述在特定實例中所闡述的特定細節，然而除非另有闡述，否則其可被理解成與另一實例相關的說明。 The terms "example" or "modified example" as used in this disclosure do not mean the same exemplary embodiment, but are provided to emphasize and illustrate different unique features. However, the above suggested examples or modified examples can also be implemented in combination with features of other examples or modified examples. For example, a specific detail set forth in a particular example may be construed as a description in relation to another example, unless stated otherwise, even though it is not set forth in another example.

在本發明中，用語「連接至」包括一個組件不僅直接連接至另一組件，而且亦間接連接至另一組件。同時，用語「電性連接」包括其中一個組件實體地連接至另一組件的情形及其中任何組件均不實體地連接至另一組件的情形二者。此外，用語「第一」、「第二」等是用於區分各個組件，而並非限制對應組件的順序、重要性等。在某種情形中，在不背離本發明的範圍的條件下，第一組件可被稱為第二組件且第二組件亦可相似地被稱為第一組件。 In the present invention, the term "connected to" includes that an element is not only directly connected to another element, but also indirectly connected to another element. Meanwhile, the term "electrically connected" includes both a situation where one component is physically connected to another component and a situation where none of the components is physically connected to the other component. In addition, the terms "first", "second", etc. are used to distinguish each component, but do not limit the order, importance, etc. of the corresponding components. In some instances, a first component may be termed a second component and a second component may similarly be termed a first component without departing from the scope of the present invention.

在本發明中，上部部分、下部部分、上側、下側、上表 面、下表面等是基於附圖而定。舉例而言，第一連接構件被定位成高於重佈線層。然而，所主張者並非僅限於此。此外，垂直方向指代上述向上的方向及向下的方向，且水平方向指代與上述向上的方向及向下的方向垂直的方向。在此種情形中，垂直橫截面指代沿垂直方向上的平面截取的情形，且此種情形的實例可為圖式中所示的剖視圖。此外，水平橫截面指代沿水平方向上的平面截取的情形，且此種情形的實例可為圖式中所示的平面圖。 In the present invention, the upper part, the lower part, the upper side, the lower side, the upper surface The face, the lower face, etc. are based on the drawings. For example, the first connection member is positioned higher than the redistribution layer. However, the claimants are not limited to this. Further, the vertical direction refers to the above-mentioned upward direction and the downward direction, and the horizontal direction refers to the direction perpendicular to the above-mentioned upward direction and downward direction. In this case, a vertical cross-section refers to a situation taken along a plane in a vertical direction, and an example of such a situation may be the cross-sectional views shown in the drawings. Also, a horizontal cross section refers to a situation taken along a plane in a horizontal direction, and an example of such a situation may be a plan view shown in the drawings.

此外，本發明中所使用的用語僅用以闡述實例，而非限制本發明。此處，除非在上下文中另有解釋，否則單數形式亦包括複數形式。 Also, the terms used in the present invention are used to illustrate examples only, and not to limit the present invention. Here, the singular forms also include the plural forms unless the context clearly dictates otherwise.

儘管以上已示出並闡述了示例性實施例，然而，對熟習此項技術者而言將顯而易見的是，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出各種潤飾及變化。 While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that, without departing from the scope of the invention as defined by the appended claims, Various retouches and variations.

電子裝置 electronic device

圖1是示意性地說明電子裝置系統的實例的方塊圖。 FIG. 1 is a block diagram schematically illustrating an example of an electronic device system.

參照圖1，電子裝置1000中可容置有主板1010。晶片相關組件1020、網路相關組件1030、其他組件1040等可實體地連接至及/或電性連接至主板1010。該些組件可連接至以下將闡述的其他組件以形成各種訊號線1090。 Referring to FIG. 1 , an electronic device 1000 may accommodate a motherboard 1010 therein. The chip-related components 1020 , the network-related components 1030 , other components 1040 , etc. may be physically and/or electrically connected to the main board 1010 . These components can be connected to other components to be described below to form various signal lines 1090 .

晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體(例如，動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(例如，唯讀記憶體(read only memory，ROM))、快閃記憶體等；應用處理器晶片，例如中央處理器(例如，中央處理單元(central processing unit，CPU))、圖形處理器(例如，圖形處理單元(graphic processing unit，GPU))、數位訊號處理器、密碼學處理器(cryptographic processor)、微處理器、微控制器等；邏輯晶片，例如類比-數位(analog-to-digital，A-D)轉換器、應用專用積體電路(application-specific integrated circuit，ASIC)等；以及類似組件。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。此外，該些晶片相關組件1020可彼此組合。 The chip-related components 1020 may include: memory chips, such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory) memory, ROM)), flash memory, etc.; application processor chips, such as central processing units (eg, central processing unit (CPU)), graphics processors (eg, graphics processing unit, GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; logic chips, such as analog-to-digital (A-D) converters, application-specific integrated circuits circuit (application-specific integrated circuit, ASIC), etc.; and similar components. However, the wafer-related components 1020 are not limited thereto, and other types of wafer-related components may also be included. Furthermore, the wafer-related components 1020 may be combined with each other.

網路相關組件1030可包括例如以下協定：無線保真(wireless fidelity，Wi-Fi)(電氣及電子工程師學會(Institute of Electrical and Electronics Engineers，IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communications，GSM)、全球定位系統(global positioning system，GPS)、通用封包無線電服務(general packet radio service，GPRS)、分碼多重存 取(code division multiple access，CDMA)、分時多重存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G協定、4G協定、5G協定、及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多個其他無線標準或協定或者有線標準或協定中的任一者。此外，該些網路相關組件1030可與晶片相關組件1020一起彼此組合。 Network-related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperability for microwave access (worldwide interoperability for microwave access, WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (high speed packet access+, HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (enhanced data GSM environment, EDGE), global system for mobile communications (GSM), global positioning system (global positioning system, GPS), general packet radio service (general packet radio service, GPRS), code division multiple storage Access (code division multiple access, CDMA), time division multiple access (time division multiple access, TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G protocol, 4G protocol, 5G protocol, and any other wireless and wireline protocols specified subsequent to the above. However, the network-related components 1030 are not limited thereto, but may also include any of a number of other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related components 1030 may be combined with each other together with the wafer-related components 1020 .

其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器、鐵氧體珠粒、低溫共燒陶瓷(low temperature co-firing ceramic，LTCC)、電磁干擾(electromagnetic interference，EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor，MLCC)等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動組件等。此外，該些其他組件1040可與晶片相關組件1020及/或網路相關組件1030一起彼此組合。 Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-firing ceramics (LTCC), electromagnetic interference (electromagnetic interference) , EMI) filter, multilayer ceramic capacitor (multilayer ceramic capacitor, MLCC) and so on. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, and the like. Furthermore, these other components 1040 may be combined with each other together with the wafer-related components 1020 and/or the network-related components 1030 .

電子裝置1000可相依於電子裝置1000的類型而包括可實體地連接至及/或電性連接至主板1010或者可不實體地連接至及/或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機1050、天線1060、顯示器1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、 陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存裝置(例如，硬碟驅動機)(圖中未示出)、光碟(compact disk，CD)驅動機(圖中未示出)、數位多功能光碟(digital versatile disk，DVD)驅動機(圖中未示出)等。然而，該些其他組件並非僅限於此，而是相依於電子裝置1000的類型而亦可包括用於各種目的的其他組件。 The electronic device 1000 may include other components that may be physically and/or electrically connected to the mainboard 1010 or may not be physically and/or electrically connected to the mainboard 1010 depending on the type of the electronic device 1000 . These other components may include, for example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown) out), compass (not shown in the figure), accelerometer (not shown in the figure), Gyroscope (not shown), speaker (not shown), mass storage device (eg, hard disk drive) (not shown), compact disk (CD) drive (not shown) (not shown in the figure), a digital versatile disk (DVD) drive (not shown in the figure), and the like. However, these other components are not limited thereto, and may also include other components for various purposes depending on the type of the electronic device 1000 .

電子裝置1000可為智慧型電話、個人數位助理、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板電腦(tablet)、膝上型電腦、隨身型易網機(netbook)、電視、視訊遊戲機(video game machine)、智慧型手錶、汽車組件等。然而，電子裝置1000並非僅限於此，而是除上述電子裝置之外亦可為用於處理資料的任何其他電子裝置。 The electronic device 1000 can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a portable Internet machine ( netbook), TVs, video game machines, smart watches, automotive components, etc. However, the electronic device 1000 is not limited to this, and can be any other electronic device for processing data besides the above-mentioned electronic device.

圖2是示意性地說明電子裝置的實例的立體圖。 FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

參照圖2，半導體封裝可出於各種目的而用於如上所述的各種電子裝置中。舉例而言，主板1110可容置於智慧型電話1100的主體1101中，且各種組件1120可實體地連接至及/或電性連接至主板1110。此外，可實體地連接至及/或電性連接至主板1110或者可不實體地連接至及/或電性連接至主板1110的另一組件(例如，照相機1130)可容置於主體1101中。在此種情形中，組件1120中的某些組件可為如上所述的晶片相關組件，且半導體封裝100可為例如晶片相關組件中的應用處理器，但組件1120及半導體封裝100並非僅限於此。電子裝置未必僅限於智慧型電話1100， 而是亦可為如上所述的另一電子裝置。 Referring to FIG. 2, semiconductor packages may be used in various electronic devices as described above for various purposes. For example, the main board 1110 can be housed in the main body 1101 of the smart phone 1100 , and the various components 1120 can be physically and/or electrically connected to the main board 1110 . In addition, another component (eg, camera 1130 ) that may be physically and/or electrically connected to the main board 1110 or not physically and/or electrically connected to the main board 1110 may be accommodated in the main body 1101 . In this case, some of the components 1120 may be chip-related components as described above, and the semiconductor package 100 may be, for example, an application processor in a chip-related component, but the components 1120 and the semiconductor package 100 are not limited thereto . The electronic device is not necessarily limited to the smart phone 1100, Rather, it can also be another electronic device as described above.

半導體封裝 Semiconductor packaging

一般而言，一定數目的精細的電子電路整合於單個半導體晶片中。然而，半導體晶片本身可不充當完整的半導體產品，且可被外部的實體衝擊或化學衝擊損害。因此，半導體晶片並非單獨使用，而是被封裝於電子裝置等中以藉此在電子裝置等中以封裝狀態使用。 Generally, a certain number of fine electronic circuits are integrated into a single semiconductor wafer. However, the semiconductor wafer itself may not function as a complete semiconductor product and may be damaged by external physical or chemical shocks. Therefore, the semiconductor wafer is not used alone, but is packaged in an electronic device or the like to thereby be used in an electronic device or the like in a packaged state.

需要進行半導體封裝，乃因於電性連接方面，半導體晶片與電子裝置的主板之間可存在電路寬度差。詳言之，半導體晶片的連接墊的尺寸及半導體晶片的各連接墊之間的間隔是十分精細的，然而在電子裝置中使用的主板的組件安裝墊的尺寸及電子裝置的主板的各組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的尺寸及半導體晶片的各連接墊之間的間隔。因此，可能難以將半導體晶片直接安裝於如上所述的主板上，且需要一種能夠減小半導體晶片與主板之間的電路寬度差的封裝技術。 Semiconductor packaging is required because there may be a difference in circuit width between the semiconductor chip and the main board of the electronic device in terms of electrical connection. In detail, the size of the connection pads of the semiconductor chip and the interval between the connection pads of the semiconductor chip are very fine, but the size of the component mounting pads of the main board used in the electronic device and the mounting of the components of the main board of the electronic device are very fine. The spacing between the pads is significantly larger than the size of the connection pads of the semiconductor die and the spacing between the connection pads of the semiconductor die. Therefore, it may be difficult to directly mount the semiconductor die on the main board as described above, and a packaging technique capable of reducing the difference in circuit width between the semiconductor die and the main board is required.

由如上所述的封裝技術所製造的半導體封裝可相依於半導體封裝的結構及目的而被劃分成扇入型半導體封裝及扇出型半導體封裝。 The semiconductor package manufactured by the packaging technology as described above may be classified into a fan-in type semiconductor package and a fan-out type semiconductor package depending on the structure and purpose of the semiconductor package.

在下文中，將參照附圖更加詳細地闡述所述扇入型半導體封裝及所述扇出型半導體封裝。 Hereinafter, the fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail with reference to the accompanying drawings.

(扇入型半導體封裝) (Fan-in semiconductor package)

圖3A及圖3B是示意性地說明扇入型半導體封裝在被封 裝之前及被封裝之後的狀態的剖視圖。 3A and 3B are schematic diagrams illustrating a fan-in semiconductor package in a packaged state. Cross-sectional views of the state before and after being packaged.

圖4是示意性地說明扇入型半導體封裝的封裝製程的剖視圖。 4 is a cross-sectional view schematically illustrating a packaging process of a fan-in type semiconductor package.

參照圖3A至圖4，半導體晶片2220可為例如處於裸露狀態下的積體電路(integrated circuit，IC)，所述積體電路包括含有矽(Si)、鍺(Ge)、砷化鎵(GaAs)等的主體、形成於主體2221的一個表面上並含有例如鋁(Al)等導電性材料的連接墊2222、及形成於主體2221的一個表面上並覆蓋連接墊2222中的至少某些連接墊2222的保護膜2223(例如，氧化物膜、氮化物膜等)。此處，由於連接墊2222十分小，因此難以將積體電路(IC)安裝於中層次印刷電路板(printed circuit board，PCB)及電子裝置的主板或類似組件上。 Referring to FIGS. 3A to 4 , the semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, the integrated circuit including silicon (Si), germanium (Ge), gallium arsenide (GaAs) ) etc., connection pads 2222 formed on one surface of the main body 2221 and containing a conductive material such as aluminum (Al), and at least some of the connection pads formed on one surface of the main body 2221 and covering the connection pads 2222 2222 and a protective film 2223 (eg, oxide film, nitride film, etc.). Here, since the connection pads 2222 are quite small, it is difficult to mount an integrated circuit (IC) on a mid-level printed circuit board (PCB) and a motherboard or similar components of an electronic device.

因此，連接構件2240可相依於半導體晶片2220的尺寸而形成於半導體晶片2220上以對連接墊2222進行重佈線。連接構件2240可藉由以下步驟形成：使用例如感光成像介電(photoimagable dielectric，PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241；形成使連接墊2222開口的介層窗孔2243h；並且接著形成配線圖案2242及介層窗(via)2243。接著，可形成保護連接構件2240的保護層2250，可形成開口2251，且可形成凸塊下金屬層2260等。亦即，可藉由一系列製程來製造包括例如半導體晶片2220、連接構件2240、保護層2250、及凸塊下金屬層2260的扇入型半導體封裝2200。 Therefore, the connection members 2240 may be formed on the semiconductor wafer 2220 to rewire the connection pads 2222 depending on the size of the semiconductor wafer 2220 . The connection member 2240 may be formed by: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; forming a via 2243h opening the connection pad 2222; and Next, wiring patterns 2242 and vias 2243 are formed. Next, a protective layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, an under-bump metal layer 2260 and the like may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connecting member 2240, the protective layer 2250, and the under bump metal layer 2260 can be fabricated through a series of processes.

如上所述，扇入型半導體封裝可具有其中半導體晶片的所有連接墊(例如，所有的輸入/輸出(input/output，I/O)端子)均安置於所述半導體晶片內的封裝形式，且可具有優異的電性特性並可以低成本進行生產。因此，已以扇入型半導體封裝形式製造出安裝於智慧型電話中的諸多元件。詳言之，已開發出安裝於智慧型電話中的諸多元件以在具有小尺寸的同時實作快速訊號轉移。 As described above, a fan-in semiconductor package may have a package form in which all connection pads of a semiconductor die (eg, all input/output (I/O) terminals) are disposed within the semiconductor die, and Can have excellent electrical properties and can be produced at low cost. Accordingly, many components mounted in smart phones have been fabricated in fan-in semiconductor packages. In particular, many components installed in smart phones have been developed to achieve fast signal transfer while having a small size.

然而，由於在扇入型半導體晶片中，所有輸入/輸出端子均需要安置於半導體晶片內，因此扇入型半導體封裝具有大的空間限制。因此，可能難以將此結構應用至具有大量輸入/輸出端子的半導體晶片或具有小尺寸的半導體晶片。此外，由於上述缺點，扇入型半導體封裝可能無法在電子裝置的主板上直接安裝及使用。就此而言，即使半導體晶片的輸入/輸出端子的尺寸及半導體晶片的各輸入/輸出端子之間的間隔藉由重佈線製程而增大，所述半導體晶片的輸入/輸出端子的尺寸及所述半導體晶片的各輸入/輸出端子之間的間隔可能仍不足以直接將扇入型半導體封裝安裝於電子裝置的主板上。 However, since in a fan-in type semiconductor die, all input/output terminals need to be placed within the semiconductor die, the fan-in type semiconductor package has a large space limitation. Therefore, it may be difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a small size. In addition, due to the above disadvantages, the fan-in type semiconductor package may not be directly mounted and used on the motherboard of the electronic device. In this regard, even if the size of the input/output terminals of the semiconductor chip and the interval between the respective input/output terminals of the semiconductor chip are increased by the rewiring process, the size of the input/output terminals of the semiconductor chip and the The spacing between the input/output terminals of the semiconductor die may still be insufficient to directly mount the fan-in semiconductor package on the main board of the electronic device.

圖5是示意性地說明其中扇入型半導體封裝安裝於插板基板上且最終安裝於電子裝置的主板上的情形的剖視圖。 5 is a cross-sectional view schematically illustrating a situation in which a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

圖6是示意性地說明其中扇入型半導體封裝嵌置於插板基板中且最終安裝於電子裝置的主板上的狀態的剖視圖。 6 is a cross-sectional view schematically illustrating a state in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

參照圖5，在扇入型半導體封裝2200中，可經由插板基 板2301而再一次對半導體晶片2220的連接墊2222(即，輸入/輸出端子)進行重佈線，且扇入型半導體封裝2200可最終在其中扇入型半導體封裝2200安裝於插板基板2301上的狀態下安裝於電子裝置的主板2500上。此處，焊料球2270等可藉由底部填充樹脂2280等來固定，且半導體晶片的外側可被覆蓋以模製材料2290等。作為另一選擇，扇入型半導體封裝2200可嵌置於單獨的插板基板2302中，半導體晶片2220的連接墊2222(即，輸入/輸出端子)可在其中扇入型半導體封裝2200嵌置於插板基板2302中的狀態下藉由插板基板2302再一次進行重佈線，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。 Referring to FIG. 5, in the fan-in type semiconductor package 2200, an interposer substrate may be used board 2301 to rewire the connection pads 2222 (ie, input/output terminals) of the semiconductor die 2220 again, and the fan-in semiconductor package 2200 can finally be mounted on the interposer substrate 2301 It is installed on the main board 2500 of the electronic device in the state. Here, the solder balls 2270 and the like may be fixed by an underfill resin 2280 or the like, and the outer side of the semiconductor wafer may be covered with a molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302 in which the connection pads 2222 (ie, input/output terminals) of the semiconductor die 2220 may be embedded in the fan-in semiconductor package 2200 In the state of the interposer substrate 2302, rewiring is performed again through the interposer substrate 2302, and the fan-in type semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

如上所述，可能難以在所述電子裝置的主板上安置及使用所述扇入型半導體封裝。因此，扇入型半導體封裝可安裝於單獨的插板基板上，且接著藉由封裝製程而安裝於所述電子裝置的主板上，或可在其中扇入型半導體封裝嵌置於插板基板的狀態下在電子裝置的主板上安裝及使用。 As described above, it may be difficult to place and use the fan-in type semiconductor package on the motherboard of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device through the packaging process, or the fan-in semiconductor package can be embedded in the interposer substrate It is installed and used on the mainboard of the electronic device in the state of

(扇出型半導體封裝) (Fan-Out Semiconductor Package)

圖7是示意性地說明扇出型半導體封裝的剖視圖。 7 is a cross-sectional view schematically illustrating a fan-out semiconductor package.

參照圖7，在扇出型半導體封裝2100中，舉例而言，半導體晶片2120的外側可受到包封體2130的保護，且半導體晶片2120的連接墊2122可藉由連接構件2140而被重佈線至半導體晶片2120的外側。此處，在連接構件2140上可進一步形成保護層2150，且在保護層2150的開口中可進一步形成凸塊下金屬層 2160。在凸塊下金屬層2160上可進一步形成焊料球2170。半導體晶片2120可為包括主體2121、連接墊2122、保護膜(圖中未示出)等的積體電路(IC)。連接構件2140可包括絕緣層2141、形成於絕緣層2141上的重佈線層2142、及將連接墊2122及重佈線層2142電性連接至彼此的介層窗2143。 Referring to FIG. 7 , in the fan-out semiconductor package 2100 , for example, the outer side of the semiconductor chip 2120 may be protected by the encapsulant 2130 , and the connection pads 2122 of the semiconductor chip 2120 may be rewired to the The outside of the semiconductor wafer 2120 . Here, a protection layer 2150 may be further formed on the connection member 2140, and an under bump metal layer may be further formed in the opening of the protection layer 2150 2160. Solder balls 2170 may be further formed on the under bump metal layer 2160 . The semiconductor wafer 2120 may be an integrated circuit (IC) including a body 2121, connection pads 2122, a protective film (not shown in the figure), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via 2143 electrically connecting the connection pads 2122 and the redistribution layer 2142 to each other.

如上所述，扇出型半導體封裝可具有其中半導體晶片的輸入/輸出端子藉由形成於所述半導體晶片上的連接構件而進行重佈線並安置至所述半導體晶片的外側的形式。如上所述，在扇入型半導體封裝中，半導體晶片的所有輸入/輸出端子均需要安置於所述半導體晶片內。因此，當半導體晶片的尺寸減小時，需要減小球的尺寸及各球之間的節距，進而使得可能無法在扇入型半導體封裝中使用標準化球佈局。在另一方面，扇出型半導體封裝具有其中半導體晶片的輸入/輸出端子藉由如上所述的形成於所述半導體晶片上的連接端子而進行重佈線並安置至所述半導體晶片的外側的形式。因此，如下文所述，即使在半導體晶片的尺寸減小的情形中，實際上仍可在扇出型半導體封裝中使用標準化球佈局，進而使得扇出型半導體封裝可安裝於電子裝置的主板上，而無需使用單獨的插板基板。 As described above, the fan-out type semiconductor package may have a form in which the input/output terminals of the semiconductor die are rewired by connecting members formed on the semiconductor die and disposed to the outside of the semiconductor die. As mentioned above, in a fan-in type semiconductor package, all input/output terminals of a semiconductor die need to be disposed within the semiconductor die. Therefore, as the size of semiconductor wafers decreases, it is necessary to reduce the size of the balls and the pitch between the balls, which in turn may make it impossible to use standardized ball layouts in fan-in semiconductor packages. On the other hand, a fan-out type semiconductor package has a form in which the input/output terminals of the semiconductor die are rewired by the connection terminals formed on the semiconductor die as described above and placed to the outside of the semiconductor die . Therefore, as described below, even with the reduced size of semiconductor wafers, a standardized ball layout can actually be used in the fan-out semiconductor package, thereby enabling the fan-out semiconductor package to be mounted on the motherboard of an electronic device , without using a separate board base.

圖8是示意性地說明其中扇出型半導體封裝安裝於電子裝置的主板上的情形的剖視圖。 8 is a cross-sectional view schematically illustrating a situation in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

參照圖8，扇出型半導體封裝2100可藉由焊料球2170等而安裝於電子裝置的主板2500上。亦即，如上所述，扇出型半 導體封裝2100包括連接構件2140，連接構件2140形成於半導體晶片2120上且能夠將連接墊2122重佈線至在半導體晶片2120的尺寸之外的扇出區，進而使得可按照原樣在扇出型半導體封裝2100中使用標準化球佈局(standardized ball layout)。如此一來，扇出型半導體封裝2100無需使用單獨的插板基板等便可安裝於電子裝置的主板2500上。 Referring to FIG. 8 , the fan-out semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through solder balls 2170 and the like. That is, as mentioned above, the fan-out half The conductor package 2100 includes a connection member 2140 formed on the semiconductor die 2120 and capable of rerouting the connection pads 2122 to a fan-out region outside the dimensions of the semiconductor die 2120, thereby enabling the fan-out semiconductor package as-is The 2100 uses a standardized ball layout. In this way, the fan-out semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate or the like.

如上所述，由於所述扇出型半導體封裝無需使用單獨的插板基板便可安裝於所述電子裝置的主板上，因此扇出型半導體封裝可被實作成具有較使用插板基板的扇入型半導體封裝的厚度薄的厚度。因此，扇出型半導體封裝可被小型化並變薄。此外，扇出型半導體封裝具有優異的熱特性及電性特性，進而使得扇出型半導體封裝可特別適合於行動產品。此外，扇出型半導體封裝可被實作成較使用印刷電路板(PCB)的一般堆疊式封裝類型的形式更壓縮的形式，且可解決因出現翹曲(warpage)現象而造成的問題。 As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the fan-out type semiconductor package can be implemented with a fan-in higher than that using an interposer substrate The thickness of the type semiconductor package is thin. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out type semiconductor package particularly suitable for mobile products. In addition, the fan-out type semiconductor package can be implemented in a more compact form than the general package-on-package type form using a printed circuit board (PCB), and can solve the problem caused by the occurrence of a warpage phenomenon.

同時，扇出型半導體封裝指代用於如上所述將半導體晶片安裝於電子裝置的主板、或類似組件上、並保護半導體晶片免受外部衝擊的封裝技術，且所述扇出型半導體封裝是與具有與扇出型半導體封裝的比例、目的等不同的比例、目的等的印刷電路板(PCB)(例如，插板基板等)的概念不同的概念，且在所述印刷電路板中嵌置有扇入型半導體封裝。 Meanwhile, the fan-out type semiconductor package refers to a packaging technique for mounting a semiconductor chip on a main board of an electronic device, or the like, as described above, and protecting the semiconductor chip from external impact, and the fan-out type semiconductor package is related to A concept different from that of a printed circuit board (PCB) (eg, an interposer substrate, etc.) having a different scale, purpose, etc., than that of a fan-out semiconductor package, and in which the printed circuit board is embedded Fan-in semiconductor package.

在下文中，將參照附圖闡述扇出型半導體封裝，所述扇 出型半導體封裝能夠解決在將其上形成有重佈線層的第一連接構件引入至半導體晶片的包封區上時因重佈線層的厚度而產生的第二連接構件的絕緣距離不均勻問題。 Hereinafter, a fan-out type semiconductor package will be explained with reference to the accompanying drawings, the fan The out-type semiconductor package can solve the problem of uneven insulation distance of the second connection member due to the thickness of the redistribution layer when the first connection member with the redistribution layer formed thereon is introduced into the encapsulation area of the semiconductor wafer.

圖9是示意性地說明扇出型半導體封裝的實例的剖視圖。 9 is a cross-sectional view schematically illustrating an example of a fan-out type semiconductor package.

圖10是沿圖9所示的線I-I'截取的扇出型半導體封裝的剖切平面圖。 FIG. 10 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line II′ shown in FIG. 9 .

參照圖9及圖10，根據實例的扇出型半導體封裝100A可包括：第一連接構件110，具有貫穿孔110H；半導體晶片120，安置於第一連接構件110的貫穿孔110H中且具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊122；包封體130，至少局部地包封第一連接構件110及半導體晶片120的非主動表面；以及第二連接構件140，安置於所述第一連接構件及所述半導體晶片的主動表面上，且包括電性連接至連接墊122的重佈線層142a及142b。第一連接構件110可包括與第二連接構件140接觸的第一絕緣層111a、與第二連接構件140接觸並嵌置於第一絕緣層111a中的第一重佈線層112a、安置於第一絕緣層111a的與其中嵌置有第一重佈線層112a的一側相對的另一側上的第二重佈線層112b、安置於第一絕緣層111a上並覆蓋第二重佈線層112b的第二絕緣層111b、以及安置於第二絕緣層111b上的第三重佈線層112c。第一重佈線層112a、第二重佈線層112b、及第三重佈線層112c可電性連接至連接墊122。根據實例的扇出型半導體封裝100A可更包括安置於第二連接構件140上的保護層 150、安置於保護層150的開口151上的凸塊下金屬層160、以及安置於凸塊下金屬層160上的連接端子170。 9 and 10 , a fan-out semiconductor package 100A according to an example may include: a first connection member 110 having a through hole 110H; a semiconductor die 120 disposed in the through hole 110H of the first connection member 110 and having an active surface and an inactive surface opposite the active surface, on which the connection pads 122 are disposed; an encapsulation body 130 at least partially encapsulating the first connection member 110 and the inactive surface of the semiconductor wafer 120; and a first Two connecting members 140 are disposed on the first connecting member and the active surface of the semiconductor chip, and include redistribution layers 142 a and 142 b electrically connected to the connecting pads 122 . The first connection member 110 may include a first insulating layer 111a in contact with the second connection member 140, a first redistribution layer 112a in contact with the second connection member 140 and embedded in the first insulating layer 111a, a first redistribution layer 112a disposed in the first The second redistribution layer 112b on the other side of the insulating layer 111a opposite to the side in which the first redistribution layer 112a is embedded, the second redistribution layer 112b disposed on the first insulating layer 111a and covering the second redistribution layer 112b. Two insulating layers 111b, and a third redistribution layer 112c disposed on the second insulating layer 111b. The first redistribution layer 112 a , the second redistribution layer 112 b , and the third redistribution layer 112 c may be electrically connected to the connection pads 122 . The fan-out semiconductor package 100A according to an example may further include a protective layer disposed on the second connection member 140 150 , an under-bump metal layer 160 disposed on the opening 151 of the protective layer 150 , and a connection terminal 170 disposed on the under-bump metal layer 160 .

一般而言，扇出型半導體封裝具有其中例如環氧模製化合物(epoxy molding compound，EMC)等包封體簡單地包封並包圍半導體晶片的周圍的結構，且第二連接構件形成於半導體晶片之下，藉此實作所述半導體晶片的重佈線。然而，在使用所述包封體簡單地包封並包圍半導體晶片的周圍的情形中，可能難以控制因各種原因而出現的翹曲，在固定半導體晶片方面存在限制，且可能難以利用包封區域作為路由區域，進而可能使得設計的自由度等劣化。 In general, a fan-out type semiconductor package has a structure in which an encapsulant such as epoxy molding compound (EMC) simply encapsulates and surrounds the periphery of the semiconductor chip, and the second connection member is formed on the semiconductor chip Hereinafter, the rewiring of the semiconductor wafer is implemented thereby. However, in the case where the encapsulation body is used to simply encapsulate and surround the periphery of the semiconductor wafer, it may be difficult to control warpage due to various reasons, there are limitations in fixing the semiconductor wafer, and it may be difficult to utilize the encapsulation area As a routing area, the degree of freedom of design and the like may be further deteriorated.

作為解決該些問題的方法，可考慮例如以下方法：將具有呈優異的剛性的絕緣層211'的第一連接構件210'引入至其中包封有所述半導體晶片的區域中，並在如圖34中所示的第一連接構件210'中形成重佈線層212a'及重佈線層212b'、介層窗213'等以在解決翹曲問題的同時提供較寬的路由區域。然而，在此種情形中，可能因形成於第一連接構件210'的一側上的重佈線層212a'的厚度而產生台階部分H。台階部分H可使第二連接構件240'的絕緣距離不均勻。一般而言，由於因重佈線層212a'的厚度而產生的台階部分H可為至少10微米或10微米左右，因此，因台階部分H而導致的絕緣距離不均勻可為對第二連接構件的第一介層窗243a'的設計產生大的影響的因素。亦即，絕緣距離不均勻可為使實作與半導體晶片220'的連接墊222'連接的介層窗243a'的精細節距的難 度增加的因素，且如此一來，可能難以設計第二連接構件240'的高密度配線。 As a method for solving these problems, for example, a method of introducing a first connection member 210 ′ having an insulating layer 211 ′ having excellent rigidity into a region in which the semiconductor wafer is encapsulated, and performing the process as shown in FIG. Redistribution layer 212a' and redistribution layer 212b', via 213', etc. are formed in the first connection member 210' shown in 34 to provide a wider routing area while solving the warpage problem. However, in this case, the stepped portion H may be generated due to the thickness of the redistribution layer 212a' formed on one side of the first connection member 210'. The stepped portion H may make the insulation distance of the second connection member 240' uneven. Generally speaking, since the step portion H caused by the thickness of the redistribution layer 212a' may be at least 10 microns or about 10 microns, the non-uniform insulation distance caused by the step portion H may be harmful to the second connection member. The design of the first via 243a' has a large influence factor. That is, non-uniform insulation distances can be difficult to achieve fine pitch of vias 243a' connected to connection pads 222' of semiconductor wafer 220'. factor of increased degree of density, and as such, it may be difficult to design high-density wiring of the second connection member 240'.

相反，如在根據實例的扇出型半導體封裝100A中一樣，在其中與第二連接構件140接觸的第一連接構件110的第一重佈線層112a嵌置於第一絕緣層111a中的情形中，因第一重佈線層112a的厚度而產生的台階部分可顯著減小，進而使得第二連接構件140的絕緣距離可為恆定的。亦即，自第二連接構件140的重佈線層142a至第一絕緣層111a的下表面的距離與自第二連接構件140的重佈線層142a至連接墊122的距離之間的差可小於第一重佈線層112a的厚度。因此，可易於設計第二連接構件140的高密度配線。 In contrast, as in the fan-out type semiconductor package 100A according to the example, in the case where the first redistribution layer 112a of the first connection member 110 in contact with the second connection member 140 is embedded in the first insulating layer 111a , the stepped portion due to the thickness of the first redistribution layer 112a can be significantly reduced, so that the insulation distance of the second connection member 140 can be constant. That is, the difference between the distance from the redistribution layer 142a of the second connection member 140 to the lower surface of the first insulating layer 111a and the distance from the redistribution layer 142a of the second connection member 140 to the connection pad 122 may be smaller than the first a thickness of the redistribution layer 112a. Therefore, high-density wiring of the second connection member 140 can be easily designed.

在下文中，將更詳細地闡述包含於根據實例的扇出型半導體封裝100A中的配置中的每一者。 Hereinafter, each of the configurations included in the fan-out semiconductor package 100A according to an example will be explained in more detail.

第一連接構件110可包括對半導體晶片120的連接墊122進行重佈線的重佈線層112a及重佈線層112b，藉此減少第二連接構件140的層的數目。視需要，第一連接構件110可相依於具體材料而維持封裝100A的剛性，並用於確保包封體130等厚度均勻。在某些情形中，根據實例的扇出型半導體封裝100A可被第一連接構件110用作堆疊式封裝的一部分。第一連接構件110可具有貫穿孔110H。半導體晶片120可安置於貫穿孔110H中以與第一連接構件110間隔開預定距離。半導體晶片120的側表面可由第一連接構件110環繞。然而，此僅為實例，且第一連接構件110 的安置形式可作出各種變化，且第一連接構件110可相依於安置形式而執行不同的功能。 The first connection member 110 may include a redistribution layer 112 a and a redistribution layer 112 b for rewiring the connection pads 122 of the semiconductor wafer 120 , thereby reducing the number of layers of the second connection member 140 . Optionally, the first connecting member 110 can maintain the rigidity of the package 100A depending on the specific material, and is used to ensure a uniform thickness of the encapsulation body 130 and the like. In some cases, the fan-out semiconductor package 100A according to the example may be used by the first connection member 110 as part of a package-on-package. The first connection member 110 may have a through hole 110H. The semiconductor wafer 120 may be seated in the through hole 110H to be spaced apart from the first connection member 110 by a predetermined distance. The side surfaces of the semiconductor wafer 120 may be surrounded by the first connection members 110 . However, this is only an example, and the first connection member 110 Various changes can be made to the arrangement form of the , and the first connecting member 110 can perform different functions depending on the arrangement form.

第一連接構件110可包括與第二連接構件140接觸的第一絕緣層111a、與第二連接構件140接觸並嵌置於第一絕緣層111a中的第一重佈線層112a、安置於第一絕緣層111a的與其中嵌置有第一重佈線層112a的一側相對的另一側上的第二重佈線層112b、安置於第一絕緣層111a上並覆蓋第二重佈線層112b的第二絕緣層111b、以及安置於第二絕緣層111b上的第三重佈線層112c。第一重佈線層112a、第二重佈線層112b、及第三重佈線層112c可電性連接至連接墊122。第一連接構件110可包括在穿透過第一絕緣層111a的同時將第一重佈線層112a與第二重佈線層112b電性連接至彼此的第一介層窗113a以及在穿透過第二絕緣層111b的同時將第二重佈線層112b與第三重佈線層112c電性連接至彼此的第二介層窗113b。如上所述，由於嵌置有第一重佈線層112a，因此所述第二連接構件的絕緣層141a的絕緣距離可實質上恆定。由於第一連接構件110包括大量重佈線層112a、112b及112c，因此第二連接構件140可進一步簡化。因此，因在形成第二連接構件140期間出現的缺陷而導致的良率降低可減少。 The first connection member 110 may include a first insulating layer 111a in contact with the second connection member 140, a first redistribution layer 112a in contact with the second connection member 140 and embedded in the first insulating layer 111a, a first redistribution layer 112a disposed in the first The second redistribution layer 112b on the other side of the insulating layer 111a opposite to the side in which the first redistribution layer 112a is embedded, the second redistribution layer 112b disposed on the first insulating layer 111a and covering the second redistribution layer 112b. Two insulating layers 111b, and a third redistribution layer 112c disposed on the second insulating layer 111b. The first redistribution layer 112 a , the second redistribution layer 112 b , and the third redistribution layer 112 c may be electrically connected to the connection pads 122 . The first connection member 110 may include a first via 113a that electrically connects the first redistribution layer 112a and the second redistribution layer 112b to each other while penetrating the first insulating layer 111a, and a first via 113a that penetrates the second insulating layer 111a. The layer 111b also electrically connects the second redistribution layer 112b and the third redistribution layer 112c to each other's second vias 113b. As described above, since the first redistribution layer 112a is embedded, the insulating distance of the insulating layer 141a of the second connection member can be substantially constant. Since the first connection member 110 includes a large number of redistribution layers 112a, 112b and 112c, the second connection member 140 can be further simplified. Therefore, yield reduction due to defects occurring during the formation of the second connection member 140 may be reduced.

第一絕緣層111a及第二絕緣層111b的材料並無特別限制。舉例而言，可使用絕緣材料。此處，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或者其中熱固性樹脂或熱塑性樹脂與無機填料一起浸入至芯 體材料(例如，玻璃布、玻璃纖維等)中的樹脂，例如預浸體(prepreg)、味之素構成膜(Ajinomoto build-up film，ABF)、FR-4、雙馬來醯亞胺三嗪(bismaleimide triazine，BT)樹脂等。視需要，亦可使用感光成像介電(PID)樹脂。第一絕緣層111a及第二絕緣層111b可含有彼此相同的絕緣材料，且第一絕緣層111a與第二絕緣層111b之間具有模糊的邊界，但並非僅限於此。 The materials of the first insulating layer 111a and the second insulating layer 111b are not particularly limited. For example, insulating materials can be used. Here, the following materials may be used as the insulating material: a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide; or wherein the thermosetting resin or thermoplastic resin is impregnated to the core together with the inorganic filler Resins in bulk materials (eg, glass cloth, fiberglass, etc.) such as prepreg, Ajinomoto build-up film (ABF), FR-4, bismaleimide three Azine (bismaleimide triazine, BT) resin and so on. If desired, photoimageable dielectric (PID) resins may also be used. The first insulating layer 111a and the second insulating layer 111b may contain the same insulating material as each other, and there is an ambiguous boundary between the first insulating layer 111a and the second insulating layer 111b, but not limited thereto.

重佈線層112a、112b及112c可用於對半導體晶片120的連接墊122進行重佈線，且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成重佈線層112a、112b及112c的材料。重佈線層112a、112b及112c可相依於對應層的設計而執行各種功能。舉例而言，重佈線層112a、112b及112c可包括接地(ground，GND)圖案、功率(power，PWR)圖案、訊號(signal，S)圖案等。此處，訊號圖案可包括除接地圖案、功率圖案等之外的各種訊號圖案，例如資料訊號圖案等。此外，重佈線層112a、112b及112c可包括介層窗墊、連接端子墊等。作為非限制性實例，所有重佈線層112a、112b及112c均可包括接地圖案。在此種情形中，可顯著減少接地圖案在第二連接構件140的重佈線層142a及142b上的形成，進而使得設計配線的自由度可得以提高。 The redistribution layers 112a, 112b, and 112c may be used to redistribute the connection pads 122 of the semiconductor wafer 120, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) , nickel (Ni), lead (Pb), titanium (Ti), and conductive materials such as alloys thereof are used as materials for forming the redistribution layers 112a, 112b, and 112c. The redistribution layers 112a, 112b, and 112c may perform various functions depending on the design of the corresponding layers. For example, the redistribution layers 112a, 112b, and 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal patterns may include various signal patterns other than ground patterns, power patterns, and the like, such as data signal patterns and the like. In addition, the redistribution layers 112a, 112b and 112c may include via pads, connection terminal pads, and the like. As a non-limiting example, all of the redistribution layers 112a, 112b, and 112c may include ground patterns. In this case, the formation of ground patterns on the redistribution layers 142a and 142b of the second connection member 140 can be significantly reduced, so that the degree of freedom in designing wiring can be improved.

視需要，表面處理層(圖中未示出)可進一步形成於重佈線層112a、112b及112c中經由在包封體130中形成的開口131而暴露出的重佈線層112c上。表面處理層(圖中未示出)並無特 別限制，只要所述表面處理層為此項技術中所習知者即可。舉例而言，表面處理層可藉由電解鍍金、無電鍍金、有機可焊性保護劑(organic solderability preservative，OSP)表面處理或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金(immersion gold plating)、直接浸金(direct immersion gold，DIG)電鍍、熱空氣焊料均塗(hot air solder leveling，HASL)等來形成。 Optionally, a surface treatment layer (not shown) may be further formed on the redistribution layer 112c exposed through the opening 131 formed in the encapsulation body 130 in the redistribution layers 112a, 112b and 112c. The surface treatment layer (not shown in the figure) has no special It is not limited as long as the surface treatment layer is known in the art. For example, the surface treatment layer can be electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) surface treatment or electroless tin, electroless silver, electroless nickel/immersion gold (immersion gold) plating plating), direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc.

介層窗113a及113b可將形成於不同層上的重佈線層112a、112b及112c電性連接至彼此，藉此在第一連接構件110中形成電性路徑。亦可使用導電材料來作為形成介層窗113a及113b的材料。如在圖11A至圖11D中所示，介層窗113a及113b可被完全填充以導電材料，或可藉由在介層窗孔的壁表面上形成導電材料而形成。此外，除錐形形狀之外，介層窗113a及113b亦可具有此項技術中所習知的所有形狀，例如圓柱形狀等。同時，如藉由下文將闡述的製程所知，當形成第一介層窗113a的孔時，第一重佈線層112a的某些墊可充當塞子(stopper)，且當形成第二介層窗113b的孔時，第二重佈線層112b的某些墊可充當塞子。因此，第一介層窗113a及第二介層窗113b具有其上表面的寬度較下表面的寬度寬的錐形形狀，所述錐形形狀在製程方面可具有優勢。在此種情形中，第一介層窗113a可與第二重佈線層112b的一部分整合於一起，且第二介層窗113b可與第三重佈線層112c的一部分整合於一起。 The vias 113 a and 113 b may electrically connect the redistribution layers 112 a , 112 b and 112 c formed on different layers to each other, thereby forming electrical paths in the first connection member 110 . A conductive material may also be used as the material for forming the vias 113a and 113b. As shown in FIGS. 11A-11D , vias 113a and 113b may be completely filled with conductive material, or may be formed by forming conductive material on the wall surfaces of the vias. Besides, the vias 113a and 113b can also have all shapes known in the art, such as cylindrical shapes and the like, in addition to the tapered shape. At the same time, some pads of the first redistribution layer 112a may act as stoppers when forming the holes of the first via 113a, and when forming the second via Some pads of the second redistribution layer 112b may act as plugs when the holes of 113b are removed. Therefore, the first via 113a and the second via 113b have a tapered shape in which the width of the upper surface is wider than the width of the lower surface, and the tapered shape may be advantageous in terms of process. In this case, the first via 113a may be integrated with a portion of the second redistribution layer 112b, and the second via 113b may be integrated with a portion of the third redistribution layer 112c.

半導體晶片120可為指示其中將至少數百至數百萬個或 更多個各種元件整合於一起的晶片的積體電路(IC)。所述積體電路可為例如：應用處理晶片，例如中央處理器(例如，中央處理單元(CPU))、圖形處理器(例如，圖形處理單元(GPU))、數位訊號處理器、密碼學處理器、微處理器、微控制器等，但並非僅限於此。半導體晶片120可例如基於主動晶圓而形成。在此種情形中，可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等來作為主體121的基材(base material)。在主體121中可形成各種電路。可配置連接墊122以將半導體晶片120電性連接至另一組件。可使用例如鋁(Al)等任何導電材料來作為形成連接墊122的材料，而無需特別限制。暴露出連接墊122的保護膜123可形成於主體121上。保護膜123可由氧化物膜、氮化物膜等形成。作為另一選擇，保護膜123可由氧化物膜與氮化物膜構成的雙層形成。可藉由保護膜123在連接墊122的下表面與包封體130的下表面之間形成台階部分(step portion)。如此一來，可在某種程度上防止包封體130溢出至連接墊122的下表面中。絕緣膜(圖中未示出)等可進一步安置於任何其他需要安置的位置上。 The semiconductor wafer 120 may indicate that there will be at least hundreds to millions or More integrated circuits (ICs) on a chip with various components integrated together. The integrated circuit may be, for example, an application processing chip such as a central processing unit (eg, central processing unit (CPU)), graphics processing unit (eg, graphics processing unit (GPU)), digital signal processor, cryptographic processing devices, microprocessors, microcontrollers, etc., but not limited thereto. The semiconductor wafer 120 may be formed, for example, based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of the body 121 . Various circuits may be formed in the main body 121 . The connection pads 122 may be configured to electrically connect the semiconductor die 120 to another component. Any conductive material such as aluminum (Al) may be used as a material for forming the connection pad 122 without particular limitation. A protective film 123 exposing the connection pads 122 may be formed on the body 121 . The protective film 123 may be formed of an oxide film, a nitride film, or the like. Alternatively, the protective film 123 may be formed of a double layer composed of an oxide film and a nitride film. A step portion may be formed between the lower surface of the connection pad 122 and the lower surface of the encapsulation body 130 by the protective film 123 . In this way, the encapsulation body 130 can be prevented from overflowing into the lower surface of the connection pad 122 to some extent. An insulating film (not shown in the figure) and the like may be further disposed on any other desired position.

半導體晶片120的非主動表面可被定位成低於第一連接構件110的第三重佈線層112c的上表面。舉例而言，半導體晶片120的非主動表面可被定位成低於第一連接構件110的第二絕緣層111b的上表面。半導體晶片120的非主動表面與第一連接構件110的第三重佈線層112c的上表面之間的高度差可為2微米或大於2微米，例如為5微米或大於5微米。在此種情形中，可有效地防 止在半導體晶片120的非主動表面的隅角部分中發生破裂。此外，在施加包封體130時，半導體晶片120的非主動表面上的絕緣距離中的偏差可顯著減小。 The inactive surface of the semiconductor wafer 120 may be positioned lower than the upper surface of the third redistribution layer 112 c of the first connection member 110 . For example, the inactive surface of the semiconductor wafer 120 may be positioned lower than the upper surface of the second insulating layer 111 b of the first connection member 110 . The height difference between the inactive surface of the semiconductor wafer 120 and the upper surface of the third redistribution layer 112c of the first connection member 110 may be 2 microns or more, eg, 5 microns or more. In this case, it can effectively prevent Cracks are prevented from occurring in the corner portions of the non-active surface of the semiconductor wafer 120 . Furthermore, when the encapsulant 130 is applied, the deviation in the insulation distance on the non-active surface of the semiconductor wafer 120 can be significantly reduced.

第一連接構件110的第二重佈線層112b可定位於半導體晶片120的主動表面與非主動表面之間。第一連接構件110可被形成為具有與半導體晶片120的厚度對應的厚度。因此，形成於第一連接構件110中的第二重佈線層112b可安置於半導體晶片120的主動表面與非主動表面之間的水平高度處。 The second redistribution layer 112b of the first connection member 110 may be positioned between the active surface and the non-active surface of the semiconductor wafer 120 . The first connection member 110 may be formed to have a thickness corresponding to that of the semiconductor wafer 120 . Therefore, the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120 .

包封體130可保護第一連接構件110及/或半導體晶片120。包封體130的形狀並無特別限制，只要包封體130至少局部地包圍第一連接構件110及/或半導體晶片120即可。舉例而言，包封體130可覆蓋第一連接構件110及半導體晶片120的非主動表面，並填充貫穿孔110H的壁表面與半導體晶片120的側表面之間的空間。此外，包封體130可至少局部地填充半導體晶片120的保護膜123與第二連接構件140之間的空間。同時，包封體130相依於包封體130的具體材料而填充貫穿孔110H，藉此用於在充當黏合劑時減少彎曲(buckling)。 The encapsulation body 130 can protect the first connection member 110 and/or the semiconductor chip 120 . The shape of the encapsulation body 130 is not particularly limited, as long as the encapsulation body 130 at least partially surrounds the first connection member 110 and/or the semiconductor wafer 120 . For example, the encapsulant 130 may cover the first connection member 110 and the inactive surface of the semiconductor wafer 120 and fill the space between the wall surface of the through hole 110H and the side surface of the semiconductor wafer 120 . In addition, the encapsulation body 130 may at least partially fill the space between the protective film 123 of the semiconductor wafer 120 and the second connection member 140 . Meanwhile, the encapsulation body 130 fills the through-hole 110H depending on the specific material of the encapsulation body 130 , thereby serving to reduce buckling while serving as an adhesive.

包封體130的具體材料並無特別限制。舉例而言，可使用絕緣材料來作為包封體130的材料。此處，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或者其中加強材料(例如，無機填料)被浸入熱固性樹脂及熱塑性樹脂中的樹脂，例如味之素構成膜、FR-4、雙馬來醯 亞胺三嗪樹脂、感光成像介電樹脂等。此外，亦可使用此項技術中所習知的例如環氧模製化合物(EMC)等模製材料。視需要，亦可使用其中熱固性樹脂或熱塑性樹脂與無機填料一起浸入至芯體材料(例如，玻璃布、玻璃纖維等)中的樹脂。 The specific material of the encapsulation body 130 is not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 130 . Here, the following materials may be used as insulating materials: thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide; or resins in which reinforcing materials (eg, inorganic fillers) are impregnated into thermosetting resins and thermoplastic resins such as Ajinomoto composition film, FR-4, bismaleate Iminotriazine resin, photosensitive imaging dielectric resin, etc. In addition, molding materials such as epoxy molding compound (EMC), known in the art, may also be used. If necessary, a resin in which a thermosetting resin or a thermoplastic resin is impregnated into a core material (eg, glass cloth, glass fiber, etc.) together with an inorganic filler can also be used.

包封體130可由由多種材料形成的多個層構成。舉例而言，可以第一包封體來填充貫穿孔110H中的空間，且接著，可以第二包封體覆蓋第一連接構件110及半導體晶片120。作為另一選擇，在使用第一包封體填充貫穿孔110H中的空間的同時以預定厚度覆蓋第一連接構件110及半導體晶片120之後，可再次以預定厚度將第二包封體安置於第一包封體上。另外，包封體130可以各種形式施加。 The encapsulant 130 may be composed of multiple layers formed of various materials. For example, the space in the through hole 110H may be filled with a first encapsulation body, and then, the first connection member 110 and the semiconductor chip 120 may be covered with a second encapsulation body. Alternatively, after the first encapsulation body is used to fill the space in the through hole 110H while covering the first connection member 110 and the semiconductor wafer 120 with a predetermined thickness, the second encapsulation body may be disposed on the second encapsulation body with a predetermined thickness again. on an envelope. Additionally, the encapsulant 130 may be applied in various forms.

視需要，包封體130中可含有導電粒子以遮蔽電磁波。可使用任何導電粒子，只要所述導電粒子可遮蔽電磁波即可。舉例而言，導電粒子可由銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、焊料等形成。然而，該些材料僅為實例，且導電粒子並非特別地限定於此。 Optionally, the encapsulating body 130 may contain conductive particles to shield electromagnetic waves. Any conductive particles can be used as long as the conductive particles can shield electromagnetic waves. For example, the conductive particles may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), solder, etc. . However, these materials are only examples, and the conductive particles are not particularly limited thereto.

可配置第二連接構件140以對半導體晶片120的連接墊122進行重佈線。具有各種功能的數十至數百個連接墊122可藉由第二連接構件140而進行重佈線，並相依於其功能而藉由下文將闡述的連接端子170而實體地連接至及/或電性連接至外部。第二連接構件140可包括絕緣層141a及141b、安置於絕緣層141a及141b上的重佈線層142a及142b、以及在穿透過絕緣層141a及141b 的同時將重佈線層142a及142b連接至彼此的介層窗143a及143b。在根據實例的扇出型半導體封裝100A中，第二連接構件140可由多個重佈線層142a及142b構成。然而，第二連接構件140並非僅限於此，而是亦可由單個層構成。此外，第二連接構件140亦可具有不同數目的層。 The second connection members 140 may be configured to reroute the connection pads 122 of the semiconductor wafer 120 . Dozens to hundreds of connection pads 122 with various functions can be rewired by the second connection member 140 and physically connected to and/or electrically connected by connection terminals 170 to be described below, depending on their functions. connected to the outside. The second connection member 140 may include insulating layers 141a and 141b, redistribution layers 142a and 142b disposed on the insulating layers 141a and 141b, and penetrating through the insulating layers 141a and 141b At the same time, the redistribution layers 142a and 142b are connected to each other's vias 143a and 143b. In the fan-out type semiconductor package 100A according to the example, the second connection member 140 may be constituted by a plurality of redistribution layers 142a and 142b. However, the second connection member 140 is not limited thereto, but may also be formed of a single layer. In addition, the second connecting member 140 may also have different numbers of layers.

可使用絕緣材料作為絕緣層141a及141b的材料。在此種情形中，除上述絕緣材料之外，亦可使用例如感光成像介電(PID)樹脂等感光性絕緣材料作為絕緣材料。在此種情形中，絕緣層141a及141b可被形成為更薄的，且可更易於實作介層窗143a及143b的精細節距。視需要，絕緣層141a及141b可由彼此相同的材料或彼此不同的材料形成。絕緣層141a與141b可相依於製程而與彼此整合於一起，進而使得絕緣層141a與141b之間的邊界可為模糊的。 An insulating material may be used as the material of the insulating layers 141a and 141b. In this case, in addition to the above-mentioned insulating material, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin can also be used as the insulating material. In this case, the insulating layers 141a and 141b can be formed thinner, and the fine pitch of the vias 143a and 143b can be more easily achieved. The insulating layers 141a and 141b may be formed of the same material as each other or different materials from each other, as necessary. The insulating layers 141a and 141b may be integrated with each other depending on the process, so that the boundary between the insulating layers 141a and 141b may be blurred.

重佈線層142a及142b可用於實質上對連接墊122進行重佈線，且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成重佈線層142a及142b的材料。重佈線層142a及142b可相依於對應層的設計而執行各種功能。舉例而言，重佈線層142a及142b可包括接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等。此處，訊號圖案可包括除接地圖案、功率圖案等之外的各種訊號圖案，例如資料訊號圖案等。此外，重佈線層142a及142b可包括介層窗墊、連接端子墊等。 The redistribution layers 142a and 142b may be used to substantially redistribute the connection pads 122, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni) ), lead (Pb), titanium (Ti), alloys thereof, and other conductive materials are used as materials for forming the redistribution layers 142a and 142b. The redistribution layers 142a and 142b may perform various functions depending on the design of the corresponding layers. For example, the redistribution layers 142a and 142b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal patterns may include various signal patterns other than ground patterns, power patterns, and the like, such as data signal patterns and the like. In addition, the redistribution layers 142a and 142b may include via pads, connection terminal pads, and the like.

視需要，表面處理層(圖中未示出)可進一步形成於重佈線層142a及142b中被局部地暴露出的重佈線層142b上。表面處理層(圖中未示出)並無特別限制，只要所述表面處理層是此項技術中所習知者即可。舉例而言，表面處理層可藉由電解鍍金、無電鍍金、有機可焊性保護劑(OSP)表面處理或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(DIG)電鍍、熱空氣焊料均塗(HASL)等來形成。 As necessary, a surface treatment layer (not shown in the drawings) may be further formed on the partially exposed redistribution layer 142b among the redistribution layers 142a and 142b. The surface treatment layer (not shown in the drawings) is not particularly limited as long as the surface treatment layer is known in the art. For example, the surface treatment layer can be electrolytic gold plating, electroless gold plating, organic solderability protectant (OSP) surface treatment or electroless tin, electroless silver, electroless nickel/displacement gold, direct immersion gold (DIG) Electroplating, hot air solder leveling (HASL), etc.

介層窗143a及143b可將形成於不同層上的重佈線層142a及142b、連接墊122等電性連接至彼此，藉此在封裝100A中形成電性路徑。可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成介層窗143a及143b的材料。介層窗143a及143b可被完全填充以導電材料，或所述導電材料亦可形成於所述介層窗的壁上。此外，介層窗143a及143b可具有此項技術中所習知的所有形狀，例如錐形形狀、圓柱形狀等。 The vias 143a and 143b may electrically connect the redistribution layers 142a and 142b, the connection pads 122, etc. formed on different layers to each other, thereby forming electrical paths in the package 100A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof can be used as Material for forming vias 143a and 143b. Vias 143a and 143b can be completely filled with conductive material, or the conductive material can also be formed on the walls of the vias. Furthermore, vias 143a and 143b may have all shapes known in the art, such as conical shapes, cylindrical shapes, and the like.

第一連接構件110的重佈線層112a、112b及112c的厚度可厚於第二連接構件140的重佈線層142a及142b的厚度。第一連接構件110可具有等於或厚於半導體晶片120的厚度的厚度，且因此形成於第一連接構件110中的重佈線層112a、112b及112c亦可根據第一連接構件110的厚度而為相對較厚的。相反，第二連接構件140的重佈線層142a及142b可被形成為相對較薄於第一連接構件110的重佈線層112a、112b及112c，以使第二連接構 件140變薄。 The thickness of the redistribution layers 112 a , 112 b and 112 c of the first connection member 110 may be thicker than the thickness of the redistribution layers 142 a and 142 b of the second connection member 140 . The first connection member 110 may have a thickness equal to or thicker than that of the semiconductor wafer 120 , and thus the redistribution layers 112 a , 112 b , and 112 c formed in the first connection member 110 may also be formed according to the thickness of the first connection member 110 . relatively thick. On the contrary, the redistribution layers 142a and 142b of the second connection member 140 may be formed to be relatively thinner than the redistribution layers 112a, 112b and 112c of the first connection member 110, so that the second connection structure Piece 140 is thinned.

可額外地配置保護層150以保護第二連接構件140不受外部的實體損害或化學損害等。保護層150可具有至少局部地暴露出第二連接構件140的重佈線層142a及142b中的重佈線層142b的開口151。開口151可暴露出重佈線層142b的一個表面的全部或暴露出重佈線層142b的一個表面的僅一部分。保護層150的材料並無特別限制。舉例而言，可使用例如感光性絕緣樹脂等感光性絕緣材料。作為另一選擇，亦可使用阻焊劑(solder resist)作為保護層150的材料。作為另一選擇，可使用不含有芯體材料而含有填料的絕緣樹脂，例如含有無機填料及環氧樹脂等的味之素構成膜(ABF)。 The protective layer 150 may be additionally configured to protect the second connection member 140 from external physical damage, chemical damage, or the like. The protective layer 150 may have an opening 151 exposing the redistribution layer 142b in the redistribution layers 142a and 142b of the second connection member 140 at least partially. The opening 151 may expose all of one surface of the redistribution layer 142b or expose only a part of one surface of the redistribution layer 142b. The material of the protective layer 150 is not particularly limited. For example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, a solder resist can also be used as the material of the protective layer 150 . Alternatively, an insulating resin containing no core material but a filler, for example, an Ajinomoto forming film (ABF) containing an inorganic filler, an epoxy resin, or the like can be used.

可額外地配置凸塊下金屬層160以提高連接端子170的連接可靠性從而提高板層次(board level)可靠性。凸塊下金屬層160可安置於保護層150的開口151的內壁表面上及第二連接構件140的所暴露出的重佈線層142b上。凸塊下金屬層160可由此項技術中所習知的導電材料(即，使用此項技術中所習知的金屬化方法的金屬)形成。 The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminals 170 to improve board level reliability. The under-bump metal layer 160 may be disposed on the inner wall surface of the opening 151 of the protective layer 150 and on the exposed redistribution layer 142 b of the second connection member 140 . The under bump metal layer 160 may be formed from conductive materials known in the art (ie, metals using metallization methods known in the art).

可額外地配置連接端子170以將扇出型半導體封裝100A實體地連接至及/或電性連接至外部。舉例而言，扇出型半導體封裝100A可藉由連接端子170而安裝於電子裝置的主板上。連接端子170可由例如焊料等導電材料形成。然而，所述材料僅為實例，且連接端子的材料並非特別地限定於此。連接端子170可為焊盤 (land)、球、引腳等。連接端子170可由多層或單層形成。在其中連接端子170由多層形成的情形中，連接端子170可含有銅柱及焊料，且在其中連接端子170由單層形成的情形中，連接端子170可含有錫-銀焊料或銅。然而，該些情形僅為實例，且連接端子170並非僅限於此。連接端子170的數目、間隔、安置形狀等均無特別限制，而是可由熟習此項技術者相依於設計而作出充分變化。舉例而言，連接端子170的數目可相依於半導體晶片120的連接墊122的數目而為數十至數千個。作為另一選擇，連接端子170的數目可大於或小於上述範圍。 The connection terminals 170 may be additionally configured to physically and/or electrically connect the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A can be mounted on the main board of the electronic device through the connection terminals 170 . The connection terminal 170 may be formed of a conductive material such as solder. However, the material is only an example, and the material of the connection terminal is not particularly limited thereto. The connection terminal 170 may be a pad (land), ball, pin, etc. The connection terminal 170 may be formed of multiple layers or a single layer. In the case where the connection terminal 170 is formed of multiple layers, the connection terminal 170 may contain copper pillars and solder, and in the case where the connection terminal 170 is formed of a single layer, the connection terminal 170 may contain tin-silver solder or copper. However, these cases are only examples, and the connection terminal 170 is not limited thereto. The number, interval, placement shape, and the like of the connection terminals 170 are not particularly limited, and can be sufficiently changed depending on the design by those skilled in the art. For example, the number of the connection terminals 170 may be tens to thousands depending on the number of the connection pads 122 of the semiconductor chip 120 . Alternatively, the number of connection terminals 170 may be larger or smaller than the above range.

連接端子170中的至少一者可安置於扇出區中。所述扇出區可為自其中安置有半導體晶片120的區偏離的區。亦即，根據實例的半導體封裝100A可為扇出型封裝。在所述扇出型封裝的情形中，可靠性可相較於扇入型封裝而言為較佳的，可實作多個輸入/輸出端子，且可易於執行3D互連。此外，由於扇出型封裝相較於球柵陣列(ball grid array，BGA)封裝、焊盤柵陣列(land grid array，LGA)封裝等而言無需單獨的板便可安裝於電子裝置上，因此所述扇出型封裝可被製造成具有減小的厚度，且價格競爭力可為優異的。 At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out region may be a region offset from the region in which the semiconductor wafer 120 is disposed. That is, the semiconductor package 100A according to the example may be a fan-out package. In the case of the fan-out type package, reliability may be better compared to the fan-in type package, multiple input/output terminals may be implemented, and 3D interconnection may be easily performed. In addition, since the fan-out package can be mounted on an electronic device without a separate board compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., The fan-out package can be manufactured with a reduced thickness, and price competitiveness can be excellent.

儘管圖中未示出，然而視需要，多個半導體晶片(圖中未示出)可安置於第一連接構件110的貫穿孔110H中。此外，多個貫穿孔110H(圖中未示出)可形成於第一連接構件110中，且半導體晶片(圖中未示出)可安置於所述貫穿孔中的每一者中。 此外，除半導體晶片之外，例如電容器(condenser)、電感器等單獨的被動組件(圖中未示出)亦可在貫穿孔110H中彼此包封於一起。此外，表面安裝組件(圖中未示出)可安裝於保護層150上。 Although not shown in the drawings, a plurality of semiconductor wafers (not shown in the drawings) may be disposed in the through holes 110H of the first connection member 110 as necessary. In addition, a plurality of through holes 110H (not shown in the drawings) may be formed in the first connection member 110, and a semiconductor wafer (not shown in the drawings) may be disposed in each of the through holes. In addition, in addition to the semiconductor chip, separate passive components such as capacitors, inductors, etc. (not shown in the figure) can also be encapsulated with each other in the through holes 110H. In addition, surface mount components (not shown in the drawings) may be mounted on the protective layer 150 .

圖12A至圖12D說明圖9所示扇出型半導體封裝的示意性製造製程的實例。 12A-12D illustrate an example of a schematic fabrication process for the fan-out semiconductor package shown in FIG. 9 .

參照圖12A，首先，可製備載體膜301。可在載體膜301的一個表面或兩個表面上形成金屬膜302及303。可對金屬膜302與金屬膜303之間的黏合表面進行表面處理以便於在後續的分離製程中達成分離。作為另一選擇，可在金屬膜302與金屬膜303之間設置釋放層，藉此便於在後續的製程中達成分離。載體膜301可為此項技術中所習知的絕緣基板，且載體膜301的材料不受限制。金屬膜302及303可一般由銅(Cu)箔形成，但並非僅限於此。金屬膜302及303可為由另一種導電材料形成的薄膜。此外，可使用乾膜304來執行圖案化以形成第一重佈線層112a。可使用此項技術中所習知的微影(photolithography)方法來執行所述圖案化。乾膜304可為由此項技術中所習知的感光性材料形成的乾膜。接著，可藉由以導電材料填充乾膜304的經圖案化空間來形成第一重佈線層112a。在此種情形中，可使用電鍍(plating)方法，且金屬膜303可充當晶種層。所述電鍍方法可為電解電鍍方法、無電電鍍方法等。更詳言之，可使用化學氣相沈積(chemical vapor deposition，CVD)方法、物理氣相沈積(physical vapor deposition，PVD)方法、濺鍍(sputtering)方法、減性方法 (subtractive method)、加性方法(additive method)、半加性製程(semi-additive process，SAP)、經修改半加性製程(modified semi-additive process，MSAP)等方法來形成第一重佈線層112a，但並非僅限於此。接下來，可移除乾膜304。可藉由此項技術中所習知的例如蝕刻方法等方法來移除乾膜304。 Referring to FIG. 12A, first, a carrier film 301 may be prepared. Metal films 302 and 303 may be formed on one surface or both surfaces of the carrier film 301 . Surface treatment can be performed on the bonding surface between the metal film 302 and the metal film 303 to facilitate separation in a subsequent separation process. Alternatively, a release layer may be disposed between the metal film 302 and the metal film 303, thereby facilitating separation in subsequent processes. The carrier film 301 can be an insulating substrate known in the art, and the material of the carrier film 301 is not limited. The metal films 302 and 303 may be generally formed of copper (Cu) foil, but not limited thereto. The metal films 302 and 303 may be thin films formed of another conductive material. Also, patterning may be performed using the dry film 304 to form the first redistribution layer 112a. The patterning can be performed using photolithography methods known in the art. Dry film 304 may be a dry film formed from photosensitive materials known in the art. Next, the first redistribution layer 112a may be formed by filling the patterned spaces of the dry film 304 with a conductive material. In this case, a plating method may be used, and the metal film 303 may serve as a seed layer. The electroplating method may be an electrolytic plating method, an electroless plating method, or the like. More specifically, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a sputtering method, a subtractive method can be used (subtractive method), additive method (additive method), semi-additive process (semi-additive process, SAP), modified semi-additive process (modified semi-additive process, MSAP) and other methods to form the first redistribution layer 112a, but not limited to that. Next, the dry film 304 can be removed. Dry film 304 may be removed by methods known in the art, such as etching methods.

參照圖12B，接下來，可在金屬膜303上形成其中至少局部地嵌置有重佈線層112a的第一絕緣層111a。接著，可形成穿透過第一絕緣層111a的第一介層窗113a。此外，可在第一絕緣層111a上形成第二重佈線層112b。可藉由使用此項技術中所習知的積層(lamination)方法來對第一絕緣層111a的前驅物進行積層並固化所積層的前驅物的方法、或使用此項技術中所習知的施加方法來施加前驅物材料並固化所施加的前驅物材料的方法等來形成第一絕緣層111a。可藉由以下方法形成第一介層窗113a及第二重佈線層112b：使用微影方法、機械鑽孔、雷射鑽孔、及/或類似方法在第一絕緣層111a中形成介層窗孔；使用乾膜等來執行圖案化；以及使用電鍍方法等來填充介層窗孔及經圖案化的空間。接下來，可在第一絕緣層111a上形成覆蓋第二重佈線層112b的第二絕緣層111b。此後，可形成穿透過第二絕緣層111b的第二介層窗113b。此外，可在第二絕緣層111b上形成第三重佈線層112c。以上闡述了形成第二絕緣層111b、第二介層窗113b及第三重佈線層112c的方法。接下來，可對載體膜301進行分層。在此種情形中，在進行分層時，金屬膜302與金屬膜303可彼此分離。在此 種情形中，可使用刀片(blade)來分離金屬膜302與金屬膜303，但並非僅限於此。可使用此項技術中所習知的所有方法。同時，在一系列製程中，闡述了其中在對載體膜301進行分層之前形成第一連接構件110的情形，但所述順序並非僅限於此。亦即，在對載體膜301進行分層之後，亦可藉由上述方法形成第一連接構件110。亦即，所述順序未必僅限於上述順序。 Referring to FIG. 12B , next, a first insulating layer 111 a in which the redistribution layer 112 a is at least partially embedded may be formed on the metal film 303 . Next, a first via 113a penetrating through the first insulating layer 111a may be formed. Also, a second redistribution layer 112b may be formed on the first insulating layer 111a. A method of laminating the precursor of the first insulating layer 111a and curing the layered precursor by using a lamination method known in the art, or applying a method known in the art The first insulating layer 111a is formed by a method of applying a precursor material and curing the applied precursor material, and the like. The first via 113a and the second redistribution layer 112b may be formed by forming vias in the first insulating layer 111a using lithography, mechanical drilling, laser drilling, and/or the like use dry film, etc. to perform patterning; and use electroplating methods, etc. to fill vias and patterned spaces. Next, a second insulating layer 111b covering the second redistribution layer 112b may be formed on the first insulating layer 111a. Thereafter, a second via 113b penetrating through the second insulating layer 111b may be formed. In addition, a third redistribution layer 112c may be formed on the second insulating layer 111b. The methods for forming the second insulating layer 111b, the second via 113b and the third redistribution layer 112c are described above. Next, the carrier film 301 can be layered. In this case, when delamination is performed, the metal film 302 and the metal film 303 may be separated from each other. here In this case, a blade may be used to separate the metal film 302 and the metal film 303, but is not limited thereto. All methods known in the art can be used. Meanwhile, in a series of processes, the case in which the first connection member 110 is formed before the layering of the carrier film 301 is explained, but the sequence is not limited thereto. That is, after the carrier film 301 is layered, the first connection member 110 can also be formed by the above-described method. That is, the order is not necessarily limited to the above-mentioned order.

參照圖12C，接下來，可藉由此項技術中所習知的蝕刻方法等來移除其餘的金屬膜303，且可在第一連接構件110中形成貫穿孔110H。可使用機械鑽孔製程及/或雷射鑽孔製程來形成貫穿孔110H。然而，貫穿孔110H並非僅限於此，而是可藉由使用研磨顆粒的噴砂(sandblasting)方法、使用電漿的乾式蝕刻方法等來形成。在其中使用機械鑽孔製程及/或雷射鑽孔製程來形成貫穿孔110H的情形中，可執行例如高錳酸鹽方法等除汙處理，以移除貫穿孔110H中的樹脂污垢。此外，可將黏合膜305貼附至第一連接構件110的一側。可使用任何黏合膜作為黏合膜305，只要所述黏合膜可固定第一連接構件110即可。作為非限制性實例，可使用此項技術中所習知的膠帶(tape)等。此項技術中所習知的膠帶的實例可包括其黏合力被熱處理減弱的熱固性黏合膠帶、其黏合力被紫外光照射劣化的紫外光固化黏合膠帶等。接下來，可在第一連接構件110的貫穿孔110H中安置半導體晶片120。舉例而言，可藉由將半導體晶片120黏合至貫穿孔110H中的黏合膜305而將半導體晶片120安置於貫穿孔110H中。可將半導體晶片120安置 成面朝下的形式，以使連接墊122黏合至黏合膜305。 Referring to FIG. 12C , next, the remaining metal film 303 may be removed by an etching method or the like known in the art, and a through hole 110H may be formed in the first connection member 110 . The through holes 110H may be formed using a mechanical drilling process and/or a laser drilling process. However, the through hole 110H is not limited to this, and may be formed by a sandblasting method using abrasive particles, a dry etching method using plasma, or the like. In the case where the through hole 110H is formed using a mechanical drilling process and/or a laser drilling process, a desmear process such as a permanganate method may be performed to remove resin dirt in the through hole 110H. Also, the adhesive film 305 may be attached to one side of the first connection member 110 . Any adhesive film may be used as the adhesive film 305 as long as the adhesive film can fix the first connection member 110 . As non-limiting examples, tapes and the like known in the art may be used. Examples of adhesive tapes known in the art may include thermosetting adhesive tapes whose adhesive force is weakened by heat treatment, UV-curable adhesive tapes whose adhesive force is degraded by ultraviolet light irradiation, and the like. Next, the semiconductor wafer 120 may be placed in the through hole 110H of the first connection member 110 . For example, the semiconductor wafer 120 may be positioned in the through hole 110H by adhering the semiconductor wafer 120 to the adhesive film 305 in the through hole 110H. Semiconductor wafer 120 can be placed face down so that the connection pads 122 are adhered to the adhesive film 305 .

參照圖12D，接下來，可使用包封體130來對半導體晶片120進行包封。包封體130可在至少包封第一連接構件110及半導體晶片120的非主動表面的同時填充貫穿孔110H中的空間。可藉由此項技術中所習知的方法來形成包封體130。舉例而言，可藉由對包封體130的前驅物進行積層並固化所積層的前驅物來形成包封體130。作為另一選擇，可施加包封體130以對黏合膜305上的半導體晶片120進行包封且接著固化包封體130。可藉由固化來固定半導體晶片120。可使用例如以下方法來作為對所述前驅物進行積層的方法：執行在高溫下對前驅物壓製預定時間的熱壓製方法、對所述前驅物進行減壓、且接著將所述前驅物冷卻至室溫、在冷壓製製程中冷卻所述前驅物、且接著分離作業工具等。可使用例如使用刮板(squeegee)施加油墨的網版印刷方法、霧化油墨以施加油墨的噴霧印刷方法等作為施加方法。接著，可對黏合膜305進行分層。分層方法並無特別限制，而是可使用此項技術中習知的方法。舉例而言，在其中使用其黏合力被熱處理劣化的熱固性黏合膠帶或其黏合力被紫外光照射劣化的紫外光固化黏合膠帶作為黏合膜305的情形中，可在藉由對黏合膜305執行熱處理或紫外光照射來劣化黏合力之後對黏合膜305進行分層。接下來，可在自其移除黏合膜305的第一連接構件110及半導體晶片120的主動表面上形成第二連接構件140。可藉由以下步驟來形成第二連接構件140：依序地形成絕緣層141a及141b，且在形成絕緣層 141a及141b之後分別在對應層中形成重佈線層142a及142b以及介層窗143a及143b。視需要，可在第二連接構件140上形成保護層150。相似地，可藉由對保護層150的前驅物進行積層並固化經積層的前驅物的方法、施加形成保護層150的材料並固化所施加的材料的方法等來形成保護層150。可在保護層150中形成開口151，從而可至少局部地暴露出第二連接構件140的重佈線層142b，且亦可藉由此項技術中所習知的金屬化方法而在保護層150上形成凸塊下金屬層160。視需要，可在凸塊下金屬層160上形成連接端子170。形成連接端子170的方法並無特別限制，而連接端子170可相依於其結構或形狀而藉由此項技術中眾所習知的方法形成。可藉由回焊(reflow)來固定連接端子170，且可藉由以下方法來提高可靠性：將連接端子170的一部分嵌置於保護層150中並將連接端子170的其他部分暴露至外部以增強固定力。 Referring to FIG. 12D , next, the encapsulant 130 may be used to encapsulate the semiconductor wafer 120 . The encapsulation body 130 may fill the space in the through hole 110H while encapsulating at least the first connection member 110 and the inactive surface of the semiconductor wafer 120 . The encapsulant 130 may be formed by methods known in the art. For example, the encapsulation body 130 may be formed by laminating the precursors of the encapsulating body 130 and curing the layered precursors. Alternatively, encapsulant 130 may be applied to encapsulate semiconductor wafer 120 on adhesive film 305 and then encapsulant 130 cured. The semiconductor wafer 120 may be fixed by curing. As a method of laminating the precursor, for example, a method of performing a hot pressing method of pressing the precursor at a high temperature for a predetermined time, decompressing the precursor, and then cooling the precursor to a temperature, can be used, for example. room temperature, cooling the precursor in a cold pressing process, and then separating the tool, etc. As the application method, for example, a screen printing method in which ink is applied using a squeegee, a spray printing method in which ink is atomized to apply ink, and the like can be used. Next, the adhesive film 305 can be delaminated. The layering method is not particularly limited, and a method known in the art can be used. For example, in the case where a thermosetting adhesive tape whose adhesive force is deteriorated by heat treatment or an ultraviolet light-curing adhesive tape whose adhesive force is deteriorated by ultraviolet light irradiation is used as the adhesive film 305, the adhesive film 305 can be processed by performing heat treatment on the adhesive film 305. Or the adhesive film 305 is delaminated after being irradiated with ultraviolet light to degrade the adhesive force. Next, the second connection member 140 may be formed on the active surface of the first connection member 110 and the semiconductor wafer 120 from which the adhesive film 305 was removed. The second connection member 140 may be formed by sequentially forming the insulating layers 141a and 141b, and after forming the insulating layers Redistribution layers 142a and 142b and vias 143a and 143b are formed in corresponding layers after 141a and 141b, respectively. As necessary, a protective layer 150 may be formed on the second connection member 140 . Similarly, the protective layer 150 may be formed by a method of laminating a precursor of the protective layer 150 and curing the layered precursor, a method of applying a material forming the protective layer 150 and curing the applied material, and the like. Openings 151 may be formed in the protective layer 150 so as to at least partially expose the redistribution layer 142b of the second connection member 140, and may also be on the protective layer 150 by metallization methods known in the art An under bump metal layer 160 is formed. Connection terminals 170 may be formed on the under bump metal layer 160 as needed. The method of forming the connection terminal 170 is not particularly limited, and the connection terminal 170 may be formed by a method well known in the art depending on its structure or shape. The connection terminal 170 may be fixed by reflow, and reliability may be improved by embedding a part of the connection terminal 170 in the protective layer 150 and exposing the other part of the connection terminal 170 to the outside to Enhance fixation.

同時，為便於大量生產，在一系列製程中，在製備出具有大尺寸的載體膜301之後，可藉由如上所述的製程來製造多個扇出型半導體封裝100A。接著可藉由切割而將所述多個扇出型半導體封裝100A分割成獨立的單位扇出型半導體封裝100A。在此種情形中，生產率可為優異的。 Meanwhile, in order to facilitate mass production, in a series of processes, after preparing the carrier film 301 with a large size, a plurality of fan-out semiconductor packages 100A can be manufactured by the above-mentioned process. The plurality of fan-out semiconductor packages 100A may then be divided into individual unit fan-out semiconductor packages 100A by dicing. In this case, the productivity can be excellent.

圖13是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 13 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖14是沿圖13所示的線II-II'截取的扇出型半導體封裝的剖切平面圖。 FIG. 14 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line II-II' shown in FIG. 13 .

參照圖13及圖14，在根據經修改實例的扇出型半導體封裝100B中，金屬層114可安置於第一連接構件110的貫穿孔110H的內壁表面上。金屬層114可用於有效地分散產生於半導體晶片120中的熱。此外，金屬層114亦可用於遮蔽電磁波。此外，金屬層114可連接至第一連接構件110中的其他重佈線層112a、112b及112c的接地圖案以藉此被用作接地。金屬層114可安置於整個壁表面上，或以特定形狀進行圖案化以藉此進行安置。金屬層114可含有如上所述的導電材料，即，金屬材料。 13 and 14 , in the fan-out type semiconductor package 100B according to the modified example, the metal layer 114 may be disposed on the inner wall surface of the through hole 110H of the first connection member 110 . The metal layer 114 can be used to effectively disperse the heat generated in the semiconductor wafer 120 . In addition, the metal layer 114 can also be used for shielding electromagnetic waves. In addition, the metal layer 114 may be connected to the ground patterns of the other redistribution layers 112a, 112b, and 112c in the first connection member 110 to thereby be used as a ground. The metal layer 114 may be disposed over the entire wall surface, or may be patterned in a specific shape to thereby be disposed. The metal layer 114 may contain a conductive material as described above, ie, a metallic material.

由於扇出型半導體封裝100B的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 100B are the same as those set forth in the fan-out type semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖15是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 15 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖16是沿圖15所示的線III-III'截取的扇出型半導體封裝的剖切平面圖。 FIG. 16 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line III-III' shown in FIG. 15 .

參照圖15及圖16，在根據經修改實例的扇出型半導體封裝100C中，單獨的第一被動組件124可安置於貫穿孔110H中。此外，單獨的第二被動組件126可安置於保護層150的表面上。第一被動組件124可為例如多層陶瓷電容器(MLCC)等高電容電容器，但並非僅限於此。第二被動組件126可為例如矽系電容器等低電容電容器，但並非僅限於此。第一被動組件124及第二被動組件126可連接至相同的電源線以藉此經由所述電源線而電性 連接至半導體晶片120，進而使得電源供應效率可得以提高。 Referring to FIGS. 15 and 16 , in the fan-out semiconductor package 100C according to the modified example, the individual first passive components 124 may be disposed in the through holes 110H. Additionally, a separate second passive component 126 may be disposed on the surface of the protective layer 150 . The first passive component 124 may be a high capacitance capacitor such as a multilayer ceramic capacitor (MLCC), but is not limited thereto. The second passive component 126 can be a low-capacitance capacitor such as a silicon-based capacitor, but is not limited thereto. The first passive component 124 and the second passive component 126 may be connected to the same power line to thereby electrically connect via the power line It is connected to the semiconductor chip 120 so that the power supply efficiency can be improved.

由於扇出型半導體封裝100C的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 100C are the same as those set forth in the fan-out type semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖17是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 17 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

圖18是沿圖17所示的線IV-IV'截取的扇出型半導體封裝的剖切平面圖。 FIG. 18 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line IV-IV' shown in FIG. 17 .

參照圖17及圖18，在根據經修改實例的扇出型半導體封裝100D中，第一連接構件110可由一或多個連接單元110A至110E構成。各個連接單元110A至110E可圍繞半導體晶片120安置。各個連接單元110A至110E可包括：第一絕緣層111a-1、111a-2等；在與第二連接構件140接觸的同時嵌置於第一絕緣層111a-1、111a-2等中的第一重佈線層112a-1、112a-2等；安置於第一絕緣層111a-1、111a-2等的與第一絕緣層111a-1、111a-2等的其中嵌置有第一重佈線層112a-1、112a-2等的一側相對的另一側上的第二重佈線層112b-1、112b-2等；安置於第一絕緣層111a-1、111a-2等上並覆蓋第二重佈線層112b-1、112b-2等的第二絕緣層111b-1、111b-2等；以及分別安置於第二絕緣層111b-1、111b-2等上的第三重佈線層112c-1、112c-2等。各個連接單元110A至110E的第一重佈線層112a-1、112a-2、第二重佈線層112b-1、112b-2、及第三重佈線層112c-1、112c-2等可電性連接至連接墊122。包封體 130可至少局部地包封各個連接單元110A至110E及半導體晶片120的非主動表面。包封體130可包封各個連接單元110A至110E的所有側表面。如此一來，各個連接單元110A至110E的側表面可不暴露於外部。 17 and 18 , in the fan-out type semiconductor package 100D according to the modified example, the first connection member 110 may be constituted by one or more connection units 110A to 110E. The respective connection units 110A to 110E may be disposed around the semiconductor wafer 120 . Each of the connection units 110A to 110E may include: first insulating layers 111a-1, 111a-2, etc.; A redistribution layer 112a-1, 112a-2, etc.; the first redistribution layer is embedded in the first insulating layer 111a-1, 111a-2, etc. and the first insulating layer 111a-1, 111a-2, etc. second redistribution layers 112b-1, 112b-2, etc. on one side opposite to layers 112a-1, 112a-2, etc.; disposed over and covering first insulating layers 111a-1, 111a-2, etc. The second insulating layers 111b-1, 111b-2, etc. of the second redistribution layers 112b-1, 112b-2, etc.; and the third redistribution layers disposed on the second insulating layers 111b-1, 111b-2, etc., respectively 112c-1, 112c-2, etc. The electrical properties of the first redistribution layers 112a-1, 112a-2, the second redistribution layers 112b-1, 112b-2, and the third redistribution layers 112c-1, 112c-2 of the respective connection units 110A to 110E, etc. Connect to connection pad 122 . Encapsulation 130 may at least partially encapsulate each of the connection units 110A to 110E and the inactive surface of the semiconductor wafer 120 . The encapsulation body 130 may encapsulate all side surfaces of the respective connection units 110A to 110E. As such, the side surfaces of the respective connection units 110A to 110E may not be exposed to the outside.

由於扇出型半導體封裝100D的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 100D are the same as those set forth in the fan-out type semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖19是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 19 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

參照圖19，在根據經修改實例的扇出型半導體封裝100E中，經由穿透過包封體130的介層窗183而與第一連接構件110的第三重佈線層112c電性連接的重佈線層182可安置於包封體130上。此外，具有局部地暴露出重佈線層182的開口(未由參考編號指示)的保護層180可安置於包封體130上。單獨的表面安裝組件181及186可安置於所述開口(未由參考編號指示)上以藉此電性連接至重佈線層182。表面安裝組件181及186可相依於表面安裝組件的類型而直接連接至重佈線層182或藉由焊接(圖中未示出)等而連接至重佈線層182。作為另一選擇，表面安裝組件181及186可藉由凸塊下金屬層184及連接端子185而連接至重佈線層182。表面安裝組件181及186可為各種類型的被動組件或各種類型的積體電路。 Referring to FIG. 19 , in the fan-out semiconductor package 100E according to the modified example, redistribution electrically connected to the third redistribution layer 112 c of the first connection member 110 through the via 183 penetrating the encapsulation body 130 Layer 182 may be disposed on envelope 130 . In addition, a protective layer 180 having an opening (not indicated by a reference number) partially exposing the redistribution layer 182 may be disposed on the encapsulation body 130 . Individual surface mount components 181 and 186 may be disposed on the openings (not indicated by reference numbers) to thereby electrically connect to the redistribution layer 182 . The surface mount components 181 and 186 may be directly connected to the redistribution layer 182 or connected to the redistribution layer 182 by soldering (not shown) or the like, depending on the type of the surface mount components. Alternatively, the surface mount components 181 and 186 may be connected to the redistribution layer 182 through the under bump metal layer 184 and the connection terminals 185 . Surface mount components 181 and 186 may be various types of passive components or various types of integrated circuits.

由於扇出型半導體封裝100E的其他配置或製造方法與在 根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out semiconductor package 100E are The configuration or manufacturing method described in the fan-out type semiconductor package 100A according to the example is the same, and thus will not be repeated.

圖20是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 20 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

參照圖20，在根據經修改實例的扇出型半導體封裝100F中，記憶體晶片封裝187可堆疊於包封體130上。記憶體晶片封裝187可藉由凸塊下金屬層184及形成於凸塊下金屬層184上的連接端子185而電性連接至第一連接構件110的第三重佈線層112c，凸塊下金屬層184形成於包封體130的局部地暴露出第一連接構件110的第三重佈線層112c的開口131上。記憶體晶片封裝187可包括例如揮發性記憶體(例如，動態隨機存取記憶體(DRAM))、非揮發性記憶體(例如，唯讀記憶體(ROM))、快閃記憶體等記憶體晶片。 Referring to FIG. 20 , in the fan-out type semiconductor package 100F according to the modified example, the memory chip package 187 may be stacked on the encapsulation body 130 . The memory chip package 187 can be electrically connected to the third redistribution layer 112c of the first connection member 110 through the under bump metal layer 184 and the connection terminals 185 formed on the under bump metal layer 184. The layer 184 is formed on the opening 131 of the encapsulation body 130 that partially exposes the third redistribution layer 112c of the first connection member 110 . The memory chip package 187 may include memory such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (ROM)), flash memory, etc. wafer.

由於扇出型半導體封裝100F的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 100F are the same as those set forth in the fan-out type semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖21是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 21 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

參照圖21，在根據經修改實例的扇出型半導體封裝100G中，第一重佈線層112a可凹進第一絕緣層中，且因此第一絕緣層111a的下表面與第一重佈線層112a的下表面之間可形成台階部分。如此一來，可防止在形成包封體130時因形成包封體130的 材料溢出而污染第一重佈線層112a。同時，由於如上所述第一重佈線層112a凹進第一絕緣層111a中，因此第一連接構件110的第一重佈線層112a的下表面可定位成高於半導體晶片120的連接墊122的下表面。此外，第二連接構件140的重佈線層142a與第一連接構件110的第一重佈線層112a之間的距離可大於第二連接構件140的重佈線層142a與半導體晶片120的連接墊122之間的距離。 21 , in the fan-out type semiconductor package 100G according to the modified example, the first redistribution layer 112a may be recessed into the first insulating layer, and thus the lower surface of the first insulating layer 111a and the first redistribution layer 112a A stepped portion may be formed between the lower surfaces of the . In this way, when the encapsulation body 130 is formed, it can be prevented that the encapsulation body 130 is formed The material overflows to contaminate the first redistribution layer 112a. Meanwhile, since the first redistribution layer 112a is recessed into the first insulating layer 111a as described above, the lower surface of the first redistribution layer 112a of the first connection member 110 may be positioned higher than the connection pad 122 of the semiconductor wafer 120. lower surface. In addition, the distance between the redistribution layer 142a of the second connection member 140 and the first redistribution layer 112a of the first connection member 110 may be greater than the distance between the redistribution layer 142a of the second connection member 140 and the connection pad 122 of the semiconductor wafer 120 distance between.

由於扇出型半導體封裝100G的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 100G are the same as those set forth in the fan-out type semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖22是示意性地說明圖9所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 22 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 9 .

參照圖22，在根據經修改實例的扇出型半導體封裝100H中，第一連接構件110可更包括安置於第二絕緣層111b上並覆蓋第三重佈線層112c的第三絕緣層111c及安置於第三絕緣層111c上的第四重佈線層112d。亦即，第一連接構件110可包括更大數目的重佈線層112a、112b、112c及112d。如此一來，第二連接構件140的層的數目可進一步減少，且因此，製程良率等可如上所述得以進一步提高。 22 , in the fan-out type semiconductor package 100H according to the modified example, the first connection member 110 may further include a third insulating layer 111 c disposed on the second insulating layer 111 b and covering the third redistribution layer 112 c and disposed A fourth redistribution layer 112d on the third insulating layer 111c. That is, the first connection member 110 may include a larger number of redistribution layers 112a, 112b, 112c, and 112d. As such, the number of layers of the second connection member 140 can be further reduced, and thus, the process yield and the like can be further improved as described above.

由於扇出型半導體封裝100H的其他配置或製造方法與在根據實例的扇出型半導體封裝100A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out semiconductor package 100H are the same as those set forth in the fan-out semiconductor package 100A according to the example, detailed descriptions thereof will not be repeated.

圖23是示意性地說明扇出型半導體封裝的另一實例的剖視圖。 23 is a cross-sectional view schematically illustrating another example of a fan-out type semiconductor package.

圖24是沿圖23所示的線V-V'截取的扇出型半導體封裝的剖切平面圖。 FIG. 24 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line V-V' shown in FIG. 23 .

參照圖23及圖24，根據另一實例的扇出型半導體封裝200A可包括：第一連接構件210，具有貫穿孔210H；半導體晶片220，安置於第一連接構件210的貫穿孔210H中且具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊222；包封體230，至少局部地包封第一連接構件210及半導體晶片220的非主動表面；以及第二連接構件240，安置於第一連接構件210及半導體晶片220的主動表面上，且包括電性連接至連接墊222的重佈線層242a及242b。第一連接構件210可包括與第二連接構件240接觸的絕緣層211、在與第二連接構件240接觸的同時嵌置於絕緣層211中的第一重佈線層212a、以及安置於絕緣層211的與絕緣層211的其中嵌置有第一重佈線層212a的一側相對的另一側上的第二重佈線層212b。第一連接構件210可包括介層窗213，介層窗213在穿透過絕緣層211的同時將第一重佈線層212a與第二重佈線層212b電性連接。第一重佈線層212a及第二重佈線層212b可電性連接至連接墊222。根據另一實例的扇出型半導體封裝200A可更包括安置於第二連接構件240上的保護層250、安置於保護層250的開口251上的凸塊下金屬層260、以及安置於凸塊下金屬層260上的連接端子270。 23 and 24 , a fan-out semiconductor package 200A according to another example may include: a first connection member 210 having a through hole 210H; a semiconductor chip 220 disposed in the through hole 210H of the first connection member 210 and having a through hole 210H an active surface and an inactive surface opposite to the active surface, on which the connection pads 222 are arranged; an encapsulation body 230 at least partially encapsulating the first connection member 210 and the inactive surface of the semiconductor wafer 220; And the second connection member 240 is disposed on the first connection member 210 and the active surface of the semiconductor chip 220 and includes redistribution layers 242 a and 242 b electrically connected to the connection pads 222 . The first connection member 210 may include an insulating layer 211 in contact with the second connection member 240 , a first redistribution layer 212 a embedded in the insulating layer 211 while being in contact with the second connection member 240 , and disposed in the insulating layer 211 The second redistribution layer 212b on the other side of the insulating layer 211 opposite to the side in which the first redistribution layer 212a is embedded. The first connection member 210 may include a via 213 , and the via 213 electrically connects the first redistribution layer 212 a and the second redistribution layer 212 b while penetrating through the insulating layer 211 . The first redistribution layer 212a and the second redistribution layer 212b can be electrically connected to the connection pads 222 . The fan-out semiconductor package 200A according to another example may further include a protective layer 250 disposed on the second connection member 240 , an under-bump metal layer 260 disposed on the openings 251 of the protective layer 250 , and an under-bump metallization layer 260 disposed under the bump Connection terminals 270 on metal layer 260 .

如在根據另一實例的扇出型半導體封裝200A中一樣，在其中第一連接構件210的第一重佈線層212a與嵌置於絕緣層211中的第二連接構件240接觸的情形中，因第一重佈線層212a的厚度而產生的台階部分可顯著減小，進而使得第二連接構件240的絕緣距離可為恆定的。亦即，自第二連接構件240的重佈線層242a至絕緣層211的下表面的距離與自第二連接構件240的重佈線層242a至連接墊222的距離之間的差可小於第一重佈線層212a的厚度。因此，可易於設計第二連接構件240的高密度配線。 As in the fan-out type semiconductor package 200A according to another example, in the case where the first redistribution layer 212a of the first connection member 210 is in contact with the second connection member 240 embedded in the insulating layer 211, because The stepped portion caused by the thickness of the first redistribution layer 212a can be significantly reduced, so that the insulation distance of the second connection member 240 can be constant. That is, the difference between the distance from the redistribution layer 242a of the second connection member 240 to the lower surface of the insulating layer 211 and the distance from the redistribution layer 242a of the second connection member 240 to the connection pad 222 may be smaller than the first redistribution layer 242a. The thickness of the wiring layer 212a. Therefore, high-density wiring of the second connection member 240 can be easily designed.

在下文中，將更詳細地闡述包含於根據另一實例的扇出型半導體封裝200A中的配置中的每一者。 Hereinafter, each of the configurations included in the fan-out semiconductor package 200A according to another example will be set forth in more detail.

第一連接構件210可包括對半導體晶片220的連接墊222進行重佈線的重佈線層212a及212b，藉此減少第二連接構件240的層的數目。視需要，第一連接構件210可相依於具體材料而維持封裝200A的剛性，並用於確保包封體230等厚度均勻。第一連接構件210可具有貫穿孔210H。半導體晶片220可安置於貫穿孔210H中以與第一連接構件210間隔開預定距離。半導體晶片220的側表面可被第一連接構件210環繞。然而，此僅為實例，且第一連接構件210的安置形式可作出各種變化，且第一連接構件210可相依於安置形式而執行不同的功能。 The first connection member 210 may include redistribution layers 212 a and 212 b that rewire the connection pads 222 of the semiconductor wafer 220 , thereby reducing the number of layers of the second connection member 240 . Optionally, the first connecting member 210 can maintain the rigidity of the package 200A depending on the specific material, and is used to ensure a uniform thickness of the package body 230 and the like. The first connection member 210 may have a through hole 210H. The semiconductor wafer 220 may be seated in the through hole 210H to be spaced apart from the first connection member 210 by a predetermined distance. The side surfaces of the semiconductor wafer 220 may be surrounded by the first connection members 210 . However, this is only an example, and various changes may be made to the arrangement form of the first connection member 210, and the first connection member 210 may perform different functions depending on the arrangement form.

絕緣層211的材料並無特別限制。舉例而言，可使用絕緣材料。此處，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或其中該些樹脂與無 機填料一起浸入至芯體材料(例如，玻璃布、玻璃纖維等)中的樹脂，例如預浸體、味之素構成膜(ABF)、FR-4、雙馬來醯亞胺三嗪(BT)樹脂等。視需要，亦可使用感光成像介電(PID)樹脂。 The material of the insulating layer 211 is not particularly limited. For example, insulating materials can be used. Here, the following materials can be used as insulating materials: thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide; or wherein these resins are combined with non- Resins in which organic fillers are impregnated into core materials (eg, glass cloth, fiberglass, etc.) together, such as prepregs, Ajinomoto Constructing Film (ABF), FR-4, Bismaleimide Triazine (BT) ) resin, etc. If desired, photoimageable dielectric (PID) resins may also be used.

重佈線層212a及212b可用於對半導體晶片220的連接墊222進行重佈線，且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成重佈線層212a及212b的材料。重佈線層212a及212b可相依於對應層的設計而執行各種功能。舉例而言，重佈線層212a及212b可包括接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等。此處，訊號圖案可包括除接地圖案、功率圖案等之外的各種訊號圖案，例如資料訊號圖案等。此外，重佈線層212a及212b可包括介層窗墊、連接端子墊等。作為非限制性實例，重佈線層212a及212b二者均可包括接地圖案。在此種情形中，可顯著減少接地圖案在第二連接構件240的重佈線層242a及242b上的形成，進而使得設計配線的自由度可得以提高。 The redistribution layers 212a and 212b may be used to redistribute the connection pads 222 of the semiconductor wafer 220, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel Conductive materials such as (Ni), lead (Pb), titanium (Ti), and alloys thereof are used as materials for forming the redistribution layers 212a and 212b. The redistribution layers 212a and 212b may perform various functions depending on the design of the corresponding layers. For example, the redistribution layers 212a and 212b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal patterns may include various signal patterns other than ground patterns, power patterns, and the like, such as data signal patterns and the like. In addition, the redistribution layers 212a and 212b may include via pads, connection terminal pads, and the like. As a non-limiting example, both redistribution layers 212a and 212b may include ground patterns. In this case, the formation of ground patterns on the redistribution layers 242a and 242b of the second connection member 240 can be significantly reduced, so that the degree of freedom in designing wiring can be improved.

視需要，表面處理層(圖中未示出)可進一步形成於重佈線層212a及212b中經由在包封體230中形成的開口231而暴露出的重佈線層212b上。表面處理層(圖中未示出)並無特別限制，只要所述表面處理層為此項技術中所習知者即可。舉例而言，表面處理層可藉由電解鍍金、無電鍍金、有機可焊性保護劑(OSP)表面處理或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(DIG)電鍍、熱空氣焊料均塗(HASL)等來形成。 If necessary, a surface treatment layer (not shown in the figure) may be further formed on the redistribution layer 212b exposed through the opening 231 formed in the encapsulation body 230 in the redistribution layers 212a and 212b. The surface treatment layer (not shown in the drawings) is not particularly limited as long as the surface treatment layer is known in the art. For example, the surface treatment layer can be electrolytic gold plating, electroless gold plating, organic solderability protectant (OSP) surface treatment or electroless tin, electroless silver, electroless nickel/displacement gold, direct immersion gold (DIG) Electroplating, hot air solder leveling (HASL), etc.

介層窗213可將形成於不同層上的重佈線層212a與重佈線層212b電性連接至彼此，藉此在第一連接構件210中形成電性路徑。亦可使用導電材料來作為形成介層窗213的材料。如在圖25A至圖25D中所示，介層窗213可被完全填充以導電材料，或可藉由在介層窗孔的壁表面上形成導電材料而形成。此外，除錐形形狀之外，介層窗213亦可具有此項技術中所習知的所有形狀，例如圓柱形狀等。同時，如藉由以下將闡述的製程所知，當形成介層窗213的孔時，第一重佈線層212a中的某些墊可充當塞子(stopper)。因此，介層窗213具有其上表面的寬度較下表面的寬度寬的錐形形狀，所述錐形形狀在製程方面可具有優勢。在此種情形中，介層窗213可與第二重佈線層212b的一部分整合於一起。 The via 213 may electrically connect the redistribution layer 212 a and the redistribution layer 212 b formed on different layers to each other, thereby forming an electrical path in the first connection member 210 . A conductive material can also be used as the material for forming the via 213 . As shown in FIGS. 25A-25D , the via 213 may be completely filled with a conductive material, or may be formed by forming a conductive material on the wall surface of the via hole. Besides, the via 213 may have all shapes known in the art, such as cylindrical shapes, other than the tapered shape. At the same time, some of the pads in the first redistribution layer 212a may act as stoppers when forming the holes of the vias 213, as is known from the process described below. Therefore, the via 213 has a tapered shape in which the width of the upper surface is wider than the width of the lower surface, and the tapered shape may have advantages in terms of process. In this case, the via 213 may be integrated with a portion of the second redistribution layer 212b.

半導體晶片220可為指示其中將至少數百至數百萬個或更多個各種元件整合於一起的晶片的積體電路(IC)。所述積體電路可為例如：應用處理晶片，例如中央處理器(例如，中央處理單元(CPU))、圖形處理器(例如，圖形處理單元(GPU))、數位訊號處理器、密碼學處理器、微處理器、微控制器等，但並非僅限於此。半導體晶片220可例如基於主動晶圓而形成。在此種情形中，可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等來作為主體221的基材。在主體221中可形成各種電路。可配置連接墊222以將半導體晶片220電性連接至另一組件。可使用例如鋁(Al)等任何導電材料來作為形成連接墊222的材料，而無需特別限制。可在主體221上形成暴露出連接墊222的保護膜223。保護膜223 可由氧化物膜、氮化物膜等形成。作為另一選擇，保護膜223可由氧化物膜與氮化物膜構成的雙層形成。可藉由保護膜223而在連接墊222的下表面與包封體230的下表面之間形成台階部分。如此一來，可在某種程度上防止包封體230溢出至連接墊222的下表面中。絕緣膜(圖中未示出)等可進一步安置於任何其他需要安置的位置上。 Semiconductor wafer 220 may be an integrated circuit (IC) indicative of a wafer in which at least hundreds to millions or more of various components are integrated together. The integrated circuit may be, for example, an application processing chip such as a central processing unit (eg, central processing unit (CPU)), graphics processing unit (eg, graphics processing unit (GPU)), digital signal processor, cryptographic processing devices, microprocessors, microcontrollers, etc., but not limited thereto. The semiconductor wafer 220 may be formed, for example, based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as the base material of the body 221 . Various circuits may be formed in the main body 221 . The connection pads 222 may be configured to electrically connect the semiconductor die 220 to another component. Any conductive material such as aluminum (Al) may be used as the material for forming the connection pad 222 without particular limitation. A protective film 223 exposing the connection pads 222 may be formed on the body 221 . Protective film 223 It may be formed of an oxide film, a nitride film, or the like. Alternatively, the protective film 223 may be formed of a double layer composed of an oxide film and a nitride film. A stepped portion may be formed between the lower surface of the connection pad 222 and the lower surface of the encapsulation body 230 by the protective film 223 . In this way, the encapsulation body 230 can be prevented from overflowing into the lower surface of the connection pad 222 to some extent. An insulating film (not shown in the figure) and the like may be further disposed on any other desired position.

半導體晶片220的非主動表面可被定位成低於第一連接構件210的第二重佈線層212b的上表面。舉例而言，半導體晶片220的非主動表面可被定位成低於第一連接構件210的絕緣層211的上表面。半導體晶片220的非主動表面與第一連接構件210的第二重佈線層212b的上表面之間的高度差可為2微米或大於2微米，例如為5微米或大於5微米。在此種情形中，可有效地防止在半導體晶片220的非主動表面的隅角部分中發生破裂。此外，在施加包封體230時，半導體晶片220的非主動表面上的絕緣距離中的偏差可顯著減小。 The inactive surface of the semiconductor wafer 220 may be positioned lower than the upper surface of the second redistribution layer 212b of the first connection member 210 . For example, the non-active surface of the semiconductor wafer 220 may be positioned lower than the upper surface of the insulating layer 211 of the first connection member 210 . The height difference between the inactive surface of the semiconductor wafer 220 and the upper surface of the second redistribution layer 212b of the first connection member 210 may be 2 microns or more, eg, 5 microns or more. In this case, cracks can be effectively prevented from occurring in the corner portions of the non-active surface of the semiconductor wafer 220 . Furthermore, when the encapsulant 230 is applied, the deviation in the insulation distance on the non-active surface of the semiconductor wafer 220 can be significantly reduced.

包封體230可保護第一連接構件210及/或半導體晶片220。包封體230的形狀並無特別限制，只要包封體230至少局部地包圍第一連接構件210及/或半導體晶片220即可。舉例而言，包封體230可覆蓋第一連接構件210及半導體晶片220的非主動表面，並填充貫穿孔210H的壁表面與半導體晶片220的側表面之間的空間。此外，包封體230可至少局部地填充半導體晶片220的保護膜223與第二連接構件240之間的空間。同時，包封體230 相依於包封體230的具體材料而填充貫穿孔210H，藉此用於在充當黏合劑時減少彎曲。 The encapsulation body 230 can protect the first connection member 210 and/or the semiconductor chip 220 . The shape of the encapsulation body 230 is not particularly limited, as long as the encapsulation body 230 at least partially surrounds the first connection member 210 and/or the semiconductor wafer 220 . For example, the encapsulant 230 may cover the first connection member 210 and the inactive surface of the semiconductor wafer 220 and fill the space between the wall surface of the through hole 210H and the side surface of the semiconductor wafer 220 . In addition, the encapsulation body 230 may at least partially fill the space between the protective film 223 of the semiconductor wafer 220 and the second connection member 240 . At the same time, the encapsulation body 230 The through hole 210H is filled depending on the specific material of the encapsulant 230, thereby serving to reduce bending while acting as an adhesive.

包封體230的具體材料並無特別限制。舉例而言，可使用絕緣材料來作為包封體230的材料。此處，可使用以下材料作為絕緣材料：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺；或者其中加強材料(例如，無機填料)被浸入熱固性樹脂及熱塑性樹脂中的樹脂，例如味之素構成膜、FR-4、雙馬來醯亞胺三嗪樹脂、感光成像介電樹脂等。此外，亦可使用此項技術中所習知的例如環氧模製化合物(EMC)等模製材料。視需要，亦可使用其中熱固性樹脂或熱塑性樹脂與無機填料一起浸入至芯體材料(例如，玻璃布、玻璃纖維等)中的樹脂。 The specific material of the encapsulation body 230 is not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 230 . Here, the following materials may be used as insulating materials: thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide; or resins in which reinforcing materials (eg, inorganic fillers) are impregnated into thermosetting resins and thermoplastic resins such as Ajinomoto constitutes film, FR-4, bismaleimide triazine resin, photosensitive imaging dielectric resin, etc. In addition, molding materials such as epoxy molding compound (EMC), known in the art, may also be used. If necessary, a resin in which a thermosetting resin or a thermoplastic resin is impregnated into a core material (eg, glass cloth, glass fiber, etc.) together with an inorganic filler can also be used.

包封體230可由由多種材料形成的多個層構成。舉例而言，可以第一包封體來填充貫穿孔210H中的空間，且接著，可以第二包封體覆蓋第一連接構件210及半導體晶片220。作為另一選擇，在使用第一包封體填充貫穿孔210H中的空間的同時以預定厚度覆蓋第一連接構件210及半導體晶片220之後，可再次以預定厚度將第二包封體安置於第一包封體上。另外，包封體230可以各種形式施加。 The encapsulant 230 may be composed of multiple layers formed of various materials. For example, the space in the through hole 210H may be filled with a first encapsulation body, and then, the first connection member 210 and the semiconductor chip 220 may be covered with a second encapsulation body. Alternatively, after the first encapsulation body is used to fill the space in the through hole 210H while covering the first connection member 210 and the semiconductor wafer 220 with a predetermined thickness, the second encapsulation body may be disposed on the second encapsulation body with a predetermined thickness again. on an envelope. Additionally, the encapsulant 230 may be applied in various forms.

視需要，包封體230中可含有導電粒子以遮蔽電磁波。可使用任何導電粒子，只要所述導電粒子可遮蔽電磁波即可。舉例而言，導電粒子可由銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、焊料等形成。然而，該 些材料僅為實例，且導電粒子並非特別地限定於此。 Optionally, the encapsulation body 230 may contain conductive particles to shield electromagnetic waves. Any conductive particles can be used as long as the conductive particles can shield electromagnetic waves. For example, the conductive particles may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), solder, etc. . However, the These materials are only examples, and the conductive particles are not particularly limited thereto.

可配置第二連接構件240以對半導體晶片220的連接墊222進行重佈線。具有各種功能的數十至數百個連接墊222可藉由第二連接構件240而進行重佈線，並相依於其功能而藉由下文將闡述的連接端子270而實體地連接至及/或電性連接至外部。第二連接構件240可包括絕緣層241a及241b、安置於絕緣層241a及241b上的重佈線層242a及242b、以及在穿透過絕緣層241a及241b的同時將重佈線層242a及242b連接至彼此的介層窗243a及243b。在根據另一實例的扇出型半導體封裝200A中，第二連接構件240可由多個重佈線層242a及242b構成。然而，第二連接構件240亦可由單個層構成。此外，第二連接構件240亦可具有不同數目的層。 The second connection member 240 may be configured to reroute the connection pads 222 of the semiconductor die 220 . Dozens to hundreds of connection pads 222 with various functions can be rewired by the second connection member 240 and physically connected to and/or electrically connected by connection terminals 270 to be described below, depending on their functions. connected to the outside. The second connection member 240 may include insulating layers 241a and 241b, redistribution layers 242a and 242b disposed on the insulating layers 241a and 241b, and connecting the redistribution layers 242a and 242b to each other while penetrating through the insulating layers 241a and 241b vias 243a and 243b. In the fan-out semiconductor package 200A according to another example, the second connection member 240 may be constituted by a plurality of redistribution layers 242a and 242b. However, the second connection member 240 may also be composed of a single layer. In addition, the second connection member 240 may also have different numbers of layers.

可使用絕緣材料作為絕緣層241a及241b的材料。在此種情形中，除上述絕緣材料之外，亦可使用例如感光成像介電(PID)樹脂等感光性絕緣材料作為絕緣材料。在此種情形中，絕緣層241a及241b可被形成為更薄的，且可更易於實作介層窗243a及243b的精細節距。視需要，絕緣層241a及241b可由彼此相同的材料或彼此不同的材料形成。絕緣層241a與241b可相依於製程而彼此整合於一起，進而使得絕緣層241a與241b之間的邊界可為模糊的。 An insulating material may be used as the material of the insulating layers 241a and 241b. In this case, in addition to the above-mentioned insulating material, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin can also be used as the insulating material. In this case, the insulating layers 241a and 241b can be formed thinner, and the fine pitch of the vias 243a and 243b can be more easily achieved. The insulating layers 241a and 241b may be formed of the same material as each other or different materials from each other, as necessary. The insulating layers 241a and 241b may be integrated with each other depending on the process, so that the boundary between the insulating layers 241a and 241b may be blurred.

重佈線層242a及242b可用於實質上對連接墊222進行重佈線，且可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、 金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成重佈線層242a及242b的材料。重佈線層242a及242b可相依於對應層的設計而執行各種功能。舉例而言，重佈線層242a及242b可包括接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等。此處，訊號圖案可包括除接地圖案、功率圖案等之外的各種訊號圖案，例如資料訊號圖案等。此外，重佈線層242a及242b可包括介層窗墊、連接端子墊等。 The redistribution layers 242a and 242b may be used to substantially redistribute the connection pads 222, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), Conductive materials such as gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof are used as materials for forming the redistribution layers 242a and 242b. The redistribution layers 242a and 242b may perform various functions depending on the design of the corresponding layers. For example, the redistribution layers 242a and 242b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal patterns may include various signal patterns other than ground patterns, power patterns, and the like, such as data signal patterns and the like. In addition, the redistribution layers 242a and 242b may include via pads, connection terminal pads, and the like.

視需要，表面處理層(圖中未示出)可進一步形成於重佈線層242a及242b中被局部地暴露出的重佈線層242b上。表面處理層(圖中未示出)並無特別限制，只要所述表面處理層是此項技術中所習知者即可。舉例而言，表面處理層可藉由電解鍍金、無電鍍金、有機可焊性保護劑(OSP)表面處理或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金(DIG)電鍍、熱空氣焊料均塗(HASL)等來形成。 If necessary, a surface treatment layer (not shown in the drawings) may be further formed on the partially exposed redistribution layer 242b among the redistribution layers 242a and 242b. The surface treatment layer (not shown in the drawings) is not particularly limited as long as the surface treatment layer is known in the art. For example, the surface treatment layer can be electrolytic gold plating, electroless gold plating, organic solderability protectant (OSP) surface treatment or electroless tin, electroless silver, electroless nickel/displacement gold, direct immersion gold (DIG) Electroplating, hot air solder leveling (HASL), etc.

介層窗243a及243b可將形成於不同層上的重佈線層242a及242b、連接墊222等電性連接至彼此，藉此在封裝200A中形成電性路徑。可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)、其合金等導電材料來作為形成介層窗243a及243b的材料。介層窗243a及243b可以導電材料完全填充，或所述導電材料亦可形成於所述介層窗的壁上。此外，介層窗243a及243b可具有此項技術中所習知的所有形狀，例如錐形形狀、圓柱形狀等。 Vias 243a and 243b may electrically connect redistribution layers 242a and 242b, connection pads 222, etc. formed on different layers to each other, thereby forming electrical paths in package 200A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof can be used as Material for forming vias 243a and 243b. Vias 243a and 243b may be completely filled with conductive material, or the conductive material may also be formed on the walls of the vias. In addition, vias 243a and 243b can have all shapes known in the art, such as conical shapes, cylindrical shapes, and the like.

第一連接構件210的重佈線層212a及212b的厚度可厚於第二連接構件240的重佈線層242a及242b的厚度。第一連接構件210可具有等於或厚於半導體晶片220的厚度的厚度，且因此形成於第一連接構件210中的重佈線層212a及212b亦可根據第一連接構件210的厚度而具有厚的厚度。相反，第二連接構件240的重佈線層242a及242b可被形成為相對薄於第一連接構件210的重佈線層212a及212b的厚度，以使第二連接構件240變薄。 The thicknesses of the redistribution layers 212 a and 212 b of the first connection member 210 may be thicker than the thicknesses of the redistribution layers 242 a and 242 b of the second connection member 240 . The first connection member 210 may have a thickness equal to or thicker than that of the semiconductor wafer 220 , and thus the redistribution layers 212 a and 212 b formed in the first connection member 210 may also have a thick thickness according to the thickness of the first connection member 210 . thickness. On the contrary, the redistribution layers 242 a and 242 b of the second connection member 240 may be formed to be relatively thinner than the thicknesses of the redistribution layers 212 a and 212 b of the first connection member 210 to thin the second connection member 240 .

可額外地配置保護層250以保護第二連接構件240不受外部的實體損害或化學損害等。保護層250可具有至少局部地暴露出第二連接構件240的重佈線層242a及242b中的重佈線層242b的開口251。開口251可暴露出重佈線層242b的一個表面的全部或暴露出重佈線層242b的一個表面的僅一部分。保護層250的材料並無特別限制。舉例而言，可使用例如感光性絕緣樹脂等感光性絕緣材料。作為另一選擇，亦可使用阻焊劑作為保護層250的材料。作為另一選擇，可使用不含有芯體材料而含有填料的絕緣樹脂，例如含有無機填料及環氧樹脂等的味之素構成膜(ABF)。 The protective layer 250 may be additionally configured to protect the second connection member 240 from external physical damage, chemical damage, or the like. The protective layer 250 may have an opening 251 exposing the redistribution layer 242b in the redistribution layers 242a and 242b of the second connection member 240 at least partially. The opening 251 may expose all of one surface of the redistribution layer 242b or expose only a part of one surface of the redistribution layer 242b. The material of the protective layer 250 is not particularly limited. For example, a photosensitive insulating material such as a photosensitive insulating resin can be used. Alternatively, solder resist can also be used as the material of the protective layer 250 . Alternatively, an insulating resin containing no core material but a filler, for example, an Ajinomoto forming film (ABF) containing an inorganic filler, an epoxy resin, or the like can be used.

可額外地配置凸塊下金屬層260以提高連接端子270的連接可靠性從而提高板層次可靠性。凸塊下金屬層260可安置於保護層250的開口251的內壁表面上及第二連接構件240的所暴露出的重佈線層242b上。凸塊下金屬層260可由此項技術中所習知的導電材料(即，使用此項技術中所習知的金屬化方法的金屬)形成。 The under-bump metal layer 260 may be additionally configured to improve the connection reliability of the connection terminals 270 to improve board-level reliability. The under bump metal layer 260 may be disposed on the inner wall surface of the opening 251 of the protection layer 250 and on the exposed redistribution layer 242 b of the second connection member 240 . The under bump metal layer 260 may be formed from conductive materials known in the art (ie, metals using metallization methods known in the art).

可額外地配置連接端子270以將扇出型半導體封裝200A實體地連接至及/或電性連接至外部。舉例而言，扇出型半導體封裝200A可藉由連接端子270而安裝於電子裝置的主板上。連接端子270可由例如焊料等導電材料形成。然而，所述材料僅為實例，且連接端子的材料並非特別地限定於此。連接端子270可為焊盤、球、引腳等。連接端子270可由多層或單層形成。在其中連接端子270由多層形成的情形中，連接端子270可含有銅柱及焊料，且在其中連接端子270由單層形成的情形中，連接端子270可含有錫-銀焊料或銅。然而，該些情形僅為實例，且連接端子270並非僅限於此。連接端子270的數目、間隔、安置形狀等均無特別限制，而是可由熟習此項技術者相依於設計而作出充分變化。舉例而言，連接端子270的數目可相依於半導體晶片220的連接墊222的數目而為數十至數千個。作為另一選擇，連接端子270的數目可大於或小於上述範圍。 The connection terminals 270 may be additionally configured to physically and/or electrically connect the fan-out semiconductor package 200A to the outside. For example, the fan-out semiconductor package 200A can be mounted on the main board of the electronic device through the connection terminals 270 . The connection terminal 270 may be formed of a conductive material such as solder. However, the material is only an example, and the material of the connection terminal is not particularly limited thereto. The connection terminals 270 may be pads, balls, pins, or the like. The connection terminal 270 may be formed of multiple layers or a single layer. In the case where the connection terminal 270 is formed of multiple layers, the connection terminal 270 may contain copper pillars and solder, and in the case where the connection terminal 270 is formed of a single layer, the connection terminal 270 may contain tin-silver solder or copper. However, these cases are only examples, and the connection terminal 270 is not limited thereto. The number, interval, placement shape, and the like of the connection terminals 270 are not particularly limited, and can be sufficiently changed depending on the design by those skilled in the art. For example, the number of the connection terminals 270 may be tens to thousands depending on the number of the connection pads 222 of the semiconductor chip 220 . Alternatively, the number of connection terminals 270 may be larger or smaller than the above range.

連接端子270中的至少一者可安置於扇出區中。所述扇出區可意指自其中安置有半導體晶片220的區偏離的區。亦即，根據另一實例的半導體封裝200A可為扇出型封裝。在扇出型封裝的情形中，可靠性可相較於扇入型封裝而言為更優異的，可實作多個輸入/輸出端子，且可易於執行3D互連。此外，由於扇出型封裝相較於球柵陣列(BGA)封裝、焊盤柵陣列(LGA)封裝等而言無需單獨的板便可安裝於電子裝置上，因此所述扇出型封裝可被製造成具有薄的厚度，且價格競爭力可為優異的。 At least one of the connection terminals 270 may be disposed in the fan-out area. The fan-out area may mean an area deviated from the area in which the semiconductor wafer 220 is disposed. That is, the semiconductor package 200A according to another example may be a fan-out package. In the case of the fan-out type package, reliability may be superior compared to the fan-in type package, multiple input/output terminals may be implemented, and 3D interconnection may be easily performed. In addition, since the fan-out package can be mounted on an electronic device without a separate board compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., the fan-out package can be Manufactured to have a thin thickness, and price competitiveness can be excellent.

儘管圖中未示出，然而視需要，多個半導體晶片(圖中未示出)可安置於第一連接構件210的貫穿孔210H中。此外，多個貫穿孔210H(圖中未示出)可形成於第一連接構件210中，且半導體晶片(圖中未示出)可安置於所述貫穿孔中的每一者中。此外，除半導體晶片之外，例如電容器、電感器等單獨的被動組件(圖中未示出)亦可在貫穿孔210H中彼此包封於一起。此外，表面安裝組件(圖中未示出)可安裝於保護層250上。 Although not shown in the drawings, a plurality of semiconductor wafers (not shown in the drawings) may be disposed in the through holes 210H of the first connection member 210 as necessary. In addition, a plurality of through holes 210H (not shown in the drawings) may be formed in the first connection member 210, and a semiconductor wafer (not shown in the drawings) may be disposed in each of the through holes. In addition, in addition to the semiconductor chip, separate passive components such as capacitors, inductors, etc. (not shown in the figures) can also be encapsulated with each other in the through holes 210H. Additionally, surface mount components (not shown in the figures) may be mounted on the protective layer 250 .

圖26A至圖26D說明圖23所示扇出型半導體封裝的示意性製造製程的實例。 26A-26D illustrate an example of a schematic fabrication process for the fan-out semiconductor package shown in FIG. 23 .

參照圖26A，首先，可製備載體膜301。可在載體膜301的一個表面或兩個表面上形成金屬膜302及303。可對金屬膜302與金屬膜303之間的黏合表面進行表面處理以便於在後續的分離製程中達成分離。作為另一選擇，可在金屬膜302與金屬膜303之間設置釋放層，藉此便於在後續的製程中達成分離。載體膜301可為此項技術中所習知的絕緣基板，且載體膜301的材料不受限制。金屬膜302及303可一般由銅(Cu)箔形成，但並非僅限於此。金屬膜302及303亦可為由另一種導電材料形成的薄膜。接下來，可使用乾膜304來執行圖案化以形成第一重佈線層212a。可使用此項技術中所習知的微影方法來執行所述圖案化。乾膜304可為由此項技術中所習知的感光性材料形成的乾膜。接著，可藉由以導電材料填充乾膜304的經圖案化空間來形成第一重佈線層212a。在此種情形中，可使用電鍍方法，且金屬膜303可充當晶 種層。所述電鍍方法可為電解電鍍方法、無電電鍍方法等。更詳言之，可使用化學氣相沈積(CVD)方法、物理氣相沈積(PVD)方法、濺鍍方法、減性方法、加性方法、半加性製程(SAP)、經修改半加性製程(MSAP)等方法來形成第一重佈線層212a，但並非僅限於此。接下來，可移除乾膜304。可藉由此項技術中所習知的例如蝕刻方法等方法來移除乾膜304。 Referring to FIG. 26A, first, a carrier film 301 may be prepared. Metal films 302 and 303 may be formed on one surface or both surfaces of the carrier film 301 . Surface treatment can be performed on the bonding surface between the metal film 302 and the metal film 303 to facilitate separation in a subsequent separation process. Alternatively, a release layer may be disposed between the metal film 302 and the metal film 303, thereby facilitating separation in subsequent processes. The carrier film 301 can be an insulating substrate known in the art, and the material of the carrier film 301 is not limited. The metal films 302 and 303 may be generally formed of copper (Cu) foil, but not limited thereto. The metal films 302 and 303 may also be thin films formed of another conductive material. Next, patterning may be performed using the dry film 304 to form the first redistribution layer 212a. The patterning can be performed using lithography methods known in the art. Dry film 304 may be a dry film formed from photosensitive materials known in the art. Next, the first redistribution layer 212a may be formed by filling the patterned spaces of the dry film 304 with a conductive material. In this case, an electroplating method can be used, and the metal film 303 can function as a crystal seed layer. The electroplating method may be an electrolytic plating method, an electroless plating method, or the like. In more detail, chemical vapor deposition (CVD) methods, physical vapor deposition (PVD) methods, sputtering methods, subtractive methods, additive methods, semi-additive processes (SAP), modified semi-additive processes may be used The first redistribution layer 212a is formed by a method such as a manufacturing process (MSAP), but not limited to this. Next, the dry film 304 can be removed. Dry film 304 may be removed by methods known in the art, such as etching methods.

參照圖26B，接下來，可在金屬膜303上形成其中至少局部地嵌置有重佈線層212a的絕緣層211。此後，可形成穿透過絕緣層211的介層窗213。此外，可在絕緣層211上形成第二重佈線層212b。可藉由使用此項技術中所習知的積層方法來對絕緣層211的前驅物進行積層並固化所積層的前驅物的方法、或使用此項技術中所習知的施加方法來施加前驅物材料並固化所施加的前驅物材料的方法等來形成絕緣層211。可藉由以下方法形成介層窗213及第二重佈線層212b：使用微影方法、機械鑽孔、雷射鑽孔、及/或類似方法在絕緣層211中形成介層窗孔；使用乾膜等來執行圖案化；以及使用電鍍方法等來填充介層窗孔及經圖案化的空間。接下來，可對載體膜301進行分層。在此種情形中，在進行分層時，金屬膜302與金屬膜303可彼此分離。在此種情形中，可使用刀片來分離金屬膜302與金屬膜303，但並非僅限於此。可使用此項技術中所習知的所有方法。同時，在一系列製程中，闡述了其中在對載體膜301進行分層之前形成第一連接構件210的情形，但所述順序並非僅限於此。亦即，在對載體膜301進行分 層之後，亦可藉由上述方法形成第一連接構件210。亦即，所述順序未必僅限於上述順序。 Referring to FIG. 26B , next, an insulating layer 211 in which the redistribution layer 212 a is at least partially embedded may be formed on the metal film 303 . Thereafter, vias 213 penetrating through the insulating layer 211 may be formed. In addition, a second redistribution layer 212b may be formed on the insulating layer 211 . The precursor can be applied by a method of laminating a precursor of the insulating layer 211 and curing the layered precursor using a lamination method known in the art, or using an application method known in the art The insulating layer 211 is formed by a method of material and curing the applied precursor material, and the like. Via 213 and second redistribution layer 212b may be formed by forming vias in insulating layer 211 using lithography, mechanical drilling, laser drilling, and/or the like; using dry film, etc. to perform patterning; and electroplating methods or the like are used to fill vias and patterned spaces. Next, the carrier film 301 can be layered. In this case, when delamination is performed, the metal film 302 and the metal film 303 may be separated from each other. In this case, a blade may be used to separate the metal film 302 and the metal film 303, but not limited thereto. All methods known in the art can be used. Meanwhile, in a series of processes, the case in which the first connection member 210 is formed before the layering of the carrier film 301 is explained, but the sequence is not limited thereto. That is, after dividing the carrier film 301 After layering, the first connecting member 210 can also be formed by the above method. That is, the order is not necessarily limited to the above-mentioned order.

參照圖26C，接下來，可藉由此項技術中所習知的蝕刻方法等來移除其餘的金屬膜303，且可在第一連接構件210中形成貫穿孔210H。可使用機械鑽孔製程及/或雷射鑽孔製程來形成貫穿孔210H。然而，貫穿孔210H並非僅限於此，而是可藉由使用研磨顆粒的噴砂方法、使用電漿的乾式蝕刻方法等來形成。在其中使用機械鑽孔製程及/或雷射鑽孔製程來形成貫穿孔210H的情形中，可執行例如高錳酸鹽方法等除汙處理，以移除貫穿孔210H中的樹脂污垢。此外，可將黏合膜305貼附至第一連接構件210的一側。可使用任何黏合膜作為黏合膜305，只要所述黏合膜可固定第一連接構件210即可。作為非限制性實例，可使用此項技術中所習知的膠帶等。此項技術中所習知的膠帶的實例可包括其黏合力被熱處理減弱的熱固性黏合膠帶、其黏合力被紫外光照射劣化的紫外光固化黏合膠帶等。接下來，可在第一連接構件210的貫穿孔210H中安置半導體晶片220。舉例而言，可藉由將半導體晶片220黏合至貫穿孔210H中的黏合膜305上而將半導體晶片220安置於貫穿孔210H中。可將半導體晶片220安置成面朝下的形式，以使連接墊222黏合至黏合膜305。 Referring to FIG. 26C , next, the remaining metal film 303 may be removed by an etching method or the like known in the art, and a through hole 210H may be formed in the first connection member 210 . The through holes 210H may be formed using a mechanical drilling process and/or a laser drilling process. However, the through hole 210H is not limited to this, and may be formed by a sandblasting method using abrasive particles, a dry etching method using plasma, or the like. In the case where the through holes 210H are formed using a mechanical drilling process and/or a laser drilling process, a desmear process such as a permanganate method may be performed to remove resin dirt in the through holes 210H. Also, the adhesive film 305 may be attached to one side of the first connection member 210 . Any adhesive film may be used as the adhesive film 305 as long as the adhesive film can fix the first connection member 210 . As non-limiting examples, tapes and the like known in the art may be used. Examples of adhesive tapes known in the art may include thermosetting adhesive tapes whose adhesive force is weakened by heat treatment, UV-curable adhesive tapes whose adhesive force is degraded by ultraviolet light irradiation, and the like. Next, the semiconductor wafer 220 may be placed in the through hole 210H of the first connection member 210 . For example, the semiconductor wafer 220 may be positioned in the through hole 210H by adhering the semiconductor wafer 220 to the adhesive film 305 in the through hole 210H. The semiconductor wafer 220 may be placed face down so that the connection pads 222 are adhered to the adhesive film 305 .

參照圖26D，接下來，可使用包封體230來對半導體晶片220進行包封。包封體230可在至少包封第一連接構件210及半導體晶片220的非主動表面的同時填充貫穿孔210H中的空間。 可藉由此項技術中所習知的方法來形成包封體230。舉例而言，可藉由對包封體230的前驅物進行積層並固化所積層的前驅物來形成包封體230。作為另一選擇，可施加包封體230以對黏合膜305上的半導體晶片220進行包封且接著固化包封體230。可藉由固化來固定半導體晶片220。可使用例如以下方法來作為對所述前驅物進行積層的方法：執行在高溫下對前驅物壓製預定時間的熱壓製方法、對所述前驅物進行減壓、且接著將所述前驅物冷卻至室溫、在冷壓製製程中冷卻所述前驅物、且接著分離作業工具等。可使用例如使用刮板施加油墨的網版印刷方法、霧化油墨以施加油墨的噴霧印刷方法等作為施加方法。接著，可對黏合膜305進行分層。分層方法並無特別限制，而是可使用此項技術中所習知的方法。舉例而言，在其中使用其黏合力被熱處理劣化的熱固性黏合膠帶或其黏合力被紫外光照射劣化的紫外光固化黏合膠帶作為黏合膜305的情形中，可在藉由對黏合膜305執行熱處理或紫外光照射來劣化黏合力之後對黏合膜305進行分層。接下來，可在自其移除黏合膜305的第一連接構件210及半導體晶片220的主動表面上形成第二連接構件240。可藉由以下步驟來形成第二連接構件240：依序地形成絕緣層241a及241b，且在形成絕緣層241a及241b之後分別在對應層中形成重佈線層242a及242b以及介層窗243a及243b。視需要，可在第二連接構件240上形成保護層250。相似地，可藉由對保護層250的前驅物進行積層並固化所積層的前驅物的方法、施加形成保護層250的材料並固化所施加的 材料的方法等來形成保護層250。可在保護層250中形成開口251，從而可至少局部地暴露出第二連接構件240的重佈線層242b，且亦可藉由此項技術中所習知的金屬化方法而在保護層250上形成凸塊下金屬層260。視需要，可在凸塊下金屬層260上形成連接端子270。形成連接端子270的方法並無特別限制，而連接端子270可相依於其結構或形狀而藉由此項技術中眾所習知的方法形成。可藉由回焊來固定連接端子270，且可藉由以下方法來提高可靠性：將連接端子270的一部分嵌置於保護層250中並將連接端子270的其他部分暴露至外部以增強固定力。 Referring to FIG. 26D , next, the encapsulant 230 may be used to encapsulate the semiconductor wafer 220 . The encapsulation body 230 may fill the space in the through hole 210H while encapsulating at least the first connection member 210 and the inactive surface of the semiconductor wafer 220 . The encapsulant 230 may be formed by methods known in the art. For example, the encapsulation body 230 may be formed by laminating the precursors of the encapsulating body 230 and curing the layered precursors. Alternatively, encapsulant 230 may be applied to encapsulate semiconductor wafer 220 on adhesive film 305 and then encapsulant 230 cured. The semiconductor wafer 220 may be fixed by curing. As a method of laminating the precursor, for example, a method of performing a hot pressing method of pressing the precursor at a high temperature for a predetermined time, decompressing the precursor, and then cooling the precursor to a temperature, can be used, for example. room temperature, cooling the precursor in a cold pressing process, and then separating the tool, etc. As the application method, for example, a screen printing method in which ink is applied using a doctor blade, a spray printing method in which ink is atomized to apply ink, and the like can be used. Next, the adhesive film 305 can be delaminated. The layering method is not particularly limited, and methods known in the art can be used. For example, in the case where a thermosetting adhesive tape whose adhesive force is deteriorated by heat treatment or an ultraviolet light-curing adhesive tape whose adhesive force is deteriorated by ultraviolet light irradiation is used as the adhesive film 305, the adhesive film 305 can be processed by performing heat treatment on the adhesive film 305. Or the adhesive film 305 is delaminated after being irradiated with ultraviolet light to degrade the adhesive force. Next, a second connection member 240 may be formed on the active surface of the first connection member 210 and the semiconductor wafer 220 from which the adhesive film 305 was removed. The second connection member 240 may be formed by sequentially forming insulating layers 241a and 241b, and forming redistribution layers 242a and 242b and vias 243a and 243a in the corresponding layers after forming the insulating layers 241a and 241b, respectively. 243b. As necessary, a protective layer 250 may be formed on the second connection member 240 . Similarly, the materials for forming the protective layer 250 can be applied and cured by the method of laminating the precursors of the protective layer 250 and curing the layered precursors. The protective layer 250 is formed by a material method or the like. Openings 251 may be formed in the protective layer 250 so that the redistribution layer 242b of the second connection member 240 may be exposed at least partially, and may also be on the protective layer 250 by metallization methods known in the art An under bump metal layer 260 is formed. Connection terminals 270 may be formed on the under bump metal layer 260 as needed. The method of forming the connection terminal 270 is not particularly limited, and the connection terminal 270 can be formed by a method well known in the art depending on its structure or shape. The connection terminal 270 can be fixed by reflow, and reliability can be improved by embedding a part of the connection terminal 270 in the protective layer 250 and exposing the other part of the connection terminal 270 to the outside to enhance the fixing force .

同時，為便於大量生產，在一系列製程中，在製備出具有大尺寸的載體膜301之後，可藉由如上所述的製程來製造多個扇出型半導體封裝200A。接著可藉由切割而將所述多個扇出型半導體封裝200A分割成獨立的單位扇出型半導體封裝200A。在此種情形中，生產率可為優異的。 Meanwhile, in order to facilitate mass production, in a series of processes, after the carrier film 301 with a large size is prepared, a plurality of fan-out semiconductor packages 200A can be manufactured by the above-mentioned process. The plurality of fan-out semiconductor packages 200A may then be divided into individual unit fan-out semiconductor packages 200A by dicing. In this case, the productivity can be excellent.

圖27是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 27 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖28是沿圖27所示的線VI-VI'截取的扇出型半導體封裝的剖切平面圖。 FIG. 28 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line VI-VI' shown in FIG. 27 .

參照圖27及圖28，在根據經修改實例的扇出型半導體封裝200B中，金屬層214可安置於第一連接構件210的貫穿孔210H的內壁表面上。金屬層214可用於有效地分散產生於半導體晶片220中的熱。此外，金屬層214亦可用於遮蔽電磁波。此外，金屬 層214可連接至第一連接構件210的其他重佈線層212a及212b的接地圖案以藉此被用作接地。金屬層214可安置於整個壁表面上，或以特定形狀進行圖案化以藉此進行安置。金屬層214可含有如上所述的導電材料，即，金屬材料。 27 and 28 , in the fan-out type semiconductor package 200B according to the modified example, the metal layer 214 may be disposed on the inner wall surface of the through hole 210H of the first connection member 210 . The metal layer 214 can be used to effectively disperse the heat generated in the semiconductor wafer 220 . In addition, the metal layer 214 can also be used for shielding electromagnetic waves. In addition, metal The layer 214 may be connected to the ground patterns of the other redistribution layers 212a and 212b of the first connection member 210 to thereby be used as ground. The metal layer 214 may be disposed over the entire wall surface, or may be patterned in a specific shape to thereby be disposed. The metal layer 214 may contain a conductive material as described above, ie, a metallic material.

由於扇出型半導體封裝200B的其他配置或製造方法與在根據另一實例的扇出型半導體封裝200A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 200B are the same as those set forth in the fan-out type semiconductor package 200A according to another example, detailed descriptions thereof will not be repeated.

圖29是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 FIG. 29 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

圖30是沿圖29所示的線VII-VII'截取的扇出型半導體封裝的剖切平面圖。 FIG. 30 is a cross-sectional plan view of the fan-out type semiconductor package taken along the line VII-VII' shown in FIG. 29 .

參照圖29及圖30，在根據經修改實例的扇出型半導體封裝200C中，單獨的第一被動組件224可安置於貫穿孔210H中。此外，單獨的第二被動組件226可安置於保護層250的表面上。第一被動組件224可為例如多層陶瓷電容器(MLCC)等高電容電容器，但並非僅限於此。第二被動組件226可為例如矽系電容器等低電容電容器，但並非僅限於此。第一被動組件224及第二被動組件226可連接至相同的電源線以藉此經由所述電源線而電性連接至半導體晶片220，進而使得電源供應效率可得以提高。 Referring to FIGS. 29 and 30 , in the fan-out semiconductor package 200C according to the modified example, the individual first passive components 224 may be disposed in the through holes 210H. Additionally, a separate second passive component 226 may be disposed on the surface of the protective layer 250 . The first passive component 224 may be a high capacitance capacitor such as a multilayer ceramic capacitor (MLCC), but is not limited thereto. The second passive component 226 can be a low-capacitance capacitor such as a silicon-based capacitor, but is not limited thereto. The first passive component 224 and the second passive component 226 can be connected to the same power line so as to be electrically connected to the semiconductor chip 220 through the power line, so that the power supply efficiency can be improved.

由於扇出型半導體封裝200C的其他配置或製造方法與在根據另一實例的扇出型半導體封裝200A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 200C are the same as those set forth in the fan-out type semiconductor package 200A according to another example, detailed descriptions thereof will not be repeated.

圖31是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 31 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

參照圖31，在根據經修改實例的扇出型半導體封裝200D中，經由穿透過包封體230的介層窗283而與第一連接構件210的第二重佈線層212b電性連接的重佈線層282可安置於包封體230上。此外，具有局部地暴露出重佈線層282的開口(未由參考編號指示)的保護層280可安置於包封體230上。單獨的表面安裝組件281及286可安置於所述開口(未由參考編號指示)上以藉此電性連接至重佈線層282。表面安裝組件281及286可相依於表面安裝組件的類型而直接連接至重佈線層282或藉由焊接(圖中未示出)等而連接至重佈線層282。作為另一選擇，表面安裝組件281及286可藉由凸塊下金屬層284及連接端子285而連接至重佈線層282。表面安裝組件281及286可為各種類型的被動組件或各種類型的積體電路。 Referring to FIG. 31 , in the fan-out semiconductor package 200D according to the modified example, redistribution electrically connected to the second redistribution layer 212 b of the first connection member 210 via the via 283 penetrating through the encapsulation body 230 Layer 282 may be disposed on envelope 230 . In addition, a protective layer 280 having an opening (not indicated by a reference number) that partially exposes the redistribution layer 282 may be disposed on the encapsulation body 230 . Individual surface mount components 281 and 286 may be disposed on the openings (not indicated by reference numbers) to thereby electrically connect to the redistribution layer 282 . The surface mount components 281 and 286 may be directly connected to the redistribution layer 282 or connected to the redistribution layer 282 by soldering (not shown) or the like, depending on the type of the surface mount components. Alternatively, the surface mount components 281 and 286 may be connected to the redistribution layer 282 through the under bump metal layer 284 and the connection terminals 285 . Surface mount components 281 and 286 may be various types of passive components or various types of integrated circuits.

由於扇出型半導體封裝200D的其他配置或製造方法與在根據另一實例的扇出型半導體封裝200A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out semiconductor package 200D are the same as those set forth in the fan-out semiconductor package 200A according to another example, detailed descriptions thereof will not be repeated.

圖32是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 32 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

參照圖32，在根據經修改實例的扇出型半導體封裝200E中，記憶體晶片封裝287可堆疊於包封體230上。記憶體晶片封裝287可藉由凸塊下金屬層284及形成於凸塊下金屬層284上的 連接端子285而電性連接至第一連接構件210的第二重佈線層212b，凸塊下金屬層284形成於包封體230的局部地暴露出第一連接構件210的第二重佈線層212b的開口231上。記憶體晶片封裝287可包括例如揮發性記憶體(例如，動態隨機存取記憶體(DRAM))、非揮發性記憶體(例如，唯讀記憶體(ROM))、快閃記憶體等記憶體晶片。 Referring to FIG. 32 , in the fan-out type semiconductor package 200E according to the modified example, the memory chip package 287 may be stacked on the encapsulation body 230 . The memory chip package 287 can be formed by the under bump metal layer 284 and the The connection terminal 285 is electrically connected to the second redistribution layer 212b of the first connection member 210, and the under bump metal layer 284 is formed on the encapsulation body 230 to partially expose the second redistribution layer 212b of the first connection member 210. on the opening 231. The memory chip package 287 may include memory such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (ROM)), flash memory, etc. wafer.

由於扇出型半導體封裝200E的其他配置或製造方法與在根據另一實例的扇出型半導體封裝200A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out type semiconductor package 200E are the same as those set forth in the fan-out type semiconductor package 200A according to another example, detailed descriptions thereof will not be repeated.

圖33是示意性地說明圖23所示扇出型半導體封裝的經修改實例的剖視圖。 33 is a cross-sectional view schematically illustrating a modified example of the fan-out type semiconductor package shown in FIG. 23 .

參照圖33，在根據經修改實例的扇出型半導體封裝200F中，第一重佈線層212a可凹進絕緣層中，且因此絕緣層211的下表面與第一重佈線層212a的下表面之間可形成台階部分。如此一來，可防止在形成包封體230時因形成包封體230的材料溢出而污染第一重佈線層212a。同時，由於如上所述第一重佈線層212a凹進絕緣層211中，因此第一連接構件210的第一重佈線層212a的下表面可定位成高於半導體晶片220的連接墊222的下表面。此外，第二連接構件240的重佈線層242a與第一連接構件210的第一重佈線層212a之間的距離可大於第二連接構件240的重佈線層242a與半導體晶片220的連接墊222之間的距離。 33, in the fan-out type semiconductor package 200F according to the modified example, the first redistribution layer 212a may be recessed into the insulating layer, and thus the lower surface of the insulating layer 211 and the lower surface of the first redistribution layer 212a are between A stepped portion can be formed between. In this way, when the encapsulation body 230 is formed, the first redistribution layer 212a can be prevented from contaminating the first redistribution layer 212a due to overflow of the material for forming the encapsulation body 230 . Meanwhile, since the first redistribution layer 212a is recessed into the insulating layer 211 as described above, the lower surface of the first redistribution layer 212a of the first connection member 210 may be positioned higher than the lower surface of the connection pad 222 of the semiconductor wafer 220 . In addition, the distance between the redistribution layer 242a of the second connection member 240 and the first redistribution layer 212a of the first connection member 210 may be greater than the distance between the redistribution layer 242a of the second connection member 240 and the connection pad 222 of the semiconductor wafer 220 distance between.

由於扇出型半導體封裝200F的其他配置或製造方法與在 根據另一實例的扇出型半導體封裝200A中所闡述的配置或製造方法相同，因此將不再對其予以贅述。 Since other configurations or manufacturing methods of the fan-out semiconductor package 200F are The configuration or manufacturing method described in the fan-out type semiconductor package 200A according to another example is the same, and thus will not be repeated.

圖34是示意性地說明其中第二連接構件的絕緣距離不均勻的扇出型半導體封裝的實例的剖視圖 34 is a cross-sectional view schematically illustrating an example of a fan-out type semiconductor package in which the insulating distance of the second connection member is not uniform

參照圖34，相似地，其中第二連接構件的絕緣距離不均勻的扇出型半導體封裝200G可包括第一連接構件210'、半導體晶片220'、包封體230'、第二連接構件240'、保護層250'及連接端子270'。第一連接構件210'可具有貫穿孔210H'，並包括絕緣層211'、形成於絕緣層211'的兩個表面上的重佈線層212a'及212b'、以及穿透過絕緣層211'的介層窗213'。半導體晶片220'可包括主體221'、連接墊222'及保護膜223'。第二連接構件240'可包括絕緣層241a'及241b'、重佈線層242a'及242b'、以及介層窗243a'及243b'。形成於第一連接構件210'的下表面上的重佈線層212a'可嵌置於第二連接構件240'的絕緣材料中，進而使得可因與重佈線層212a'的厚度對應的台階部分H而導致絕緣距離不均勻。此外，由於所述扇出型半導體封裝不具有單獨的凸塊下金屬層，因此可能使得板層次可靠性劣化。 Referring to FIG. 34 , similarly, the fan-out semiconductor package 200G in which the insulation distances of the second connection members are not uniform may include the first connection member 210 ′, the semiconductor wafer 220 ′, the encapsulation body 230 ′, the second connection member 240 ′ , a protective layer 250' and a connection terminal 270'. The first connection member 210' may have a through hole 210H', and include an insulating layer 211', redistribution layers 212a' and 212b' formed on both surfaces of the insulating layer 211', and a dielectric penetrating through the insulating layer 211'. Floor window 213'. The semiconductor wafer 220' may include a body 221', connection pads 222' and a protective film 223'. The second connection member 240' may include insulating layers 241a' and 241b', redistribution layers 242a' and 242b', and vias 243a' and 243b'. The redistribution layer 212a' formed on the lower surface of the first connection member 210' may be embedded in the insulating material of the second connection member 240', so that the step portion H corresponding to the thickness of the redistribution layer 212a' As a result, the insulation distance is not uniform. Furthermore, since the fan-out type semiconductor package does not have a separate under bump metal layer, board level reliability may be degraded.

如以上所述，根據本發明中的示例性實施例，可提供扇出型半導體封裝及其製造方法，所述扇出型半導體封裝能夠在解決所述扇出型半導體封裝的翹曲問題的同時提供較寬的路由區域，且具有便於設計第二連接構件的高密度配線的創新型結構。 As described above, according to the exemplary embodiments in the present invention, a fan-out type semiconductor package capable of solving the warpage problem of the fan-out type semiconductor package and a method for manufacturing the same can be provided Provides a wider routing area and has an innovative structure that facilitates the design of high-density wiring of the second connecting member.

2100‧‧‧扇出型半導體封裝 2100‧‧‧Fan-Out Semiconductor Package

2120‧‧‧半導體晶片 2120‧‧‧Semiconductor Chips

2121‧‧‧主體 2121‧‧‧Subject

2122‧‧‧連接墊 2122‧‧‧Connection pad

2130‧‧‧包封體 2130‧‧‧Encapsulation

2140‧‧‧連接構件 2140‧‧‧Connecting components

2141‧‧‧絕緣層 2141‧‧‧Insulating layer

2142‧‧‧重佈線層 2142‧‧‧Redistribution layer

2143‧‧‧介層窗 2143‧‧‧Via

2150‧‧‧保護層 2150‧‧‧Protective layer

2160‧‧‧凸塊下金屬層 2160‧‧‧Under bump metallization

2170‧‧‧焊料球 2170‧‧‧Solder Ball

Claims (13)

一種扇出型半導體封裝，包括：第一連接構件，具有貫穿孔；半導體晶片，安置於所述第一連接構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊；包封體，至少局部地包封所述第一連接構件及所述半導體晶片的所述非主動表面；以及第二連接構件，包括：絕緣層，安置於所述第一連接構件及所述半導體晶片的所述主動表面下方；以及重佈線層，安置於所述絕緣層的下表面上且電性連接至所述連接墊，其中所述第一連接構件包括：第一絕緣層，安置於所述第二連接構件的所述絕緣層的上表面上，同時接觸所述第二連接構件的所述絕緣層；第一重佈線層，嵌置於所述第一絕緣層的下側中，同時接觸所述第二連接構件的所述絕緣層；第二重佈線層，安置於所述第一絕緣層的上側上，所述第一絕緣層的上側與其中嵌置有所述第一重佈線層的所述第一絕緣層的下側相對；第二絕緣層，安置於所述第一絕緣層上並覆蓋所述第二重佈線層；以及第三重佈線層，安置於所述第二絕緣層上，所述第一重佈線層、所述第二重佈線層及所述第三重佈線層電性連接至所述連接墊，其中所述第二重佈線層突出設置於嵌置有所述第一重佈線層 的所述第一絕緣層的上表面上，其中所述第二重佈線層的下表面實體地連接所述第一絕緣層的上表面，其中所述第二重佈線層分別經由第一導電介層窗及第二導電介層窗而電性連接至所述第一重佈線層及所述第三重佈線層，所述第一導電介層窗及所述第二導電介層窗分別穿透過所述第一絕緣層及所述第二絕緣層，其中所述第一絕緣層的下表面與所述第一重佈線層的下表面之間形成有具有台階的凹陷部分，其中所述凹陷部分的下表面的寬度與所述第一重佈線層的所述下表面的寬度實質上相同，其中所述第一重佈線層至所述第三重佈線層中的每一者均包括接地圖案，其中所述第一重佈線層的厚度、所述第二重佈線層的厚度及所述第三重佈線層的厚度均厚於所述第二連接構件的所述重佈線層的厚度。 A fan-out semiconductor package, comprising: a first connection member having a through hole; a semiconductor wafer disposed in the through hole of the first connection member and having an active surface and a non-active surface opposite to the active surface , a connection pad is arranged on the active surface; an encapsulation body at least partially encapsulates the first connection member and the non-active surface of the semiconductor wafer; and a second connection member, comprising: an insulating layer, a redistribution layer disposed on the lower surface of the insulating layer and electrically connected to the connection pads, wherein the first connecting member and the active surface of the semiconductor wafer are disposed below; The connecting member includes: a first insulating layer disposed on the upper surface of the insulating layer of the second connecting member while contacting the insulating layer of the second connecting member; a first redistribution layer embedded in In the lower side of the first insulating layer, the insulating layer of the second connecting member is simultaneously contacted; the second redistribution layer is arranged on the upper side of the first insulating layer, and the second insulating layer is placed on the upper side of the first insulating layer. an upper side opposite to a lower side of the first insulating layer in which the first redistribution layer is embedded; a second insulating layer disposed on the first insulating layer and covering the second redistribution layer; and A third redistribution layer is disposed on the second insulating layer, the first redistribution layer, the second redistribution layer and the third redistribution layer are electrically connected to the connection pads, wherein all the The second redistribution layer is protrudingly disposed on the embedded first redistribution layer on the upper surface of the first insulating layer, wherein the lower surface of the second redistribution layer is physically connected to the upper surface of the first insulating layer, wherein the second redistribution layer is respectively through the first conductive medium A layer window and a second conductive layer window are electrically connected to the first redistribution layer and the third redistribution layer, and the first conductive layer window and the second conductive layer window respectively penetrate through The first insulating layer and the second insulating layer, wherein a recessed portion having a step is formed between the lower surface of the first insulating layer and the lower surface of the first redistribution layer, wherein the recessed portion The width of the lower surface of the first redistribution layer is substantially the same as the width of the lower surface of the first redistribution layer, wherein each of the first redistribution layer to the third redistribution layer includes a ground pattern, The thickness of the first redistribution layer, the thickness of the second redistribution layer and the thickness of the third redistribution layer are all thicker than the thickness of the redistribution layer of the second connection member. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一連接構件更包括安置於所述第二絕緣層上並覆蓋所述第三重佈線層的第三絕緣層、以及安置於所述第三絕緣層上的第四重佈線層，所述第四重佈線層電性連接至所述連接墊。 The fan-out semiconductor package of claim 1, wherein the first connection member further comprises a third insulating layer disposed on the second insulating layer and covering the third redistribution layer, and a fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第二連接構件的重佈線層與所述第一重佈線層之間的距離大於所述第二連接構件的重佈線層與所述連接墊之間的距離。 The fan-out semiconductor package of claim 1, wherein a distance between the redistribution layer of the second connection member and the first redistribution layer is greater than the redistribution layer of the second connection member distance from the connection pads. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括：保護層，安置於所述第二連接構件上且具有開口，所述開口局部地暴露出所述第二連接構件的重佈線層；凸塊下金屬層，安置於所述開口上且連接至所述第二連接構件的暴露的重佈線層；以及連接端子，安置於所述凸塊下金屬層上且電性連接至所述連接墊。 The fan-out semiconductor package of claim 1, further comprising: a protective layer disposed on the second connecting member and having an opening, the opening partially exposing the weight of the second connecting member a wiring layer; an under-bump metal layer disposed on the opening and connected to the exposed redistribution layer of the second connection member; and a connection terminal disposed on the under-bump metal layer and electrically connected to the connection pad. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述包封體具有局部地暴露出所述第三重佈線層的開口。 The fan-out semiconductor package of claim 1, wherein the encapsulation body has an opening partially exposing the third redistribution layer. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括：第五重佈線層，安置於所述包封體上且電性連接至所述第三重佈線層；以及保護層，安置於所述包封體上且具有開口，所述開口局部地暴露出安置於所述包封體上的所述第五重佈線層。 The fan-out semiconductor package according to item 1 of the scope of the application, further comprising: a fifth redistribution layer disposed on the encapsulation body and electrically connected to the third redistribution layer; and a protection layer, It is disposed on the encapsulation body and has an opening, and the opening partially exposes the fifth redistribution layer disposed on the encapsulation body. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一重佈線層的下表面被定位成高於所述連接墊的下表面。 The fan-out semiconductor package of claim 1, wherein a lower surface of the first redistribution layer is positioned higher than a lower surface of the connection pad. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第二重佈線層定位於所述半導體晶片的所述主動表面與所述非主動表面之間。 The fan-out semiconductor package of claim 1, wherein the second redistribution layer is positioned between the active surface and the non-active surface of the semiconductor die. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述包封體含有芯體材料、無機填料及絕緣樹脂。 The fan-out semiconductor package according to claim 1, wherein the encapsulation body contains a core material, an inorganic filler and an insulating resin. 一種扇出型半導體封裝的製造方法，所述製造方法包括：製備載體膜；在所述載體膜上形成第一連接構件；移除所述載體膜；形成穿透過所述第一連接構件的貫穿孔；在所述貫穿孔中安置半導體晶片，所述半導體晶片具有主動表面及與所述主動表面相對的非主動表面，在所述主動表面上安置有連接墊；使用包封體至少局部地包封所述第一連接構件及所述半導體晶片的所述非主動表面；以及在所述第一連接構件及所述半導體晶片的所述主動表面上形成第二連接構件，所述第二連接構件包括電性連接至所述連接墊的重佈線層，其中形成所述第一連接構件包括：在所述載體膜上形成第一重佈線層，在所述載體膜上形成用於嵌置所述第一重佈線層的第一絕緣層，以及在所述第一絕緣層的與其中嵌置有所述第一重佈 線層的一側相對的另一側上形成第二重佈線層，所述第一重佈線層與所述第二重佈線層電性連接至所述連接墊。 A method of manufacturing a fan-out semiconductor package, the manufacturing method comprising: preparing a carrier film; forming a first connection member on the carrier film; removing the carrier film; forming a through-hole penetrating the first connection member a hole; placing a semiconductor wafer in the through hole, the semiconductor wafer having an active surface and an inactive surface opposite the active surface, on which a connection pad is placed; encapsulating at least partially with an encapsulant sealing the first connection member and the inactive surface of the semiconductor wafer; and forming a second connection member on the first connection member and the active surface of the semiconductor wafer, the second connection member including a redistribution layer electrically connected to the connection pad, wherein forming the first connection member includes forming a first redistribution layer on the carrier film for embedding the The first insulating layer of the first redistribution layer, and the first redistribution layer embedded in the first insulating layer and the first redistribution layer A second redistribution layer is formed on the other side opposite to one side of the wire layer, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pads. 如申請專利範圍第10項所述的扇出型半導體封裝的製造方法，其中形成所述第一連接構件更包括：在所述第一絕緣層上形成覆蓋所述第二重佈線層的第二絕緣層，以及在所述第二絕緣層上形成第三重佈線層，所述第三重佈線層電性連接至所述連接墊。 The method for manufacturing a fan-out semiconductor package according to claim 10, wherein forming the first connection member further comprises: forming a second redistribution layer covering the second redistribution layer on the first insulating layer an insulating layer, and a third redistribution layer is formed on the second insulating layer, the third redistribution layer is electrically connected to the connection pad. 如申請專利範圍第11項所述的扇出型半導體封裝的製造方法，更包括使所述包封體的一部分開口，以暴露出所述第三重佈線層的一部分。 The method for manufacturing a fan-out semiconductor package as claimed in claim 11, further comprising opening a portion of the encapsulation body to expose a portion of the third redistribution layer. 如申請專利範圍第11項所述的扇出型半導體封裝的製造方法，更包括：在所述包封體上形成電性連接至所述第三重佈線層的重佈線層；在所述包封體上形成保護層，所述保護層覆蓋形成於所述包封體上的重佈線層；以及使所述保護層的一部分開口，以暴露出形成於所述包封體上的重佈線層的一部分。 The method for manufacturing a fan-out semiconductor package according to the claim 11, further comprising: forming a redistribution layer electrically connected to the third redistribution layer on the package body; forming a protective layer on the encapsulation body, the protective layer covering the redistribution layer formed on the encapsulation body; and opening a part of the protective layer to expose the redistribution layer formed on the encapsulation body a part of.
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