TWI758821B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI758821B TWI758821B TW109127523A TW109127523A TWI758821B TW I758821 B TWI758821 B TW I758821B TW 109127523 A TW109127523 A TW 109127523A TW 109127523 A TW109127523 A TW 109127523A TW I758821 B TWI758821 B TW I758821B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 167
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 16
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 70
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 70
- 238000000034 method Methods 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 76
- 238000009413 insulation Methods 0.000 description 23
- 238000000926 separation method Methods 0.000 description 22
- 230000004048 modification Effects 0.000 description 17
- 238000012986 modification Methods 0.000 description 17
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
實施方式係關於一種半導體裝置及其製造方法。
本實施方式之半導體裝置具備半導體區域、絕緣部、第1區域(源極)、第2區域(汲極)、控制電極(閘極電極)、第1電極、及第1絕緣膜。半導體區域包括第1表面,具有第1導電型。絕緣部形成於半導體區域,具有較第1表面沿半導體區域之深度方向後退之第2表面。第1區域位於絕緣部之第1部分與絕緣部之第2部分之間且設於半導體區域上。第2區域位於第1部分與第2部分之間,與第1區域分開,且設於半導體區域上。控制電極設於第1表面上方,位於第1區域與第2區域之間。第1電極設於第1區域之上,與第1區域相接。第1絕緣膜設於第1表面與第2表面之間的階差部之半導體區域之側壁。第1絕緣膜為包含鉿之絕緣膜。
Description
此處所記載之實施方式係關於一種半導體裝置及其製造方法。
近年來,於LSI(Large Scale Integration,大規模積體電路)技術中,隨著積體化及元件動作之高速化,閘極長度之短距離化、源極區域及汲極區域之接合深度之淺化不斷發展。又,例如NAND(Not And,反及)型快閃記憶體等記憶胞之驅動用電晶體尺寸於決定記憶胞之半間距(HP:Half Pitch)之方面成為重要因素。
作為縮小電晶體尺寸之方法之一,有效的是將活性區域縮小化,將源極接點與絕緣分離區域之間之距離縮小化。然而,隨著源極接點與絕緣分離區域之間之距離之縮小化,源極接點搭於絕緣分離區域,源極接點與源極擴散接面之間之距離會靠近,因此導致接合洩漏上升,縮小化變得困難。
本發明之實施方式提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置及其製造方法。
實施方式之半導體裝置具備半導體區域、絕緣部、第1區域、第2區域、控制電極、第1電極、及第1絕緣膜。半導體區域包括第1表面,具有第1導電型。絕緣部形成於半導體區域,具有較第1表面沿半導
體區域之深度方向後退之第2表面。第1區域位於絕緣部之第1部分與絕緣部之第2部分之間且設於半導體區域上。第2區域位於第1部分與第2部分之間,與第1區域分開,且設於半導體區域上。控制電極設於第1表面上方,位於第1區域與第2區域之間。第1電極設於第1區域之上,與第1區域相接。第1絕緣膜設於第1表面與第2表面之間的階差部之半導體區域之側壁。第1絕緣膜為包含鉿之絕緣膜。
1:半導體裝置
1A:半導體裝置
2A:半導體裝置
10:半導體區域
12:絕緣分離區域(絕緣部)
14:控制電極(閘極電極)
16:氧化矽膜
18:氮化矽膜
20:閘極氧化膜
22:第1區域(源極)
23:第2區域(汲極)
24:源極擴展區域
25:汲極擴展區域
26:絕緣膜
28:層間絕緣膜
30:襯墊絕緣膜
32S:源極電極
32D:汲極電極
34G:閘極矽化物區域
34S:源極矽化物區域
34D:汲極矽化物區域
261:側壁絕緣膜
262:側壁絕緣膜(第1絕緣膜)
AA:活性區域
CD:汲極接點
CHD:汲極接觸孔
CHS:源極接觸孔
CS:第1電極(源極接點)
D:汲極區域
G:閘極電極
GC:閘極接點
S:源極區域
SF1:第1表面
SF2:第2表面
STI:絕緣分離區域
圖1A係實施方式之半導體裝置之模式性平面圖案構成圖。
圖1B係將活性區域縮小化的實施方式之半導體裝置之模式性平面圖案構成圖。
圖1C係進行縮小化直至源極接點及汲極接點之端部與絕緣分離區域相接的實施方式之半導體裝置之模式性平面圖案構成圖。
圖1D係進行縮小化直至源極接點及汲極接點之端部搭於絕緣分離區域的實施方式之變化例之半導體裝置之模式性平面圖案構成圖。
圖2A~圖2F係第1實施方式之半導體裝置之製造方法之一步驟且為沿圖1C之I-I線之模式性剖面構造圖。
圖2G及圖2H係第1實施方式之變化例之半導體裝置之製造方法之一步驟且為沿圖1D之II-II線之模式性剖面構造圖。
圖3A~圖3G係第2實施方式之半導體裝置之製造方法之一步驟且為沿圖1C之I-I線之模式性剖面構造圖。
圖3H~圖3J係第2實施方式之變化例之半導體裝置之製造方法之一步驟且為沿圖1D之II-II線之模式性剖面構造圖。
其次,參照圖式對實施方式進行說明。於以下所說明之圖式之記載中,對相同或類似之部分標註相同或類似之符號。但是,圖式為模式性者,應注意各構成零件之厚度與平面尺寸之關係等與實際中不同。故而,具體厚度或尺寸應參照以下之說明進行判斷。又,圖式彼此間當然亦包含相互之尺寸之關係或比率不同之部分。
又,以下所示之實施方式中例示用於將技術思想具體化之裝置或方法,但並不特定各構成零件之材質、形狀、構造、配置等。該實施方式於申請專利範圍內可進行各種變更。
以下說明之實施方式之半導體裝置係以金屬-氧化膜-半導體場效電晶體(MOSFET:Metal Oxide Semiconductor Field Effect Transistor)為對象。又,於以下說明之實施方式中,有時亦將絕緣分離區域簡單記載為STI(淺溝隔離(Shallow Trench Isolation))。
[第1實施方式]
(平面圖案構成)
第1實施方式之半導體裝置1之模式性平面圖案構成如圖1A~圖1C所示般配置於X-Y平面上而表示。第1實施方式之變化例之半導體裝置1之模式性平面圖案構成如圖1D所示般配置於X-Y平面上而表示。
如圖1A所示,第1實施方式之半導體裝置1具備源極區域S、汲極區域D、及被源極區域S及汲極區域D夾著而配置之閘極電極G。活性區域AA具備源極區域S及汲極區域D、及被源極區域S及汲極區域D夾著而配置之通道區域,由絕緣分離區域包圍。絕緣分離區域例如由淺溝隔離(STI:Shallow Trench Isolation)形成。如圖1A所示,源極區域S之X
方向之尺寸由S1表示,Y方向之尺寸由W1表示,汲極區域D之X方向之尺寸由D1表示,Y方向之尺寸由W1表示。閘極電極G之X方向之尺寸由L1表示。W1、L1分別相當於實施方式之半導體裝置之通道寬度、通道長度。於源極區域S上配置有源極接點CS,於汲極區域D上配置有汲極接點CD。於沿Y方向延伸之閘極電極G上配置有閘極接點GC。源極接點CS之尺寸於X方向上由CI表示,於Y方向上由C1表示。汲極接點CD及閘極接點GC之尺寸亦與源極接點CS相同。
如圖1B所示,表示將活性區域AA於X方向上縮小化的第1實施方式之半導體裝置1之模式性平面圖案構成例。如圖1B所示,源極區域S之X方向之尺寸由S2表示,Y方向之尺寸由W1表示,汲極區域D之X方向之尺寸由D2表示,Y方向之尺寸由W1表示。此處,S2<S1成立,D2<D1成立。
閘極電極G之X方向之尺寸由L2表示。W1、L2分別相當於通道寬度、通道長度。於源極區域S上配置有源極接點CS,於汲極區域D上配置有汲極接點CD。於沿Y方向延伸之閘極電極G上配置有閘極接點GC。源極接點CS之尺寸於X方向上由CI表示,於Y方向上由C1表示,汲極接點CD及閘極接點GC之尺寸亦與源極接點CS相同。
如圖1C所示,表示進而將活性區域AA於X方向上縮小化,且縮小化至源極接點CS及汲極接點CD之端部與絕緣分離區域STI相接的第1實施方式之半導體裝置1之模式性平面圖案構成例。如圖1C所示,源極區域S之X方向之尺寸由S3表示,Y方向之尺寸由W1表示,汲極區域D之X方向之尺寸由D3表示,Y方向之尺寸由W1表示。此處,S3<S2<S1成立,D3<D2<D1成立。閘極電極G之X方向之尺寸由L3表示。
W1、L3分別相當於通道寬度、通道長度。於源極區域S上配置有端部與絕緣分離區域STI接觸之源極接點CS,於汲極區域D上配置有端部與絕緣分離區域STI接觸之汲極接點CD。於沿Y方向延伸之閘極電極G上配置有閘極接點GC。源極接點CS之尺寸於X方向上由CI表示,於Y方向上由C1表示,汲極接點CD及閘極接點GC之尺寸亦與源極接點CS相同。
如圖1D所示,表示進而將活性區域AA縮小化,且縮小化至源極接點CS及汲極接點CD之端部搭於絕緣分離區域STI的第1實施方式之變化例之半導體裝置1A之平面圖案構成例。如圖1D所示,源極區域S之X方向之尺寸由S4表示,Y方向之尺寸由W1表示,汲極區域D之X方向之尺寸由D4表示,Y方向之尺寸由W1表示。此處,S4<S3<S2<S1成立,D4<D3<D2<D1成立。閘極電極G之X方向之尺寸由L4表示。W1、L4分別相當於通道寬度、通道長度。於源極區域S上配置有端部接於絕緣分離區域STI之源極接點CS,於汲極區域D上配置有端部接於絕緣分離區域STI之汲極接點CD。於沿Y方向延伸之閘極電極G上配置有閘極接點GC。源極接點CS之尺寸於X方向上由CI表示,於Y方向上由C1表示,汲極接點CD之尺寸亦與源極接點CS及閘極接點GC之尺寸相同。再者,絕緣分離區域(STI)具有特定之寬度,但於圖1A~圖1D中,該方面被省略。又,圖1A~圖1D係以第1實施方式為對象進行了說明,但亦同樣適用於第2實施方式。
(洩漏增大之機制)
作為縮小電晶體尺寸之方法之一,如圖1A~圖1D所示,有效的是將活性區域AA縮小化,縮短源極接點CS及汲極接點CD與絕緣分離區域STI間之距離。然而,隨著源極接點CS及汲極接點CD與絕緣分離區域STI之
間之距離之縮小化,源極接點CS及汲極接點CD搭於絕緣分離區域STI後,源極接點與源極擴散pn接面之間之距離會靠近,因此導致接合洩漏上升。由於源極擴散層與半導體區域間之pn接面與源極接點CS界面靠近,因此於汲極、源極間施加偏壓電壓時,空乏層於通道內擴展時之源極擴散層與p型半導體區域間之pn接面之漏電流增大。若源極接點CS搭於絕緣分離區域STI,則當源極接點CS打開時會露出p型半導體區域(活性區域AA)端部。此處由於置入源極電極,因此源極接點CS與活性區域AA之端部之源極擴散層之距離縮小且接合洩漏上升。
於本實施方式之半導體裝置中,藉由使絕緣分離區域STI沿半導體區域之深度方向後退而凹陷,於因該凹陷而露出之半導體區域之側壁形成相對於氧化膜及氮化膜而言選擇比較高之絕緣膜,從而能夠抑制接合洩漏。又,藉由在閘極側壁亦形成相對於氧化膜及氮化膜而言選擇比較高之絕緣膜,能夠自對準地控制閘極電極G與源極接點CS之間之距離。同樣地,能夠自對準地控制閘極電極G與汲極接點CD之間之距離。其結果,於本實施方式中,能夠提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置。
(第1實施方式之半導體裝置之構成)
如圖2A及圖2B所示,表示第1實施方式之半導體裝置1且為沿圖1C之I-I線之模式性剖面構造。此處,圖2A係開設有源極接觸孔CHS及汲極接觸孔CHD之構造,圖2B係形成有源極接點CS及汲極接點CD之構造。
第1實施方式之半導體裝置1具備半導體區域10、絕緣分離區域(絕緣部)12、第1區域(源極)22、第2區域(汲極)23、控制電極(閘極電極)14、第1電極CS、及側壁絕緣膜(第1絕緣膜)262。半導體區域10包括
第1表面SF1,具有第1導電型。絕緣分離區域(絕緣部)12形成於半導體區域10,具有較第1表面SF1沿半導體區域10之深度方向後退之第2表面SF2。第1區域(源極)22位於絕緣分離區域(絕緣部)12之第1部分與絕緣分離區域(絕緣部)12之第2部分之間且設於半導體區域10上。第2區域(汲極)23位於第1部分與第2部分之間,與第1區域(源極)22分開,且設於半導體區域10上。控制電極(閘極電極)14設於第1表面SF1上方,位於第1區域(源極)22與第2區域(汲極)23之間。第1電極CS設於第1區域(源極)22之上,與第1區域(源極)22相接。側壁絕緣膜(第1絕緣膜)262設於第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁。側壁絕緣膜(第1絕緣膜)262為包含鉿之絕緣膜。以下進行詳細說明。
如圖2A所示,第1實施方式之半導體裝置1具備第1導電型之半導體區域10、絕緣分離區域(絕緣部)12、控制電極(閘極電極)14、側壁絕緣膜261、與第1導電型為相反導電型之第1區域(源極)22及第2區域(汲極)23、源極接觸孔CHS及汲極接觸孔CHD、源極電極32S、汲極電極32D、及側壁絕緣膜(第1絕緣膜)262。
半導體區域10例如具備相對於n型半導體基板形成p井擴散層之p型半導體區域。半導體區域10亦可具備p型半導體基板。
絕緣分離區域(絕緣部)12形成於半導體區域10之第1表面SF1,具有較第1表面SF1沿半導體區域10之深度方向後退之第2表面SF2。絕緣分離區域(絕緣部)12可由STI形成。再者,如圖2C~圖2H所示,絕緣分離區域(絕緣部)12具有特定之寬度。又,半導體區域10之深度方向係與上述X-Y平面垂直之方向。
控制電極(閘極電極)14介隔閘極氧化膜20形成於由絕緣分
離區域(絕緣部)12包圍之半導體區域10之上方。
控制電極(閘極電極)14設於第1表面SF1上,位於第1區域(源極)22與第2區域(汲極)23之間。源極電極32S設於第1區域(源極)22之上,與第1區域(源極)22連接。汲極電極32D設於第2區域(汲極)23之上,與第2區域(汲極)23連接。
側壁絕緣膜261配置於控制電極(閘極電極)14兩端之側壁,具備相對於氧化矽膜及氮化矽膜而言蝕刻選擇比較高之膜。
第1區域(源極)22及第2區域(汲極)23形成於控制電極(閘極電極)14之兩端部之第1表面SF1。
於控制電極(閘極電極)14兩端之第1表面SF1,具備與第1區域(源極)22鄰接之源極擴展區域24及與第2區域(汲極)23鄰接之汲極擴展區域25。
第1區域(源極)22位於絕緣分離區域(絕緣部)12之間且設於半導體區域10上。第2區域(汲極)23位於絕緣分離區域(絕緣部)12之間,於X方向上與第1區域(源極)22分開,且設於半導體區域10上。
源極接觸孔CHS形成於第1區域(源極)22上,汲極接觸孔CHD形成於汲極區域D上。
又,如圖2B所示,源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而構成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而構成汲極接點CD。
側壁絕緣膜(第1絕緣膜)262配置於第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁,具備相對於氧化矽膜及氮化矽膜而言蝕刻選擇比較高之絕緣膜。側壁絕緣膜(第1絕緣膜)262可與側壁絕
緣膜261同時形成。
側壁絕緣膜261及側壁絕緣膜(第1絕緣膜)262例如可具備鉿系氧化膜。鉿系氧化膜係相對於氧化矽膜及氮化矽膜而言蝕刻選擇比較高之膜,蝕刻選擇比約為10以上。
側壁絕緣膜261及側壁絕緣膜(第1絕緣膜)262例如可包含選自氧化鉿(HfOX)、矽氧化鉿(HfSiOX)、氮氧矽化鉿(HfSiON)之群中之任一不同之材料。
側壁絕緣膜261及側壁絕緣膜(第1絕緣膜)262之厚度係數nm以上數10nm以下。又,側壁絕緣膜261及側壁絕緣膜(第1絕緣膜)262之厚度亦可約2nm以上約20nm左右以下。
第1表面SF1及第2表面SF2之深度方向之長度係約數nm以上數10nm以下。又,第1表面SF1及第2表面SF2之深度方向之長度亦可約10nm以上約50nm以下。
於第1表面SF1與第2表面SF2之間的階差部之側壁形成側壁絕緣膜(第1絕緣膜)262,只要作為活性區域AA之半導體區域10或第1區域(源極)22及第2區域(汲極)23之端部由側壁絕緣膜(第1絕緣膜)262被覆而未露出,則能夠抑制接合洩漏之上升。
於控制電極(閘極電極)14之側壁,具備積層之氧化矽膜16及氮化矽膜18,側壁絕緣膜261積層配置於氮化矽膜18。
如圖2B所示,源極接點CS可與絕緣分離區域(絕緣部)12與第1區域(源極)22之界面相接而配置。同樣地,如圖2B所示,汲極接點CD亦可與絕緣分離區域(絕緣部)12與第2區域(汲極)23之界面相接而配置。
於第1實施方式之半導體裝置中,藉由使絕緣分離區域(絕
緣部)12沿半導體區域10之深度方向後退而凹陷,於因該凹陷而露出之半導體區域10或第1區域(源極)22及第2區域(汲極)23之側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,能夠抑制接合洩漏。
又,於第1實施方式之半導體裝置1中,藉由在閘極側壁亦形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜261,能夠自對準地控制控制電極(閘極電極)14與源極接點CS之間之距離。同樣地,能夠自對準地控制控制電極(閘極電極)14與汲極接點CD之間之距離。其結果,於第1實施方式中,能夠提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置。
(第1實施方式之變化例之半導體裝置之構成)
如圖2G及圖2H所示,表示第1實施方式之變化例之半導體裝置1A且為沿圖1D之II-II線之模式性剖面構造。此處,圖2G係開設有源極接觸孔CHS及汲極接觸孔CHD之構造,圖2H係形成有源極接點CS及汲極接點CD之構造。
如圖2G所示,第1實施方式之變化例之半導體裝置1A具備第1導電型之半導體區域10、絕緣分離區域(絕緣部)12、控制電極(閘極電極)14、側壁絕緣膜261、第1區域(源極)22及第2區域(汲極)23、源極接觸孔CHS及汲極接觸孔CHD、及側壁絕緣膜(第1絕緣膜)262。
又,如圖2H所示,源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而構成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而構成汲極接點CD。
又,如圖2H所示,源極接點CS可跨及絕緣分離區域(絕緣
部)12及第1區域(源極)22而配置。同樣地,如圖2H所示,汲極接點CD可跨及絕緣分離區域(絕緣部)12及第2區域(汲極)23而配置。其他構成與第1實施方式相同。
於第1實施方式之變化例之半導體裝置1A中,藉由使絕緣分離區域(絕緣部)12沿半導體區域10之深度方向後退而凹陷,於因該凹陷而露出之半導體區域10或第1區域(源極)22及第2區域(汲極)23之側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,亦能夠抑制接合洩漏。
若源極接點CS搭於絕緣分離區域(絕緣部)12,則當源極接點CS打開時會露出半導體區域10或第1區域(源極)22及第2區域(汲極)23之端部,但藉由在該側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,即使於絕緣分離區域(絕緣部)12上之開口部置入源極電極32S及汲極電極32D亦能夠抑制接合洩漏。即,即使源極電極32S及汲極電極32D誤落在STI上亦能夠避免接合洩漏。其結果,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
又,於第1實施方式之變化例之半導體裝置1A中,藉由在閘極側壁亦形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜261,亦能夠自對準地控制控制電極(閘極電極)14與源極接點CS之間之距離。同樣地,能夠自對準地控制控制電極(閘極電極)14與汲極接點CD之間之距離。其結果,於第1實施方式之變化例中,能夠提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置。
(第1實施方式之半導體裝置之製造方法)
如圖2A~圖2F所示,表示第1實施方式之半導體裝置之製造方法。
第1實施方式之半導體裝置之製造方法具有如下步驟:於第1導電型之半導體區域10之第1表面SF1形成絕緣分離區域(絕緣部)12;於由絕緣分離區域(絕緣部)12包圍之半導體區域10上方介隔閘極氧化膜20形成控制電極(閘極電極)14;於控制電極(閘極電極)14兩端之第1表面SF1形成與第1導電型為相反導電型之第1區域(源極)22及第2區域(汲極)23;蝕刻絕緣分離區域(絕緣部)12直至較第1表面SF1沿半導體區域10之深度方向後退之第2表面SF2;於第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁形成包含鉿之第1側壁絕緣膜(第1絕緣膜)262,於控制電極(閘極電極)14兩端之側壁形成包含鉿之第2側壁絕緣膜261;形成層間絕緣膜28;於層間絕緣膜28形成接觸孔CHS;於接觸孔CHS內形成與第1區域(源極)22連接之源極電極CS。以下將進行詳細說明。
(A1)首先,如圖2C所示,於p型半導體區域10之第1表面SF1形成絕緣分離區域(絕緣部)12,於由絕緣分離區域(絕緣部)12包圍之半導體區域10上方介隔閘極氧化膜20形成控制電極(閘極電極)14。此處,絕緣分離區域(絕緣部)12例如由四乙氧基矽烷(TEOS;Tetraethoxysilane)形成。控制電極(閘極電極)14例如由有摻雜之多晶矽等形成。
(A2)其次,例如利用化學氣相沈積(CVD:Chemical Vapor Deposition)法,於控制電極(閘極電極)14之側壁形成氧化矽膜16。此處,氧化矽膜16例如由TEOS形成。
(A3)其次,使用離子注入技術,於控制電極(閘極電極)14兩端之第1表面SF1形成n-源極擴展區域24及n-汲極擴展區域25。
(A4)其次,例如利用CVD法,於控制電極(閘極電極)14側
壁之氧化矽膜16上形成氮化矽膜18。
(A5)其次,使用離子注入技術,於控制電極(閘極電極)14兩端之第1表面SF1形成n+第1區域(源極)22及n+第2區域(汲極)23。
(B)其次,如圖2D所示,使用反應性離子蝕刻(RIE:Reactive Ion Etching)技術,對絕緣分離區域(絕緣部)12之表面進行蝕刻,形成具有較第1表面SF1沿半導體區域10之深度方向後退之第2表面SF2的STI。如圖2D所示,蝕刻絕緣分離區域(絕緣部)12之表面之同時亦蝕刻控制電極(閘極電極)14側壁之氧化矽膜16。
(C)其次,如圖2E所示,使用濺鍍技術等,於器件整面形成絕緣膜26。絕緣膜26係相對於氧化矽膜及氮化矽膜而言蝕刻選擇比較高之膜。
(D)其次,如圖2F所示,蝕刻絕緣膜26,形成配置於控制電極(閘極電極)14兩端之側壁之側壁絕緣膜261,及於第1表面SF1與第2表面SF2之間的階差部之半導體區域10或n+第1區域(源極)22及n+第2區域(汲極)23之側壁形成側壁絕緣膜(第1絕緣膜)262。再者,於絕緣膜26之蝕刻步驟中,於器件整面形成絕緣膜26後,於結晶化之前進行圖案化,利用乾式蝕刻或者濕式蝕刻進行去除。再者,可並用乾式蝕刻及濕式蝕刻。
(E1)其次,如圖2A所示,使用CVD技術等,對器件整面形成襯墊絕緣膜30。此處,襯墊絕緣膜30可應用氮化矽膜。
(E2)其次,如圖2A所示,去除第1區域(源極)22及第2區域(汲極)23之上之襯墊絕緣膜30,露出第1區域(源極)22及第2區域(汲極)23之表面後,使用CVD技術等對器件整面形成層間絕緣膜28後,使用化學機械研磨(CMP:Chemical Mechanical Polishing)技術進行平坦化。此
處,層間絕緣膜28例如作為與TEOS或者CMP之相容性良好之絕緣膜,可應用NSG(None-doped Silicate Glass,非摻雜矽酸鹽玻璃)膜等。藉由使用NSG膜,能夠以較高之研磨速率使NSG膜之表面良好地平坦化。再者,於形成上述襯墊絕緣膜30後,亦可於器件整面形成層間絕緣膜28。
(E3)其次,如圖2A所示,針對層間絕緣膜28,使用RIE等乾式蝕刻技術,於第1區域(源極)22及第2區域(汲極)23上形成源極接觸孔CHS及汲極接觸孔CHD。
再者,於形成上述襯墊絕緣膜30後,於在器件整面形成層間絕緣膜28之情形時,針對層間絕緣膜28開設源極接觸孔CHS及汲極接觸孔CHD之同時去除第1區域(源極)22及第2區域(汲極)23之上之襯墊絕緣膜30,露出第1區域(源極)22及第2區域(汲極)23之表面。
(F)其次,如圖2B所示,形成經由源極接觸孔CHS及汲極接觸孔CHD與第1區域(源極)22及第2區域(汲極)23連接之源極電極32S及汲極電極32D。源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而形成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而形成汲極接點CD。如圖2B所示,源極接點CS可接於絕緣分離區域(絕緣部)12與第1區域(源極)22之界面而配置。同樣地,如圖2B所示,汲極接點CD可接於絕緣分離區域(絕緣部)12與第2區域(汲極)23之界面而配置。
如圖2A所示,由於在控制電極(閘極電極)14兩端之側壁形成有側壁絕緣膜261,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,即使層間絕緣膜28及襯墊絕緣膜30被過蝕刻,側壁絕緣膜261相對而言亦不易被蝕刻。即,於形成源極接觸孔CHS及汲極接觸孔CHD時,利用側
壁絕緣膜261自對準地停止蝕刻。故而,能夠縮短源極接點CS與控制電極(閘極電極)14之間之距離。同樣地,能夠縮短汲極接點CD與控制電極(閘極電極)14之間之距離。
由於在第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁形成有側壁絕緣膜(第1絕緣膜)262,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,層間絕緣膜28及襯墊絕緣膜30容易被蝕刻,但側壁絕緣膜(第1絕緣膜)262相對而言不易蝕刻。其結果,如圖2B所示,即使源極接觸孔CHS及汲極接觸孔CHD與絕緣分離區域(絕緣部)12相接亦能夠避免接合洩漏。故而,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
(第1實施方式之變化例之半導體裝置之製造方法)
第1實施方式之變化例之半導體裝置之製造方法如圖2C~圖2F及圖2G及圖2H所示般表示。
第1實施方式之半導體裝置之製造方法之步驟A1~步驟A5及步驟B~步驟D於第1實施方式之變化例之半導體裝置之製造方法中亦共通。
(G1)上述步驟D之後,如圖2G所示,使用CVD技術等,對器件整面形成襯墊絕緣膜30。此處,襯墊絕緣膜30可應用氮化矽膜。
(G2)其次,如圖2G所示,於形成層間絕緣膜28後,使用CMP技術進行平坦化。此處,層間絕緣膜28例如可應用TEOS或者NSG膜等。藉由使用NSG膜,能夠以較高之研磨速率使NSG膜之表面良好地平坦化。
(G3)其次,如圖2G所示,對層間絕緣膜28使用RIE等乾式蝕刻技術,跨及第1區域(源極)22及絕緣分離區域(絕緣部)12形成源極接觸孔CHS,跨及第2區域(汲極)23及絕緣分離區域(絕緣部)12形成汲極接觸孔CHD。
(H)其次,如圖2H所示,形成經由源極接觸孔CHS及汲極接觸孔CHD與第1區域(源極)22及第2區域(汲極)23連接之源極電極32S及汲極電極32D。源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而形成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而形成汲極接點CD。
由於在第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁形成有側壁絕緣膜(第1絕緣膜)262,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,層間絕緣膜28及襯墊絕緣膜30容易被蝕刻,但側壁絕緣膜(第1絕緣膜)262相對而言不易被蝕刻。其結果,如圖2H所示,即使源極接點CS及汲極接點CD誤落在絕緣分離區域(絕緣部)12上亦能夠避免接合洩漏。故而,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
[第2實施方式]
如圖3A~圖3C所示,表示第2實施方式之半導體裝置2且為沿圖1C之I-I線之模式性剖面構造。
如圖3A~圖3C所示,第2實施方式之半導體裝置2具備第1導電型之半導體區域10、絕緣分離區域(絕緣部)12、控制電極(閘極電極)14、側壁絕緣膜261、第1區域(源極)22及第2區域(汲極)23、源極接觸
孔CHS及汲極接觸孔CHD、源極電極32S、汲極電極32D、側壁絕緣膜(第1絕緣膜)262、配置於控制電極(閘極電極)14上之閘極矽化物區域34G、配置於第1區域(源極)22上之源極矽化物區域34S、及配置於第2區域(汲極)23上之汲極矽化物區域34D。
源極矽化物區域34S及汲極矽化物區域34D包含選自Co、W、Ti、Ni之群中之任一不同之矽化物。閘極矽化物區域34G包含選自Co、W、Ti、及Ni之群中之任一不同之元素。
又,如圖3C所示,源極電極32S經由源極接觸孔CHS與源極矽化物區域34S電性連接而構成源極接點CS,汲極電極32D經由汲極接觸孔CHD與汲極矽化物區域34D電性連接而構成汲極接點CD。
如圖3C所示,源極接點CS可接於絕緣分離區域(絕緣部)12與第1區域(源極)22及源極矽化物區域34S之界面而配置。同樣地,如圖3C所示,汲極接點CD可接於絕緣分離區域(絕緣部)12與第2區域(汲極)23及汲極矽化物區域34D之界面而配置。其他構成與第1實施方式相同。
於第2實施方式之半導體裝置中,藉由使絕緣分離區域(絕緣部)12沿半導體區域10之深度方向後退而凹陷,於因該凹陷而露出之半導體區域10或源極矽化物區域34S及汲極矽化物區域34D之側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,亦能夠抑制接合洩漏。
又,於第2實施方式之半導體裝置1中,藉由在閘極側壁亦形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜261,能夠自對準地控制控制電極(閘極電極)14與源極接點CS之間之距離。同樣地,能夠自對準地控制控制電極(閘極電極)14與汲極接點CD之間之距離。其結
果,於第2實施方式中,能夠提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置。
(第2實施方式之變化例之半導體裝置之構成)
如圖3H~圖3J所示,表示第2實施方式之變化例之半導體裝置2A且為沿圖1D之II-II線之模式性剖面構造。
如圖3H~圖3J所示,第2實施方式之變化例之半導體裝置2A具備半導體區域10、絕緣分離區域(絕緣部)12、控制電極(閘極電極)14、側壁絕緣膜261、第1區域(源極)22及第2區域(汲極)23、源極接觸孔CHS及汲極接觸孔CHD、側壁絕緣膜(第1絕緣膜)262、配置於控制電極(閘極電極)14上之閘極矽化物區域34G、配置於第1區域(源極)22上之源極矽化物區域34S、及配置於第2區域(汲極)23上之汲極矽化物區域34D。
源極矽化物區域34S及汲極矽化物區域34D包含選自Co、W、Ti、Ni之群中之任一不同之矽化物。閘極矽化物區域34G包含選自Co、W、Ti、Ni、多晶矽之群中之任一不同之矽化物。
又,如圖3J所示,源極電極32S經由源極接觸孔CHS與源極矽化物區域34S電性連接而構成源極接點CS,汲極電極32D經由汲極接觸孔CHD與汲極矽化物區域34D電性連接而構成汲極接點CD。
又,如圖3J所示,源極接點CS可跨及絕緣分離區域(絕緣部)12、第1區域(源極)22及源極矽化物區域34S而配置。同樣地,如圖3J所示,汲極接點CD可跨及絕緣分離區域(絕緣部)12、第2區域(汲極)23及汲極矽化物區域34D而配置。其他構成與第2實施方式相同。
於第2實施方式之變化例之半導體裝置2A中,藉由使絕緣分離區域(絕緣部)12沿半導體區域10之深度方向後退而凹陷,於因該凹陷
而露出之半導體區域10或源極矽化物區域34S及汲極矽化物區域34D之側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,亦能夠抑制接合洩漏。
若源極接點CS搭於絕緣分離區域(絕緣部)12,則當源極接點CS打開時會露出半導體區域10或源極矽化物區域34S及汲極矽化物區域34D之端部,但藉由在該側壁形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜(第1絕緣膜)262,即使於絕緣分離區域(絕緣部)12上之開口部置入源極電極32S及汲極電極32D亦能夠抑制接合洩漏。即,即使源極電極32S及汲極電極32D誤落在STI上亦能夠避免接合洩漏。其結果,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
又,於第2實施方式之變化例之半導體裝置2A中,藉由在閘極側壁亦形成相對於氧化膜及氮化膜而言選擇比較高之側壁絕緣膜261,亦能夠自對準地控制控制電極(閘極電極)14與源極接點CS之間之距離。同樣地,能夠自對準地控制控制電極(閘極電極)14與汲極接點CD之間之距離。其結果,於第2實施方式之變化例中,能夠提供一種抑制接合洩漏之上升並且可縮小化之半導體裝置。
(第2實施方式之半導體裝置之製造方法)
如圖3A~圖3G所示,表示第2實施方式之半導體裝置之製造方法。
(A1)首先,如圖3D所示,於半導體區域10之第1表面SF1形成絕緣分離區域(絕緣部)12,於由絕緣分離區域(絕緣部)12包圍之半導體區域10上介隔閘極氧化膜20形成控制電極(閘極電極)14。此處,絕緣分離區域(絕緣部)12例如由TEOS形成。控制電極(閘極電極)14例如由有摻
雜之多晶矽等形成。
(A2)其次,例如利用CVD法,於控制電極(閘極電極)14之側壁形成氧化矽膜16。此處,氧化矽膜16例如由TEOS形成。
(A3)其次,使用離子注入技術,於控制電極(閘極電極)14兩端之第1表面SF1形成n-源極擴展區域24及n-汲極擴展區域25。
(A4)其次,例如利用CVD法,於控制電極(閘極電極)14側壁之氧化矽膜16上形成氮化矽膜18。
(A5)其次,使用離子注入技術,於控制電極(閘極電極)14兩端之第1表面SF1形成n+第1區域(源極)22及n+第2區域(汲極)23。
(A6)其次,於器件整面形成矽化物金屬,於控制電極(閘極電極)14上形成閘極矽化物區域34G,於第1區域(源極)22上形成源極矽化物區域34S,於第2區域(汲極)23上形成汲極矽化物區域34D。藉由在第1區域(源極)22之表面、第2區域(汲極)23之表面、及控制電極(閘極電極)14之表面形成作為金屬與矽之化合物之金屬矽化物,能夠減小薄片電阻或接點電阻。又,能夠自對準地形成矽化物。源極矽化物區域34S及汲極矽化物區域34D可包含選自Co、W、Ti、Ni之群中之任一不同之矽化物。又,閘極矽化物區域34G可包含選自Co、W、Ti、及Ni之群中之任一不同之元素。
(B)其次,如圖3E所示,使用RIE技術,對絕緣分離區域(絕緣部)12之表面進行蝕刻,形成具有較第1表面SF1沿半導體區域10之深度方向後退之第2表面SF2的STI。如圖3B所示,於蝕刻絕緣分離區域(絕緣部)12之表面之同時亦蝕刻控制電極(閘極電極)14側壁之氧化矽膜16。
(C)其次,如圖3F所示,使用濺鍍技術等,於器件整面形
成絕緣膜26。絕緣膜26係相對於氧化矽膜及氮化矽膜而言蝕刻選擇比較高之膜。
(D)其次,如圖3G所示,蝕刻絕緣膜26,於控制電極(閘極電極)14兩端之側壁形成側壁絕緣膜261。又,於第1表面SF1與第2表面SF2之間的階差部之側壁形成側壁絕緣膜(第1絕緣膜)262。利用側壁絕緣膜(第1絕緣膜)262,能夠保護第1表面SF1與第2表面SF2之間的階差部之半導體區域10或n+第1區域(源極)22及源極矽化物區域34S、n+第2區域(汲極)23及汲極矽化物區域34D之露出面。再者,於絕緣膜26之蝕刻步驟中,於器件整面形成絕緣膜26後,於結晶化之前進行圖案化,利用乾式蝕刻或者濕式蝕刻進行去除。再者,可併用乾式蝕刻及濕式蝕刻。
(E1)其次,如圖3A所示,使用CVD技術等,對器件整面形成襯墊絕緣膜30。此處,襯墊絕緣膜30可應用氮化矽膜。
(E2)其次,如圖3A所示,使用CVD技術等,對器件整面形成層間絕緣膜28後,使用CMP技術進行平坦化。此處,層間絕緣膜28例如可應用TEOS或者NSG膜等。
(E3)其次,如圖3A所示,針對層間絕緣膜28,使用RIE等乾式蝕刻技術,實施因被覆源極矽化物區域34S及汲極矽化物區域34D之襯墊絕緣膜30而停止之蝕刻,於源極接觸孔CHS及汲極接觸孔CHD之底部露出襯墊絕緣膜30。
(F)其次,如圖3B所示,使用RIE等乾式蝕刻技術,對被覆源極矽化物區域34S及汲極矽化物區域34D之襯墊絕緣膜30進行蝕刻,於源極矽化物區域34S及汲極矽化物區域34D上形成源極接觸孔CHS及汲極接觸孔CHD。
(G)其次,如圖3C所示,形成經由源極接觸孔CHS及汲極接觸孔CHD與源極矽化物區域34S及汲極矽化物區域34D連接之源極電極32S及汲極電極32D。源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而形成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而形成汲極接點CD。如圖3C所示,源極接點CS可接於絕緣分離區域(絕緣部)12與第1區域(源極)22之界面而配置。同樣地,如圖3C所示,汲極接點CD可接於絕緣分離區域(絕緣部)12與第2區域(汲極)23之界面而配置。
如圖3B所示,由於在控制電極(閘極電極)14兩端之側壁形成有側壁絕緣膜261,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,即使層間絕緣膜28及襯墊絕緣膜30被過蝕刻,側壁絕緣膜261相對而言亦不易被蝕刻。即,於形成源極接觸孔CHS及汲極接觸孔CHD時,利用側壁絕緣膜261,自對準地停止蝕刻。故而,能夠縮短源極接點CS與控制電極(閘極電極)14之間之距離。同樣地,能夠縮短汲極接點CD與控制電極(閘極電極)14之間之距離。
由於在第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁形成有側壁絕緣膜(第1絕緣膜)262,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,層間絕緣膜28及襯墊絕緣膜30容易被蝕刻,但側壁絕緣膜(第1絕緣膜)262相對而言不易被蝕刻。其結果,如圖3C所示,即使源極接觸孔CHS及汲極接觸孔CHD與絕緣分離區域(絕緣部)12相接,亦能夠避免接合洩漏。故而,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
(第2實施方式之變化例之半導體裝置之製造方法)
如圖3A~圖3D及圖3H~圖3J所示,表示第2實施方式之變化例之半導體裝置2A之製造方法。
第2實施方式之半導體裝置2A之製造方法之步驟A1~步驟A6及步驟B~步驟D於第2實施方式之變化例之半導體裝置之製造方法中亦共通。
(H1)於上述步驟D之後,如圖3H所示,具有使用CVD技術等對器件整面形成襯墊絕緣膜30之步驟。此處,襯墊絕緣膜30可應用氮化矽膜。
(H2)其次,如圖3H所示,使用CVD技術等,對器件整面形成層間絕緣膜28後,使用CMP技術進行平坦化。此處,層間絕緣膜28例如可應用TEOS或者NSG膜等。
(H3)其次,如圖3H所示,針對層間絕緣膜28,使用RIE等乾式蝕刻技術,實施因被覆源極矽化物區域34S及汲極矽化物區域34D之襯墊絕緣膜30而停止之蝕刻,於源極接觸孔CHS及汲極接觸孔CHD之底部露出襯墊絕緣膜30。
(I)其次,如圖3I所示,具有如下步驟:使用RIE等乾式蝕刻技術,對被覆源極矽化物區域34S及汲極矽化物區域34D之襯墊絕緣膜30進行蝕刻,跨及源極矽化物區域34S及絕緣分離區域(絕緣部)12形成源極接觸孔CHS,跨及汲極矽化物區域34D及絕緣分離區域(絕緣部)12形成汲極接觸孔CHD。
(J)其次,如圖3J所示,形成經由源極接觸孔CHS及汲極接觸孔CHD與源極矽化物區域34S及汲極矽化物區域34D連接之源極電極
32S及汲極電極32D。源極電極32S經由源極接觸孔CHS與第1區域(源極)22電性連接而形成源極接點CS,汲極電極32D經由汲極接觸孔CHD與第2區域(汲極)23電性連接而形成汲極接點CD。
由於在第1表面SF1與第2表面SF2之間的階差部之半導體區域10之側壁形成有側壁絕緣膜(第1絕緣膜)262,因此於形成源極接觸孔CHS及汲極接觸孔CHD時,層間絕緣膜28及襯墊絕緣膜30容易被蝕刻,但側壁絕緣膜(第1絕緣膜)262相對而言不易被蝕刻。其結果,如圖3J所示,即使源極接點CS及汲極接點CD誤落在絕緣分離區域(絕緣部)12上,亦能夠避免接合洩漏。故而,能夠縮短源極接點CS與絕緣分離區域(絕緣部)12之間之距離。同樣地,能夠縮短汲極接點CD與絕緣分離區域(絕緣部)12之間之距離。
於本實施方式之半導體裝置及其製造方法中,主要對n通道MOSFET進行了說明,但同樣亦可應用於導電型相反之p通道MOSFET。又,本實施方式之半導體裝置亦可應用於CMOS結構之高速邏輯LSI。又,本實施方式之半導體裝置例如亦可應用於構成NAND型快閃記憶體之周邊電路之高電壓pMOSFET、高電壓nMOSFET、低電壓pMOSFET、低電壓nMOSFET等。
已對本發明之若干實施方式進行了說明,但該等實施方式係作為例子而提出,並不用於限定發明之範圍。該等新穎實施方式能以其他多種方式實施,且能夠於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施方式或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明及其均等之範圍內。
本申請案享有以日本專利申請2020-26136號(申請日:2020年2月19日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:半導體裝置
AA:活性區域
CD:汲極接點
CS:第1電極(源極接點)
D:汲極區域
G:閘極電極
GC:閘極接點
S:源極區域
Claims (17)
- 一種半導體裝置,其具有: 第1導電型之半導體區域,其包含第1表面; 絕緣部,其形成於上述半導體區域,具有較上述第1表面沿上述半導體區域之深度方向後退之第2表面; 第1區域,其位於上述絕緣部之第1部分與上述絕緣部之第2部分之間,且設於上述半導體區域上; 第2區域,其位於上述第1部分與上述第2部分之間,與上述第1區域分開,且設於上述半導體區域上; 控制電極,其設於上述第1表面上方,位於上述第1區域與上述第2區域之間; 第1電極,其設於上述第1區域之上,與上述第1區域相接;及 第1絕緣膜,其設於上述第1表面與上述第2表面之間的階差部之上述半導體區域之側壁;且 上述第1絕緣膜為包含鉿之絕緣膜。
- 如請求項1之半導體裝置,其進而具有:位於上述控制電極兩端之側壁之第2絕緣膜。
- 如請求項2之半導體裝置,其中上述第1絕緣膜及上述第2絕緣膜包含鉿及氧。
- 如請求項3之半導體裝置,其中上述第1絕緣膜及上述第2絕緣膜包含選自氧化鉿、矽氧化鉿、及氮氧矽化鉿之群中之任一不同之材料。
- 如請求項2之半導體裝置,其中上述第1絕緣膜及上述第2絕緣膜之厚度係2 nm以上20 nm以下。
- 如請求項2之半導體裝置,其中上述第1表面至上述第2表面之深度方向之長度係2 nm以上20 nm以下。
- 如請求項2之半導體裝置,其更具備:依序積層於上述控制電極之側壁之氧化矽膜及氮化矽膜,上述第2絕緣膜積層於上述控制電極之側壁上所積層之上述氮化矽膜上。
- 如請求項1之半導體裝置,其中上述第1電極係接於上述絕緣部與上述第1區域之界面而設置。
- 如請求項1之半導體裝置,其中上述第1電極係跨及上述絕緣部及上述第1區域而設置。
- 如請求項1之半導體裝置,其中上述控制電極、上述第1區域及上述第2區域具備矽化物區域。
- 如請求項10之半導體裝置,其中上述矽化物區域包含選自Co、W、Ti、及Ni之群之任一不同之元素。
- 一種半導體裝置之製造方法,其係: 於第1導電型之半導體區域之第1表面形成絕緣部, 於由上述絕緣部包圍之上述半導體區域之上方介隔閘極氧化膜形成閘極電極, 於上述閘極電極兩端之上述第1表面形成與上述第1導電型為相反導電型之源極區域及汲極區域, 藉由蝕刻上述絕緣部,形成較上述第1表面沿上述半導體區域之深度方向後退之第2表面, 於上述第1表面與上述第2表面之間的階差部之上述半導體區域之側壁形成包含鉿之第1側壁絕緣膜,於上述閘極電極兩端之側壁形成包含鉿之第2側壁絕緣膜, 形成層間絕緣膜, 於上述層間絕緣膜形成接觸孔,及 於上述接觸孔內形成與上述源極區域連接之源極電極。
- 如請求項12之半導體裝置之製造方法,其中上述第1側壁絕緣膜及上述第2側壁絕緣膜包含選自氧化鉿、矽氧化鉿、及氮氧矽化鉿之群中之任一不同之材料。
- 如請求項12之半導體裝置之製造方法,其中上述接觸孔係與上述絕緣部與上述源極區域之界面相接而形成。
- 如請求項12之半導體裝置之製造方法,其中上述接觸孔係跨及上述絕緣部及上述源極區域而形成。
- 如請求項12之半導體裝置之製造方法,其中於上述閘極電極之上形成閘極矽化物區域,於上述源極區域之上形成源極矽化物區域。
- 如請求項16之半導體裝置之製造方法,其中上述閘極矽化物區域及上述源極矽化物區域包含選自Co、W、Ti、及Ni之群中之任一不同之元素。
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US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
TW201635495A (zh) * | 2014-12-25 | 2016-10-01 | Renesas Electronics Corp | 半導體裝置及其製造方法 |
US20170092723A1 (en) * | 2015-09-29 | 2017-03-30 | International Business Machines Corporation | High-k spacer for extension-free cmos devices with high mobility channel materials |
TW201916179A (zh) * | 2017-09-28 | 2019-04-16 | 日商瑞薩電子股份有限公司 | 半導體裝置及其製造方法 |
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US7560780B2 (en) * | 2005-12-08 | 2009-07-14 | Intel Corporation | Active region spacer for semiconductor devices and method to form the same |
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US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
TW201635495A (zh) * | 2014-12-25 | 2016-10-01 | Renesas Electronics Corp | 半導體裝置及其製造方法 |
US20170092723A1 (en) * | 2015-09-29 | 2017-03-30 | International Business Machines Corporation | High-k spacer for extension-free cmos devices with high mobility channel materials |
TW201916179A (zh) * | 2017-09-28 | 2019-04-16 | 日商瑞薩電子股份有限公司 | 半導體裝置及其製造方法 |
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