JP5640379B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 245
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims description 131
- 238000000034 method Methods 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 description 38
- 238000010586 diagram Methods 0.000 description 29
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 17
- 239000010410 layer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Description
1.第1実施形態(溝が矩形形状)
2.第2実施形態(溝がテーパー形状)
3.その他
(A)装置構成
図1〜図4は、本発明の第1実施形態に係る半導体装置100を示す図である。
上記の半導体装置を製造する製造方法の要部に関して説明する。
上記の半導体装置を製造する際には、まず、図5,図6に示すように、トランジスタ形成工程を実施する。
つぎに、図7,図8に示すように、平坦化膜形成工程を実施する。
つぎに、図9,図10に示すように、ダミーゲート電極・ダミーゲート絶縁膜除去工程を実施する。
つぎに、図11,図12に示すように、溝形成工程を実施する。
つぎに、図13,図14に示すように、高誘電体膜形成工程を実施する。
つぎに、図15,図16に示すように、金属膜形成工程を実施する。
つぎに、図2〜図4に示したように、ゲート電極・ゲート絶縁膜形成工程を実施して、半導体素子110を完成させる。
以上のように、本実施形態においては、半導体基板101に半導体素子110が設けられている。この半導体素子110は、電界効果トランジスタであって、ゲート絶縁膜111z,ゲート電極111g,一対のソース・ドレイン領域112s,112dを有する。半導体素子110において、ゲート絶縁膜111zは、半導体基板101の表面に設けられている。また、ゲート電極111gは、半導体基板101の表面においてゲート絶縁膜111zを介して設けられている。そして、一対のソース・ドレイン領域112s,112dは、半導体基板101においてゲート電極111gを挟むように設けられている。
つまり、一対のソース・ドレイン領域112s,112dは、凸部CVと凹部TRとの各部分において、上面が平坦であり、半導体基板101内で同じ深さまで形成されている。
本発明の第2実施形態について説明する。
図17は、本発明の第2実施形態に係る半導体装置100bを示す図である。
以上のように、本実施形態においては、第1実施形態の場合と同様に、FETである半導体素子110bにおいて、チャネルの幅方向xが凹凸形状に形成されている。このため、実効的なチャネル幅を増加させることができる。また、凹凸形状の側壁にてチャネルが形成されるので、Πゲートと同様な効果等によって、Sファクタを改善できる。
なお、上記においては、図17に示したように、溝Mbの底面が半導体基板101の表面(xy面)に対して水平に沿った場合について示したが、これに限定されない。
本発明の実施に際しては、上記の実施形態に限定されるものではなく、種々の変形形態を採用することができる。
Claims (1)
- 半導体基板の表面において半導体素子を構成するゲート絶縁膜およびゲート電極を形成する部分にダミーゲート絶縁膜を介してダミーゲート電極を形成すると共に、前記半導体素子を構成する一対のソース・ドレイン領域を、当該ダミーゲート電極を挟むように形成する第1ステップと、
前記ダミーゲート電極の上面が露出し、前記一対のソース・ドレイン領域の上面が被覆されるように前記半導体基板の表面に平坦化膜を形成する第2ステップと、
前記ダミーゲート電極および前記ダミーゲート絶縁膜を除去することによって、前記半導体基板において前記ダミーゲート電極および前記ダミーゲート絶縁膜が形成されていた表面を露出させ、当該表面部分に前記ソース・ドレイン領域に対して自己整合的な構成の開口を形成する第3ステップと、
前記半導体基板において前記ソース・ドレイン領域に対して自己整合的な構成の前記開口内における前記半導体基板の表面についてエッチング処理を実施することで、前記半導体基板において前記ゲート電極が設けられる部分の表面を凹凸面に形成し、前記半導体基板の凹凸面のうち凸部では、前記一対のソース・ドレイン領域の表面と同一の面となり、前記半導体基板の凹凸面のうち凹部では、前記一対のソース・ドレイン領域の表面から内部へ向けて溝を設ける第4ステップと、
前記半導体基板に形成された前記凹凸面を被覆するように絶縁膜を成膜することによって、前記半導体基板の凹凸面のうち凸部では、前記一対のソース・ドレイン領域の表面と同一の面を覆うように前記ゲート絶縁膜を形成し、前記半導体基板の凹凸面のうち凹部では、前記一対のソース・ドレイン領域の表面から内部へ向けて設けられた溝の面を覆うように前記ゲート絶縁膜を形成する第5ステップと、
前記凹凸面に形成されたゲート絶縁膜を被覆するように導電膜を成膜することによって、前記半導体基板の凹凸面のうち凸部では、前記ゲート絶縁膜の上面にゲート電極を形成し、前記半導体基板の凹凸面のうち凹部では、前記ゲート絶縁膜が設けられた溝の内部を埋め込むようにゲート電極を形成する第6ステップと
を有し、
前記半導体基板の凹凸面の凸部と凹部とにおいて、前記一対のソース・ドレイン領域が同一の形状になるように、かつ、前記ゲート電極に対して自己整合的に、当該一対のソース・ドレイン領域を形成する、
半導体装置の製造方法。
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JP2009298319A JP5640379B2 (ja) | 2009-12-28 | 2009-12-28 | 半導体装置の製造方法 |
US12/967,857 US8937349B2 (en) | 2009-12-28 | 2010-12-14 | Semiconductor component and manufacturing method thereof |
CN2010105982465A CN102130171B (zh) | 2009-12-28 | 2010-12-21 | 半导体元件和用于制造半导体元件的方法 |
US14/573,771 US9548360B2 (en) | 2009-12-28 | 2014-12-17 | Semiconductor component and manufacturing method thereof |
US15/371,826 US9748384B2 (en) | 2009-12-28 | 2016-12-07 | Semiconductor component and manufacturing method thereof |
US15/658,950 US9991383B2 (en) | 2009-12-28 | 2017-07-25 | Semiconductor component and manufacturing method thereof |
US15/956,254 US10727335B2 (en) | 2009-12-28 | 2018-04-18 | Semiconductor component and manufacturing method thereof |
US16/899,157 US11043590B2 (en) | 2009-12-28 | 2020-06-11 | Semiconductor component and manufacturing method thereof |
US17/329,393 US11848380B2 (en) | 2009-12-28 | 2021-05-25 | Semiconductor component and manufacturing method thereof |
US18/506,567 US20240088290A1 (en) | 2009-12-28 | 2023-11-10 | Semiconductor component and manufacturing method thereof |
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JP5640379B2 true JP5640379B2 (ja) | 2014-12-17 |
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JP5640379B2 (ja) * | 2009-12-28 | 2014-12-17 | ソニー株式会社 | 半導体装置の製造方法 |
CN102931235B (zh) * | 2011-08-12 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其制造方法 |
CN103000504A (zh) * | 2011-09-14 | 2013-03-27 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
FR2995135B1 (fr) * | 2012-09-05 | 2015-12-04 | Commissariat Energie Atomique | Procede de realisation de transistors fet |
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US9748384B2 (en) | 2017-08-29 |
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US11043590B2 (en) | 2021-06-22 |
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