TWI757554B - 半導體封裝裝置 - Google Patents

半導體封裝裝置 Download PDF

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Publication number
TWI757554B
TWI757554B TW107135484A TW107135484A TWI757554B TW I757554 B TWI757554 B TW I757554B TW 107135484 A TW107135484 A TW 107135484A TW 107135484 A TW107135484 A TW 107135484A TW I757554 B TWI757554 B TW I757554B
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Taiwan
Prior art keywords
electronic component
heat dissipation
dissipation cover
apertures
thermal isolation
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TW107135484A
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English (en)
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TW202010072A (zh
Inventor
洪志斌
陳瑭原
楊金鳳
施孟鎧
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日月光半導體製造股份有限公司
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Publication of TW202010072A publication Critical patent/TW202010072A/zh
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Abstract

一種半導體封裝裝置包括一基板、一第一電子組件、一第二電子組件、一散熱蓋及熱隔離。該基板具有一表面。該第一電子組件及該第二電子組件位於該基板之該表面上方，且經配置沿實質上平行於該表面之一方向。該第一電子組件及該第二電子組件由其間一空間分隔開。該散熱蓋位於該第一電子組件及該第二電子組件上方。該散熱蓋包括至少位於該第一電子組件與該第二電子組件之間的該空間上方的一或多個孔隙。該熱隔離處於該散熱蓋之該一或多個孔隙中。

Description

半導體封裝裝置
本發明係關於半導體封裝裝置，且更特定言之，係關於具有自電子組件散熱之散熱蓋，及減少具有不同工作功率之相鄰電子組件之間的熱傳遞的熱隔離的半導體封裝裝置。
半導體工業在一些半導體封裝裝置中之多種電子組件之集成密度方面已取得了發展。此增大之集成密度往往對應於在該等半導體封裝裝置中之增大之功率密度。在一些實施中，隨著半導體封裝裝置之功率密度增長，散熱可變為合意的。因此，在一些實施中，提供具有經改良熱導率之半導體封裝裝置可為有用的。
近年來已使用2.5D/3D半導體封裝裝置以提供高效能、減小封裝體積，並降低功率消耗。然而，在2.5D/3D半導體封裝裝置中，可含有具有不同工作功率之兩個或兩個以上晶片。自較高溫度晶片至較低溫度晶片的熱傳遞可能對後者造成損害。
在一些實施例中，一半導體封裝裝置包括一基板、一第一電子組件、一第二電子組件、一散熱蓋及熱隔離。該基板具有一表面。該第一電子組件及該第二電子組件位於該基板之該表面上方，且經配置沿實質上平行於該表面之一方向。該第一電子組件及該第二電子組件由一空間分隔開。該散熱蓋位於該第一電子組件及該第二電子組件上方，且包括至少位於該第一電子組件與該第二電子組件之間的該空間上方的一或多個孔隙。熱隔離安置於該散熱蓋之一或多個孔隙中。
在一些實施例中，一半導體封裝裝置包括一基板、複數個電子組件、一散熱蓋及熱隔離。該基板具有一表面。該等電子組件位於該基板之該表面上方。該散熱蓋位於該等電子組件上方，其中該散熱蓋包括一或多個孔隙。該熱隔離安置於該散熱蓋之該一或多個孔隙中，且該散熱蓋之熱導率與該熱隔離之熱導率的比率高於30。
在一些實施例中，一半導體封裝裝置包括一基板、一第一電子組件、一第二電子組件、一散熱蓋及熱隔離。該基板具有一表面。該第一電子組件及該第二電子組件位於該基板之該表面上方，且經配置沿實質上平行於該表面之一方向。該第一電子組件及該第二電子組件由一空間分隔開。該散熱蓋位於該第一電子組件及該第二電子組件上方，且包括至少位於該第一電子組件與該第二電子組件之間的該空間上方的一或多個孔隙。該熱隔離安置於該散熱蓋之該一或多個孔隙中。當該第一電子組件及該第二電子組件處於操作中時，該第一電子組件與該第二電子組件之間的溫度差大於3℃。
以下揭示內容提供用於實施所提供標的物之不同特徵的許多不同實施例或實例。在下文描述組件及配置之特定實例以闡明本發明之某些態樣。當然，此等組件及配置僅係實例且並不意欲係限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上之形成可包括第一特徵及第二特徵直接接觸地形成或安置之實施例，且亦可包括額外特徵在第一特徵與第二特徵之間形成或安置，使得第一特徵及第二特徵不直接接觸之實施例。另外，本發明可在各種實例中重複參考編號及/或字母。此重複係出於簡單性及清楚之目的，且自身並不規定所論述之各種實施例及/或組態之間的關係。
除非另外規定，否則諸如「上方」、「下方」、「向上」、「左邊」、「右邊」、「向下」、「頂部」、「底部」、「垂直」、「水平」、「側」、「較高」、「下部」、「上部」、「上方」、「下面」等空間描述係相對於圖中展示之定向加以指示。應理解，本文中所使用之空間描述僅出於說明之目的，且本文中所描述之結構之實際實施可以任何定向或方式在空間上配置，其限制條件為此等配置並不偏離本發明之實施例之優點。
以下描述包括對一些半導體封裝裝置，及製造其之方法之描述。在一些實施例中，半導體封裝裝置包括具有較高熱導率之散熱蓋及具有較低熱導率之熱隔離。具有較高熱導率之散熱蓋有助於沿垂直方向改良散熱，使得藉由電子組件在操作中產生的熱量有效地耗散。具有較低熱導率之熱隔離由一或多個孔隙實現，且有助於沿橫向方向抑制散熱蓋中之熱傳遞，由此防止對較低功率電子組件造成損害。
圖1為根據本發明之一些實施例之半導體封裝裝置1的截面圖，且圖2為根據本發明之一些實施例之半導體封裝裝置1的俯視圖。如圖1及圖2中所展示，半導體封裝裝置1包括基板10、諸如一或多個電子組件32及一或多個電子組件34之複數個電子組件、散熱蓋40及熱隔離50。基板10具有表面10A，及與表面10A相對之另一表面10B。在一些實施例中，表面10A實質上平行於表面10B。在一些實施例中，基板10可包括印刷電路板或其類似者。一或多個電路層12可安置於基板10中，使得安置於表面10A及表面10B上的組件可經由電路層12電連接。在一些實施例中，諸如焊料球之傳導結構14可安置於基板10之表面10B上，以供外部電連接。
電子組件32及電子組件34安置於基板10之表面10A上方，且經配置沿實質上平行於表面10A之方向D1。在一些實施例中，電子組件32及電子組件34安置於實質上相同層處。電子組件32及電子組件34為不同類型之電子組件。電子組件32及電子組件34具有不同特性；舉例而言，電子組件32之功率高於電子組件34之功率。高功率電子組件32在操作期間產生較多熱量，導致較高溫度，而低功率電子組件34相比處於操作期間之高功率電子組件32產生較少熱量，導致較低溫度。電子組件34易受高溫損壞，且往往在溫度上升高於其適當可操作溫度時被破壞。在一些實施例中，電子組件32可為特殊應用積體電路(ASIC)或其類似者，且電子組件34為諸如高頻寬記憶體(HBM)晶片之記憶體晶片或其類似者。電子組件32及電子組件34由其間的空間36分隔開，以防止電子組件32與電子組件34形成接觸，因此在方向D1上緩解電子組件32與電子組件34之間的熱傳遞。
在一些實施例中，諸如矽內插件之內插件20可安置於基板10與電子組件32/34之間。內插件20可包括諸如矽穿孔(TSV)之導電通孔22，且電子組件32/34可經由內插件20電連接至基板10。在一些實施例中，諸如焊料凸塊之傳導結構24可安置於內插件20與基板10之間，以將內插件20電連接至基板10。底膠26可安置於內插件20與基板10之間，以囊封且保護傳導結構24。
在一些實施例中，電子組件32及電子組件34可藉由覆晶接合(FCP)技術電連接至內插件20。半導體封裝裝置1可進一步包括將電子組件32與內插件20電連接的傳導結構32A，及將電子組件34與內插件20電連接的傳導結構34A。傳導結構32A及傳導結構34A可個別地包括導電襯墊、焊料凸塊、傳導柱或其組合。在一些實施例中，底膠32B可安置於電子組件32與內插件20之間，以囊封且保護傳導結構32A。另一底膠34B可安置於電子組件34與內插件20之間，以囊封且保護傳導結構34A。
散熱蓋40安置於電子組件32/34上方。散熱蓋40包括面向電子組件32/34之底部表面40B，及與底部表面40B相對之上部表面40A。在一些實施例中，環結構42可安置於基板10之表面10A上方。環結構42可安置於基板10之周邊區處，且包圍內插件20及電子組件32/34。在一些實施例中，環結構42藉由黏著層44附接至基板20。散熱蓋40可藉由另一黏著層46附接至環結構42。散熱蓋40經組態以沿實質上垂直於基板10之表面10A的方向D2提供散熱路徑，以耗散藉由電子組件32/34在操作期間產生的熱量。散熱蓋40之材料包括高度導熱材料。在一些實施例中，散熱蓋40之材料之熱導率高於(但不限於)200瓦/米*克耳文(W/m*K)。藉助於實例，散熱蓋40之材料可包括金屬或金屬合金，諸如熱導率為約210 W/m*K之鋁(Al)、熱導率為約390 W/m*K之銅(Cu)、其合金或其類似者。在一些實施例中，環結構42亦可經組態以沿方向D1提供散熱路徑，以耗散藉由電子組件32/34在操作期間產生之熱量。散熱蓋40及環結構42之材料可相同或不同。散熱蓋40包括至少位於電子組件32與電子組件34之間的空間36上方的一或多個孔隙40H。
在一些實施例中，散熱蓋40與電子組件32及電子組件34分隔開。舉例而言，散熱蓋40與電子組件32/34之間的間隙範圍為自約1微米至約200微米，或範圍為自約1微米至約100微米，但不限於此。
半導體封裝裝置1進一步包括散熱蓋40之一或多個孔隙40H中的熱隔離50。散熱蓋40之熱導率高於熱隔離50之熱導率。藉助於實例，散熱蓋40之熱導率與熱隔離50之熱導率的比率超過30、超過50或甚至更高。熱隔離50經組態以沿方向D1減輕散熱蓋40中之熱傳遞。舉例而言，當電子組件32相比電子組件34產生較高溫度時，散熱蓋40中位於電子組件32正上方之部分的溫度將高於散熱蓋40中位於電子組件34正上方之部分的溫度。孔隙40H中之熱隔離50可幫助阻止散熱蓋40中位於孔隙40H之相對側面上的部分之間的熱傳遞。因此，電子組件32及電子組件34可個別地保持於其適當可操作溫度範圍內。散熱蓋40及熱隔離50之組合亦幫助含有在其適當範圍內的半導體封裝裝置1之熱阻。在一些實施例中，熱隔離50包括氣態熱隔離。藉助於實例，氣態熱隔離可包括熱導率為約0.026 W/m*K之空氣熱隔離。在一些實施例中，一或多個孔隙40H可經密封，且氣體可泵出以形成真空熱隔離。
如圖2中所示，孔隙40H可包括沿垂直於方向D1之方向D3延伸的實質上矩形孔隙。散熱蓋40之孔隙40H具有在方向D1上量測之寬度W1，且空間36具有在方向D1上量測之寬度W2。在一些實施例中，寬度W1與寬度W2之比率大於50%。藉助於實例，孔隙40H之寬度W1為約2毫米，且空間36之寬度W2的範圍為自約2毫米至約4微米。
由高度導熱材料製成之散熱蓋40針對電子組件32/34沿垂直方向提供短且快速的散熱路徑，且因此，藉由電子組件32/34產生之熱量可向上傳遞，以允許電子組件32/34之冷卻。在另一方面，安置於散熱蓋40之孔隙40H中的熱隔離50由具有低熱導率之材料製成，且其沿橫向方向減輕散熱蓋40中之熱傳遞。熱隔離50可藉由沿橫向方向阻斷散熱蓋40中之熱傳遞，幫助阻止低功率電子組件34之溫度上升。
本發明提供之半導體封裝裝置不限於上述實施例，且可包括其他不同實施例，諸如描述如下之彼等實施例。為簡化描述及為在本發明之各實施例之間方便比較起見，以下實施例中之每一者中之相同或類似組件係以相同編號標記且未冗餘地描述。
圖3A、圖3B、圖3C、圖3D及圖3E為說明製造根據本發明之一些實施例之半導體封裝裝置的方法的示意圖。如圖3A中所示，容納內插件20。一或多個電子組件32接合至內插件20之表面。在一些實施例中，諸如焊料凸塊之傳導結構24可安置於內插件20之另一表面上，且內插件20可經由傳導結構24接合至另一組件。在一些實施例中，電子組件32藉由覆晶接合(FCB)技術接合至內插件20，且經由諸如導電襯墊、焊料凸塊、傳導柱或其組合之傳導結構32A電連接至內插件20之導電通孔22。如圖3B中所示，底膠32B被塗於電子組件32與內插件20之間，且固化。
如圖3C中所展示，內插件20經由另一表面接合至諸如印刷電路板之基板10。另一底膠26被塗於內插件20與基板10之間，且固化。如圖3D中所展示，環結構42用黏著層44附接至基板10。一或多個電子組件34接合至內插件20之表面。在一些實施例中，電子組件34藉由FCB技術接合至內插件20，且經由諸如導電襯墊、焊料凸塊、傳導柱或其組合之傳導結構34A電連接至內插件20之導電通孔22。底膠34B被塗於電子組件34與內插件20之間，且固化。電子組件32及電子組件34由空間36分隔開。在一些實施例中，電子組件34可連同電子組件32接合至內插件20。在一些實施例中，電子組件32與電子組件34可係水平的，舉例而言，電子組件32之上部表面與電子組件34之上部表面可實質上水平。
如圖3E中所展示，散熱蓋40用黏著層46附接至環結構42。散熱蓋40包括一或多個孔隙40H。熱隔離50形成於一或多個孔隙40H中。熱隔離50可包括氣態熱隔離、固態熱隔離、真空熱隔離或其一組合。在一些實施例中，諸如焊料球之傳導結構14可形成於基板10之表面10B上，以形成如圖1及圖2中所說明的半導體封裝裝置1。
圖4為根據本發明之一些實施例之半導體封裝裝置2的俯視圖。如圖4中所展示，散熱蓋40包括位於電子組件32與電子組件34之間的空間36上方的若干孔隙40H。孔隙40H可彼此斷開，且經配置實質上沿方向D3。熱隔離50可安置於散熱蓋40之孔隙40H中之每一者中。
圖5為根據本發明之一些實施例之半導體封裝裝置3的截面圖。如圖5中所展示，散熱蓋40可與電子組件32及/或電子組件34接觸。散熱蓋40與電子組件32/34之間的接觸沿垂直方向提供較短且直接的散熱路徑，且因此，藉由電子組件32/34產生之熱量可向上傳遞，且有助於電子組件32/34之冷卻。安置於一或多個孔隙40H中之熱隔離50可沿方向D1 (橫向方向)減輕散熱蓋40中之熱傳遞。
圖6為根據本發明之一些實施例之半導體封裝裝置4的截面圖。如圖6中所示，半導體封裝裝置4包括介於散熱蓋40與電子組件32/34之間的熱界面材料(TIM) 60。
散熱蓋40與電子組件32/34之間的熱界面材料60之熱導率高於諸如空氣之媒體的熱導率。熱界面材料60沿方向D2 (垂直方向)提供更高效的散熱路徑，且因此，藉由電子組件32/34產生之熱量可向上傳遞，以促進電子組件32/34之冷卻。安置於一或多個孔隙40H中之熱隔離50可沿方向D1 (橫向方向)減輕散熱蓋40中之熱傳遞。
圖7A為根據本發明之一些實施例之半導體封裝裝置5的截面圖，且圖7B為根據本發明之一些實施例之半導體封裝裝置5的俯視圖。如圖7A及圖7B中所展示，散熱蓋40具有複數個孔隙40H，包括實質上位於電子組件32與電子組件34之間的空間36上方的孔隙40H1及位於電子組件32及/或電子組件34上方的一或多個孔隙40H2。在一些實施例中，孔隙40H2可重疊電子組件32/34、部分地重疊電子組件32/34，或與電子組件32/34未對準。在一些實施例中，孔隙40H1/40H2可經配置沿方向D1。孔隙40H1/40H2可(但不限於)在方向D1上等間隔。孔隙40H1/40H2中之每一者可沿方向D3延伸。孔隙40H1/40H2之大小及形狀可係(但不限於)相同的。舉例而言，孔隙40H1/40H2中之每一者可具有實質上矩形形狀或其類似者。熱隔離50安置於散熱蓋40之40H1/40H2中。
孔隙40H1/40H2之數目及位置可經組態以沿方向D1增強散熱蓋40中的熱隔離，從而減輕沿方向D1的熱傳遞。舉例而言，一個孔隙40H1形成於位於空間36上方的散熱蓋40中，且四個孔隙40H2形成於位於電子組件32/34上方或與其相鄰的散熱蓋40中。在一些其他實施例中，孔隙40H1/40H2之數目及位置可修改。圖8A、圖8B及圖8C為根據本發明之一些實施例之半導體封裝裝置的俯視圖。如圖8A中所示，一個孔隙40H1形成於位於空間36上方的散熱蓋40中，且一個孔隙40H2形成於位於電子組件32上方的散熱蓋40中。如圖8B中所示，一個孔隙40H1形成於位於空間36上方的散熱蓋40中，且兩個孔隙40H2形成於位於電子組件32/34上方的散熱蓋40中。如圖8C中所示，一個孔隙40H1形成於位於空間36上方的散熱蓋40中，且三個孔隙40H2形成於位於電子組件32/34上方的散熱蓋40中。
在一些實施例中，一或多個孔隙40H之區域與散熱蓋40之區域(例如，散熱蓋40之頂部表面的區域，或散熱蓋40之底部表面的區域)的孔隙比範圍實質上為自約8%至約53%。在一些實施例中，一或多個孔隙40H之區域與散熱蓋40之區域的孔隙比實質上範圍為自約8%至約46%。在一些實施例中，一或多個孔隙40H之區域與散熱蓋40之區域的孔隙比實質上範圍為自約31%至約53%。在一些實施例中，一或多個孔隙40H之區域與散熱蓋40之區域的孔隙比實質上範圍為自約31%至約46%。可藉由增大孔隙40H之區域及/或孔隙40H之數目來修改孔隙40H之孔隙比。
圖9為根據本發明之一些實施例之半導體封裝裝置6的截面圖。如圖9中所示，半導體封裝裝置6可進一步包括位於散熱蓋40上的熱界面材料62。熱界面材料62之熱導率低於散熱蓋40之熱導率。藉助於實例，散熱蓋40之熱導率與熱界面材料62之熱導率的比率高於30。在一些實施例中，熱界面材料62覆蓋散熱蓋40之上部表面40A。在一些實施例中，熱界面材料62之上部表面62A係實質上平坦的。
圖10為根據本發明之一些實施例之半導體封裝裝置7的截面圖。如圖10中所示，相比於圖9之半導體封裝裝置6，半導體封裝裝置6之熱界面材料62的上部表面62A係彎曲的。
圖11為根據本發明之一些實施例之半導體封裝裝置8的截面圖。如圖11中所示，熱隔離50包括固態熱隔離。熱隔離50之熱導率低於散熱蓋40之熱導率。藉助於實例，散熱蓋40之熱導率與熱隔離50之熱導率的比率高於30。在一些實施例中，固態熱隔離包括熱導率低於約10 W/m*K的熱界面材料。在一些實施例中，熱隔離50安置於一或多個孔隙40H中。熱隔離50可部分地或完整地安置於一或多個孔隙40H中。熱隔離50可與散熱蓋40實質上水平。舉例而言，固態熱隔離50之上部表面50A及/或底部表面50B可與散熱蓋40之上部表面40A及/或底部表面40B水平。在一些實施例中，熱隔離50及散熱蓋40可經設定，除其間具有氣隙或熱界面材料的電子組件32/34之外。在一些實施例中，熱隔離50及散熱蓋40可與電子組件32/34接觸。
圖12為根據本發明之一些實施例之半導體封裝裝置9的截面圖。如圖12中所示，相比於圖11之半導體封裝裝置8，半導體封裝裝置9之固態熱隔離50安置於一或多個孔隙40H中，且經進一步延伸以覆蓋散熱蓋40之上部表面40A之至少一部分。在一些實施例中，熱隔離50部分安置於一或多個孔隙40H中。
圖13為根據本發明之一些實施例之半導體封裝裝置100的截面圖。如圖13中所示，相比於圖12之半導體封裝裝置9，半導體封裝裝置100之熱隔離50完整安置於一或多個孔隙40H中。
圖14為根據本發明之一些實施例之半導體封裝裝置101的截面圖。如圖14中所示，相比於圖11之半導體封裝裝置8，半導體封裝裝置101進一步包括位於散熱蓋40之上部表面40A上方，且覆蓋固態熱隔離50之上部表面50A的熱界面材料62。
圖15為根據本發明之一些實施例之半導體封裝裝置102的截面圖。如圖15中所示，相比於圖14之半導體封裝裝置101，半導體封裝裝置102進一步包括安置於熱界面材料62上方的散熱片70。散熱片70可與熱界面材料62接觸，或使用黏著劑接合至熱界面材料62。在一些實施例中，散熱片70之熱導率高於熱界面材料62之熱導率。用於散熱片70之材料的實例可包括金屬、合金或其類似者。半導體封裝裝置103之熱隔離50為諸如空氣熱隔離或真空熱隔離之氣態熱隔離。在一些實施例中，氣態熱隔離可藉由熱界面材料62及散熱片70密封。
圖16為根據本發明之一些實施例之半導體封裝裝置103的截面圖。如圖15中所示，相比於圖15之半導體封裝裝置102，半導體封裝裝置102之熱隔離50包括固態熱隔離。
在本發明中，半導體封裝裝置包括具有較高熱導率之散熱蓋40與具有較低熱導率之熱隔離50的組合。具有較高熱導率之散熱蓋40沿垂直方向改良散熱，使得藉由電子組件32/34在操作中產生之熱量有效地耗散。安置於一或多個孔隙40H中的具有較低熱導率之熱隔離50沿橫向方向抑制散熱蓋40中之熱傳遞，由此減少電子組件32/34之間的干涉。在一些實施例中，處於操作中的電子組件32與電子組件34之間的溫度差被用作評估沿橫向方向的散熱蓋中之熱傳遞經良好抑制的指示符。熱阻θ jc可被用作評估沿垂直方向之散熱的另一指示符。熱阻θ jc可表示為θ jc=(Tj-Tc)/P，其中θ jc為熱阻，Tj為半導體封裝裝置之結溫，Tc為半導體封裝裝置之表面溫度，且P為半導體封裝裝置之功率耗散。
在不同應用中，可設定具有不同功率之電子組件之間的溫度差及熱阻θ jc以滿足不同要求。在一些實施例中，將具有不同功率之電子組件之間的溫度差設定為大於3℃或更高，從而避免電子組件之間的干涉。在一些實施例中，將熱阻θ jc設定為小於0.041℃/W、0.04℃/W，或甚至更低以滿足散熱要求。對於2.5D/3D半導體封裝裝置，具有不同功率之電子組件之間的溫度差可大於3℃，從而避免電子組件之間的干涉，且熱阻θ jc可小於0.041℃/W以滿足散熱要求。
表1列出本發明之半導體封裝裝置之若干實施例的模擬結果。 表1
Figure 107135484-A0304-0001
表1之模擬中的半導體封裝裝置具有類似於圖16中所示之半導體封裝裝置之結構的結構。熱隔離50安置於孔隙40H中，且具有約2.89 W/m*K之熱導率。散熱蓋40/熱界面材料62與散熱片70之間的熱界面材料62之熱導率為約6.8 W/m*K。熱界面材料62之厚度為約1 mil。孔隙之寬度為約2 mm。散熱蓋40與散熱片70之材料包括銅。表1中之樣本1-7的封裝裝置具有不同的孔隙之數目及孔隙比。
如表1中所示，可藉由更改填充有熱隔離材料之孔隙的數目及孔隙比來修改具有不同功率之電子組件之間的溫度差∆T，以滿足不同要求。增大孔隙之數目及孔隙比可增大溫度差∆T。可藉由更改填充有熱隔離材料之孔隙之數目及孔隙比來修改熱阻θ jc，以滿足不同要求。在一些實施例中，控制孔隙比使其範圍為自約8%至約53%，溫度差∆T可大於1.6℃，且熱阻θ jc可小於0.053℃/W。在一些實施例中，控制孔隙比使其範圍為自約8%至約46%，溫度差∆T可大於1.6℃，且熱阻θ jc可小於0.041℃/W。在一些實施例中，控制孔隙比使其範圍為自約31%至約53%，溫度差∆T可大於3.2℃，且熱阻θ jc可小於0.053℃/W。在一些實施例中，控制孔隙比使其範圍為自約31%至約46%，溫度差∆T可大於3.2℃，且熱阻θ jc可小於0.040℃/W。
在本發明之一些實施例中，半導體封裝裝置包括具有較高熱導率之散熱蓋與具有較低熱導率之熱隔離的組合。具有較高熱導率之散熱蓋沿垂直方向改良散熱，使得藉由電子組件在操作中產生之熱量有效地耗散。安置於一或多個孔隙中的具有較低熱導率之熱隔離沿橫向方向抑制散熱蓋中之熱傳遞，由此防止對較低功率電子組件造成損害。
除非上下文另外清楚地規定，否則如本文所用，單數術語「一(a/an)」及「該」可包括複數個指示物。
如本文所使用，術語「導電性(conductive)」、「導電(electrically conductive)」及「電導率(electrical conductivity)」指輸送電流之能力。導電材料通常指示呈現對於電流流動之極小或零阻力之彼等材料。電導率之一個量度為西門子每米(S/m)。通常，導電材料具有大於約104 S/m之導電性，諸如至少105 S/m或至少106 S/m。材料之電導率有時可隨溫度而變化。除非另外規定，否則材料之電導率係在室溫下量測。
如本文中所使用，術語「大致上」、「實質上」、「相當大的」及「約」係用以描述及考量小的變化。當與事件或情形結合使用時，術語可指其中事件或情形明確發生之情況以及其中事件或情形極近似於發生之情況。舉例而言，當結合數值使用時，該等術語可指小於或等於彼數值之±10%的變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%之變化範圍。舉例而言，若兩個數值之間的差小於或等於該等值之平均值的±10%，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%，則可認為該兩個值「實質上」相同或相等。舉例而言，「實質上」平行可指相對於0°而言小於或等於±10°之變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或小於或等於±0.05°之變化範圍。舉例而言，「實質上」垂直可指相對於90°而言±10°之變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或者小於或等於±0.05°之變化範圍。
另外，有時在本文中按範圍格式呈現量、比率及其他數值。應理解，此類範圍格式係為便利及簡潔起見而使用，且應靈活地理解為不僅包括明確指定為範圍限制之數值，且亦包括涵蓋於彼範圍內之所有個別數值或子範圍，如同明確指定每一數值及子範圍一般。
儘管已參考本發明之特定實施例描述且說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。說明可不必按比例繪製。歸因於製造程序及容限，本發明中之藝術再現與實際裝置之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可作出修改，以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此等修改意欲在此處附加之申請專利範圍之範疇內。儘管參看按特定次序執行之特定操作描述本文中所揭示之方法，但應理解，在不脫離本發明之教示的情況下，可組合、再細分，或重新定序此等操作以形成等效方法。因此，除非本文中特定地指示，否則操作之次序及分組並非本發明之限制。
1‧‧‧半導體封裝裝置2‧‧‧半導體封裝裝置3‧‧‧半導體封裝裝置4‧‧‧半導體封裝裝置5‧‧‧半導體封裝裝置6‧‧‧半導體封裝裝置7‧‧‧半導體封裝裝置8‧‧‧半導體封裝裝置9‧‧‧半導體封裝裝置10‧‧‧基板10A‧‧‧表面10B‧‧‧表面12‧‧‧電路層14‧‧‧傳導結構20‧‧‧內插件22‧‧‧導電通孔24‧‧‧傳導結構26‧‧‧底膠32‧‧‧電子組件32A‧‧‧傳導結構32B‧‧‧底膠34‧‧‧電子組件34A‧‧‧傳導結構34B‧‧‧底膠36‧‧‧空間40‧‧‧散熱蓋40A‧‧‧上部表面40B‧‧‧底部表面40H‧‧‧孔隙40H1‧‧‧孔隙40H2‧‧‧孔隙42‧‧‧環結構44‧‧‧黏著層46‧‧‧黏著層50‧‧‧熱隔離50A‧‧‧上部表面50B‧‧‧底部表面62‧‧‧熱界面材料62A‧‧‧上部表面70‧‧‧散熱片100‧‧‧半導體封裝裝置101‧‧‧半導體封裝裝置102‧‧‧半導體封裝裝置103‧‧‧半導體封裝裝置D1-D3‧‧‧方向W1-W2‧‧‧寬度
當結合附圖閱讀時，自以下詳細描述最佳地理解本發明之一些實施例的態樣。各種結構可能未按比例繪製，且各種結構之尺寸可出於論述清晰起見任意增大或減小。 圖1為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖2為根據本發明之一些實施例之半導體封裝裝置的俯視圖； 圖3A、圖3B、圖3C、圖3D及圖3E為說明製造根據本發明之一些實施例之半導體封裝裝置的方法的示意圖； 圖4為根據本發明之一些實施例之半導體封裝裝置的俯視圖； 圖5為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖6為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖7A為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖7B為根據本發明之一些實施例之半導體封裝裝置的俯視圖； 圖8A、圖8B及圖8C為根據本發明之一些實施例之半導體封裝裝置的俯視圖； 圖9為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖10為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖11為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖12為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖13為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖14為根據本發明之一些實施例之半導體封裝裝置的截面圖； 圖15為根據本發明之一些實施例之半導體封裝裝置的截面圖；及 圖16為根據本發明之一些實施例之半導體封裝裝置的截面圖。
1‧‧‧半導體封裝裝置
10‧‧‧基板
10A‧‧‧表面
10B‧‧‧表面
12‧‧‧電路層
14‧‧‧傳導結構
20‧‧‧內插件
22‧‧‧導電通孔
24‧‧‧傳導結構
26‧‧‧底膠
32‧‧‧電子組件
32A‧‧‧傳導結構
32B‧‧‧底膠
34‧‧‧電子組件
34A‧‧‧傳導結構
34B‧‧‧底膠
36‧‧‧空間
40‧‧‧散熱蓋
40A‧‧‧上部表面
40B‧‧‧底部表面
40H‧‧‧孔隙
42‧‧‧環結構
44‧‧‧黏著層
46‧‧‧黏著層
50‧‧‧熱隔離
D1‧‧‧方向
D2‧‧‧方向

Claims (17)

  1. 一種半導體封裝裝置，其包含：一基板，其具有一表面；一第一電子組件及一第二電子組件，其安置於該基板之該表面上方，且經配置沿實質上平行於該表面之一方向，其中該第一電子組件及該第二電子組件由其間一空間分隔開；一散熱蓋，其安置於該第一電子組件及該第二電子組件上方，其中該散熱蓋包括至少位於該第一電子組件與該第二電子組件之間的該空間上方的一或多個孔隙；及熱隔離，其安置於該散熱蓋之該一或多個孔隙中；其中該一或多個孔隙包括位於該第一電子組件與該第二電子組件之間的該空間上方的一第一孔隙，及位於該第一電子組件或該第二電子組件之至少其中一者上方的一或多個第二孔隙，且該第一孔隙不同於該一或多個第二孔隙，其中該第一孔隙部分地重疊該第一電子組件的一邊緣及該第二電子組件的一邊緣；及其中該第一電子組件之功率高於該第二電子組件之功率，且該一或多個第二孔隙及該一或多個第二孔隙中的該熱隔離位於該第一電子組件上方。
  2. 如請求項1之半導體封裝裝置，其中該散熱蓋之一熱導率高於該熱隔離之一熱導率。
  3. 如請求項2之半導體封裝裝置，其中該散熱蓋之該熱導率與該熱隔離之該熱導率的一比率高於30。
  4. 如請求項1之半導體封裝裝置，其中該一或多個孔隙之一區域與該散熱蓋之一區域的一孔隙比實質上範圍為自約8%至約53%。
  5. 如請求項4之半導體封裝裝置，其中該一或多個孔隙之該區域與該散熱蓋之該區域的該孔隙比實質上範圍為自約8%至約46%。
  6. 如請求項4之半導體封裝裝置，其中該一或多個孔隙之該區域與該散熱蓋之該區域的該孔隙比實質上範圍為自約31%至約53%。
  7. 如請求項4之半導體封裝裝置，其中該一或多個孔隙之該區域與該散熱蓋之該區域的該孔隙比實質上範圍為自約31%至約46%。
  8. 如請求項1之半導體封裝裝置，其中該散熱蓋與該第一電子組件及該第二電子組件直接接觸。
  9. 如請求項1之半導體封裝裝置，其中該散熱蓋與該第一電子組件及該第二電子組件分隔開。
  10. 如請求項9之半導體封裝裝置，其中位於該散熱蓋與該第一電子組件/該第二電子組件之間且在垂直於該基板之該表面的一第二方向上量測的一 間隙範圍為自約1微米至約200微米。
  11. 如請求項1之半導體封裝裝置，其中該熱隔離包含一氣態熱隔離、一固態熱隔離、一真空熱隔離或其一組合。
  12. 如請求項1之半導體封裝裝置，其中該散熱蓋包括面向該第一電子組件及該第二電子組件之一底部表面，及與該底部表面相對之一上部表面，該熱隔離為固態熱隔離，且該熱隔離進一步直接接觸該散熱蓋之該上部表面的至少一部分。
  13. 如請求項1之半導體封裝裝置，其進一步包含介於該散熱蓋與該第一電子組件之間，且介於該散熱蓋與該第二電子組件之間的一第一熱界面材料。
  14. 如請求項1之半導體封裝裝置，其進一步包含位於該散熱蓋及該熱隔離上方的一第二熱界面材料。
  15. 如請求項14之半導體封裝裝置，其進一步包含位於該第二熱界面材料上方的一散熱片。
  16. 如請求項1之半導體封裝裝置，其中該第一孔隙及該一或多個第二孔隙的延伸方向實質上平行。
  17. 一種半導體封裝裝置，其包含：一基板，其具有一表面；複數個電子組件，其安置於該基板之該表面上方，其中至少兩個相鄰的該些電子組件由一空間分隔開；一散熱蓋，其安置於該等電子組件上方，其中該散熱蓋包括一或多個孔隙，其中該一或多個孔隙包括位於該空間上方的一第一孔隙，及位於該些電子組件之至少其中一者上方的一或多個第二孔隙，且該第一孔隙物理性地不同於該一或多個第二孔隙；及熱隔離，其安置於該散熱蓋之該一或多個孔隙中，且該散熱蓋之一熱導率與該熱隔離之一熱導率的一比率高於30；其中該熱隔離包含一固態熱隔離，該固態熱隔離位於該一或多個第二孔隙中且直接接觸該等電子組件之至少其中一者。
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