TWI752295B - Optoelectronic semiconductor device - Google Patents

Optoelectronic semiconductor device Download PDF

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TWI752295B
TWI752295B TW108102987A TW108102987A TWI752295B TW I752295 B TWI752295 B TW I752295B TW 108102987 A TW108102987 A TW 108102987A TW 108102987 A TW108102987 A TW 108102987A TW I752295 B TWI752295 B TW I752295B
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semiconductor device
semiconductor layer
semiconductor
optoelectronic semiconductor
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TW202029520A (en
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吳凡磊
李世昌
陳怡名
詹燿寧
蔡均富
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晶元光電股份有限公司
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An optoelectronic semiconductor device includes a first semiconductor layer, a second semiconductor layer and an active structure. The second semiconductor layer is over the first semiconductor layer. The active structure is between the first semiconductor layer and the second semiconductor layer. At a current density larger than or equal to 3.5 A/mm2 , the semiconductor device has an emission spectrum including a first peak position w1 and a second peak position w2, w2＞w1. A separation ratio between the first peak position and the second peak position is 0.5%~10% and the separation ratio id defined by the following formula:

Description

光電半導體裝置Optoelectronic semiconductor device

本發明是有關於一種半導體裝置，且特別是有關於一種光電半導體裝置。The present invention relates to a semiconductor device, and in particular to an optoelectronic semiconductor device.

半導體裝置包含由Ⅲ-Ⅴ族元素組成的化合物半導體，例如磷化鎵(GaP)、砷化鎵(GaAs)或氮化鎵(GaN)，半導體裝置可以為光電半導體裝置如發光二極體(LED)、雷射二極體、光偵測器、太陽能電池或為功率裝置(Power Device)。發光二極體包含一p型半導體層、一n型半導體層與一活性結構設於p型半導體層與n型半導體層之間，使得在一外加電場作用下，n型半導體層及p型半導體層所分別提供的電子及電洞在活性結構複合，以將電能轉換成光能。如何提升光電半導體裝置的光電轉換效率，實為研發人員研發的重點之一。The semiconductor device includes compound semiconductors composed of III-V group elements, such as gallium phosphide (GaP), gallium arsenide (GaAs) or gallium nitride (GaN), and the semiconductor device may be an optoelectronic semiconductor device such as a light emitting diode (LED). ), laser diodes, photodetectors, solar cells or power devices. The light-emitting diode includes a p-type semiconductor layer, an n-type semiconductor layer and an active structure arranged between the p-type semiconductor layer and the n-type semiconductor layer, so that under the action of an external electric field, the n-type semiconductor layer and the p-type semiconductor layer The electrons and holes provided by the layers, respectively, recombine in the active structure to convert electrical energy into light energy. How to improve the photoelectric conversion efficiency of optoelectronic semiconductor devices is actually one of the focuses of R&D personnel.

本發明係有關於一種光電半導體裝置。The present invention relates to an optoelectronic semiconductor device.

根據一實施例，係提出一種光電半導體裝置，其包括一第一半導體層、一第二半導體層、及一活性結構。第二半導體層位於第一半導體層上。活性結構位於第一半導體層及第二半導體層之間。在半導體裝置的電流密度大於3.5 A/mm2 時，半導體裝置具有一發光光譜包含一第一波峰位置w1及一第二波峰位置w2，w2＞w1，且第一波峰位置及第二波峰位置具有一分離率介於0.5%~10%，且分離率符合以下公式：

Figure 02_image003
。According to an embodiment, an optoelectronic semiconductor device is provided, which includes a first semiconductor layer, a second semiconductor layer, and an active structure. The second semiconductor layer is on the first semiconductor layer. The active structure is located between the first semiconductor layer and the second semiconductor layer. When the current density of the semiconductor device is greater than 3.5 A/mm 2 , the semiconductor device has a light emission spectrum including a first peak position w1 and a second peak position w2, w2>w1, and the first peak position and the second peak position have A separation rate is between 0.5% and 10%, and the separation rate conforms to the following formula:
Figure 02_image003
.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下：In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

為讓本揭露之上述目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the above-mentioned objects, features, and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings:

第1圖繪示根據一實施例概念之光電半導體裝置100的剖面示意圖。第2圖是根據一實施例繪示本揭露之半導體光電半導體裝置100的上視圖，第1圖對應為第2圖AA'線之剖面示意圖。光電半導體裝置100具有一半導體疊層1及一基板30。在本實施例中，基板30上方可依序設置導電黏結層31、反射結構32、導電結構33、絕緣層35、第一窗戶層34、半導體疊層1。第一電極結構2與第二電極結構36配置在半導體疊層1的相反側。FIG. 1 illustrates a schematic cross-sectional view of an optoelectronic semiconductor device 100 according to an embodiment concept. FIG. 2 is a top view illustrating the semiconductor optoelectronic semiconductor device 100 of the present disclosure according to an embodiment, and FIG. 1 corresponds to a schematic cross-sectional view taken along line AA' in FIG. 2 . The optoelectronic semiconductor device 100 has a semiconductor stack 1 and a substrate 30 . In this embodiment, a conductive adhesive layer 31 , a reflective structure 32 , a conductive structure 33 , an insulating layer 35 , a first window layer 34 , and a semiconductor stack 1 may be disposed on the substrate 30 in sequence. The first electrode structure 2 and the second electrode structure 36 are arranged on opposite sides of the semiconductor stack 1 .

半導體疊層1包含一第一半導體層111、一第二半導體層112及一活性結構113位於第一半導體層111及第二半導體層112之間，換言之，活性結構113與第二半導體層112依一堆疊方向(即圖示中Z方向，其可實質上垂直於X方向)依序位於第一半導體層111上。一實施例中，光電半導體裝置100為一發光裝置，半導體疊層1為發光疊層，第一半導體層111及第二半導體層112例如為包覆層（cladding layer）及/或限制層（confinement layer），且具有一大於活性結構之能隙，藉此提高電子、電洞於活性結構113中結合以發光的機率。活性結構113可以發出一發射光，該發射光具有一峰值波長（peak wavelength）約為200 nm～1800 nm；在一實施例中，半導體疊層1之發射光為紅外光，且該發射光之峰值波長約為750 nm～1700 nm。The semiconductor stack 1 includes a first semiconductor layer 111 , a second semiconductor layer 112 and an active structure 113 located between the first semiconductor layer 111 and the second semiconductor layer 112 , in other words, the active structure 113 and the second semiconductor layer 112 are in accordance with A stacking direction (ie, the Z direction in the figure, which may be substantially perpendicular to the X direction) is sequentially positioned on the first semiconductor layer 111 . In one embodiment, the optoelectronic semiconductor device 100 is a light-emitting device, the semiconductor stack 1 is a light-emitting stack, and the first semiconductor layer 111 and the second semiconductor layer 112 are, for example, cladding layers and/or confinement layers. layer), and has an energy gap larger than that of the active structure, thereby increasing the probability that electrons and holes combine in the active structure 113 to emit light. The active structure 113 can emit an emission light, and the emission light has a peak wavelength (peak wavelength) of about 200 nm to 1800 nm; in one embodiment, the emission light of the semiconductor stack 1 is infrared light, and the emission light is The peak wavelength is about 750 nm to 1700 nm.

半導體疊層1具有一第一表面11，第一電極結構2位於該第一表面11上，在本實施例中，第一表面1為一粗糙面，以增加光電半導體裝置100的光取出效率。第一窗戶層34設在第一半導體111上且具有一第二表面34a遠離半導體疊層1的第一表面11。The semiconductor stack 1 has a first surface 11 on which the first electrode structure 2 is located. In this embodiment, the first surface 1 is a rough surface to increase the light extraction efficiency of the optoelectronic semiconductor device 100 . The first window layer 34 is disposed on the first semiconductor 111 and has a second surface 34 a away from the first surface 11 of the semiconductor stack 1 .

第一半導體層111及第二半導體層112分別具有不同之一第一導電性及一第二導電性，以分別提供電子與電洞，或者分別提供電洞與電子。活性結構113可以包含單異質結構(single heterostructure)、雙異質結構(double heterostructure)或多層量子井(multiple quantum wells)。第一半導體層111、第二半導體層112及活性結構113之材料為三五族化合物半導體，例如可以為：GaAs、InGaAs、AlGaAs、AlInGaAs、GaP、InGaP、AlInP、AlGaInP、GaN、InGaN、AlGaN、AlInGaN、AlAsSb、InGaAsP、InGaAsN、AlGaAsP等。在本發明實施例中，若無特別說明，上述化學表示式包含「符合化學劑量之化合物」及「非符合化學劑量之化合物」，其中，「符合化學劑量之化合物」例如為三族元素的總元素劑量與五族元素的總元素劑量相同，反之，「非符合化學劑量之化合物」例如為三族元素的總元素劑量與五族元素的總元素劑量不同。舉例而言，化學表示式為AlGaAs即代表包含三族元素鋁(Al)及鎵(Ga)，以及包含五族元素砷(As)，其中三族元素(鋁及鎵)的總元素劑量可以與五族元素(砷)的總元素劑量相同或相異。另外，若上述由化學表示式表示的各化合物為符合化學劑量之化合物時，AlGaAs即代表Alx1 Ga1-x1 As，其中，鋁含量x可符合0＜x1＜1；AlInP代表Alx2 In1-x2 P，其中，鋁含量x可符合0＜x2＜1；AlGaInP代表(Al1y Ga1-y1 )1-x3 Inx3 P，其中，0＜x3＜1；AlGaN代表Alx4 Ga1-x4 N，其中，鋁含量x4可符合0＜x4＜1；AlAsSb代表AlAsx5 Sb1-x5 ，其中，0＜x5＜1；InGaP代表Inx5 Ga1-x5 P，其中，0＜x5＜1；InGaAsP代表Inx6 Ga1-x6 As(1-y2) Py2 ，其中，0＜x6＜1, 0＜y2＜1；InGaAsN代表Inx7 Ga1-x7 As1-y3 Ny3 ，其中，0＜x7＜1，0＜y3＜1；AlGaAsP代表Alx8 Ga1-x8 As1-y4 Py4 ，其中，鋁含量x可符合0＜x8＜1，0＜y4＜1；InGaAs代表Inx9 Ga1-x9 As，其中，0＜x9＜1。The first semiconductor layer 111 and the second semiconductor layer 112 have a different first conductivity and a second conductivity, respectively, so as to provide electrons and holes, or provide holes and electrons, respectively. The active structure 113 may comprise a single heterostructure, a double heterostructure, or multiple quantum wells. The materials of the first semiconductor layer 111, the second semiconductor layer 112 and the active structure 113 are group III and V compound semiconductors, such as: GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present invention, unless otherwise specified, the above chemical expressions include "compounds that meet stoichiometric doses" and "compounds that do not meet stoichiometric doses", wherein, "compounds that meet stoichiometric doses" are, for example, the total of the three group elements. The element dosage is the same as the total element dosage of the Group V elements. On the contrary, the "non-stoichiometric compound" is, for example, the total element dosage of the Group III element is different from the total element dosage of the Group V element. For example, the chemical expression is AlGaAs, which means that the group 3 elements aluminum (Al) and gallium (Ga) are included, and the group 5 element arsenic (As) is included, wherein the total element dose of the third group elements (aluminum and gallium) can be The total element dose of the Group V element (arsenic) is the same or different. In addition, if each compound represented by the above chemical formula is a compound that meets the stoichiometric dose, AlGaAs represents Al x1 Ga 1-x1 As, wherein the aluminum content x can satisfy 0<x1<1; AlInP represents Al x2 In 1 -x2 P, where the aluminum content x may satisfy 0<x2<1; AlGaInP stands for (Al1 y Ga 1-y1 ) 1-x3 In x3 P, where 0<x3<1; AlGaN stands for Al x4 Ga 1-x4 N, where the aluminum content x4 can satisfy 0<x4<1; AlAsSb represents AlAs x5 Sb 1-x5 , where 0<x5<1; InGaP represents Inx5 Ga 1-x5 P, where 0<x5<1; Representative InGaAsP In x6 Ga 1-x6 As (1-y2) P y2, where, 0 <x6 <1, 0 <y2 <1; InGaAsN representative of In x7 Ga 1-x7 As 1 -y3 N y3, where 0 < x7 <1,0 <y3 <1; Representative AlGaAsP Al x8 Ga 1-x8 As 1-y4 P y4, wherein the aluminum content x may conform 0 <x8 <1,0 <y4 <1; InGaAs representative of In x9 Ga 1 -x9 As, where 0<x9<1.

一實施例中，第一半導體層111與第二半導體層112的組成均包含鋁，且具有相同的鋁含量。在本實施例中，光電半導體裝置100另包含一第二窗戶層(圖未示)位於第二半導體層112上，且第二窗戶層的厚度大於第二半導體層112，藉此增加光取出效率。第二窗戶層的鋁含量小於第二半導體層的鋁含量且材料為Al0.2 Ga0.8 As。第二窗戶層的厚度為9mm。In one embodiment, the compositions of the first semiconductor layer 111 and the second semiconductor layer 112 both contain aluminum and have the same aluminum content. In this embodiment, the optoelectronic semiconductor device 100 further includes a second window layer (not shown) on the second semiconductor layer 112, and the thickness of the second window layer is greater than that of the second semiconductor layer 112, thereby increasing the light extraction efficiency . The aluminum content of the second window layer is smaller than that of the second semiconductor layer and the material is Al 0.2 Ga 0.8 As. The thickness of the second window layer is 9mm.

一實施例中，活性結構113具有多層量子井(multiple quantum wells)結構，包含在堆疊方向(如第1圖的Z方向)上交替堆疊的複數個量子井層(quantum well layer)與複數個阻障層(barrier layer)，且阻障層的能障大於量子井層，藉此限制載子分布。此外，複數個量子井層彼此之間可以具有相同或不同的材料組成及能障，在此係不多做限制。一實施例中，複數阻障層的其中之一具有鋁元素，且其鋁含量與第一半導體層111的鋁含量不同，具體而言，複數阻障層的其中之一的鋁含量小於第一半導體層111的鋁含量。一實施例中，第一半導體層111具有鋁元素，阻障層的其中之一具有鋁元素。在一實施例中，第一半導體層111的鋁含量與阻障層的其中之一的鋁含量之差異至少為8%，較佳為10～25%，更佳為12～20%。或者，複數阻障層中每一層皆具有鋁元素，且每一層中的鋁含量皆小於第一半導體層111的鋁含量。一實施例中，每一阻障層中的鋁含量與第一半導體層111的鋁含量之差異至少為8%，較佳為10～25%，更佳為12～20%。In one embodiment, the active structure 113 has a multiple quantum wells structure, including a plurality of quantum well layers and a plurality of resistive well layers alternately stacked in a stacking direction (eg, the Z direction in FIG. 1 ). A barrier layer, and the energy barrier of the barrier layer is larger than the quantum well layer, thereby limiting the carrier distribution. In addition, the plurality of quantum well layers may have the same or different material compositions and energy barriers, which are not limited here. In one embodiment, one of the plurality of barrier layers has aluminum element, and its aluminum content is different from that of the first semiconductor layer 111 . Specifically, the aluminum content of one of the plurality of barrier layers is smaller than that of the first semiconductor layer 111 . The aluminum content of the semiconductor layer 111 . In one embodiment, the first semiconductor layer 111 has aluminum element, and one of the barrier layers has aluminum element. In one embodiment, the difference between the aluminum content of the first semiconductor layer 111 and the aluminum content of one of the barrier layers is at least 8%, preferably 10-25%, more preferably 12-20%. Alternatively, each of the plurality of barrier layers has aluminum element, and the aluminum content of each layer is smaller than that of the first semiconductor layer 111 . In one embodiment, the difference between the aluminum content of each barrier layer and the aluminum content of the first semiconductor layer 111 is at least 8%, preferably 10-25%, more preferably 12-20%.

第一半導體層111、第二半導體層112及活性結構113的折射率(refractive index)可依其材料的元素組成改變。在本實施例中，第一半導體層111、第二半導體層112及活性結構113的材料為AlGaAs，且當鋁含量越高，其折射率越低，兩者大致呈線性關係，例如：折射率n與鋁含量x的關係為n=3.3-0.53x+0.09x2 。一實施例中，第一半導體層111具有第一折射率，活性結構113之阻障層的其中之一具有第二折射率。第一折射率與第二折射率的差異至少為0.04。The refractive indices of the first semiconductor layer 111 , the second semiconductor layer 112 and the active structure 113 can be changed according to the elemental composition of their materials. In this embodiment, the materials of the first semiconductor layer 111 , the second semiconductor layer 112 and the active structure 113 are AlGaAs, and the higher the aluminum content, the lower the refractive index, and the two are approximately linearly related, for example: the refractive index The relationship between n and the aluminum content x is n=3.3-0.53x+0.09x 2 . In one embodiment, the first semiconductor layer 111 has a first refractive index, and one of the barrier layers of the active structure 113 has a second refractive index. The difference between the first refractive index and the second refractive index is at least 0.04.

本揭露並不限於如第1圖所示之單一半導體疊層1的結構。其它實施例中，光電半導體裝置100可具有多個半導體疊層配置在第一電極結構2及第二電極結構36之間，例如配置在第一電極結構2及第一窗戶層34之間。所述多個半導體疊層可具有相同或不同的結構及/或性質。一實施例中，半導體裝置具有兩個半導體疊層的結構，例如在第1圖所示之半導體疊層1的上方或下方可配置另一半導體疊層，此設計優點之一係可以增加半導體裝置的發光效率。所述另一半導體疊層可類似半導體疊層1，例如具有一第三半導體層位於半導體疊層1的第二半導體層112上、一第四半導體層位於第三半導體層上、及位在第三半導體層與第四半導體層之間的一活性結構。半導體疊層1的活性結構113(第一活性結構)與所述另一半導體疊層的活性結構(第二活性結構)可具有相同或相異的能隙以發出相同或相異波長的光。一實施例中，可在兩個半導體疊層之間配置穿隧結構。穿隧結構可為單層或多層，且每一層的摻雜濃度大於5´1018 /cm3 ，可讓電子藉由穿隧效應通過，穿隧結構的材料可以為三五族半導體，例如包含鎵(Ga)、鋁(Al)、銦(In)、磷(P)、氮(N)、鋅(Zn)、鎘(Cd)或硒(Se)之化合物。另一實施例中，穿隧結構可置換為黏結結構，用以接合其上、下方的半導體疊層。黏結結構可為單層或多層，且材料包含導電材料如金屬氧化物材料或三五族半導體材料。金屬氧化材料例如為氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋅(ZnO)、氧化鎂(MgO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化銦鋅(IZO)或氧化鉭(Ta2 O5 )；三五族半導體材料例如為砷化鋁鎵(AlGaAs)、氮化鎵(GaN)或磷化鎵(GaP)。在另一實施例中，黏結結構包含絕緣材料，例如Su8、苯并環丁烯（BCB）、過氟環丁烷（PFCB）、環氧樹脂（Epoxy）、丙烯酸樹脂（Acrylic Resin）、環烯烴聚合物（COC）、聚甲基丙烯酸甲酯（PMMA）、聚對苯二甲酸乙二酯（PET）、聚亞醯胺(PI)、聚碳酸酯（PC）、聚醚醯亞胺（Polyetherimide）、氟碳聚合物（Fluorocarbon Polymer）、玻璃(Glass)、氧化鋁(Al2 O3 )、氧化矽(SiO2 )、氧化鈦(TiO2 )、氮化矽(SiNx)、旋塗玻璃(SOG)或四乙氧基矽烷(TEOS)。The present disclosure is not limited to the structure of a single semiconductor stack 1 as shown in FIG. 1 . In other embodiments, the optoelectronic semiconductor device 100 may have a plurality of semiconductor stacks disposed between the first electrode structure 2 and the second electrode structure 36 , eg, between the first electrode structure 2 and the first window layer 34 . The plurality of semiconductor stacks may have the same or different structures and/or properties. In one embodiment, the semiconductor device has a structure of two semiconductor stacks. For example, another semiconductor stack can be arranged above or below the semiconductor stack 1 shown in FIG. 1. One of the advantages of this design is that the number of semiconductor devices can be increased. luminous efficiency. The other semiconductor stack may be similar to the semiconductor stack 1, for example, having a third semiconductor layer on the second semiconductor layer 112 of the semiconductor stack 1, a fourth semiconductor layer on the third semiconductor layer, and a third semiconductor layer on the second semiconductor layer 112 of the semiconductor stack 1. An active structure between the third semiconductor layer and the fourth semiconductor layer. The active structure 113 (first active structure) of the semiconductor stack 1 and the active structure (second active structure) of the other semiconductor stack may have the same or different energy gaps to emit light of the same or different wavelengths. In one embodiment, a tunneling structure may be configured between two semiconductor stacks. The tunneling structure can be single-layer or multi-layer, and the doping concentration of each layer is greater than 5´10 18 /cm 3 , which can allow electrons to pass through the tunneling effect. The material of the tunneling structure can be group III or five semiconductors, such as Compounds of Gallium (Ga), Aluminum (Al), Indium (In), Phosphorus (P), Nitrogen (N), Zinc (Zn), Cadmium (Cd) or Selenium (Se). In another embodiment, the tunnel structure can be replaced with a bonding structure for bonding the semiconductor stacks above and below it. The bonding structure can be a single layer or a multi-layer, and the material includes a conductive material such as a metal oxide material or a III-V semiconductor material. Metal oxide materials are, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc oxide (ZnO), magnesium oxide (MgO), Aluminum oxide zinc (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), indium zinc oxide (IZO) or tantalum oxide (Ta 2 O 5 ); Group III and V semiconductor materials such as It is aluminum gallium arsenide (AlGaAs), gallium nitride (GaN) or gallium phosphide (GaP). In another embodiment, the bonding structure includes insulating materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide (Polyetherimide) ), Fluorocarbon Polymer (Fluorocarbon Polymer), Glass (Glass), Alumina (Al 2 O 3 ), Silicon Oxide (SiO 2 ), Titanium Oxide (TiO 2 ), Silicon Nitride (SiNx), Spin-on Glass ( SOG) or tetraethoxysilane (TEOS).

第一電極結構2可位於半導體疊層1之上。第二電極結構36可位於基板30之下，但本揭露不以此為限。The first electrode structure 2 may be located on the semiconductor stack 1 . The second electrode structure 36 may be located under the substrate 30, but the present disclosure is not limited thereto.

基板30可用以支持位於其上之半導體疊層1與其它層或結構。半導體疊層1可以透過有機金屬化學氣相沉積法(MOCVD)、分子束磊晶法(MBE)或氫化物氣相磊晶法(HVPE)等磊晶方法成長於基板30或另一成長基板上，若是在成長基板上生成的半導體疊層1則可藉由基板轉移技術，將半導體疊層1接合至基板30並可選擇性地移除成長基板。在一實施例中，半導體疊層1係生長於成長基板後，再透過基板轉移技術，透過導電黏結層31接合於基板30。具體而言，基板30對於活性結構113所發射的光可為透明、半透明或不透明，亦可以為導電、半導體或絕緣。在本實施例中，光電半導體裝置100為一垂直式型態，因此，基板30係為一導電材料，且包含金屬材料、金屬合金材料、金屬氧化物材料、半導體材料或含碳材料。金屬材料包含銅(Cu)、鋁(Al)、鉻(Cr)、錫(Sn)、金(Au)、鎳(Ni)、鈦(Ti)、鉑(Pt)、鉛(Pb)、鋅(Zn)、鎘(Cd)、銻(Sb)、鉬(Mo)、鎢(W)或鈷(Co)；金屬合金材料為包含上述金屬材料之合金；金屬氧化物材料可以包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、氧化銦鋅(IZO)、氧化鎵(Ga2 O3 )、鎵酸鋰(LiGaO2 )、鋁酸鋰(LiAlO2 )或鋁酸鎂(MgAl2 O4 )；半導體材料可以包含但不限於IV族半導體或III-V族半導體，例如：矽(Si)、鍺(Ge)、碳化矽(SiC)、氮化鎵(GaN)、氮化鋁(AlN)、磷化鎵(GaP)、砷化鎵(GaAs)、磷砷化鎵(AsGaP)、硒化鋅(ZnSe)、硒化鋅(ZnSe)或磷化銦(InP)等；含碳材料可以包含但不限於類鑽碳薄膜(Diamond-Like carbon，DLC)或石墨烯。The substrate 30 may be used to support the semiconductor stack 1 and other layers or structures located thereon. The semiconductor stack 1 can be grown on the substrate 30 or another growth substrate by epitaxial methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). If the semiconductor stack 1 is formed on the growth substrate, the semiconductor stack 1 can be bonded to the substrate 30 by a substrate transfer technique and the growth substrate can be selectively removed. In one embodiment, the semiconductor stack 1 is grown on the growth substrate, and then bonded to the substrate 30 through the conductive adhesive layer 31 through a substrate transfer technique. Specifically, the substrate 30 can be transparent, translucent or opaque to the light emitted by the active structure 113, and can also be conductive, semiconductor or insulating. In the present embodiment, the optoelectronic semiconductor device 100 is a vertical type, so the substrate 30 is a conductive material, and includes a metal material, a metal alloy material, a metal oxide material, a semiconductor material or a carbonaceous material. Metal materials include copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc ( Zn), cadmium (Cd), antimony (Sb), molybdenum (Mo), tungsten (W) or cobalt (Co); the metal alloy material is an alloy containing the above metal materials; the metal oxide material can include but is not limited to indium oxide Tin (ITO), Indium Oxide (InO), Tin Oxide (SnO), Cadmium Tin Oxide (CTO), Antimony Tin Oxide (ATO), Alumina Zinc Oxide (AZO), Zinc Tin Oxide (ZTO), Gallium Zinc Oxide (GZO) ), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium oxide (Ga 2 O 3 ), lithium gallate (LiGaO 2 ), lithium aluminate (LiAlO 2 ) or magnesium aluminate (MgAl 2 O 4 ); semiconductor materials may include, but are not limited to, group IV semiconductors or group III-V semiconductors, such as: silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), nitrogen Aluminum (AlN), Gallium Phosphide (GaP), Gallium Arsenide (GaAs), Gallium Arsenide Phosphide (AsGaP), Zinc Selenide (ZnSe), Zinc Selenide (ZnSe) or Indium Phosphide (InP), etc.; The carbonaceous material may include, but is not limited to, diamond-like carbon (Diamond-Like carbon, DLC) or graphene.

在另一實施例中，當光電半導體裝置100為非垂直式型態時，例如：第一電極結構2及第二電極結構36位於半導體疊層1的同一側之水平式型態，基板30可包含絕緣材料，例如藍寶石(sapphire)、玻璃(glass)、石英(Quartz)、壓克力(Acryl)、環氧樹脂（Epoxy）、絕緣氮化物(如：SiN)或絕緣氧化物(如SiO2 )等。在本實施例中，光電半導體裝置為近場紅外線發光元件，且基板30的材料包含磷化銦(InP)或砷化鎵(GaAs)，例如基板30的材料為InP或GaAs或者實質上由InP或GaAs所組成。In another embodiment, when the optoelectronic semiconductor device 100 is of a non-vertical type, such as a horizontal type in which the first electrode structure 2 and the second electrode structure 36 are located on the same side of the semiconductor stack 1 , the substrate 30 can be Contains insulating materials such as sapphire, glass, Quartz, Acryl, Epoxy, insulating nitrides (eg SiN) or insulating oxides (eg SiO 2 ) )Wait. In this embodiment, the optoelectronic semiconductor device is a near-field infrared light emitting element, and the material of the substrate 30 includes indium phosphide (InP) or gallium arsenide (GaAs), for example, the material of the substrate 30 is InP or GaAs or substantially composed of InP or GaAs.

導電黏結層31之材料可包含導電材料，例如金屬氧化物材料、半導體材料、金屬材料、金屬合金材料或含碳材料。舉例來說，金屬氧化物材料可以包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、氧化銦鈰(indium cerium oxide，ICO)、氧化銦鎢(IWO)、氧化銦鈦(indium titanium oxide，ITiO)、氧化銦鋅(IZO)、氧化銦鎵(indium gallium oxide，IGO) 、氧化鎵鋁鋅(gallium and aluminum codoped zinc oxide，GAZO)。半導體材料可以包含但不限於磷化鎵(GaP)。金屬材料可以包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、銦(In)、鉑(Pt)或鎢(W)。金屬合金材料為包含上述金屬材料之合金。含碳材料可以包含但不限於石墨烯(Graphene)。導電黏結層31可將連接基板30連接至反射結構32，且可具有複數個從屬層(未顯示)。The material of the conductive adhesive layer 31 may include conductive materials, such as metal oxide materials, semiconductor materials, metal materials, metal alloy materials or carbon-containing materials. For example, metal oxide materials may include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum oxide zinc ( AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO) ), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium and aluminum codoped zinc oxide (GAZO). The semiconductor material may include, but is not limited to, gallium phosphide (GaP). The metal material may include, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), indium (In ), platinum (Pt) or tungsten (W). The metal alloy material is an alloy containing the above-mentioned metal material. The carbonaceous material may include, but is not limited to, Graphene. The conductive adhesive layer 31 can connect the connection substrate 30 to the reflective structure 32 and can have a plurality of subordinate layers (not shown).

在一實施例中，反射結構32可用以反射來自半導體疊層1之發射光，以增加光電半導體裝置100的光取出效率。反射結構32的材料可包含但不限於金屬材料或金屬合金材料，例如：銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)；金屬合金材料為包含上述材料之合金。如第1圖所示，本實施例中，反射結構32包含一反射層326、一反射黏結層324位於反射層326之下、一阻障層322位於反射黏結層324之下、以及一電接觸層320位於阻障層322之下。反射層326可反射來自半導體疊層1之發射光。反射黏結層324可用以連接反射層326與阻障層322。阻障層322可用以防止導電黏結層31之材料於製程中擴散至反射層326而破壞反射層326的結構，藉此維持反射層326的反射率，且電接觸層320可以與下方的導電黏結層31形成低電阻的接觸。In one embodiment, the reflective structure 32 can be used to reflect the emitted light from the semiconductor stack 1 to increase the light extraction efficiency of the optoelectronic semiconductor device 100 . The material of the reflective structure 32 may include, but is not limited to, metal materials or metal alloy materials, such as copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W); the metal alloy material is an alloy containing the above-mentioned materials. As shown in FIG. 1, in this embodiment, the reflective structure 32 includes a reflective layer 326, a reflective adhesive layer 324 under the reflective layer 326, a barrier layer 322 under the reflective adhesive layer 324, and an electrical contact Layer 320 is below barrier layer 322 . The reflection layer 326 can reflect the emitted light from the semiconductor stack 1 . The reflective adhesive layer 324 can be used to connect the reflective layer 326 and the barrier layer 322 . The barrier layer 322 can be used to prevent the material of the conductive adhesive layer 31 from diffusing to the reflective layer 326 during the manufacturing process to damage the structure of the reflective layer 326, thereby maintaining the reflectivity of the reflective layer 326, and the electrical contact layer 320 can be bonded to the underlying conductive layer Layer 31 forms a low resistance contact.

導電結構33位於第一半導體層111下方，並可對於半導體疊層1所發之發射光為透明，用以增加第一窗戶層34與反射結構32之間的電流傳導與擴散，在一些實施例中，導電結構33可與反射結構32共同形成全方位反射鏡(Omni-Directional Reflector，ODR)。導電結構33的材料可包含金屬氧化物材料、金屬材料、金屬合金材料、含碳材料或上述材料之組合。金屬氧化材料如氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)。金屬材料如金(Au)、鍺(Ge)、鈹(Be)。金屬合金材料則為包含上述金屬材料之合金。含碳材料可以包含但不限於石墨烯。The conductive structure 33 is located under the first semiconductor layer 111 and can be transparent to the emitted light from the semiconductor stack 1 to increase current conduction and diffusion between the first window layer 34 and the reflective structure 32, in some embodiments Among them, the conductive structure 33 and the reflective structure 32 can jointly form an omni-directional reflector (ODR). The material of the conductive structure 33 may include metal oxide material, metal material, metal alloy material, carbonaceous material or a combination of the above materials. Metal oxide materials such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO) , Gallium Zinc Oxide (GZO), Indium Tungsten Oxide (IWO), Zinc Oxide (ZnO), Gallium Phosphide (GaP), Indium Cerium Oxide (ICO), Indium Tungsten Oxide (IWO), Indium Titanium Oxide (ITiO), Oxide Indium Zinc (IZO), Indium Gallium Oxide (IGO), Gallium Aluminum Zinc Oxide (GAZO). Metal materials such as gold (Au), germanium (Ge), beryllium (Be). The metal alloy material is an alloy containing the above-mentioned metal materials. The carbonaceous material may include, but is not limited to, graphene.

如第1圖所示，在一實施例中，導電結構33具有一第一導電層331，位於反射結構32上方，以及一第二導電層332位於半導體疊層1與第一導電層331之間。第一導電層331與第二導電層332的材料可以不同，例如第一導電層331之材料為氧化銦鋅(IZO)，第二導電層332之材料為氧化銦錫(ITO)，但不以此為限。As shown in FIG. 1, in one embodiment, the conductive structure 33 has a first conductive layer 331 located above the reflective structure 32, and a second conductive layer 332 located between the semiconductor stack 1 and the first conductive layer 331 . The materials of the first conductive layer 331 and the second conductive layer 332 may be different, for example, the material of the first conductive layer 331 is indium zinc oxide (IZO), the material of the second conductive layer 332 is indium tin oxide (ITO), but not This is limited.

第二導電層332可與絕緣層35及/或第一窗戶層34直接接觸，且覆蓋絕緣層35至少一表面。一實施例中，第一窗戶層34之第二表面34a面向絕緣層35並朝向基板30的方向，且絕緣層35具有一上表面35a面向第一窗戶層34。在一實施例中，由光電半導體裝置100的上視觀之，上表面35a的表面積相對於第二表面34a之表面積之百分比為1.5%~50%，較佳為2%~30%，如此可使光電半導體裝置100具有較佳之發光效率。另一實施例中，絕緣層35的上表面35a可為一粗糙表面，以散射半導體疊層1所發之光而提升光電半導體裝置100之出光效率。The second conductive layer 332 may be in direct contact with the insulating layer 35 and/or the first window layer 34 and cover at least one surface of the insulating layer 35 . In one embodiment, the second surface 34 a of the first window layer 34 faces the insulating layer 35 and faces the direction of the substrate 30 , and the insulating layer 35 has an upper surface 35 a facing the first window layer 34 . In one embodiment, from the top view of the optoelectronic semiconductor device 100, the percentage of the surface area of the upper surface 35a relative to the surface area of the second surface 34a is 1.5%-50%, preferably 2%-30%, so that The optoelectronic semiconductor device 100 has better luminous efficiency. In another embodiment, the upper surface 35a of the insulating layer 35 may be a rough surface, so as to scatter the light emitted by the semiconductor stack 1 and improve the light extraction efficiency of the optoelectronic semiconductor device 100 .

如第1圖所示，在一實施例中，絕緣層35可具有圖案化分佈，例如絕緣層35的分布由俯視觀之可以呈現具規則性或非規則性。絕緣層35可設置對應於第一電極結構2下，以減少電流流經第一電極結構2下的半導體疊層1，並避免第一電極結構2下的半導體疊層1所發出的光被第一電極結構2吸收。此外，藉由絕緣層35的設置，可促使電流擴散至非第一電極結構2下半導體疊層1的位置。絕緣層35的材料可以選擇為對於半導體疊層1所發之發射光之穿透率大於90%，絕緣層35之材料可以選擇包含氧化物絕緣材料或非氧化物絕緣材料，氧化物絕緣材料例如為氧化矽(SiOx )，非氧化物絕緣材料例如為苯并環丁烯（BCB）、環烯烴聚合物（COC）、氟碳聚合物（Fluorocarbon Polymer）氟化鈣(CaF2 )、氟化鎂(MgF2 )或氮化矽(SiNx)。As shown in FIG. 1 , in one embodiment, the insulating layer 35 may have a patterned distribution, for example, the distribution of the insulating layer 35 may be regular or irregular from a top view. The insulating layer 35 may be disposed under the first electrode structure 2 to reduce the current flowing through the semiconductor stack 1 under the first electrode structure 2 and prevent the light emitted by the semiconductor stack 1 under the first electrode structure 2 from being affected by the first electrode structure 2. An electrode structure 2 absorbs. In addition, by disposing the insulating layer 35 , the current can be promoted to diffuse to the position of the semiconductor stack 1 which is not under the first electrode structure 2 . The material of the insulating layer 35 can be selected so that the transmittance of the emitted light emitted by the semiconductor stack 1 is greater than 90%. The material of the insulating layer 35 can be selected to include oxide insulating materials or non-oxide insulating materials, such as oxide insulating materials. For silicon oxide (SiO x ), non-oxide insulating materials such as benzocyclobutene (BCB), cycloolefin polymer (COC), fluorocarbon polymer (Fluorocarbon Polymer), calcium fluoride (CaF 2 ), fluorinated Magnesium (MgF 2 ) or Silicon Nitride (SiNx).

在一實施例中，絕緣層35之折射率小於第一窗戶層34之折射率，且第一窗戶層34與絕緣層35間介面之臨界角小於第一窗戶層34與導電結構33間介面的臨界角，使半導體疊層1所發之發射光射向絕緣層35後，在第一窗戶層34與絕緣層35之間的介面形成全反射的機率增加。此外，穿過第一窗戶層34與導電結構33之間的介面而進入導電結構33之光因絕緣層35具有低折射率，故在導電結構33與絕緣層35之間的介面亦可能產生全反射，因而提升光電半導體裝置100的出光效率，舉例來說，絕緣層35的折射率可以選擇小於1.7，較佳為1.3~1.6。在一實施例中，絕緣層35之厚度小於導電結構33之一半厚度。另一實施例中，絕緣層35之厚度小於導電結構33之1/5厚度，如此可避免或減少導電結構33形成後的表面平坦化製程破壞絕緣層35之結構。在一實施例中，絕緣層35至少一表面被導電結構33覆蓋，如此可增加導電結構33的接合面積，而強化絕緣層35與第一窗戶層34之間的接合，提升結構的機械強度。在一實施例中，複數個孔隙351形成於絕緣層35之中，且導電結構33填入複數個孔隙351中，並與第一窗戶層34直接接觸以形成電性連接。In one embodiment, the refractive index of the insulating layer 35 is smaller than the refractive index of the first window layer 34 , and the critical angle of the interface between the first window layer 34 and the insulating layer 35 is smaller than that of the interface between the first window layer 34 and the conductive structure 33 . At the critical angle, after the light emitted from the semiconductor stack 1 is directed to the insulating layer 35 , the probability of total reflection at the interface between the first window layer 34 and the insulating layer 35 is increased. In addition, the light entering the conductive structure 33 through the interface between the first window layer 34 and the conductive structure 33 may have a low refractive index at the interface between the conductive structure 33 and the insulating layer 35 due to the low refractive index of the insulating layer 35 . Therefore, the light extraction efficiency of the optoelectronic semiconductor device 100 is improved. For example, the refractive index of the insulating layer 35 can be selected to be less than 1.7, preferably 1.3 to 1.6. In one embodiment, the thickness of the insulating layer 35 is less than half the thickness of the conductive structure 33 . In another embodiment, the thickness of the insulating layer 35 is less than 1/5 of the thickness of the conductive structure 33 , so as to avoid or reduce the surface planarization process after the conductive structure 33 is formed from damaging the structure of the insulating layer 35 . In one embodiment, at least one surface of the insulating layer 35 is covered by the conductive structure 33 , which increases the bonding area of the conductive structure 33 , strengthens the bonding between the insulating layer 35 and the first window layer 34 , and improves the mechanical strength of the structure. In one embodiment, a plurality of holes 351 are formed in the insulating layer 35 , and the conductive structures 33 are filled in the plurality of holes 351 and are in direct contact with the first window layer 34 to form electrical connection.

第一窗戶層34之導電性可與第一半導體層111之導電性相同，例如同為n型或p型，第一窗戶層34對於半導體疊層1所發之發射光為透明，其材料可包含金屬氧化物材料或半導體材料，金屬氧化物材料如氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、氧化鎂(MgO)、或氧化銦鋅(IZO)；半導體材料例如為砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)、氮化鎵(GaN)、磷化鎵(GaP)。The conductivity of the first window layer 34 can be the same as the conductivity of the first semiconductor layer 111 , for example, both are n-type or p-type. The first window layer 34 is transparent to the light emitted by the semiconductor stack 1 , and its material can be Contains metal oxide materials or semiconductor materials, metal oxide materials such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum oxide zinc (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), magnesium oxide (MgO), or indium zinc oxide (IZO); semiconductor material such as arsenic Gallium Nitride (GaAs), Aluminum Gallium Arsenide (AlGaAs), Gallium Nitride (GaN), Gallium Phosphide (GaP).

第一電極結構2及第二電極結構36位於半導體疊層1的相對兩側，以形成一垂直型的光電半導體裝置100。如圖所示之光電半導體裝置100之結構僅為例示，並非用以限制，例如在本揭露內容的一些實施例中，第一電極結構2與第二電極結構36亦可位於半導體疊層1的同一側，以形成一水平式的半導體裝置。第一電極結構2與第二電極結構36均可用以連接外部電源並提供電流使半導體疊層1發光。一實施例中，第二電極結構36係形成於基板30的背面，第二電極結構36的材料可以與第一電極結構2的材料相同或不同，第一電極結構2與第二電極結構36的材料可包含金屬材料、合金材料、金屬氧化物材料、或含碳材料。舉例來說，金屬材料可以包含但不限於鋁(Al)、鉻(Cr)、銅(Cu)、錫(Sn)、金(Au)、鎳(Ni)、鈦(Ti)、鉑(Pt)、鉛(Pb)、鋅(Zn)、鎘(Cd)、銻(Sb)或鈷(Co)，合金材料包含上述金屬組合的合金，且金屬氧化物材料可以包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、或氧化銦鋅(IZO)。含碳材料可以包含但不限於類鑽碳薄膜(DLC)或石墨烯。The first electrode structure 2 and the second electrode structure 36 are located on opposite sides of the semiconductor stack 1 to form a vertical optoelectronic semiconductor device 100 . The structure of the optoelectronic semiconductor device 100 shown in the figure is only an example, and is not intended to be limiting. For example, in some embodiments of the present disclosure, the first electrode structure 2 and the second electrode structure 36 may also be located in the semiconductor stack 1 . on the same side to form a horizontal semiconductor device. Both the first electrode structure 2 and the second electrode structure 36 can be used for connecting an external power source and supplying current to make the semiconductor stack 1 emit light. In one embodiment, the second electrode structure 36 is formed on the backside of the substrate 30 , and the material of the second electrode structure 36 may be the same as or different from the material of the first electrode structure 2 . The material may comprise a metal material, an alloy material, a metal oxide material, or a carbonaceous material. For example, the metal material may include, but is not limited to, aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt) , lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb) or cobalt (Co), the alloy material includes an alloy of the above metal combinations, and the metal oxide material may include but is not limited to indium tin oxide (ITO ), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), oxide Indium tungsten (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). The carbonaceous material may include, but is not limited to, diamond-like carbon thin film (DLC) or graphene.

如第3圖所示，光電半導體裝置100’與光電半導體裝置100具有類似的結構，相關描述可參考前面段落，於此將不再撰述。第二導電層332係位於第一窗戶層34及絕緣層35之間。第二導電層332直接接觸第一窗戶層34，絕緣層35直接接觸第二導電層332而無直接接觸第一窗戶層34。第一導電層331填入孔隙351中，且透過第二導電層332與第一窗戶層34電性連接。絕緣層35圖案化分布於第二導電層332下方，上表面35a的表面積為第二表面34a的表面積之1.5%~50%，較佳為2%~30%，如此可使光電半導體裝置100具有較佳之發光效率。As shown in FIG. 3, the optoelectronic semiconductor device 100' and the optoelectronic semiconductor device 100 have similar structures, and the related descriptions can be referred to the previous paragraphs, which will not be repeated here. The second conductive layer 332 is located between the first window layer 34 and the insulating layer 35 . The second conductive layer 332 directly contacts the first window layer 34 , and the insulating layer 35 directly contacts the second conductive layer 332 without directly contacting the first window layer 34 . The first conductive layer 331 is filled in the pores 351 and is electrically connected to the first window layer 34 through the second conductive layer 332 . The insulating layer 35 is patterned and distributed under the second conductive layer 332, and the surface area of the upper surface 35a is 1.5%-50% of the surface area of the second surface 34a, preferably 2%-30%, so that the optoelectronic semiconductor device 100 can have Better luminous efficiency.

一實施例中，當提供一電流至光電半導體裝置100中，該電流大於3.5A或半導體疊層1的電流密度大於3.5 A/mm2 時，半導體疊層1放射出之發射光的發光光譜具有兩個波峰位置(峰值波長)，即第一波峰位置w1與第二波峰位置w2，於一實施例中，第一波峰位置w1與第二波峰位置w2皆大於900 nm或者大於930 nm。第二波峰位置w2大於第一波峰位置w1(即：w2＞w1)，且第一波峰位置w1及第二波峰位置w2之間彼此分開一距離且具有分離率為0.5%～10%，較佳為1%～6%。分離率係符合以下公式(一)： 分離率

Figure 02_image005
...公式(一)In one embodiment, when a current is supplied to the optoelectronic semiconductor device 100 and the current is greater than 3.5 A or the current density of the semiconductor stack 1 is greater than 3.5 A/mm 2 , the emission spectrum of the emitted light from the semiconductor stack 1 has The two peak positions (peak wavelengths), namely the first peak position w1 and the second peak position w2, in one embodiment, both the first peak position w1 and the second peak position w2 are greater than 900 nm or greater than 930 nm. The second wave crest position w2 is greater than the first wave crest position w1 (ie: w2>w1), and the first wave crest position w1 and the second wave crest position w2 are separated from each other by a distance with a separation rate of 0.5% to 10%, preferably 1% to 6%. The separation rate is in accordance with the following formula (1): Separation rate
Figure 02_image005
...Formula (1)

或者，光電半導體裝置100係可以透過前述之鋁含量差異、折射率差異，於通電後，放射出之發射光的發光光譜具有兩個波峰位置，即第一波峰位置w1與第二波峰位置w2。兩個峰值位置之分離率為0.5%至10%之間，較佳為1%～6%。Alternatively, the optoelectronic semiconductor device 100 can pass through the aforementioned difference in aluminum content and refractive index, and after power-on, the emission spectrum of the emitted light has two peak positions, namely the first peak position w1 and the second peak position w2. The separation ratio between the two peak positions is between 0.5% and 10%, preferably between 1% and 6%.

第4A-4D圖係為光電半導體裝置之發光光譜具有兩個波峰位置之例示。Figures 4A-4D are examples of the light emission spectrum of the optoelectronic semiconductor device having two peak positions.

如第4A圖所示，發光光譜包含一第一波峰P1及一第二波峰P2。第一波峰P1具有第一波峰位置w1及第二波峰P2具有第二波峰位置w2。第一波峰P1更具有第一發光強度I1，且第一發光強度I1為第一波峰位置w1在一範圍內(例如：第一波峰位置w1±3 nm)具有相對的最大強度。類似地，第二波峰P2更具有第二發光強度I2，且第二發光強度I2為第二波峰位置w2在一範圍內(例如：第二波峰位置w2±3nm)具有相對的最大強度。第二波峰位置w2大於第一波峰位置w1。第一發光強度I1與第二發光強度I2可相同或不同。在一實施例中，第一發光強度I1大於第二發光強度I2。於本實施例中，第二發光強度I2大於第一發光強度I1，且第二發光強度對於第一發光強度的較佳具有一比值為0.2～2，且上述比值更佳為1.1～1.5。第一波峰位置w1與第二波峰位置w2皆大於900 nm，詳言之， 第一波峰位置w1為946 nm，第二波峰位置w2為956 nm，分離率約為1.06 %。As shown in FIG. 4A , the emission spectrum includes a first peak P1 and a second peak P2. The first peak P1 has a first peak position w1 and the second peak P2 has a second peak position w2. The first peak P1 further has a first luminous intensity I1, and the first luminous intensity I1 is a relative maximum intensity within a range of the first peak position w1 (eg, the first peak position w1±3 nm). Similarly, the second peak P2 further has a second luminous intensity I2, and the second luminous intensity I2 is a relative maximum intensity within a range (eg, the second peak position w2±3 nm) of the second peak position w2. The second crest position w2 is greater than the first crest position w1. The first luminous intensity I1 and the second luminous intensity I2 may be the same or different. In one embodiment, the first luminous intensity I1 is greater than the second luminous intensity I2. In this embodiment, the second luminous intensity I2 is greater than the first luminous intensity I1, and a ratio of the second luminous intensity to the first luminous intensity is preferably 0.2˜2, and the above ratio is preferably 1.1˜1.5. The first wave peak position w1 and the second wave peak position w2 are both greater than 900 nm. Specifically, the first wave peak position w1 is 946 nm, the second wave peak position w2 is 956 nm, and the separation rate is about 1.06%.

第4B圖所示之發光光譜，其第一波峰位置w1為948 nm，第二波峰位置w2為974 nm，分離率約為2.74%。In the luminescence spectrum shown in Figure 4B, the first peak position w1 is 948 nm, the second peak position w2 is 974 nm, and the separation rate is about 2.74%.

第4C圖所示之發光光譜，第一波峰位置w1為908 nm，第二波峰位置w2為959 nm，分離率約為5.62%。In the luminescence spectrum shown in Figure 4C, the first peak position w1 is 908 nm, the second peak position w2 is 959 nm, and the separation rate is about 5.62%.

第4D圖所示之發光光譜，第一波峰位置w1為919 nm，第二波峰位置w2為949 nm，分離率為3.26%。In the luminescence spectrum shown in Figure 4D, the first peak position w1 is 919 nm, the second peak position w2 is 949 nm, and the separation rate is 3.26%.

上述第一波峰位置w1及第二波峰位置w2的定義將於後說明。The definitions of the first peak position w1 and the second peak position w2 will be described later.

第5圖為一實施例之光電半導體裝置於不同電流下的發光光譜。光電半導體裝置之結構可參考第1圖，第一半導體層111、第二半導體層112及活性結構113的阻障層材料皆為AlGaAs。第一半導體層111及第二半導體層112之主體材料相同且第一半導體層111及第二半導體層112具有不同的摻雜物以使其具有不同的導電性。第一半導體層111與第二半導體層112的鋁含量為36%(x1=0.36)。阻障層的數量為三層，每一阻障層的鋁含量為20%(x1=0.2)。此實施例中，第一半導體層111的鋁含量與阻障層的鋁含量的差異為16%，第二半導體層112的鋁含量與阻障層的鋁含量的差異亦為16%，且光電半導體裝置100的半導體疊層1具有一面積約為1.138 mm2 (即42 mil2 )。FIG. 5 shows the luminescence spectra of the optoelectronic semiconductor device of an embodiment under different currents. The structure of the optoelectronic semiconductor device can be referred to in FIG. 1. The barrier layer materials of the first semiconductor layer 111, the second semiconductor layer 112 and the active structure 113 are all AlGaAs. The body materials of the first semiconductor layer 111 and the second semiconductor layer 112 are the same, and the first semiconductor layer 111 and the second semiconductor layer 112 have different dopants to have different conductivity. The aluminum content of the first semiconductor layer 111 and the second semiconductor layer 112 is 36% (x1=0.36). The number of barrier layers is three, and the aluminum content of each barrier layer is 20% (x1=0.2). In this embodiment, the difference between the aluminum content of the first semiconductor layer 111 and the aluminum content of the barrier layer is 16%, the difference between the aluminum content of the second semiconductor layer 112 and the aluminum content of the barrier layer is also 16%, and the photoelectric The semiconductor stack 1 of the semiconductor device 100 has an area of about 1.138 mm 2 (ie, 42 mil 2 ).

第5圖係對上述光電半導體裝置100分別施加電流為1A、2A、3A、3.5A、4A、4.5A、4.75A、5A而得之發光光譜。在上述電流下，半導體疊層中的電流密度分別約為0.9A/mm2 、1.8A/mm2 、2.6 A/mm2 、3.0 A/mm2 、3.5 A/mm2 、4.0 A/mm2 、4.2 A/mm2 、4.4 A/mm2 ，而施加電流的時間則一致為666ms。當施加電流為1～4A時，光電半導體裝置100的發光光譜僅具有一個波峰，然而，當繼續施加電流至大於4A(即半導體疊層中的電流密度大於3.5A/mm2 時)，例如電流達4.5A時，光電半導體裝置100之發射光譜具有兩個波峰，分別為第一波峰位置在946nm的第一波峰及第二波峰位置在956 nm的第二波峰，第一波峰位置及第二波峰位置的分離率為1.06%。當施加電流為4.75 A時，波峰分離的狀況更加明顯，第一波峰位置在946 nm，第二波峰位置在960 nm，分離率為1.48%，且第一發光強度小於第二發光強度。當施加電流為5A時，第一波峰位置為947 nm，第二波峰位置為960 nm，分離率為1.37%，且第二發光強度I2大於第一發光強度I1。第一波峰位置及第二波峰位置會隨著電流不同而改變。FIG. 5 shows emission spectra obtained by applying currents of 1A, 2A, 3A, 3.5A, 4A, 4.5A, 4.75A, and 5A to the optoelectronic semiconductor device 100, respectively. At the above currents, the current densities in the semiconductor stack are about 0.9 A/mm 2 , 1.8 A/mm 2 , 2.6 A/mm 2 , 3.0 A/mm 2 , 3.5 A/mm 2 , 4.0 A/mm 2 , respectively , 4.2 A/mm 2 , 4.4 A/mm 2 , and the time for applying the current is uniformly 666ms. When the applied current is 1˜4A, the light emission spectrum of the optoelectronic semiconductor device 100 has only one peak, however, when the current is continued to be applied to more than 4A (ie, the current density in the semiconductor stack is more than 3.5A/mm 2 ), for example, the current When reaching 4.5A, the emission spectrum of the optoelectronic semiconductor device 100 has two peaks, the first peak at 946 nm and the second peak at 956 nm, the first peak and the second peak respectively. The separation rate of positions was 1.06%. When the applied current is 4.75 A, the separation of the peaks is more obvious, the first peak is at 946 nm, the second peak is at 960 nm, the separation rate is 1.48%, and the first luminescence intensity is lower than the second luminescence intensity. When the applied current is 5A, the first peak position is 947 nm, the second peak position is 960 nm, the separation rate is 1.37%, and the second luminescence intensity I2 is greater than the first luminescence intensity I1. The position of the first wave crest and the position of the second wave crest will vary with different currents.

參照第5圖所述的結果可知，當提供至半導體疊層1的電流密度大於3.5 A/mm2 時，半導體疊層1之發光光譜中可具有兩個波峰位置。Referring to the results described in FIG. 5 , it can be seen that when the current density supplied to the semiconductor stack 1 is greater than 3.5 A/mm 2 , the emission spectrum of the semiconductor stack 1 may have two peak positions.

表1列示一實施例之半導體裝置的第一半導體層112具有不同鋁含量(A-D)、鋁含量差異、折射率差異及相關光譜性質(波峰數量及波峰位置)。光譜性質係施加4.5A的電流至半導體疊層1後量測而得，半導體疊層1的電流密度約為4.0A/mm2 。半導體裝置具有如第1圖之結構。阻障層與第一半導體層的主體材料皆為AlGaAs且阻障層的鋁含量皆為20%(即x1=0.2)。由表1可知第一半導體層112的鋁含量具有36%及32%(A、B)，半導體疊層之發射光可具有兩個波峰位置；第一半導體層112的鋁含量具有28%及24%(C、D)，半導體疊層之發光光譜中只具有一個波峰位置。由此可知，當第一半導體層與阻障層之間的鋁含量差異大於8%時，及/或當第一半導體層與阻障層之間的折射率差異大於0.04時，半導體疊層之發光光譜中可具有兩個波峰位置，且兩個波峰位置的分離率為0.5%~10%。 表1   第一半導體層的鋁含量 鋁含量差異 折射率差異 波峰數量 波峰位置 A 36% 16% 0.077 2 946 nm、956 nm B 32% 12% 0.058 2 917 nm、946 nm C 28% 8% 0.039 1 948 nm D 24% 4% 0.020 1 939  Table 1 shows that the first semiconductor layer 112 of the semiconductor device of an embodiment has different aluminum contents (AD), differences in aluminum contents, differences in refractive index, and related spectral properties (number of peaks and positions of peaks). The spectral properties are measured after applying a current of 4.5 A to the semiconductor stack 1 , and the current density of the semiconductor stack 1 is about 4.0 A/mm 2 . The semiconductor device has the structure shown in FIG. 1 . The host materials of the barrier layer and the first semiconductor layer are both AlGaAs, and the aluminum content of the barrier layer is both 20% (ie x1=0.2). It can be seen from Table 1 that the aluminum content of the first semiconductor layer 112 has 36% and 32% (A, B), the emission light of the semiconductor stack can have two peak positions; the aluminum content of the first semiconductor layer 112 has 28% and 24%. %(C, D), there is only one peak position in the emission spectrum of the semiconductor stack. It can be seen that when the difference in aluminum content between the first semiconductor layer and the barrier layer is greater than 8%, and/or when the difference in refractive index between the first semiconductor layer and the barrier layer is greater than 0.04, the There can be two peak positions in the luminescence spectrum, and the separation rate of the two peak positions is 0.5% to 10%. Table 1 Aluminum content of the first semiconductor layer Differences in aluminum content Refractive Index Difference Number of crests crest position A 36% 16% 0.077 2 946 nm, 956 nm B 32% 12% 0.058 2 917 nm, 946 nm C 28% 8% 0.039 1 948nm D twenty four% 4% 0.020 1 939

第6圖為一實施例之光電半導體裝置於不同電流下的發光光譜。光電半導體裝置之結構可參考第1圖，然第二窗戶層的厚度為7mm。FIG. 6 is a light emission spectrum of an optoelectronic semiconductor device of an embodiment under different currents. The structure of the optoelectronic semiconductor device can be referred to in Figure 1, and the thickness of the second window layer is 7 mm.

第7圖為另一實施例之光電半導體於不同電流下裝置的發光光譜。光電半導體裝置之結構可參考第1圖，然，光電半導體裝置包含兩個半導體疊層，且包含一穿隧結構位於兩個半導體疊層之間。FIG. 7 shows the luminescence spectra of the optoelectronic semiconductor device of another embodiment under different currents. The structure of the optoelectronic semiconductor device can be referred to FIG. 1. However, the optoelectronic semiconductor device includes two semiconductor stacks, and includes a tunnel structure between the two semiconductor stacks.

從第6圖及第7圖的結果可發現，跟單一半導體疊層結構相比，在提供相同的電流下，具有兩個半導體疊層的光電半導體裝置之發光光譜更容易具有兩個波峰位置。例如：施加電流達到5A(即電流密度為4.4 A/mm2 )時，具有一個半導體疊層的的光電半導體裝置才具有兩個波峰位置，然而，具有兩個半導體疊層的的光電半導體裝置在施加4A的電流(即電流密度為3.5 A/mm2 )時，即具有明顯的兩個波峰位置。當施加的電流達到5A(即電流密度為4.4 A/mm2 )時，具有兩個半導體疊層的光電半導體裝置之發光光譜具有兩個波峰的現象更加明顯。From the results in Figures 6 and 7, it can be found that, compared with the single-semiconductor stack structure, the luminescence spectrum of the optoelectronic semiconductor device with two semiconductor stacks is more likely to have two peak positions when the same current is supplied. For example, when the applied current reaches 5A (ie, the current density is 4.4 A/mm 2 ), the opto-semiconductor device with one semiconductor stack has two peak positions, however, the opto-semiconductor device with two semiconductor stacks has two peak positions. When a current of 4A is applied (ie, the current density is 3.5 A/mm 2 ), there are two distinct peak positions. When the applied current reaches 5A (ie, the current density is 4.4 A/mm 2 ), the phenomenon that the light emission spectrum of the optoelectronic semiconductor device with two semiconductor stacks has two peaks is more obvious.

第8圖為一實施例之光電半導體裝置於不同施加電流時間下的發光光譜。光電半導體裝置之結構可參考第1圖，且施加電流為5A，且施加電流的時間，如：5ms、10ms、25ms、50ms、100ms、500ms、1ms、2ms。從第8圖顯示的趨勢可知，當施加電流的時間越長時，半導體疊層之發光光譜更容易具有兩個波峰位置。如第8圖所示，當施加電流的時間為500ms時，半導體疊層的發光光譜出現了兩個波峰位置，而在增加施加電流的時間至1ms及2ms時，發光光譜具有兩個波峰的情況更為明顯。FIG. 8 shows the luminescence spectra of the optoelectronic semiconductor device of an embodiment under different current application times. Refer to Figure 1 for the structure of the optoelectronic semiconductor device, and the applied current is 5A, and the current applied time is 5ms, 10ms, 25ms, 50ms, 100ms, 500ms, 1ms, 2ms. It can be seen from the trend shown in FIG. 8 that when the current is applied for a longer time, the emission spectrum of the semiconductor stack is more likely to have two peak positions. As shown in Fig. 8, when the current application time is 500ms, the emission spectrum of the semiconductor stack has two peak positions, and when the current application time is increased to 1ms and 2ms, the emission spectrum has two peaks more obvious.

第9圖為另一實施例之光電半導體裝置的發光光譜。光電半導體裝置之結構可參考第1圖，然，光電半導體裝置不具有絕緣層，即絕緣層的上表面的表面積相對於第一窗戶層的第二表面的表面積之百分比為0%，因此導電結構完全與第一窗戶層接觸。FIG. 9 is a light emission spectrum of an optoelectronic semiconductor device according to another embodiment. The structure of the optoelectronic semiconductor device can refer to Figure 1. However, the optoelectronic semiconductor device does not have an insulating layer, that is, the percentage of the surface area of the upper surface of the insulating layer relative to the surface area of the second surface of the first window layer is 0%, so the conductive structure Make full contact with the first window layer.

第10圖為第1A圖之光電半導體裝置的發光光譜，此光電半導體裝置具有圖形化的絕緣層。Fig. 10 is a light emission spectrum of the optoelectronic semiconductor device of Fig. 1A, which has a patterned insulating layer.

第9、10圖皆為施加5A的電流(即電流密度為4.4 A/mm2 )、施加電流的時間為100 ms於光電半導體裝置時所獲得之發光光譜。從第9、10圖顯示的結果可知，當絕緣層的上表面的表面積相對於第一窗戶層的第二表面的表面積之百分比越大時，半導體疊層之發光光譜更容易具有兩個波峰位置。Figures 9 and 10 are the luminescence spectra obtained when a current of 5 A (ie, a current density of 4.4 A/mm 2 ) was applied to the optoelectronic semiconductor device for a duration of 100 ms of current application. From the results shown in Figures 9 and 10, it can be seen that when the percentage of the surface area of the upper surface of the insulating layer relative to the surface area of the second surface of the first window layer is larger, the emission spectrum of the semiconductor stack is more likely to have two peak positions .

上述第一波峰位置w1及第二波峰位置w2可由直接數值判讀或透過數據處理軟體分析等方式而得。如第4A或4B圖所示，當發光光譜具有兩個相對高強度的明顯波峰位置時，第一波峰位置w1及第二波峰位置w2可直接由數值判讀，即具有相對高強度的強度數值所對應的波長定義為第一波峰位置w1及第二波峰位置w2。當第一波峰位置w1及第二波峰位置w2無法用直接數值判讀方式判定時，可使用數據處理軟體(例如:originLab) 方式而得到第一波峰位置w1及第二波峰位置w2，如第4C或4D圖所示。簡言之，將發光光譜的數值匯入originLab並藉由curve fitting功能得到一回歸曲線。此回歸曲線相對於發光光譜的數值具有一決定係數(Coefficient of determination，R2 )，當該決定係數大於或等於0.95時，即可定義出第一波峰位置w1及第二波峰位置w2。The first wave crest position w1 and the second wave crest position w2 can be obtained by direct numerical interpretation or through data processing software analysis. As shown in Fig. 4A or 4B, when the luminescence spectrum has two obvious peak positions with relatively high intensity, the first peak position w1 and the second peak position w2 can be directly interpreted by numerical value, that is, the intensity value with relatively high intensity is determined by the numerical value. The corresponding wavelengths are defined as the first peak position w1 and the second peak position w2. When the first wave crest position w1 and the second wave crest position w2 cannot be determined by direct numerical interpretation, data processing software (for example: originLab) can be used to obtain the first wave crest position w1 and the second wave crest position w2, such as 4C or 4D figure shown. In short, the values of the luminescence spectrum are imported into originLab and a regression curve is obtained by the curve fitting function. The regression curve has a coefficient of determination (R 2 ) relative to the value of the luminescence spectrum. When the coefficient of determination is greater than or equal to 0.95, the first peak position w1 and the second peak position w2 can be defined.

具體而言，首先，當將光電半導體裝置的發光光譜以OriginLab 2017版本進行分析時，發光光譜中具有最高強度所對應的波長位置定義為預設值(Wx)。接著，依次序選取下列的選項：analysis→fitting→nonlinear curve fitting。在setting標籤的function selection中的Function下拉選擇Gauss，並至Advanced中的Number of Replicas下拉選擇1，以模擬出兩個高斯分布曲線。兩個高斯分布曲線分別具有兩個預設波峰位置(xc及xc_2，且xc＞xc_2)。Specifically, first, when analyzing the luminescence spectrum of the optoelectronic semiconductor device in OriginLab 2017 version, the wavelength position corresponding to the highest intensity in the luminescence spectrum is defined as a preset value (Wx). Next, select the following options in order: analysis→fitting→nonlinear curve fitting. Select Gauss from the Function drop-down in the function selection of the setting tab, and select 1 from the Number of Replicas drop-down in Advanced to simulate two Gaussian distribution curves. The two Gaussian distribution curves have two preset peak positions (xc and xc_2, and xc>xc_2).

接著，若前述之最高強度所對應的波長位置較接近xc，則至Parameters標籤中，將Wx輸入xc的欄位中。若前述之最高強度所對應的波長位置較接近xc_2，將Wx輸入xc_2的欄位中，並將該欄位的Fixed打勾，接著按下代表"Fit until converged"的按鈕進行運算。然後，將Fixed欄位的打勾取消，再按下代表"Fit until converged"的按鈕進行運算。若運算結果的決定係數大於或等於0.95即完成運算。此時，在xc欄位的數值即代表第一波峰位置(w1)，在xc_2的波長即代表第二波峰位置(w2)。若運算結果的決定係數小於0.95，則調整在"Param"中的參數(例如：y0、xc、w、A、xc_2、w_2、A_2)，直到決定係數不小於0.95即完成運算。在調整參數的過程中，實際上可以一次選擇一個參數，輸入數值至相對應的欄位中，並將該欄位的Fixed打勾，接著按下代表"Fit until converged"的按鈕進行運算。然後，將Fixed欄位的打勾取消，再按下代表"Fit until converged"的按鈕進行運算。Next, if the wavelength position corresponding to the aforementioned highest intensity is closer to xc, then go to the Parameters tab and input Wx into the field of xc. If the wavelength position corresponding to the highest intensity mentioned above is closer to xc_2, enter Wx into the field of xc_2, tick the Fixed in this field, and then press the button representing "Fit until converged" to perform the calculation. Then, uncheck the Fixed field, and press the button representing "Fit until converged" to perform the calculation. If the coefficient of determination of the operation result is greater than or equal to 0.95, the operation is completed. At this time, the value in the xc column represents the first peak position (w1), and the wavelength in xc_2 represents the second peak position (w2). If the coefficient of determination of the operation result is less than 0.95, adjust the parameters in "Param" (eg: y0, xc, w, A, xc_2, w_2, A_2) until the coefficient of determination is not less than 0.95 to complete the operation. In the process of adjusting parameters, you can actually select one parameter at a time, enter the value into the corresponding field, tick the Fixed in the field, and then press the button representing "Fit until converged" to perform the operation. Then, uncheck the Fixed field, and press the button representing "Fit until converged" to perform the calculation.

第11圖為本揭露內容一實施例之光電半導體裝置的封裝結構示意圖。請參照第11圖，封裝結構200包含光電半導體裝置100、封裝基板21、載體23、接合線25、接觸結構26以及封裝材料28。封裝基板21可包含陶瓷或玻璃材料。封裝基板21中具有多個通孔22。通孔22中可填充有導電性材料如金屬等而有助於導電或/且散熱。載體23位於封裝基板21一側的表面上，且亦包含導電性材料，如金屬。接觸結構26位於封裝基板21另一側的表面上。在本實施例中，接觸結構26包含接觸墊26a以及接觸墊26b，且接觸墊26a以及接觸墊26b可藉由通孔22而與載體23電性連接。在一實施例中，接觸結構26可進一步包含散熱墊(thermal pad)(未繪示)，例如位於接觸墊26a與接觸墊26b之間。光電半導體裝置100位於載體23上，且可為本揭露內容任一實施例所述的光電半導體裝置。在本實施例中，載體23包含第一部分23a及第二部分23b，光電半導體裝置100藉由接合線25而與載體23的第二部分23b電性連接。接合線25的材質可包含金屬，例如金、銀、銅、鋁或至少包含上述任一元素之合金。封裝材料28覆蓋於光電半導體裝置100上，具有保護光電半導體裝置100之效果。具體來說，封裝材料28可包含樹脂材料如環氧樹脂(epoxy)、矽氧烷樹脂(silicone)等。封裝材料28更可包含複數個波長轉換粒子(圖未示)以轉換光電半導體裝置100所發出的第一光為一第二光。第二光的波長大於第一光的波長。在其他實施例中，上述封裝結構200中的光電半導體裝置100可以為光電半導體裝置100’，或者，在一些實施例中，封裝結構200包含多個光電半導體裝置100及/或100’，且該些多個光電半導體裝置100及/或100’可以串聯、並聯或串並連接。FIG. 11 is a schematic diagram of a package structure of an optoelectronic semiconductor device according to an embodiment of the disclosure. Referring to FIG. 11 , the package structure 200 includes an optoelectronic semiconductor device 100 , a package substrate 21 , a carrier 23 , bonding wires 25 , a contact structure 26 and a package material 28 . The package substrate 21 may contain ceramic or glass materials. The package substrate 21 has a plurality of through holes 22 therein. The through holes 22 may be filled with conductive materials such as metal to facilitate conduction and/or heat dissipation. The carrier 23 is located on the surface of one side of the package substrate 21 , and also includes a conductive material, such as metal. The contact structure 26 is located on the surface of the other side of the package substrate 21 . In this embodiment, the contact structure 26 includes a contact pad 26 a and a contact pad 26 b , and the contact pad 26 a and the contact pad 26 b can be electrically connected to the carrier 23 through the through hole 22 . In one embodiment, the contact structure 26 may further include a thermal pad (not shown), eg, between the contact pad 26a and the contact pad 26b. The optoelectronic semiconductor device 100 is located on the carrier 23 and can be the optoelectronic semiconductor device described in any of the embodiments of the present disclosure. In this embodiment, the carrier 23 includes a first portion 23 a and a second portion 23 b , and the optoelectronic semiconductor device 100 is electrically connected to the second portion 23 b of the carrier 23 through the bonding wire 25 . The material of the bonding wire 25 may include metal, such as gold, silver, copper, aluminum, or an alloy including at least any of the above elements. The packaging material 28 covers the optoelectronic semiconductor device 100 and has the effect of protecting the optoelectronic semiconductor device 100 . Specifically, the encapsulation material 28 may include resin materials such as epoxy, silicone, and the like. The packaging material 28 may further include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the optoelectronic semiconductor device 100 into a second light. The wavelength of the second light is greater than the wavelength of the first light. In other embodiments, the optoelectronic semiconductor device 100 in the above-mentioned package structure 200 may be an optoelectronic semiconductor device 100', or, in some embodiments, the package structure 200 includes a plurality of optoelectronic semiconductor devices 100 and/or 100', and the The plurality of optoelectronic semiconductor devices 100 and/or 100' may be connected in series, in parallel, or in series and parallel.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100,100’:光電半導體裝置1:半導體疊層11:第一表面111:第一半導體層112:第二半導體層113:活性結構2:第一電極結構30:基板31:導電黏結層32:反射結構320:電接觸層322:阻障層324:反射黏結層326:反射層33:導電結構331:第一導電層332:第二導電層34:第一窗戶層34a:第二表面35:絕緣層351:孔隙35a:上表面36:第二電極結構X、Z:方向25:接合線26:接觸結構200:封裝結構21:封裝基板22:通孔23:載體23a:第一部分23b:第二部分26a、26b:接觸墊28:封裝材料100,100': Optoelectronic semiconductor device 1: Semiconductor stack 11: First surface 111: First semiconductor layer 112: Second semiconductor layer 113: Active structure 2: First electrode structure 30: Substrate 31: Conductive bonding layer 32: Reflective structure 320: Electrical Contact Layer 322: Barrier Layer 324: Reflective Bonding Layer 326: Reflective Layer 33: Conductive Structure 331: First Conductive Layer 332: Second Conductive Layer 34: First Window Layer 34a: Second Surface 35: Insulating Layer 351: Aperture 35a: Upper surface 36: Second electrode structure X, Z: Direction 25: Bonding wire 26: Contact structure 200: Package structure 21: Package substrate 22: Through hole 23: Carrier 23a: First part 23b: Second part 26a, 26b: Contact pads 28: Encapsulation material

第1圖繪示根據一實施例之光電半導體裝置的剖面示意圖。 第2圖繪示根據一實施例之光電半導體裝置的上視示意圖。 第3圖繪示根據一實施例之光電半導體裝置的剖面示意圖。 第4A-4D圖為光電半導體裝置之發光光譜具有兩個波峰位置之例示。 第5圖為一實施例之光電半導體裝置於不同電流下的發光光譜。 第6圖為一實施例之光電半導體裝置於不同電流下的發光光譜。 第7圖為一實施例之光電半導體裝置於不同電流下的發光光譜。 第8圖為一實施例之光電半導體裝置於不同施加電流時間下的發光光譜。 第9圖為一實施例之光電半導體裝置的發光光譜。 第10圖為一實施例之光電半導體裝置的發光光譜。 第11圖為一實施例之光電半導體裝置的封裝結構示意圖。FIG. 1 is a schematic cross-sectional view of an optoelectronic semiconductor device according to an embodiment. FIG. 2 shows a schematic top view of an optoelectronic semiconductor device according to an embodiment. FIG. 3 is a schematic cross-sectional view of an optoelectronic semiconductor device according to an embodiment. Figures 4A-4D are examples of the light emission spectrum of the optoelectronic semiconductor device having two peak positions. FIG. 5 shows the luminescence spectra of the optoelectronic semiconductor device of an embodiment under different currents. FIG. 6 is a light emission spectrum of an optoelectronic semiconductor device of an embodiment under different currents. FIG. 7 is a light emission spectrum of an optoelectronic semiconductor device of an embodiment under different currents. FIG. 8 shows the luminescence spectra of the optoelectronic semiconductor device of an embodiment under different current application times. FIG. 9 is a light emission spectrum of an optoelectronic semiconductor device according to an embodiment. FIG. 10 is a light emission spectrum of an optoelectronic semiconductor device according to an embodiment. FIG. 11 is a schematic diagram of a package structure of an optoelectronic semiconductor device according to an embodiment.

100:光電半導體裝置 100: Optoelectronic semiconductor devices

1:半導體疊層 1: Semiconductor stack

111:第一半導體層 111: the first semiconductor layer

112:第二半導體層 112: the second semiconductor layer

113:活性結構 113: Active structure

2:第一電極結構 2: The first electrode structure

30:基板 30: Substrate

31:導電黏結層 31: Conductive bonding layer

32:反射結構 32: Reflective Structure

320:電接觸層 320: Electrical Contact Layer

322:阻障層 322: Barrier Layer

324:反射黏結層 324: Reflective bonding layer

326:反射層 326: Reflective layer

33:導電結構 33: Conductive structure

331:第一導電層 331: the first conductive layer

332:第二導電層 332: the second conductive layer

34:第一窗戶層 34: First Window Layer

35:絕緣層 35: Insulation layer

351:孔隙 351: Pore

35a:上表面 35a: upper surface

36:第二電極結構 36: Second electrode structure

X、Z:方向 X, Z: direction

11:第一表面 11: The first surface

34a:第二表面 34a: Second surface

Claims (10)

一種光電半導體裝置，包括：一第一半導體層；一第二半導體層，位於該第一半導體層上；及一活性結構，位於該第一半導體層及該第二半導體層之間；其中，在該光電半導體裝置的電流密度大於3.5A/mm2時，該光電半導體裝置具有一發光光譜包含一第一波峰位置w1及一第二波峰位置w2，w2>w1，且該第一波峰位置及該第二波峰位置具有一分離率介於0.5%~10%，且該分離率符合以下公式：
Figure 108102987-A0305-02-0030-1
 An optoelectronic semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer located on the first semiconductor layer; and an active structure located between the first semiconductor layer and the second semiconductor layer; wherein When the current density of the optoelectronic semiconductor device is greater than 3.5A/mm 2 , the optoelectronic semiconductor device has a light emission spectrum including a first peak position w1 and a second peak position w2, w2>w1, and the first peak position and the The second peak position has a separation rate between 0.5% and 10%, and the separation rate conforms to the following formula:
Figure 108102987-A0305-02-0030-1
 如申請專利範圍第1項所述之光電半導體裝置，其中該第一半導體層具有一第一鋁含量，該活性結構具有一阻障層，該阻障層具有一第二鋁含量，該第一鋁含量與該第二鋁含量的差異至少為8%。 The optoelectronic semiconductor device of claim 1, wherein the first semiconductor layer has a first aluminum content, the active structure has a barrier layer, the barrier layer has a second aluminum content, and the first The aluminum content differs from the second aluminum content by at least 8%. 如申請專利範圍第1項所述之光電半導體裝置，其中該第一半導體層與該第二半導體層具有相同的鋁含量。 The optoelectronic semiconductor device of claim 1, wherein the first semiconductor layer and the second semiconductor layer have the same aluminum content. 如申請專利範圍第1項所述之光電半導體裝置，其中該第一半導體層具有一第一折射率，該活性結構包含複數個阻障層，該些阻障層的其中之一具有一第二折射率 大於該第一折射率，該第一折射率與該第二折射率的差異至少為0.04。 The optoelectronic semiconductor device of claim 1, wherein the first semiconductor layer has a first refractive index, the active structure includes a plurality of barrier layers, and one of the barrier layers has a second refractive index refractive index Greater than the first refractive index, the difference between the first refractive index and the second refractive index is at least 0.04. 如申請專利範圍第1項所述之光電半導體裝置，更包含一絕緣層位於該第一半導體層下方，該絕緣層係圖形化以與部分的該第一半導體層電性連接。 The optoelectronic semiconductor device as described in item 1 of the claimed scope further comprises an insulating layer located under the first semiconductor layer, and the insulating layer is patterned to be electrically connected with a part of the first semiconductor layer. 如申請專利範圍第5項所述之光電半導體裝置，其中該絕緣層具有一面積為該第一半導體層的面積的1.5%-50%。 The optoelectronic semiconductor device of claim 5, wherein the insulating layer has an area of 1.5%-50% of the area of the first semiconductor layer. 如申請專利範圍第1項所述之光電半導體裝置，其中該第一波峰位置與該第二波峰位置皆大於750nm。 The optoelectronic semiconductor device as described in claim 1, wherein both the first peak position and the second peak position are greater than 750 nm. 如申請專利範圍第1項所述之光電半導體裝置，其中該發射光在該第一波峰位置具有一第一發光強度，且在該第二波峰位置具有一第二發光強度，該第二發光強度不同於該第一發光強度。 The optoelectronic semiconductor device of claim 1, wherein the emitted light has a first luminous intensity at the first peak position, and has a second luminous intensity at the second peak position, the second luminous intensity different from the first luminous intensity. 如申請專利範圍第1項所述之光電半導體裝置，其中該活性結構為第一活性結構，該光電半導體裝置更包括一第三半導體層位於該第二半導體層上、一第四半導體層位於該第三半導體層上、及一第二活性結構位於該第三半導層與該第四半導體層之間。 The optoelectronic semiconductor device as described in claim 1, wherein the active structure is a first active structure, the optoelectronic semiconductor device further comprises a third semiconductor layer on the second semiconductor layer, and a fourth semiconductor layer on the On the third semiconductor layer, and a second active structure is located between the third semiconductor layer and the fourth semiconductor layer. 如申請專利範圍第1項所述之光電半導體裝置，其中該分離率為1%~6%。 The optoelectronic semiconductor device as described in claim 1, wherein the separation rate is 1% to 6%.
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TW200411031A (en) * 2002-03-22 2004-07-01 Nichia Corp Nitride phosphor and method for preparation thereof, and light emitting device
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Publication number Priority date Publication date Assignee Title
TW200411031A (en) * 2002-03-22 2004-07-01 Nichia Corp Nitride phosphor and method for preparation thereof, and light emitting device
TW201733180A (en) * 2015-12-01 2017-09-16 半導體能源研究所股份有限公司 Light-emitting element, light-emitting device, electronic device, and lighting device

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