CN220569701U

CN220569701U - Semiconductor element and semiconductor assembly

Info

Publication number: CN220569701U
Application number: CN202222719593.XU
Authority: CN
Inventors: 颜世男; 叶博文
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2020-12-23
Filing date: 2021-12-08
Publication date: 2024-03-08
Anticipated expiration: 2031-12-08
Also published as: CN217740551U; TW202226614A

Abstract

The utility model discloses a semiconductor element, which comprises an epitaxial structure, a first electrode and a second electrode. The first epitaxial stack has a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, and a first active region between the first semiconductor structure and the second semiconductor structure. The contact portion contacts the first semiconductor structure and has an opening of a first width. The insulating portion contacts the contact portion and has a first aperture of a second width. The first electrode is located on the second semiconductor structure and comprises an electrode pad and an extension electrode. The opening, the first hole and the electrode pad are overlapped in a vertical direction, the contact part and the extension electrode are overlapped in a vertical direction, and the first width is different from the second width.

Description

Semiconductor element and semiconductor assembly

The present application is a divisional application of China patent application (application No. 202123062555.3, application date: 2021, 12, 08, title of utility model: semiconductor element).

Technical Field

The present utility model relates to semiconductor devices, and more particularly to semiconductor light emitting devices, such as light emitting diodes.

Background

The use of semiconductor devices is very wide, and development and research of related materials are continuously being conducted. For example, III-V semiconductor materials containing III-V elements can be used in various optoelectronic semiconductor devices such as light emitting diodes (Light emitting diode, LEDs), laser Diodes (LDs), photodetectors or Solar cells (Solar cells), or can be power devices such as switches or rectifiers, which can be used in the fields of lighting, medical treatment, display, communication, sensing, power systems, etc. A light emitting diode, which is one of semiconductor light emitting elements, has advantages of low power consumption, long life, and the like, and thus is widely used.

Disclosure of Invention

The utility model aims to provide a semiconductor element for solving the problems existing in the prior art.

The present utility model provides a semiconductor element comprising: an epitaxial structure comprising a first epitaxial stack including a first semiconductor structure, a second semiconductor structure and a first active region between the first semiconductor structure and the second semiconductor structure, the second semiconductor structure having a different conductivity type than the first semiconductor structure; a plurality of contact portions under and contacting the first semiconductor structure; a plurality of insulating parts positioned below and contacting the contact part; a first electrode on the second semiconductor structure and including an electrode pad and an extension electrode; the contact part, the insulating part and the electrode pad are mutually staggered in a vertical direction, and the contact part and the extension electrode are overlapped in the vertical direction.

In a cross-sectional view, the semiconductor device further includes a first aperture disposed between two adjacent contact portions and a second aperture disposed between two adjacent insulating portions, the first aperture and the second aperture overlapping the electrode pad in the vertical direction.

In a horizontal direction, the width of the first aperture and the width of the second aperture are larger than the width of the electrode pad.

The thickness of the contact portion is smaller than the thickness of the insulating portion.

The width of the first hole is smaller than the width of the second hole in a horizontal direction.

The first semiconductor structure is provided with a first surface facing the first active region and a second surface contacting the contact part, and the width of the first surface is smaller than that of the second surface.

The semiconductor device further includes a conductive layer under the insulating portion, the conductive layer contacting the insulating portion and filling the first and second voids.

The conductive layer is filled in contact with the contact portion.

The conductive layer is connected with the first semiconductor structure.

The second hole overlaps the plurality of contact portions in the vertical direction.

The light emitted from the semiconductor element is infrared light.

The peak wavelength of the light-emitting wavelength of the first active region is 730nm to 1100nm.

The epitaxial structure further comprises a second epitaxial layer stack on the first epitaxial layer stack, the second epitaxial layer stack having a third semiconductor structure, a fourth semiconductor structure and a second active region between the third semiconductor structure and the fourth semiconductor structure, the third semiconductor structure and the fourth semiconductor structure having different conductivity types.

The semiconductor element further includes an intermediate layer between the first epitaxial layer stack and the second epitaxial layer stack, the intermediate layer comprising a pn junction.

The first active region and the second active region both emit infrared light with peak wavelength of 730nm to 1100nm.

The first semiconductor structure is p-type and the second semiconductor structure is n-type.

The semiconductor device further includes a bonding structure and a substrate, the bonding structure being located between the first epitaxial layer stack and the substrate.

The semiconductor device further includes a reflective layer between the first epitaxial layer stack and the bonding structure.

The semiconductor device further includes a second electrode connected to a side of the substrate remote from the first semiconductor structure.

The utility model further provides a semiconductor assembly comprising: packaging a substrate; the semiconductor element is positioned on the packaging substrate; and an encapsulation layer covering the semiconductor element.

The utility model has the advantages that the semiconductor element has better photoelectric performance through the design, for example: the light-emitting intensity is increased, the forward voltage (Vf) is reduced, and the light-emitting device can be applied to products in the fields of illumination, medical treatment, display, communication, sensing, power supply systems and the like, such as lamps, monitors, mobile phones, tablet computers, vehicle instrument panels, televisions, computers, wearing devices (such as watches, bracelets, necklaces and the like), traffic signs, outdoor displays, medical equipment and the like.

Drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the utility model;

fig. 2 is a schematic diagram of an epitaxial structure of a semiconductor device according to another embodiment of the present utility model;

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram illustrating a partial cross-sectional structure of a sensing module according to an embodiment of the utility model.

Symbol description

100. Semiconductor device with a semiconductor element having a plurality of electrodes

1. First epitaxial stack

11. First semiconductor structure

111. Contact portion

12. Second semiconductor structure

13. First active region

131. First well layer

132. First barrier layer

133. Second well layer

134. Second barrier layer

135. Third well layer

136. Third barrier layer

14. First confinement layer

15. Second confinement layer

2. First electrode

21. Electrode pad

22. Extension electrode

3. Second electrode

4. Conductive layer

5. Reflective layer

6. Joint structure

7. Substrate

8. Insulation part

8a pore

81. Intermediate layer

811. First heavily doped layer

812. Second heavily doped layer

9. Second epitaxial layer stack

91. Third semiconductor structure

92. Fourth semiconductor structure

93. Second active region

931. Fourth well layer

932. Fourth barrier layer

933. Fifth well layer

934. Fifth barrier layer

935. Sixth well layer

936. Sixth barrier layer

94. Third confinement layer

95. Fourth confinement layer

T1 first thickness

T2 second thickness

T3 third thickness

T4 fourth thickness

300. Semiconductor assembly

31. Packaging substrate

32. Through hole

33. Carrier body

33a first part

33b second part

35. Bonding wire

36. Contact structure

36a first contact pad

36b second contact pad

38. Encapsulation layer

400. Sensing module

420. Carrier for riding

411. First semiconductor element

431. Second semiconductor element

421. First retaining wall

422. Second retaining wall

423. Third retaining wall

424. Carrier plate

425. A first space

426. Second space

Detailed Description

The following embodiments will illustrate the concept of the present utility model with accompanying drawings in which like or identical components will be described using like or identical reference numerals, and the shapes or sizes of the elements in the drawings are merely exemplary and are not limited thereto in nature unless otherwise specified. It is to be noted that elements not shown or described in the drawings may be in a form known to those skilled in the art.

Unless otherwise specified, the general formula InGaP represents In _x0 Ga _1-x0 P, 0 therein<x0<1, a step of; alInP of the general formula represents Al _x1 In _1-x1 P, 0 therein<x1<1, a step of; alGaInP of the general formula Al _x2 Ga _x3 In _1-x2-x3 P, 0 therein<x2<1 and 0<x3<1, a step of; the general formula InGaAsP represents In _x4 Ga _1-x4 As _x5 P _1-x5 Wherein 0 is<x4<1，0<x5<1, a step of; alGaInAs of the general formula Al _x6 Ga _x7 In _1-x6-x7 As, 0 therein<x6<1，0<x7<1, a step of; inGaNAs of the formula In _x8 Ga _1-x8 N _x9 As _1-x9 Wherein 0 is<x8<1，0<x9<1, a step of; inGaAs of the general formula represents In _x10 Ga _1-x10 As, 0 therein<x10<1, a step of; alGaAs of the general formula represents Al _x11 Ga _1-x11 As, 0 therein<x11<1. The content of each element can be adjusted for different purposes, such as but not limited to adjusting the energy gap size, or when the semiconductor device is a light emitting device, the dominant wavelength (domain wavelength) or peak wavelength (peak wavelength) of the light emitting device can be adjusted accordingly.

The semiconductor element of the present utility model is, for example, a light emitting element (e.g., light-emitting diode (light-emitting diode), laser diode (laser diode)), a light absorbing element (e.g., photo-detector), or a non-light emitting element. The composition and dopant (dopant) of each layer included in the semiconductor device of the present utility model may be analyzed by any suitable means, such as a secondary ion mass spectrometer (secondary ion mass spectrometer, SIMS), and the thickness of each layer may be analyzed by any suitable means, such as a transmission electron microscope (transmission electron microscopy, TEM) or a scanning electron microscope (scanning electron microscope, SEM).

It will be appreciated by those of ordinary skill in the art that other components may be added on the basis of the embodiments described below. For example, unless specifically stated otherwise, a similar description of a "first layer (or structure) being located on a second layer (or structure) may include embodiments in which the first layer (or structure) is in direct contact with the second layer (or structure), as well as embodiments in which the first layer (or structure) and the second layer (or structure) have other structures therebetween that are not in direct contact with each other. In addition, it should be understood that the positional relationship of the layers (or structures) and the like may be changed from viewing from different orientations.

In addition, in the present utility model, the recitation of a layer or structure "consisting essentially of M" means that the layer or structure has a predominant composition of M, but does not preclude inclusion of dopants or unavoidable impurities (impurities).

Fig. 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the utility model. The semiconductor device 100 comprises an epitaxial structure, and the epitaxial structure comprises a first epitaxial stack 1. The semiconductor device 100 further includes a first electrode 2 and a second electrode 3 respectively disposed on the upper and lower sides of the first epitaxial layer 1, a conductive layer 4, a reflective layer 5, a bonding structure 6 and a substrate 7. The conductive layer 4 is located between the first epitaxial layer stack 1 and the reflective layer 5 and the bonding structure 6 is located between the substrate 7 and the reflective layer 5. As shown in fig. 1, the semiconductor device 100 optionally includes a plurality of insulating portions 8 between the conductive layer 4 and the first epitaxial layer 1, and a plurality of voids 8a between the plurality of insulating portions 8. The conductive layer 4 contacts the plurality of insulating portions 8 and fills in the plurality of voids 8a and contacts the first epitaxial stack 1. The first electrode 2 may include an electrode pad 21 and an extension electrode 22 connected to the electrode pad 21. In an embodiment, the first electrode 2 comprises only the electrode pad and no extension electrode.

The first epitaxial layer 1 comprises a first semiconductor structure 11, a second semiconductor structure 12, a first active region 13 between the first semiconductor structure 11 and the second semiconductor structure 12, a first confinement layer 14 between the first active region 13 and the first semiconductor structure 11, and a second confinement layer 15 between the first active region 13 and the second semiconductor structure 12. The first semiconductor structure 11 and the second semiconductor structure 12 may have different conductive types. For example, the first semiconductor structure 11 is n-type and the second semiconductor structure 12 is p-type; alternatively, the first semiconductor structure 11 is p-type and the second semiconductor structure 12 is n-type. Thus, the first semiconductor structure 11 and the second semiconductor structure 12 can provide electrons and holes or holes and electrons, respectively. The first semiconductor structure 11 has a first dopant and the second semiconductor structure 12 has a second dopant, such that the first semiconductor structure 11 and the second semiconductor structure 12 have different conductivities. The first dopant and the second dopant may be carbon (C), zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg), or tellurium (Te), respectively. In the present embodiment, the second semiconductor structure 12 is N-type, and the first dopant is tellurium (Te) or silicon (Si), the first semiconductorThe body structure 11 is P-type, the first dopant is magnesium (Mg) or carbon (C), and the doping concentration of the first semiconductor structure 11 and the second semiconductor structure 12 is about 5×10 ¹⁷ /cm ³ Up to 1X 10 ²⁰ /cm ³ . The energy gaps of the first semiconductor structure 11 and the second semiconductor structure 12 are larger than the first confinement layer 14 and the second confinement layer 15, respectively, thereby confining carriers further in the first active region 13.

The first epitaxial layer 1 may optionally comprise a plurality of contacts 111, seen in cross-section of the semiconductor device 100, remote from the first active region 13 and close to the conductive layer 4. The semiconductor device 100 includes a gap 111a between two adjacent contact portions 111. The plurality of contacts 111 have a first dopant, and the first dopant concentration in the plurality of contacts 111 is greater than the first dopant concentration of the first semiconductor structure 11. In the present embodiment, no contact portion 111 is provided under the electrode pad 21, that is, the electrode pad 21 and the plurality of contact portions 111 are offset from each other in the vertical direction. In other words, in the vertical direction, the electrode pad 21 overlaps the gap 111 a. In the horizontal direction, the width of the gap 111a is larger than the width of the electrode pad 21. In other embodiments, the contact portions 111, the electrode pads 21 and the extension electrodes 22 may be offset from each other. By the above-described offset relationship between the first electrode 2 and the contact portion 111, current can be prevented from being conducted directly from below the first electrode 2, thereby increasing current distribution and further improving the luminance of the semiconductor element 100. The material of the plurality of contacts 111 may comprise a III-V semiconductor material, such as a binary III-V semiconductor material, e.g., gaAs, gaP, gaN, etc.

The plurality of insulating portions 8 are located under the plurality of contact portions 111 and contact the plurality of contact portions 111. The plurality of insulating portions 8 includes a first insulating portion 81 and a second insulating portion 82. The plurality of apertures 8a includes a first aperture 8a1 located between the first insulating portion 81 and the second insulating portion 82. In one embodiment, no insulating portion 8 is disposed under the electrode pad 21, i.e., the electrode pad 21 and the plurality of insulating portions 8 are vertically offset from each other. In other words, the electrode pad 21 overlaps the first aperture 8a1 in the vertical direction. In the horizontal direction, the width of the first aperture 8a1 is larger than the width of the electrode pad 21. In one embodiment, the width of the first aperture 8a1 is greater than the width of the gap 111 a.

In an embodiment, the plurality of insulating parts 8 further includes a third insulating part 83. The plurality of apertures 8a further includes a second aperture 8a2 located between the second insulating portion 82 and the third insulating portion 83, and the second aperture 8a2 overlaps the contact portion 111 and does not overlap the electrode pad 21 in the vertical direction. In one embodiment, the conductive layer 4 may fill the first hole 8a1 and the second hole 8a2 and contact the plurality of contacts 111, and the conductive layer 4 may fill the gap 111a to connect with the first semiconductor structure 11.

The first semiconductor structure 11, the second semiconductor structure 12, the first active region 13, the first confinement layer 14 and the second confinement layer 15 may each comprise a iii-v semiconductor material. The above-mentioned group iii-v semiconductor material may contain Al, ga, as, P or In. In one embodiment, the first semiconductor structure 11, the second semiconductor structure 12, the first active region 13, the first confinement layer 14 and the second confinement layer 15 do not contain N. Specifically, the above-mentioned III-V semiconductor material may be a binary compound semiconductor (such as GaAs or GaP), a ternary compound semiconductor (such as InGaAs, alGaAs, inGaP or AlInP), or a quaternary compound semiconductor (such as AlGaInAs, alGaInP, inGaAsP, inGaAsN or AlGaAsP). In one embodiment, the first active region 13 is substantially composed of a ternary compound semiconductor (e.g., inGaAs, alGaAs, inGaP or AlInP) or a quaternary compound semiconductor (e.g., alGaInAs, alGaInP, inGaAsP or AlGaAsP).

The semiconductor device 100 may include a double heterostructure (double heterostructure, DH), a double-sided double heterostructure (DDH) or a multiple quantum well (multiple quantum wells, MQW) structure. According to an embodiment, when the semiconductor device 100 is a light emitting device, the first active region 13 can emit a light from the first semiconductor structure 11 toward the second semiconductor structure 12. The light rays include visible light or invisible light. The wavelength of the light emitted by the semiconductor device 100 is determined by the material of the first active region 13. The material of the first active region 13 may comprise InGaAs, alGaAsP or GaAsP, inGaAsP, alGaAs, alGaInAs, inGaP or AlGaInP. For example: the first active region 13 may emit infrared light having a peak wavelength of 700 to 1700nm, red light having a peak wavelength of 610 to 700nm, or yellow light having a peak wavelength of 530 to 600 nm. In the present embodiment, the first active region 13 emits infrared light having a peak wavelength of 730nm to 1100nm.

In this embodiment, the crystal system of each layer of material of the epitaxial structure is cubic (cubic) and belongs to a sphalerite structure (zincblende structure). In one embodiment, the polarization is absent from the layers of the epitaxial structure, i.e., the polarization vector of each layer is approximately zero.

With continued reference to fig. 1, the first active region 13 is located between the first confinement layer 14 and the second confinement layer 15, and in this embodiment, the first active region 13 is directly connected to the first confinement layer 14, and the first active region 13 is directly connected to the second confinement layer 15. The first active region 13 includes a first well layer 131, a first barrier layer 132, a second well layer 133 and a second barrier layer 134 sequentially stacked on the first confinement layer 14, and the first well layer 131 is closer to the first confinement layer 14 than the second well layer 133. The first active region 13 may further include a third well layer 135 and a third barrier layer 136 sequentially stacked on the second barrier layer 134, and the second well layer 133 is closer to the first confinement layer 14 than the third well layer 135. The first, second and third well layers 131, 133 and 135 include indium (In), and the indium composition ratio In the first well layer 131 is smaller than the indium composition ratio In the second well layer 133, and the indium composition ratio In the second well layer 133 is smaller than the indium composition ratio In the third well layer 135. When the first active region 13 has a plurality of well layers and barrier layers overlapping each other, the indium composition ratio of the well layers in the first active region 13 increases from the first confinement layer 14 toward the second confinement layer 15. In an embodiment, the difference in the indium composition ratio between the first well layer 131 and the second well layer 133 is 0.1% to 0.3%, the difference in the indium composition ratio between the second well layer 133 and the third well layer 135 is 0.1% to 0.3%, and the difference in the indium composition ratio between the first well layer 131 and the third well layer 133 is 0.2% to 0.6%.

In other embodiments, the first active structure 13 has a plurality of well layers (131, 133, 135) with the indium composition ratio increasing from the first confinement layer 14 to the second confinement layer 15, and a plurality of well layers with a fixed indium composition ratio are further disposed on the third well layer 135. That is, the plurality of well layers have a fixed indium composition ratio from the first confinement layer 14 toward the second confinement layer 15, and the fixed indium composition ratio is greater than that of the third well layer 135. In another embodiment, the fixed indium composition ratio is smaller than the indium composition ratio of the third well layer 135.

In one embodiment, the first confinement layer 14, the second confinement layer 15, and the barrier layer (132, 134, 136) may have the same or different energy gaps. The first confinement layer 14, the second confinement layer 15, and the barrier layer (132, 134, 136) may have the same or different materials. The energy gaps of the first confinement layer 14 and the second confinement layer 15 are larger than the energy gaps of the well layers (131, 133, 135), and can also help to confine carriers in the first active region 13.

In the present embodiment, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAs. In other embodiments, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is AlGaAsP; in another embodiment, the material of the first well layer 131 and the second well layer 133 is InGaAs, and the material of the second barrier layer 132 and the second barrier layer 134 is GaAsP. In the first active region 13 of the semiconductor device 100 of this embodiment, the thickness of the well layer (131, 133, 135) is smaller than the thickness of the barrier layer (132, 134, 136). The well layer and/or barrier layer may or may not include dopants.

In another embodiment, the thickness of the first well layer 131 is smaller than the thickness of the second well layer 133, and the thickness of the second well layer 133 is smaller than the thickness of the third well layer 135. When the first active region 13 has a plurality of well layers and barrier layers overlapping each other, the thickness of the well layers in the first active region 13 increases from the first confinement layer 14 toward the second confinement layer 15. By the above-mentioned design method of the indium composition ratio and/or thickness of the first well layer 131 and the second well layer 133, the semiconductor device 100 can have better photoelectric performance, for example: an increase in emission intensity, a decrease in forward voltage (Vf), and the like.

When the semiconductor device is a light emitting device and is driven, a phenomenon that an original peak (first signal) is shifted toward a long wavelength or a second signal of a longer wavelength appears right of the original peak occurs. The above design of the indium composition ratio and/or thickness of the first well layer 131 and the second well layer 133 is also helpful to prevent the semiconductor device from generating unexpected spectral variation, and achieve the effect of maintaining the stability of the light emitting wavelength of the semiconductor device under different current driving.

The first confinement layer 14 and the second confinement layer 15 are used to prevent carriers in the first active region 13 from overflowing. In the embodiment of the utility model, the first confinement layer 14 has a first thickness T1, and the second confinement layer 15 has a second thickness T2 greater than the first thickness T1, so as to prevent the second dopant in the second semiconductor structure 12 from entering the first active region 13 to affect the light emitting characteristic of the semiconductor device 100. In this embodiment, the first thickness T1 is, for example, 150nm to 400nm, and the second thickness T2 is, for example, 300nm to 650nm. In one embodiment, T2/T1 is greater than 2. The thicker second confinement layer 15 effectively blocks the second dopant in the second semiconductor structure 12 from entering the first active region 13, thereby reducing the dopant concentration of the second dopant in the first active region 13. In other words, the first active region 13 may have the second dopant and the dopant concentration is less than 1×10 ¹⁶ /cm ³ . By the design manner that the second thickness T2 is greater than the first thickness T1, the semiconductor device 100 can have better optoelectronic performance, for example: an increase in emission intensity, a decrease in forward voltage (Vf), and the like. In addition, the thinner first confinement layer 14 also helps to facilitate the carriers entering the first active region 13, so as to achieve the effect of improving the photoelectric performance of the semiconductor device 100. In this embodiment, the first confinement layer 14 is directly connected to the first semiconductor structure 11, and the second confinement layer 15 is directly connected to the second semiconductor structure 12.

In one embodiment, the first confinement layer 14 and the second confinement layer 15 may or may not include dopants. The dopant may be intentionally doped or unintentionally doped. When the dopants in the first confinement layer 14 and the second confinement layer 15 are unintentionally doped, the dopants enter the first confinement layer 14 and the second confinement layer 15 during the epitaxy process, and the concentration of the unintentionally doped dopants is substantially (e.g., 1 to 2 orders of magnitude) smaller than that in the first semiconductor structure 11 and the second semiconductor structure 12, and in one embodiment, the intentionally or unintentionally doped dopants are present in the first confinement layer 14 and the second confinement layer 15The mass concentration is less than 1×10 ¹⁷ /cm ³ . The first thickness T1 and the second thickness T2 are smaller than the thickness of the first semiconductor structure 11 and the thickness of the second semiconductor structure 13, respectively, and the first thickness T1 and the second thickness T2 of the present embodiment are both larger than the thicknesses of the barrier layers (132, 134, 136) and the well layers (131, 133, 135) in the first active region 13.

The substrate 7 comprises a conductive or insulating material. Conductive materials such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si). An insulating material such as Sapphire (saphire). In other embodiments, the substrate 7 is a growth substrate, i.e. the first epitaxial stack 1 may be epitaxially formed on the substrate 7 by, for example, metal-organic chemical vapor deposition (MOCVD). In one embodiment, the base 7 is a bonding substrate, not a growth substrate, which may be bonded to the first epitaxial layer 1 by the bonding structure 6, as shown in fig. 1.

The first electrode 2 and the second electrode 3 are used for electrical connection with an external power source. The materials of the first electrode 2 and the second electrode 3 may be the same or different, and for example, each includes a metal oxide material, a metal, or an alloy. The metal oxide material includes Indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium Zinc Oxide (IZO), or the like. Examples of the metal include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu). The alloy may comprise at least two selected from the group consisting of the above metals, such as germanium Jin Nie (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), or zinc gold (ZnAu), etc.

The insulating portion 8 includes an insulating material having a refractive index (index) of less than 2, such as silicon nitride (SiN) _x ) Alumina (AlO) _x ) Silicon oxide (SiO) _x ) Magnesium fluoride (MgF) _x ) Or a combination thereof. The conductive layer 4 may comprise a metal oxide material, such as: indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), zinc aluminum oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), and oxideIndium tungsten (IWO), zinc oxide (ZnO), indium Zinc Oxide (IZO), or combinations of the above.

The reflective layer 5 can reflect the light emitted from the first active region 13 to emit the light out of the semiconductor device 100 toward the first electrode 2. The reflective layer 5 may comprise a semiconductor material, a metal or an alloy. The semiconductor material may comprise a III-V semiconductor material, such as a binary, ternary, or quaternary III-V semiconductor material. The metal includes, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), or the like. The alloy may comprise at least two selected from the group consisting of the metals described above. In one embodiment, the reflective layer 5 may comprise a Bragg reflection structure (Distributed Bragg Reflector structure, DBR). The Bragg reflection structure may be formed of an alternating stack of two or more semiconductor materials of different refractive indices, such as AlAs/GaAs, alGaAs/GaAs or InGaP/GaAs.

The bonding structure 6 connects the substrate 7 and the reflective layer 5. In one embodiment, the bonding structure 6 may be a single layer or multiple layers (not shown). The material of the bonding structure 6 may comprise a transparent conductive material, a metal or an alloy. The transparent conductive material includes, but is not limited to, indium Tin Oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), antimony Tin Oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), gallium Zinc Oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium Cerium Oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium Zinc Oxide (IZO), indium Gallium Oxide (IGO), gallium Aluminum Zinc Oxide (GAZO), graphene (graphene), or a combination of the above materials. The metal includes, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), or the like. The alloy may comprise at least two selected from the group consisting of the metals described above.

Fig. 2 is a schematic diagram of an epitaxial structure of a semiconductor device according to another embodiment of the present utility model. In this embodiment, the epitaxial structure further includes a second epitaxial layer 9 on the first epitaxial layer 1 in addition to the first epitaxial layer 1, and an intermediate layer 81 is disposed between the first epitaxial layer 1 and the second epitaxial layer 9. The second epitaxial layer 9 comprises a third semiconductor structure 91, a fourth semiconductor structure 92, a second active region 93 between the third semiconductor structure 91 and the fourth semiconductor structure 92, a third confinement layer 94 between the second active region 93 and the third semiconductor structure 91, and a fourth confinement layer 95 between the second active region 93 and the fourth semiconductor structure 92, and the third confinement layer 94 is closer to the first confinement layer 14 than the fourth confinement layer 95. The third semiconductor structure 91 and the fourth semiconductor structure 92 may have different conductive types. For example, the third semiconductor structure 91 is n-type and the fourth semiconductor structure 92 is p-type; alternatively, the third semiconductor structure 91 is p-type and the fourth semiconductor structure 92 is n-type. Thus, the third semiconductor structure 91 and the fourth semiconductor structure 92 can provide electrons and holes, respectively, the third semiconductor structure 91 has a third dopant, and the fourth semiconductor structure 92 has a fourth dopant, so that it has different conductivities. The third dopant may be the same as or different from the first dopant and the fourth dopant may be the same as or different from the second dopant. The materials of the third dopant and the fourth dopant may be selected with reference to the materials of the first dopant and the second dopant.

In the present embodiment, the third semiconductor structure 91 has a conductivity type opposite to that of the second semiconductor structure 12 and the same conductivity type as that of the first semiconductor structure 11. The intermediate layer 81 arranged between the third semiconductor structure 91 and the second semiconductor structure 12 is used for tunneling carriers between the first semiconductor stack 1 and the second semiconductor stack 9. In detail, the intermediate layer 81 comprises a pn junction formed by a first heavily doped layer 811 (e.g. an n-type conductive semiconductor layer) having a first conductivity and a second heavily doped layer 812 (e.g. a p-type conductive semiconductor layer) having a second conductivity. The first and second heavily doped layers 811 and 812 have a doping concentration that is at least an order of magnitude (order) higher than the doping concentration of the second and third semiconductor structures 12 and 91, e.g., higher than 1×10 ¹⁸ /cm ³ To provide a low resistance electrical junction during operation.

The second active region 93 has a similar structure, material composition, and emission wavelength to the first active region 13, for example: both the second active region 93 and the first active region 13 emit infrared light having a peak wavelength of 730nm to 1100nm. In detail, the second active region 93 includes a fourth well layer 931, a fourth barrier layer 932, a fifth well layer 933 and a fifth barrier layer 934 sequentially stacked on the third confinement layer 94, and the fourth well layer 931 is closer to the third confinement layer 94 than the fifth well layer 933. The second active region 93 may further include a sixth well layer 935 and a sixth barrier layer 936 sequentially stacked on the fifth barrier layer 934, the fifth well layer 933 being closer to the third confinement layer 94 than the sixth well layer 935. The fourth well layer 931, the fifth well layer 933, and the sixth well layer 935 include indium (In), and an indium composition ratio In the fourth well layer 931 is smaller than an indium composition ratio In the fifth well layer 933, and an indium composition ratio In the fifth well layer 933 is smaller than an indium composition ratio In the sixth well layer 935. When the second active region 93 has a plurality of well layers and barrier layers overlapping each other, the indium composition ratio of the well layers in the second active region 93 increases from the third confinement layer 94 toward the fourth confinement layer 95. In another embodiment, the thickness of the fourth well layer 931 is smaller than the thickness of the fifth well layer 933, and the thickness of the fifth well layer 933 is smaller than the thickness of the sixth well layer 935. When the second active region 93 has a plurality of well layers and barrier layers overlapping each other, the thickness of the well layers in the second active region 93 increases from the third confinement layer 94 toward the fourth confinement layer 95. As described above, the semiconductor device can have better photoelectric performance by designing the indium composition ratio and/or thickness of the well layer.

The third confinement layer 94 and the fourth confinement layer 95 are used to prevent carriers in the second active region 93 from overflowing. The third confinement layer 94 has a third thickness T3, and the fourth confinement layer 95 has a fourth thickness T4 greater than the third thickness T3, so as to prevent the fourth dopant in the fourth semiconductor structure 92 from entering the second active region 93 and affecting the light emitting characteristics of the semiconductor device. In the present embodiment, the third thickness T3 is, for example, 150nm to 400nm, and the fourth thickness T4 is, for example, 300nm to 650nm. In one embodiment, T4/T3 is greater than 2, the third thickness T3 is substantially equal to the first thickness T1, and the fourth thickness T4 is substantially equal to the second thickness T2. In another embodiment, T3> T1, T4> T2, and T2> T1, T4> T3; in yet another embodiment, T3< T1, T4< T2, and T2> T1, T4> T3.

The thickness of the confining layers 14, 15, 94, 95 is designed (i.e., the second thickness T2 is greater than the first thickness T1 and/or the second thickness T2The fourth thickness T4 is greater than the third thickness T3), the indium composition ratio design of the well layer in the first active region 13 and/or the second active region 93 (i.e.: the indium composition ratio of the well layer increases from the first confinement layer 14 toward the second confinement layer 15 and/or from the third confinement layer 94 toward the fourth confinement layer 95), the thickness design of the well layer in the first active region 13 and/or the second active region 93 (i.e.: the thickness of the well layer increases from the first confinement layer 14 toward the second confinement layer 15 and/or from the third confinement layer 94 toward the fourth confinement layer 95, if the dopant concentration of the first semiconductor structure 11 and/or the second semiconductor structure 12 is increased by 8×10 ¹⁷ ～5×10 ¹⁸ /cm ³ And/or the aluminum content of the first semiconductor structure 11 and/or the second semiconductor structure 12 is 25% -50%, which is beneficial to increasing the carrier concentration and/or enhancing the current dispersion effect, thereby improving the luminous intensity of the semiconductor device 100. The epitaxial structure features described above are particularly suitable for semiconductor devices for high current density operation, e.g., a current density of 0.5A/mm ² To 2A/mm ² Is provided. The current density is the quotient of the current value applied to the semiconductor element 100 during operation and the surface area of the substrate 7. For example: the current applied to the semiconductor element during operation was 100mA, and the substrate area of the semiconductor element was 0.125mm ² The current density is 0.8A/mm ² . The above aluminum content refers to atomic percent of aluminum, for example, when the material of the first semiconductor structure 11 and/or the second semiconductor structure 12 is AlGaAs and the aluminum content is 25%, the material composition is Al _0.25 Ga _0.75 As。

For example, in one embodiment, the semiconductor device is a light emitting device and has a first thickness T1 smaller than a second thickness T2, if the dopant concentration of the semiconductor device is 8×10, respectively, in combination with the first semiconductor structure 11 ¹⁷ ～5×10 ¹⁸ /cm ³ When operated at a current density of 1.7A/mm, as compared to a light-emitting element without the above epitaxial structural features ² When the light-emitting element of the present embodiment is used, the light-emitting intensity can be increased by 2.8%. In another embodiment, the semiconductor device is a light emitting device and has a design with a first thickness T1 smaller than a second thickness T2, if subdividedIs matched with the epitaxial structure characteristics with the aluminum content of 25% -50% of the first semiconductor structure 11, and compared with the light-emitting element without the epitaxial structure characteristics, the current density is 1.7A/mm when operating ² When the light-emitting element of the present embodiment is used, the light-emitting intensity can be increased by 6.1%.

Fig. 3 is a schematic cross-sectional view of a semiconductor device 300 according to an embodiment of the utility model. Referring to fig. 3, the semiconductor device 300 includes a semiconductor element 100, a package substrate 31, a carrier 33, bonding wires 35, a contact structure 36 and a package layer 38. The package substrate 31 may comprise a ceramic or glass material. The package substrate 31 has a plurality of through holes 32 therein. The vias 32 may be filled with a conductive material such as metal or the like to aid in conducting electricity or/and dissipating heat. The carrier 33 is located on a surface of one side of the package substrate 31 and also includes a conductive material such as a metal. The contact structure 36 is located on the other surface of the package substrate 31. In the present embodiment, the contact structure 36 includes a first contact pad 36a and a second contact pad 36b, and the first contact pad 36a and the second contact pad 36b can be electrically connected to the carrier 33 through the through hole 32. In one embodiment, the contact structure 36 may further include a thermal pad (not shown), for example, between the first contact pad 36a and the second contact pad 36 b.

The semiconductor element 100 is located on the carrier 33. In the present embodiment, the carrier 33 includes a first portion 33a and a second portion 33b, and the semiconductor element 100 is electrically connected to the second portion 33b of the carrier 33 by the bonding wire 35. The material of the bonding wire 35 may comprise a metal such as gold, silver, copper, aluminum, or an alloy comprising at least any of the foregoing elements. The encapsulation layer 38 covers the semiconductor device 100, and has an effect of protecting the semiconductor device 100. Specifically, the encapsulation layer 38 may include a resin material such as epoxy (epoxy), silicone (silicone), or the like. The encapsulation layer 38 may optionally include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor device 100 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

Fig. 4 is a schematic cross-sectional view of a portion of a sensing module 400 according to an embodiment of the utility model, wherein the sensing module 400 includes a carrier 420, a first semiconductor device 411 and a second semiconductor device 431. The first semiconductor element 411 and/or the second semiconductor element 431 may be the above-described semiconductor elements. The carrier 420 comprises a first wall 421, a second wall 422, a third wall 423, a carrier 424, a first space 425 and a second space 426, wherein the first semiconductor element 411 is located in the space 425 between the first wall 421 and the second wall 422, and the second semiconductor element 431 is located in the space 426 between the second wall 422 and the third wall 423. The first semiconductor device 411 and/or the second semiconductor device 431 may be a vertical chip as shown in fig. 1, or a flip chip or a front-mounted chip having the epitaxial structure of fig. 1 or 2. The first semiconductor device 411 and the second semiconductor device 431 are disposed on the carrier 424 and electrically connected to a circuit connection structure (not shown) on the carrier 424. In the present embodiment, the first semiconductor device 411 is a light emitting device, the second semiconductor device 431 is a light receiving device, and the sensing module 400 can be placed in a wearable device (e.g. a wristwatch, an earphone), the light emitted by the first semiconductor device 411 passes through the skin and irradiates the body cells and blood, and the light scattered/reflected from the body cells and blood is absorbed by the second semiconductor device 431, so as to detect the physiological signal of the human body according to the change of the reflected/scattered light, such as: heart rate, blood glucose, blood pressure, blood oxygen concentration, etc.

Specifically, the epitaxial structure, the semiconductor element and the semiconductor component of the utility model can be applied to products in the fields of illumination, medical treatment, display, communication, sensing, power supply systems and the like, such as lamps, monitors, mobile phones, tablet computers, vehicle dashboards, televisions, computers, wearing devices (such as watches, bracelets, necklaces and the like), traffic signs, outdoor displays, medical equipment and the like.

Although the present utility model has been disclosed in connection with the above embodiments, it should be understood by those skilled in the art that the present utility model is not limited thereto, and that modifications and variations may be made without departing from the spirit and scope of the present utility model, which is to be limited only by the appended claims. Furthermore, the foregoing embodiments may be combined with or substituted for each other where appropriate, and are not limited to the specific embodiments described. For example, the parameters related to the specific components disclosed in one embodiment or the connection relationship between the specific components and other components can be applied to other embodiments, and all fall within the scope of the present utility model.

Claims

1. A semiconductor element, characterized in that the semiconductor element comprises:

an epitaxial structure comprising a first epitaxial stack including a first semiconductor structure, a second semiconductor structure and a first active region between the first semiconductor structure and the second semiconductor structure, the second semiconductor structure having a different conductivity type than the first semiconductor structure;

a plurality of contact portions under and contacting the first semiconductor structure;

a plurality of insulating parts positioned under and contacting the plurality of contact parts;

a first electrode on the second semiconductor structure and including an electrode pad and an extension electrode;

the plurality of contact portions and the plurality of insulation portions are offset from the electrode pad in the vertical direction, and the plurality of contact portions and the extension electrode overlap in the vertical direction.

2. The semiconductor device according to claim 1, wherein the plurality of insulating portions includes a first insulating portion and a second insulating portion, and wherein in a cross-sectional view, the semiconductor device further includes a gap between two adjacent ones of the plurality of contact portions, and a first aperture between the first insulating portion and the second insulating portion, the gap and the first aperture overlapping the electrode pad in the vertical direction.

3. The semiconductor device of claim 2, wherein the width of the gap and the width of the first aperture are greater than the width of the electrode pad in a horizontal direction.

4. The semiconductor device of claim 1, wherein a thickness of the contact portion is less than a thickness of the insulating portion.

5. The semiconductor device of claim 2, wherein a width of the gap in a horizontal direction is smaller than a width of the first aperture.

6. The semiconductor device of claim 1, wherein the first semiconductor structure has a first surface facing the first active region and a second surface contacting the plurality of contacts, and wherein a width of the first surface is smaller than a width of the second surface.

7. The semiconductor device of claim 2, further comprising a conductive layer under the plurality of insulating portions, the conductive layer contacting the plurality of insulating portions and filling the gap and the first aperture.

8. The semiconductor device of claim 7, wherein the conductive layer contacts the plurality of contacts.

9. The semiconductor device of claim 7, wherein the conductive layer is connected to the first semiconductor structure.

10. The semiconductor device according to claim 2, wherein the plurality of insulating portions further comprises a third insulating portion, wherein in the cross-sectional view, the semiconductor device further comprises a second aperture between the second insulating portion and the third insulating portion, the second aperture overlapping the contact portion in the vertical direction.

11. The semiconductor device according to claim 1, wherein the light emitted from the semiconductor device is infrared light.

12. The semiconductor device according to claim 11, wherein a peak wavelength of the emission wavelength of the first active region is 730nm to 1100nm.

13. The semiconductor device of claim 1, wherein the epitaxial structure further comprises a second epitaxial stack on the first epitaxial stack, the second epitaxial stack having a third semiconductor structure, a fourth semiconductor structure, and a second active region between the third semiconductor structure and the fourth semiconductor structure, the third semiconductor structure and the fourth semiconductor structure having different conductivity types.

14. The semiconductor device of claim 13, further comprising an intermediate layer between the first epitaxial layer stack and the second epitaxial layer stack, the intermediate layer comprising a pn junction.

15. The semiconductor device according to claim 13, wherein the first active region and the second active region each emit infrared light having a peak wavelength of 730nm to 1100nm.

16. The semiconductor device of claim 1, wherein the first semiconductor structure is p-type and the second semiconductor structure is n-type.

17. The semiconductor device of claim 1, further comprising a bonding structure and a substrate, the bonding structure being located between the first epitaxial layer stack and the substrate.

18. The semiconductor device of claim 17, further comprising a reflective layer between said first epitaxial layer stack and said bonding structure.

19. The semiconductor device of claim 17, further comprising a second electrode connected to a side of said substrate remote from said first semiconductor structure.

20. A semiconductor assembly, comprising:

packaging a substrate;

the semiconductor device of any one of claims 1-19, located on the package substrate; and

and the packaging layer covers the semiconductor element.