TWI840665B - Semiconductor device and semiconductor component including the same - Google Patents

Semiconductor device and semiconductor component including the same Download PDF

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TWI840665B
TWI840665B TW110115959A TW110115959A TWI840665B TW I840665 B TWI840665 B TW I840665B TW 110115959 A TW110115959 A TW 110115959A TW 110115959 A TW110115959 A TW 110115959A TW I840665 B TWI840665 B TW I840665B
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electrode
semiconductor
electrode pad
semiconductor device
area
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TW202245296A (en
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張昀雅
偉善 楊
馮子耘
詹燿寧
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晶元光電股份有限公司
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Abstract

A semiconductor device includes an epitaxial stack having a top surface composed of nine areas which substantially have the same surface area, and an electrode on the top surface having a first electrode pad and an extended electrode connecting to the first electrode pad. The extended electrode includes nine parts respectively disposed on the nine areas. The parts of the extended electrode respectively have a shielding ratio, and at least five parts of the nine parts substantially have the same shielding ratio.

Description

半導體元件及包含其之半導體組件Semiconductor element and semiconductor assembly containing the same

本發明是關於半導體元件，特別是有關於半導體發光元件，例如發光二極體。 The present invention relates to semiconductor devices, in particular to semiconductor light-emitting devices, such as light-emitting diodes.

半導體元件的用途十分廣泛，相關材料的開發研究也持續進行。舉例來說，包含三族及五族元素的III-V族半導體材料可應用於各種光電半導體元件如發光二極體(Light emitting diode，LED)、雷射二極體(Laser diode，LD)、光電偵測器或太陽能電池(Solar cell)，或者可以是例如開關或整流器的功率元件，能用於照明、醫療、顯示、通訊、感測、電源系統等領域。作為半導體發光元件之一的發光二極體具有耗電量低以及壽命長等優點，因此大量被應用。 Semiconductor components have a wide range of uses, and the development and research of related materials are also ongoing. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic semiconductor components such as light emitting diodes (LEDs), laser diodes (LDs), photodetectors or solar cells, or can be power components such as switches or rectifiers, which can be used in lighting, medical treatment, display, communication, sensing, power supply systems and other fields. As one of the semiconductor light-emitting components, light-emitting diodes have the advantages of low power consumption and long life, so they are widely used.

本發明內容提供一種半導體元件包括一磊晶疊層，具有一上表面由九個區域組成，且九個區域具有大致相同的面積，且磊晶疊層包含一第一半導體結構、一第二半導體結構位於第一半導體結構上、及一活性區位於第一半導體結構及第二半導體結構之間，第二半導 體結構為n型；以及一第一電極，位於該上表面上且與第二半導體結構直接接觸，第一電極包含一第一電極墊及一延伸電極連接於第一電極墊。延伸電極具有九個部分分別各位於九個區域上，九個部分各具有一遮光比率，且遮光比率中至少有大致相同。 The present invention provides a semiconductor element including an epitaxial stack having an upper surface composed of nine regions, and the nine regions have approximately the same area, and the epitaxial stack includes a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active region located between the first semiconductor structure and the second semiconductor structure, and the second semiconductor structure is n-type; and a first electrode located on the upper surface and directly in contact with the second semiconductor structure, the first electrode including a first electrode pad and an extended electrode connected to the first electrode pad. The extended electrode has nine parts respectively located on the nine regions, and the nine parts each have a shading ratio, and at least one of the shading ratios is approximately the same.

100:半導體元件 100:Semiconductor components

1:磊晶疊層 1: Epitaxial stacking

11:第一半導體結構 11: First semiconductor structure

111:接觸部 111: Contact area

12:第二半導體結構 12: Second semiconductor structure

13:活性區 13: Active area

2:第一電極 2: First electrode

2A:第一電極墊 2A: First electrode pad

2B:第二電極墊 2B: Second electrode pad

22:延伸電極 22: Extended electrode

22a:第一部 22a: Part 1

22b:第二部 22b: Part 2

22c:第三部 22c: Part 3

22d:第四部 22d: Part 4

221:第一部分 221: Part 1

222:第二部分 222: Part 2

223:第三部分 223: Part 3

224:第四部份 224: Part 4

225:第五部分 225: Part 5

226:第六部分 226: Part 6

227:第七部分 227: Part 7

228:第八部分 228: Part 8

229:第九部分 229: Part 9

3:第二電極 3: Second electrode

4:導電層 4: Conductive layer

5:反射層 5: Reflective layer

6:接合結構 6:Joint structure

7:基底 7: Base

8:絕緣部 8: Insulation Department

8a:孔隙 8a: Porosity

81:中間層 81: Middle layer

300:半導體組件 300:Semiconductor components

31:封裝基板 31:Packaging substrate

32:通孔 32:Through hole

33:載體 33: Carrier

33a:第一部 33a: Part 1

33b:第二部 33b: Part 2

35:接合線 35:Joining line

36:接觸結構 36: Contact structure

36a:第一接觸墊 36a: First contact pad

36b:第二接觸墊 36b: Second contact pad

38:封裝層 38: Packaging layer

400:感測模組 400:Sensor module

420:承載體 420:Carrier

411:第一半導體元件 411: First semiconductor element

431:第二半導體元件 431: Second semiconductor element

421:第一擋牆 421: The first barrier

422:第二擋牆 422: The second barrier

423:第三擋牆 423: The third barrier

424:載板 424:Carrier board

425:第一空間 425: First Space

426:第二空間 426: Second Space

S1:第一區域 S1: First area

S2:第二區域 S2: Second area

S3:第三區域 S3: The third area

S4:第四區域 S4: The fourth area

S5:第五區域 S5: The fifth area

S6:第六區域 S6: The sixth area

S7:第七區域 S7: Area 7

S8:第八區域 S8: The eighth area

S9:第九區域 S9: Area 9

E1:第一邊 E1: First side

E2:第二邊 E2: Second side

V:虛擬線 V:Virtual line

C:中心 C: Center

L1:對角線 L1: diagonal

L2:第一對稱線 L2: first symmetry line

L3:第二對稱線 L3: Second symmetry line

w1:第一寬度 w1: first width

w2:第二寬度 w2: second width

D:距離 D: Distance

第1圖為為本揭露內容一實施例之半導體元件的剖面示意圖。 Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

第2圖為本揭露內容一實施例之半導體元件的上視示意圖。 Figure 2 is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

第3圖為本揭露內容另一實施例之半導體元件的上視示意圖 Figure 3 is a top view schematic diagram of a semiconductor device of another embodiment of the present disclosure.

第4圖為本揭露內容一實施例之半導體組件的剖面結構示意圖。 Figure 4 is a schematic diagram of the cross-sectional structure of a semiconductor component of an embodiment of the present disclosure.

第5圖為本揭露內容一實施例之感測模組的部分剖面結構示意圖。 Figure 5 is a schematic diagram of a partial cross-sectional structure of a sensing module of an embodiment of the present disclosure.

以下實施例將伴隨著圖式說明本發明之概念，在圖式或說明中，相似或相同之構件將使用相似或相同之標號進行說明，並且若未特別說明，圖式中各元件之形狀或尺寸僅為例示，實際上並不限於此。需特別注意的是，圖中未繪示或描述之元件，可以是熟習此技藝之人士所知之形式。 The following embodiments will be accompanied by drawings to illustrate the concept of the present invention. In the drawings or descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or sizes of the components in the drawings are only examples and are not limited thereto. It should be noted that the components not shown or described in the drawings may be in a form known to those skilled in the art.

在未特別說明的情況下，通式InGaP代表Inx0Ga1-x0P，其中0<x0<1；通式AlInP代表Alx1In1-x1P，其中0<x1<1；通式AlGaInP代表Alx2Gax3In1-x2-x3P，其中0<x2<1且0<x3<1；通式InGaAsP代表Inx4Ga1-x4Asx5P1-x5，其中0<x4<1，0<x5<1；通式AlGaInAs代表Alx6Gax7In1-x6-x7As，其中0<x6<1，0<x7<1；通式InGaNAs代表Inx8Ga1-x8Nx9As1-x9，其中0<x8<1，0<x9<1；通式InGaAs代表Inx10Ga1- x10As，其中0<x10<1；通式AlGaAs代表Alx11Ga1-x11As，其中0<x11<1。可依不同目的調整各元素的含量，例如但不限於調整能隙大小，或是當半導體元件為一發光元件時，可藉此調整發光元件的主波長(domain wavelength)或峰值波長(peak wavelength)。 Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, wherein 0<x0<1; the general formula AlInP represents Al x1 In 1-x1 P, wherein 0<x1<1; the general formula AlGaInP represents Al x2 Ga x3 In 1-x2-x3 P, wherein 0<x2<1 and 0<x3<1; the general formula InGaAsP represents In x4 Ga 1-x4 As x5 P 1-x5 , wherein 0<x4<1, 0<x5<1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6-x7 As, wherein 0<x6<1, 0<x7<1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 , wherein 0<x8<1, 0<x9<1; the general formula InGaAs represents In x10 Ga 1- x10 As, where 0<x10<1; the general formula AlGaAs represents Al x11 Ga 1-x11 As, where 0<x11<1. The content of each element can be adjusted for different purposes, such as but not limited to adjusting the energy gap size, or when the semiconductor device is a light-emitting device, the domain wavelength or peak wavelength of the light-emitting device can be adjusted.

本揭露內容的半導體元件例如是發光元件(例如：發光二極體(light-emitting diode)、雷射二極體(laser diode))、吸光元件(例如：光電二極體(photo-detector))或不發光元件。本揭露內容的半導體元件包含的各層組成及摻質(dopant)可用任何適合的方式分析而得，例如二次離子質譜儀(secondary ion mass spectrometer，SIMS)，而各層之厚度亦可用任何適合的方式分析而得，例如穿透式電子顯微鏡(transmission electron microscopy，TEM)或是掃描式電子顯微鏡(scanning electron microscope，SEM)等。 The semiconductor element disclosed herein is, for example, a light-emitting element (e.g., a light-emitting diode, a laser diode), a light-absorbing element (e.g., a photodiode), or a non-light-emitting element. The composition and dopant of each layer included in the semiconductor element disclosed herein can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM).

所屬領域中具通常知識者應理解，可以在以下所說明各實施例之基礎上添加其他構件。舉例來說，在未特別說明之情況下，「第一層(或結構)位於第二層(或結構)上」的類似描述可包含第一層(或結構)與第二層(或結構)直接接觸的實施例，也可包含第一層(或結構)與第二層(或結構)之間具有其他結構而彼此未直接接觸的實施例。另外，應理解各層(或結構)的上下位置關係等可能因由不同方位觀察而有所改變。 Those with common knowledge in the relevant field should understand that other components can be added on the basis of the embodiments described below. For example, unless otherwise specified, similar descriptions such as "the first layer (or structure) is located on the second layer (or structure)" may include embodiments in which the first layer (or structure) and the second layer (or structure) are in direct contact, and may also include embodiments in which there are other structures between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. In addition, it should be understood that the upper and lower positional relationship of each layer (or structure) may change due to observation from different directions.

此外，於本揭露內容中，一層或結構「實質上由M所組成」之敘述表示上述層或結構的主要組成為M，但並不排除上述層或結構包含摻質或不可避免的雜質(impurities)。 In addition, in the present disclosure, the statement that a layer or structure is "substantially composed of M" means that the main component of the above layer or structure is M, but does not exclude that the above layer or structure contains doping or unavoidable impurities.

第1圖為本揭露內容一實施例之半導體元件100的剖面示意圖。半導體元件100包含一磊晶疊層1。半導體元件100更包含一第一電極2及一第二電 極3分別位於磊晶疊層1的上下兩側，且可選擇性包含一導電層4、一反射層5、一接合結構6、一基底7及複數個絕緣部8。導電層4位於磊晶疊層1與反射層5之間，複數個絕緣部8位於磊晶疊層1和導電層4之間，接合結構6位於基底7與反射層5之間。在另一實施例中，半導體元件僅包含基底7、磊晶疊層1位於基底7上、第一電極2位於磊晶疊層1上、及第二電極3位於基底7的下表面。 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes an epitaxial stack 1. The semiconductor device 100 further includes a first electrode 2 and a second electrode 3 located at the upper and lower sides of the epitaxial stack 1, respectively, and may optionally include a conductive layer 4, a reflective layer 5, a bonding structure 6, a substrate 7, and a plurality of insulating portions 8. The conductive layer 4 is located between the epitaxial stack 1 and the reflective layer 5, the plurality of insulating portions 8 are located between the epitaxial stack 1 and the conductive layer 4, and the bonding structure 6 is located between the substrate 7 and the reflective layer 5. In another embodiment, the semiconductor element only includes a substrate 7, an epitaxial stack 1 located on the substrate 7, a first electrode 2 located on the epitaxial stack 1, and a second electrode 3 located on the lower surface of the substrate 7.

第2圖為本揭露內容一實施例之半導體元件100的上視示意圖，第1圖為半導體元件100沿第2圖之A-A線的剖面示意圖。磊晶疊層1包含一上表面S，第一電極2包含第一電極墊2A及延伸電極22位於上表面S，第一電極墊2A與延伸電極22互相連接。在本實施例中，上表面S具有第一邊E1及第二邊E2垂直於第一邊E1，且第一邊E1的長度大致等於第二邊E2的長度，即本實施例的上表面S為一正方形。選擇性地，半導體元件100的第一電極2可包含第二電極墊2B。在本實施例中，第二電極墊2B透過延伸電極22連接於第一電極墊2A，且第一電極墊2A具有一第一寬度w1平行於第一邊E1，連接於第一電極墊2A之延伸電極22具有一第二寬度w2平行於第一邊E1，第一電極墊2A及第二電極墊2B大致為圓形且為後續供打線(wire bonding)的區域，故第一寬度w1大於第二寬度w2，例如

Figure 110115959-A0305-02-0007-2
為3~10。為使電流散布更為均勻，第一電極墊2A與第二電極墊2B之間具有一距離D平行於第二邊E2，且此距離大於
Figure 110115959-A0305-02-0007-3
的第二邊E2之邊長，小於
Figure 110115959-A0305-02-0007-4
的第二邊E2之邊長。 FIG. 2 is a schematic top view of a semiconductor device 100 according to an embodiment of the present disclosure, and FIG. 1 is a schematic cross-sectional view of the semiconductor device 100 along line AA of FIG. 2. The epitaxial stack 1 includes an upper surface S, and the first electrode 2 includes a first electrode pad 2A and an extended electrode 22 located on the upper surface S, and the first electrode pad 2A and the extended electrode 22 are connected to each other. In this embodiment, the upper surface S has a first side E1 and a second side E2 perpendicular to the first side E1, and the length of the first side E1 is substantially equal to the length of the second side E2, that is, the upper surface S of this embodiment is a square. Optionally, the first electrode 2 of the semiconductor device 100 may include a second electrode pad 2B. In this embodiment, the second electrode pad 2B is connected to the first electrode pad 2A through the extension electrode 22, and the first electrode pad 2A has a first width w1 parallel to the first side E1, and the extension electrode 22 connected to the first electrode pad 2A has a second width w2 parallel to the first side E1. The first electrode pad 2A and the second electrode pad 2B are substantially circular and are areas for subsequent wire bonding, so the first width w1 is greater than the second width w2, for example
Figure 110115959-A0305-02-0007-2
In order to make the current distribution more uniform, there is a distance D between the first electrode pad 2A and the second electrode pad 2B parallel to the second side E2, and the distance is greater than
Figure 110115959-A0305-02-0007-3
The length of the second side E2 is less than
Figure 110115959-A0305-02-0007-4
The length of the second side E2.

上表面S由第一區域S1、第二區域S2、第三區域S3、第四區域S4、第五區域S5、第六區域S6、第七區域S7、第八區域S8及第九區域S9組成，上述區域具有大致相同的面積，且第一電極墊2A位於第四區域S4與第五區域S5，第二電極墊2B位於第五區域S5與第六區域S6。延伸電極22包含第一部份221位於 第一區域S1上、第二部分222位於第二區域S2上、第三部分223位於第三區域S3上、第四部份224位於第四區域S4上、第五部分225位於第五區域S5上、第六部分226位於第六區域S6上、第七部分227位於第七區域S7上、第八部分228位於第八區域S8上及第九部分229位於第九區域S9上。延伸電極22的各部分具有一遮光比率，且第一部份221至第九部分229中至少有五個部分具有大致相同的遮光比率(shieldingratio，SR)，例如：五個、六個、七個、八個、九個部分具有大致相同的遮光比率。上述遮光比率係指該部分的面積與該區域的面積之百分比，舉例來說，第一部分221具有第一遮光比率SR1，計算公式為：

Figure 110115959-A0305-02-0008-1
The upper surface S is composed of a first region S1, a second region S2, a third region S3, a fourth region S4, a fifth region S5, a sixth region S6, a seventh region S7, an eighth region S8 and a ninth region S9. The above regions have approximately the same area, and the first electrode pad 2A is located in the fourth region S4 and the fifth region S5, and the second electrode pad 2B is located in the fifth region S5 and the sixth region S6. The extended electrode 22 includes a first portion 221 located on the first region S1, a second portion 222 located on the second region S2, a third portion 223 located on the third region S3, a fourth portion 224 located on the fourth region S4, a fifth portion 225 located on the fifth region S5, a sixth portion 226 located on the sixth region S6, a seventh portion 227 located on the seventh region S7, an eighth portion 228 located on the eighth region S8, and a ninth portion 229 located on the ninth region S9. Each portion of the extended electrode 22 has a shielding ratio, and at least five portions of the first portion 221 to the ninth portion 229 have substantially the same shielding ratio (SR), for example, five, six, seven, eight, and nine portions have substantially the same shielding ratio. The above-mentioned shading ratio refers to the percentage of the area of the part to the area of the region. For example, the first part 221 has a first shading ratio SR1, and the calculation formula is:
Figure 110115959-A0305-02-0008-1

詳言之，在本實施例中，以四條虛擬線V將上表面S平均劃分為三行與三列，總共九個區域(第一區域S1至第九區域S9)，並且第一部分221具有第一遮光比率SR1、第二部分222具有第二遮光比率SR2、第三部分223具有第三遮光比率SR3、第四部分224具有第四遮光比率SR4、第五部分225具有第五遮光比率SR5、第六部分226具有第六遮光比率SR6、第七部分227具有第七遮光比率SR7、第八部分228具有第八遮光比率SR8、第九部分229具有第九遮光比率SR9。上述「大致相同的遮光比率」係指該些部分之間的遮光比率相差小於3%，藉此，半導體元件100可具有較佳的電流分散效率，並達到較高的發光效率(流明/瓦)。本實施例中，第一部份221至第九部分229中有八個部分具有大致相同的遮光比率，例如：SR1、SR2、SR3、SR4、SR6、SR7、SR8及SR9為4%~7%，SR5大於9%或為9%~14%。 Specifically, in this embodiment, the upper surface S is evenly divided into three rows and three columns by four virtual lines V, with a total of nine regions (first region S1 to ninth region S9), and the first portion 221 has a first shading ratio SR1, the second portion 222 has a second shading ratio SR2, the third portion 223 has a third shading ratio SR3, the fourth portion 224 has a fourth shading ratio SR4, the fifth portion 225 has a fifth shading ratio SR5, the sixth portion 226 has a sixth shading ratio SR6, the seventh portion 227 has a seventh shading ratio SR7, the eighth portion 228 has an eighth shading ratio SR8, and the ninth portion 229 has a ninth shading ratio SR9. The above-mentioned "substantially the same shading ratio" means that the difference in shading ratio between these portions is less than 3%, thereby, the semiconductor device 100 can have a better current spreading efficiency and achieve a higher luminous efficiency (lumens/watt). In this embodiment, eight of the first part 221 to the ninth part 229 have approximately the same shading ratio, for example: SR1, SR2, SR3, SR4, SR6, SR7, SR8 and SR9 are 4% to 7%, and SR5 is greater than 9% or 9% to 14%.

第一部分221、第二部分222、第三部分223、第四部分224、第六部分226、第七部分227、第八部分228及第九部分229具有大致相同的遮光比率。 由於第五部分225的延伸電極22位於上表面S之中心區域，需與四周的延伸電極22互相連接，故具有大於邊緣區域(例如第一區域S1、第二區域S2、第三區域S3、第四區域S4、第六區域S6、第七區域S7、第八區域S8、第九區域S9)的遮光比率，意即，在本實施例中，上表面S具有中心區域及邊緣區域，且位於中心區域的延伸電極22之遮光比率大於位於邊緣區域的延伸電極22之遮光比率。 The first part 221, the second part 222, the third part 223, the fourth part 224, the sixth part 226, the seventh part 227, the eighth part 228 and the ninth part 229 have substantially the same shading ratio. Since the extended electrode 22 of the fifth part 225 is located in the central area of the upper surface S and needs to be connected to the extended electrodes 22 on the surrounding areas, it has a shading ratio greater than that of the edge area (e.g., the first area S1, the second area S2, the third area S3, the fourth area S4, the sixth area S6, the seventh area S7, the eighth area S8, and the ninth area S9), that is, in this embodiment, the upper surface S has a central area and an edge area, and the shading ratio of the extended electrode 22 located in the central area is greater than the shading ratio of the extended electrode 22 located in the edge area.

此外，第一電極2具有總遮光比率，為第一電極2的總面積與上表面S的面積之百分比，且總遮光比率小於15%，例如：6%~12%、7%~10%或8%~9%。延伸電極22的第二寬度w2為5μm~12μm，例如：6μm~11μm、7μm~10μm或8μm~9μm。在一實施例中，延伸電極22的各部份221~229可具有相同或不同的寬度，例如，本實施例中，第五部分225的寬度大於其餘部分的寬度。或者，延伸電極22的每一部份221~229的寬度可具有漸變的寬度，藉此增加電流擴散。例如，每一部份221~229的寬度可由中心區域往邊緣區域的方向逐漸變大或變小。在一實施例中，第一電極墊2A及第二電極墊2B可以選擇僅置於上表面S的中心區域(例如第五區域S5)，或者亦可選擇僅置於邊緣區域(例如第一區域S1、第二區域S2、第三區域S3、第四區域S4、第六區域S6、第七區域S7、第八區域S8、第九區域S9)。在本實施例中，第一電極墊2A及第二電極墊2B位於中心區域及邊緣區域，且彼此相距200μm至400μm，例如250μm、300μm或350μm。 In addition, the first electrode 2 has a total shading ratio, which is a percentage of the total area of the first electrode 2 to the area of the upper surface S, and the total shading ratio is less than 15%, for example: 6%~12%, 7%~10% or 8%~9%. The second width w2 of the extended electrode 22 is 5μm~12μm, for example: 6μm~11μm, 7μm~10μm or 8μm~9μm. In one embodiment, the portions 221~229 of the extended electrode 22 may have the same or different widths. For example, in this embodiment, the width of the fifth portion 225 is greater than the width of the remaining portions. Alternatively, the width of each portion 221~229 of the extended electrode 22 may have a gradual width, thereby increasing current diffusion. For example, the width of each portion 221-229 may gradually increase or decrease from the central area to the edge area. In one embodiment, the first electrode pad 2A and the second electrode pad 2B may be selected to be placed only in the central area of the upper surface S (e.g., the fifth area S5), or may be selected to be placed only in the edge area (e.g., the first area S1, the second area S2, the third area S3, the fourth area S4, the sixth area S6, the seventh area S7, the eighth area S8, and the ninth area S9). In this embodiment, the first electrode pad 2A and the second electrode pad 2B are located in the central area and the edge area, and are 200μm to 400μm apart from each other, such as 250μm, 300μm or 350μm.

上述第一電極2的分布與設計，如搭配上表面S之第一邊E1及/或第二邊E2的長度(邊長)大於30mil及小於100mil之磊晶疊層1，將可具有更佳的電流分散效果，並可獲得更大幅的發光效率。例如：邊長為30mil~70mil、35mil~60mil或40mil~55mil。由於上述尺寸之磊晶疊層1對電流分散均勻度的要求高，透過本實施例的第一電極2設計，可以有效達到電流均勻分散的效果。 The distribution and design of the first electrode 2 mentioned above, if combined with an epitaxial stack 1 whose length (side length) of the first side E1 and/or the second side E2 of the upper surface S is greater than 30mil and less than 100mil, will have a better current dispersion effect and can obtain a greater luminous efficiency. For example: the side length is 30mil~70mil, 35mil~60mil or 40mil~55mil. Since the epitaxial stack 1 of the above size has a high requirement for the uniformity of current dispersion, the design of the first electrode 2 of this embodiment can effectively achieve the effect of uniform current dispersion.

上述具有大致相同遮光比率的部分(例如：第一部分221、第二部分222、第三部分223、第四部分224、第六部分226、第七部分227、第八部分228及第九部分229)皆具有端點T，且位於相鄰區域之延伸電極22(例如：第一部分221和第二部分222；第七部分227和第八部分228)的端點T互相分離，在本實施例中，相鄰區域的端點T相距120μm~220μm。透過相鄰區域的延伸電極22之端點T不互相連接，可以避免延伸電極22在上表面S上產生封閉圖形。藉此，不但可使電流均勻分散，在製程上亦具有良率較高的優點。 The above-mentioned parts with approximately the same shading ratio (for example: the first part 221, the second part 222, the third part 223, the fourth part 224, the sixth part 226, the seventh part 227, the eighth part 228 and the ninth part 229) all have end points T, and the end points T of the extended electrodes 22 located in adjacent areas (for example: the first part 221 and the second part 222; the seventh part 227 and the eighth part 228) are separated from each other. In this embodiment, the end points T of the adjacent areas are 120μm~220μm apart. By not connecting the end points T of the extended electrodes 22 in the adjacent areas to each other, the extended electrodes 22 can be prevented from generating a closed pattern on the upper surface S. In this way, not only can the current be evenly dispersed, but also the process has the advantage of a higher yield rate.

在本實施例中，上表面S具有一對角線L1，延伸電極22具有複數個第一部22a平行於對角線L1及複數個第二部22b垂直於對角線L1。詳言之，延伸電極22的第一部分221、第三部份223、第七部分227及第九部份229各自具有一第一部22a平行於對角線L1及一第二部22b垂直於對角線L1。第一部分221、第三部分223、第七部分227及第九部分229的延伸電極22具有相同的形狀，例如為X字形。 In this embodiment, the upper surface S has a diagonal line L1, and the extended electrode 22 has a plurality of first portions 22a parallel to the diagonal line L1 and a plurality of second portions 22b perpendicular to the diagonal line L1. Specifically, the first portion 221, the third portion 223, the seventh portion 227, and the ninth portion 229 of the extended electrode 22 each have a first portion 22a parallel to the diagonal line L1 and a second portion 22b perpendicular to the diagonal line L1. The extended electrodes 22 of the first portion 221, the third portion 223, the seventh portion 227, and the ninth portion 229 have the same shape, such as an X shape.

如第2圖所示，一第一對稱線L2通過中心C且平行於第二邊E2，並可將上表面S的面積分為平均兩等分。一第二對稱線L3通過中心C且垂直於第一對稱線L2。延伸電極22具有複數個第三部22c平行於第一對稱線L2及複數個第四部22d垂直於第一對稱線L2。詳言之，延伸電極22的第二部分222、第四部份224、第五部分225、第六部份226及第八部份228各具有第三部22c及第四部22d。本實施例中，第二部分222及第八部分228具有相同的形狀，例如為十字形。如以第一對稱線L2為基準(鏡面)，第一部分221鏡像對稱於第七部分227、第二部分222鏡像對稱於第八部分228、第三部分223鏡像對稱於第九部分229。本實施例的第四部分224及第六部分226具有相同的形狀，如以第二對稱線L3為基 準(鏡面)，第一部分223鏡像對稱於第三部分223、第四部分224鏡像對稱於第六部分226、第七部分227鏡像對稱於第九部分229。在本實施例中，第五部分225的第三部22c具有相對兩端分別連接至第一電極墊2A及第二電極墊2B，第四部22d具有相對兩端分別連接至第二部分222及第八部分228，且第五部分225的第三部22c及第四部22d大致上相交於上表面S的中心C。在本實施例中，延伸電極22由複數個第一部22a、複數個第二部22b、複數個第三部22c及複數個第四部22d所構成。 As shown in FIG. 2 , a first symmetry line L2 passes through the center C and is parallel to the second side E2, and can divide the area of the upper surface S into two equal parts. A second symmetry line L3 passes through the center C and is perpendicular to the first symmetry line L2. The extended electrode 22 has a plurality of third portions 22c parallel to the first symmetry line L2 and a plurality of fourth portions 22d perpendicular to the first symmetry line L2. In detail, the second portion 222, the fourth portion 224, the fifth portion 225, the sixth portion 226 and the eighth portion 228 of the extended electrode 22 each have a third portion 22c and a fourth portion 22d. In this embodiment, the second portion 222 and the eighth portion 228 have the same shape, such as a cross. If the first symmetry line L2 is used as a reference (mirror plane), the first portion 221 is mirror-symmetrical to the seventh portion 227, the second portion 222 is mirror-symmetrical to the eighth portion 228, and the third portion 223 is mirror-symmetrical to the ninth portion 229. The fourth portion 224 and the sixth portion 226 of this embodiment have the same shape. If the second symmetry line L3 is used as a reference (mirror plane), the first portion 223 is mirror-symmetrical to the third portion 223, the fourth portion 224 is mirror-symmetrical to the sixth portion 226, and the seventh portion 227 is mirror-symmetrical to the ninth portion 229. In this embodiment, the third portion 22c of the fifth portion 225 has two opposite ends connected to the first electrode pad 2A and the second electrode pad 2B respectively, the fourth portion 22d has two opposite ends connected to the second portion 222 and the eighth portion 228 respectively, and the third portion 22c and the fourth portion 22d of the fifth portion 225 substantially intersect at the center C of the upper surface S. In this embodiment, the extended electrode 22 is composed of a plurality of first portions 22a, a plurality of second portions 22b, a plurality of third portions 22c and a plurality of fourth portions 22d.

第3圖為本揭露內容另一實施例之半導體元件200的上視示意圖。本實施例之半導體元件200的結構與上述半導體元件100相似，差異在於第一電極2在第五區域S5之分布不同。詳言之，延伸電極22的第五部分225具有兩個第一部22a及一個第三部22c，第三部22c之兩端分別連接於第一電極墊2A及第二電極墊2B，其中一個第一部22a的一端連接於第一電極墊2A、另一端連接於第二部分222，且另一個第一部22a的一端連接於第二電極墊2B、另一端連接於第八部分228。 FIG. 3 is a schematic top view of a semiconductor device 200 of another embodiment of the present disclosure. The structure of the semiconductor device 200 of the present embodiment is similar to the semiconductor device 100 described above, except that the first electrode 2 is distributed differently in the fifth region S5. Specifically, the fifth portion 225 of the extended electrode 22 has two first portions 22a and one third portion 22c, and the two ends of the third portion 22c are connected to the first electrode pad 2A and the second electrode pad 2B, respectively, wherein one end of one first portion 22a is connected to the first electrode pad 2A and the other end is connected to the second portion 222, and one end of another first portion 22a is connected to the second electrode pad 2B and the other end is connected to the eighth portion 228.

如第1圖所示，磊晶疊層1包含一第一半導體結構11、一第二半導體結構12、一活性區13位於第一半導體結構11及第二半導體結構12之間、一第一侷限層14位於活性區13及第一半導體結構11之間、及一第二侷限層15位於活性區13及第二半導體結構12之間。上述磊晶疊層1之上表面S即為第二半導體結構12之表面，第一電極2與該第二半導體結構12直接接觸。第一半導體結構11與第二半導體結構12可具有相異的導電型態。例如，第一半導體結構11為n型，第二半導體結構12為p型；或者，第一半導體結構11為p型，第二半導體結構12為n型。藉此，第一半導體結構11與第二半導體結構12可分別提供電子與電洞或電 洞與電子。第一半導體結構11具有一第一摻質，第二半導體結構12具有一第二摻質，使第一半導體結構11及第二半導體結構12具有不同的導電性。第一摻質及第二摻質可以分別為碳(C)、鋅(Zn)、矽(Si)、鍺(Ge)、錫(Sn)、硒(Se)、鎂(Mg)或碲(Te)。在本實施例中，第一半導體結構11為p型，第二半導體結構12為n型，且第一半導體結構11及第二半導體結構12的摻雜濃度為5×1017/cm3至1×1020/cm3。第一半導體結構11及第二半導體結構12的能隙分別大於第一侷限層14及第二侷限層15，藉此將載子更進一步地限制在活性區13中。 As shown in FIG. 1 , the epitaxial stack 1 includes a first semiconductor structure 11, a second semiconductor structure 12, an active region 13 between the first semiconductor structure 11 and the second semiconductor structure 12, a first confinement layer 14 between the active region 13 and the first semiconductor structure 11, and a second confinement layer 15 between the active region 13 and the second semiconductor structure 12. The upper surface S of the epitaxial stack 1 is the surface of the second semiconductor structure 12, and the first electrode 2 is in direct contact with the second semiconductor structure 12. The first semiconductor structure 11 and the second semiconductor structure 12 may have different conductivity types. For example, the first semiconductor structure 11 is of n-type and the second semiconductor structure 12 is of p-type; or, the first semiconductor structure 11 is of p-type and the second semiconductor structure 12 is of n-type. Thus, the first semiconductor structure 11 and the second semiconductor structure 12 can provide electrons and holes or holes and electrons, respectively. The first semiconductor structure 11 has a first dopant and the second semiconductor structure 12 has a second dopant, so that the first semiconductor structure 11 and the second semiconductor structure 12 have different conductivities. The first dopant and the second dopant can be carbon (C), zinc (Zn), silicon (Si), germanium (Ge), tin (Sn), selenium (Se), magnesium (Mg) or tellurium (Te), respectively. In this embodiment, the first semiconductor structure 11 is of p-type, the second semiconductor structure 12 is of n-type, and the doping concentration of the first semiconductor structure 11 and the second semiconductor structure 12 is 5×10 17 /cm 3 to 1×10 20 /cm 3 . The energy gaps of the first semiconductor structure 11 and the second semiconductor structure 12 are larger than the first confinement layer 14 and the second confinement layer 15, respectively, thereby further confining the carriers in the active region 13.

活性區13位於第一侷限層14及第二侷限層15之間，且於本實施例中，活性區13與第一侷限層14直接相接，且活性區13與第二侷限層15直接相接。在本實施例中，活性區13包含複數個互相堆疊的阱層及阻障層(圖未示)，阱層的材料為InGaAs，阻障層的材料為AlGaAsP。在其他實施例中，阱層的材料為InGaAs，阻障層的材料為AlGaAs；在另一實施例中，阱層材料為InGaAs，阻障層的材料為GaAsP。本實施例半導體元件100的活性區13中，阱層的厚度小於阻障層的厚度。阱層及/或阻障層可包含或未包含摻質。 The active region 13 is located between the first confinement layer 14 and the second confinement layer 15, and in this embodiment, the active region 13 is directly connected to the first confinement layer 14, and the active region 13 is directly connected to the second confinement layer 15. In this embodiment, the active region 13 includes a plurality of well layers and barrier layers stacked on each other (not shown), the material of the well layer is InGaAs, and the material of the barrier layer is AlGaAsP. In other embodiments, the material of the well layer is InGaAs, and the material of the barrier layer is AlGaAs; in another embodiment, the material of the well layer is InGaAs, and the material of the barrier layer is GaAsP. In the active region 13 of the semiconductor device 100 of this embodiment, the thickness of the well layer is less than the thickness of the barrier layer. The well layer and/or barrier layer may or may not contain dopants.

由半導體元件的剖面觀之，磊晶疊層1可選擇性包含複數接觸部111遠離活性區13且靠近導電層4。複數接觸部111具有第一摻質，且複數接觸部111中的第一摻質濃度大於第一半導體結構11的第一摻質濃度。於本實施例中，於第一電極墊2A及第二電極墊2B下方未設有接觸部111，即第一電極墊2A與接觸部111互相錯位，第二電極墊2B與接觸部111互相錯位。在其他實施例中，複數接觸部111與第一電極墊2A、第二電極墊2B及延伸電極22可互相錯位。藉由上述之第一電極2與接觸部111的錯位關係，可以防止電流直接由第一電極2下方導通，藉此增加電流散布，進而提高半導體元件100的發光效率。複數接觸部111 的材料可包含III-V族半導體材料，例如二元III-V族半導體材料如GaAs、GaP、GaN等。 From the cross-section of the semiconductor device, the epitaxial stack 1 may selectively include a plurality of contact portions 111 away from the active region 13 and close to the conductive layer 4. The plurality of contact portions 111 have a first dopant, and the first dopant concentration in the plurality of contact portions 111 is greater than the first dopant concentration of the first semiconductor structure 11. In this embodiment, no contact portion 111 is provided under the first electrode pad 2A and the second electrode pad 2B, that is, the first electrode pad 2A and the contact portion 111 are misaligned with each other, and the second electrode pad 2B and the contact portion 111 are misaligned with each other. In other embodiments, the plurality of contact portions 111 and the first electrode pad 2A, the second electrode pad 2B and the extension electrode 22 may be misaligned with each other. By the misaligned relationship between the first electrode 2 and the contact portion 111, it is possible to prevent the current from being directly conducted from below the first electrode 2, thereby increasing the current spreading and further improving the luminous efficiency of the semiconductor element 100. The material of the plurality of contact portions 111 may include III-V semiconductor materials, such as binary III-V semiconductor materials such as GaAs, GaP, GaN, etc.

第一半導體結構11、第二半導體結構12、活性區13、第一侷限層14以及第二侷限層15可分別包含三五族半導體材料。上述三五族半導體材料可包含Al、Ga、As、P或In。在一實施例中，第一半導體結構11、第二半導體結構12、活性區13、第一侷限層14以及第二侷限層15不包含N。具體來說，上述三五族半導體材料可為二元化合物半導體(如GaAs或GaP)、三元化合物半導體(如InGaAs、AlGaAs、InGaP或AlInP)或四元化合物半導體(如AlGaInAs、AlGaInP、InGaAsP、InGaAsN或AlGaAsP)。於一實施例，活性區13實質上由三元化合物半導體(如InGaAs、AlGaAs、InGaP或AlInP)或四元化合物半導體(如AlGaInAs、AlGaInP、InGaAsP或AlGaAsP)所組成。 The first semiconductor structure 11, the second semiconductor structure 12, the active region 13, the first confinement layer 14, and the second confinement layer 15 may include Group III-V semiconductor materials, respectively. The Group III-V semiconductor materials may include Al, Ga, As, P, or In. In one embodiment, the first semiconductor structure 11, the second semiconductor structure 12, the active region 13, the first confinement layer 14, and the second confinement layer 15 do not include N. Specifically, the Group III-V semiconductor materials may be binary compound semiconductors (such as GaAs or GaP), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP, or AlInP), or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the active region 13 is substantially composed of a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP or AlInP) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, InGaAsP or AlGaAsP).

半導體元件100可包含雙異質結構(double heterostructure，DH)、雙側雙異質結構(double-side double heterostructure，DDH)或多重量子井(multiple quantum wells，MQW)結構。根據一實施例，當半導體元件100為發光元件時，活性區13可由第一半導體結構11朝第二半導體結構12的方向發出一光線。所述光線包含可見光或不可見光。半導體元件100所發出之光線波長決定於活性區13之材料。活性區13之材料可包含InGaAs、AlGaAsP或GaAsP、InGaAsP、AlGaAs、AlGaInAs、InGaP或AlGaInP。舉例來說：活性區13可以發射出峰值波長為700至1700nm的紅外光、峰值波長為610nm至700nm的紅光、或是峰值波長為530nm至600nm的黃光。於本實施例中，活性區13發出峰值波長為730nm至1100nm的紅外光。 The semiconductor device 100 may include a double heterostructure (DH), a double-side double heterostructure (DDH) or a multiple quantum wells (MQW) structure. According to one embodiment, when the semiconductor device 100 is a light-emitting device, the active region 13 may emit a light from the first semiconductor structure 11 toward the second semiconductor structure 12. The light includes visible light or invisible light. The wavelength of the light emitted by the semiconductor device 100 is determined by the material of the active region 13. The material of the active region 13 may include InGaAs, AlGaAsP or GaAsP, InGaAsP, AlGaAs, AlGaInAs, InGaP or AlGaInP. For example, the active region 13 can emit infrared light with a peak wavelength of 700 to 1700 nm, red light with a peak wavelength of 610 to 700 nm, or yellow light with a peak wavelength of 530 to 600 nm. In this embodiment, the active region 13 emits infrared light with a peak wavelength of 730 to 1100 nm.

基底7包含導電或絕緣材料。導電材料例如砷化鎵(GaAs)、磷化銦(InP)、碳化矽(SiC)、磷化鎵(Gap)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、 鍺(Ge)或矽(Si)。絕緣材料例如藍寶石(Sapphire)。在其他實施例中，基底7為一成長基板，即於基底7上可透過例如有機金屬化學氣相沉積法(MOCVD)磊晶形成磊晶疊層1。在一實施例中，基底7為一接合基板而非成長基板，其可藉由接合結構6而與磊晶疊層1相接合，如第1圖所示。 The substrate 7 includes a conductive or insulating material. Conductive materials include gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (Gap), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge) or silicon (Si). Insulating materials include sapphire. In other embodiments, the substrate 7 is a growth substrate, that is, an epitaxial stack 1 can be formed on the substrate 7 by, for example, metal organic chemical vapor deposition (MOCVD) epitaxy. In one embodiment, the substrate 7 is a bonding substrate rather than a growth substrate, which can be bonded to the epitaxial stack 1 by a bonding structure 6, as shown in FIG. 1.

第一電極2以及第二電極3用於與外部電源電性連接。第一電極2以及第二電極3的材料可相同或不同，例如分別包含金屬氧化材料、金屬或合金。金屬氧化材料包含氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)或氧化銦鋅(IZO)等。金屬可列舉如鍺(Ge)、鈹(Be)、鋅(Zn)、金(Au)、鉑(Pt)、鈦(Ti)、鋁(Al)、鎳(Ni)或銅(Cu)等。合金可包含選自由上述金屬所組成之群組中的至少兩者，例如鍺金鎳(GeAuNi)、鈹金(BeAu)、鍺金(GeAu)或鋅金(ZnAu)等。 The first electrode 2 and the second electrode 3 are used to be electrically connected to an external power source. The materials of the first electrode 2 and the second electrode 3 may be the same or different, for example, respectively including metal oxide materials, metals or alloys. The metal oxide material includes indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). The metal can be listed as germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni) or copper (Cu). The alloy may include at least two selected from the group consisting of the above metals, such as germanium-gold-nickel (GeAuNi), benzene-gold (BeAu), germanium-gold (GeAu) or zinc-gold (ZnAu).

絕緣部8包括折射係數(refractive index)小於2的絕緣材料，例如氮化矽(SiNx)、氧化鋁(AlOx)、氧化矽(SiOx)、氟化鎂(MgFx)或其組合。如第1圖所示，複數絕緣部8之間具有多個孔隙8a，導電層4可覆蓋於複數絕緣部8並填入孔隙8a中，且導電層4與磊晶疊層1在孔隙8a處可形成接觸區域。藉此，導電層4可與磊晶疊層1電連接。導電層4可包含金屬氧化材料，例如：氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化銦鎢(IWO)、氧化鋅(ZnO)、氧化銦鋅(IZO)或上述材料之組合。 The insulating portion 8 includes an insulating material with a refractive index less than 2, such as silicon nitride ( SiNx ), aluminum oxide ( AlOx ), silicon oxide ( SiOx ), magnesium fluoride ( MgFx ) or a combination thereof. As shown in FIG. 1 , there are a plurality of pores 8a between the plurality of insulating portions 8. The conductive layer 4 can cover the plurality of insulating portions 8 and fill the pores 8a. The conductive layer 4 and the epitaxial stack 1 can form a contact region at the pores 8a. Thereby, the conductive layer 4 can be electrically connected to the epitaxial stack 1. The conductive layer 4 may include a metal oxide material, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO) or a combination of the above materials.

反射層5可反射活性區13所發出的光線以朝第一電極2方向射出半導體元件100外。反射層5可包含半導體材料、金屬或合金。半導體材料 可包含三五族半導體材料，例如二元、三元或四元三五族半導體材料。金屬包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)或銀(Ag)等。合金可包含選自由上述金屬所組成之群組中的至少兩者。在一實施例中，反射層5可包含布拉格反射結構(Distributed Bragg Reflector structure，DBR)。布拉格反射結構可由不同折射率的兩種以上之半導體材料交替堆疊而形成，例如由AlAs/GaAs、AlGaAs/GaAs或InGaP/GaAs所形成。 The reflective layer 5 can reflect the light emitted by the active region 13 to emit it out of the semiconductor element 100 toward the first electrode 2. The reflective layer 5 can include semiconductor materials, metals or alloys. The semiconductor material can include III-V semiconductor materials, such as binary, ternary or quaternary III-V semiconductor materials. Metals include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au) or silver (Ag). The alloy can include at least two selected from the group consisting of the above metals. In one embodiment, the reflective layer 5 can include a Bragg reflector structure (Distributed Bragg Reflector structure, DBR). The Bragg reflector structure can be formed by alternately stacking two or more semiconductor materials with different refractive indices, such as AlAs/GaAs, AlGaAs/GaAs or InGaP/GaAs.

接合結構6連接基底7與反射層5。在一實施例中，接合結構6可為單層或多層(未繪示)。接合結構6之材料可包含透明導電材料、金屬或合金。透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)、石墨烯(graphene)或上述材料之組合。金屬包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鈦(Ti)、鎳(Ni)、鉑(Pt)或鎢(W)等。合金可包含選自由上述金屬所組成之群組中的至少兩者。 The bonding structure 6 connects the substrate 7 and the reflective layer 5. In one embodiment, the bonding structure 6 can be a single layer or multiple layers (not shown). The material of the bonding structure 6 can include a transparent conductive material, a metal or an alloy. The transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium caesium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene or a combination of the above materials. The metal includes but is not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), platinum (Pt) or tungsten (W). The alloy may include at least two selected from the group consisting of the above metals.

第4圖為本揭露內容一實施例之半導體組件300的剖面結構示意圖。請參照第4圖，半導體組件300包含半導體元件100或半導體元件200、封裝基板31、載體33、接合線35、接觸結構36以及封裝層38。封裝基板31可包含陶瓷或玻璃材料。封裝基板31中具有多個通孔32。通孔32中可填充有導電性材料如金屬等而有助於導電或/且散熱。載體33位於封裝基板31一側的表面上，且亦包含導電性材料，如金屬。接觸結構36位於封裝基板31另一側的表面上。在本實施例中，接觸結構36包含第一接觸墊36a以及第二接觸墊36b，且第一接觸墊 36a以及第二接觸墊36b可藉由通孔32而與載體33電性連接。在一實施例中，接觸結構36可進一步包含散熱墊(thermal pad)(未繪示)，例如位於第一接觸墊36a與第二接觸墊36b之間。 FIG. 4 is a schematic diagram of the cross-sectional structure of a semiconductor component 300 of an embodiment of the present disclosure. Referring to FIG. 4, the semiconductor component 300 includes a semiconductor element 100 or a semiconductor element 200, a packaging substrate 31, a carrier 33, a bonding wire 35, a contact structure 36, and a packaging layer 38. The packaging substrate 31 may include a ceramic or glass material. The packaging substrate 31 has a plurality of through holes 32. The through holes 32 may be filled with conductive materials such as metals to facilitate electrical conduction and/or heat dissipation. The carrier 33 is located on the surface of one side of the packaging substrate 31 and also includes conductive materials such as metals. The contact structure 36 is located on the surface of the other side of the packaging substrate 31. In this embodiment, the contact structure 36 includes a first contact pad 36a and a second contact pad 36b, and the first contact pad 36a and the second contact pad 36b can be electrically connected to the carrier 33 through the through hole 32. In one embodiment, the contact structure 36 can further include a thermal pad (not shown), for example, located between the first contact pad 36a and the second contact pad 36b.

半導體元件100/200位於載體33上。在本實施例中，載體33包含第一部33a及第二部33b，半導體元件100藉由接合線35而與載體33的第二部33b電性連接。接合線35的材質可包含金屬，例如金、銀、銅、鋁或至少包含上述任一元素之合金。封裝層38覆蓋於半導體元件100/200上，具有保護半導體元件100之效果。具體來說，封裝層38可包含樹脂材料如環氧樹脂(epoxy)、矽氧烷樹脂(silicone)等。封裝層38選擇性地可包含複數個波長轉換粒子(圖未示)以轉換半導體元件100/200所發出的第一光為一第二光。第二光的波長大於第一光的波長。 The semiconductor element 100/200 is located on a carrier 33. In the present embodiment, the carrier 33 includes a first portion 33a and a second portion 33b, and the semiconductor element 100 is electrically connected to the second portion 33b of the carrier 33 via a bonding wire 35. The material of the bonding wire 35 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of the above elements. The encapsulation layer 38 covers the semiconductor element 100/200 and has the effect of protecting the semiconductor element 100. Specifically, the encapsulation layer 38 may include a resin material such as epoxy, silicone, etc. The encapsulation layer 38 may selectively include a plurality of wavelength conversion particles (not shown) to convert the first light emitted by the semiconductor element 100/200 into a second light. The wavelength of the second light is greater than that of the first light.

第5圖為本揭露內容一實施例之感測模組400的部分剖面結構示意圖，感測模組400包含一承載體420、第一半導體元件411及第二半導體元件431。第一半導體元件411及/或第二半導體元件431可以為上述的半導體元件100/200。承載體420包含第一擋牆421、第二擋牆422、第三擋牆423、載板424、一第一空間425及第二空間426，第一半導體元件411位於第一擋牆421與第二擋牆422之間的空間425中，第二半導體元件431位於第二擋牆422與第三擋牆423之間的空間426中。第一半導體元件411及/或第二半導體元件431可以為如第1圖之垂直式晶片。第一半導體元件411及第二半導體元件431位於載板424上，並與載板424上的電路連接結構(圖未示)形成電性連接。在本實施中，第一半導體元件411為一發光元件，第二半導體元件431為一光接收元件，且感測模組400可置於穿戴裝置(例如；手錶、耳機)中，第一半導體元件411發出之光線穿過皮膚並照射身體細胞以及血液，再藉由第二半導體元件431吸收從身體細胞以及血液散射 /反射回來的光，根據此反射、散射光的變化，用以偵測人體的生理訊號，例如：心率、血糖、血壓、血氧濃度等。 FIG. 5 is a schematic diagram of a partial cross-sectional structure of a sensing module 400 according to an embodiment of the present disclosure. The sensing module 400 includes a carrier 420, a first semiconductor element 411, and a second semiconductor element 431. The first semiconductor element 411 and/or the second semiconductor element 431 may be the semiconductor element 100/200 described above. The carrier 420 includes a first baffle 421, a second baffle 422, a third baffle 423, a carrier 424, a first space 425, and a second space 426. The first semiconductor element 411 is located in the space 425 between the first baffle 421 and the second baffle 422, and the second semiconductor element 431 is located in the space 426 between the second baffle 422 and the third baffle 423. The first semiconductor element 411 and/or the second semiconductor element 431 can be a vertical chip as shown in FIG. 1. The first semiconductor element 411 and the second semiconductor element 431 are located on the carrier 424 and are electrically connected to the circuit connection structure (not shown) on the carrier 424. In this embodiment, the first semiconductor element 411 is a light-emitting element, the second semiconductor element 431 is a light-receiving element, and the sensing module 400 can be placed in a wearable device (e.g., a watch, earphones). The light emitted by the first semiconductor element 411 passes through the skin and irradiates the body cells and blood, and then the second semiconductor element 431 absorbs the light scattered/reflected from the body cells and blood. According to the changes in the reflected and scattered light, physiological signals of the human body, such as heart rate, blood sugar, blood pressure, blood oxygen concentration, etc., are detected.

具體來說，本揭露內容之磊晶結構、半導體元件及半導體組件可應用於照明、醫療、顯示、通訊、感測、電源系統等領域的產品，例如燈具、監視器、手機、平板電腦、車用儀表板、電視、電腦、穿戴裝置(如手錶、手環、項鍊等)、交通號誌、戶外顯示器、醫療器材等。 Specifically, the epitaxial structures, semiconductor elements and semiconductor components disclosed herein can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply system, etc., such as lamps, monitors, mobile phones, tablet computers, car dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signs, outdoor displays, medical equipment, etc.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，所屬技術領域中具有通常知識者應理解，在不脫離本發明之精神和範圍內可作些許之修飾或變更，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外，上述實施例內容在適當的情況下可互相組合或替換，而非僅限於所描述之特定實施例。舉例而言，在一實施例中所揭露特定構件之相關參數或特定構件與其他構件的連接關係亦可應用於其他實施例中，且均落於本發明之權利保護範圍。 Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the relevant technical field should understand that some modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application. In addition, the contents of the above embodiments can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component disclosed in an embodiment or the connection relationship between a specific component and other components can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

100:半導體元件 100:Semiconductor components

2A:第一電極墊 2A: First electrode pad

2B:第二電極墊 2B: Second electrode pad

22:延伸電極 22: Extended electrode

22a:第一部 22a: Part 1

22b:第二部 22b: Part 2

22c:第三部 22c: Part 3

22d:第四部 22d: Part 4

221:第一部分 221: Part 1

222:第二部分 222: Part 2

223:第三部分 223: Part 3

224:第四部份 224: Part 4

225:第五部分 225: Part 5

226:第六部分 226: Part 6

227:第七部分 227: Part 7

228:第八部分 228: Part 8

229:第九部分 229: Part 9

S1:第一區域 S1: First area

S2:第二區域 S2: Second area

S3:第三區域 S3: The third area

S4:第四區域 S4: The fourth area

S5:第五區域 S5: The fifth area

S6:第六區域 S6: The sixth area

S7:第七區域 S7: Area 7

S8:第八區域 S8: The eighth area

S9:第九區域 S9: Area 9

E1:第一邊 E1: First side

E2:第二邊 E2: Second side

V:虛擬線 V:Virtual line

C:中心 C: Center

L1:對角線 L1: diagonal

L2:第一對稱線 L2: first symmetry line

L3:第二對稱線 L3: Second symmetry line

w1:第一寬度 w1: first width

w2:第二寬度 w2: second width

D:距離 D: Distance

Claims (10)

一種半導體元件，包括：一磊晶疊層，具有一上表面由九個區域組成，且該九個區域具有大致相同的面積，且該磊晶疊層包含一第一半導體結構、一第二半導體結構位於該第一半導體結構上、及一活性區位於該第一半導體結構及該第二半導體結構之間，該第二半導體結構為n型；以及一第一電極，位於該上表面上且與該第二半導體結構直接接觸，該第一電極包含一第一電極墊及一延伸電極連接於該第一電極墊；其中，該延伸電極具有九個部分分別各位於該九個區域上，該九個部分各具有一遮光比率，且該些遮光比率中至少有五個大致相同。 A semiconductor element includes: an epitaxial stack having an upper surface composed of nine regions, and the nine regions have substantially the same area, and the epitaxial stack includes a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active region located between the first semiconductor structure and the second semiconductor structure, and the second semiconductor structure is n-type; and a first electrode located on the upper surface and directly in contact with the second semiconductor structure, the first electrode including a first electrode pad and an extended electrode connected to the first electrode pad; wherein the extended electrode has nine parts respectively located on the nine regions, and the nine parts each have a shading ratio, and at least five of the shading ratios are substantially the same. 一種半導體元件包括：一磊晶疊層，具有一上表面由九個區域組成，且該九個區域具有大致相同的面積；以及一第一電極，位於該上表面上，包含一第一電極墊、一第二電極墊及一延伸電極連接於該第一電極墊，且該第二電極墊透過該延伸電極與該第一電極墊連接；其中，該延伸電極具有九個部分分別各位於該九個區域上，該九個部份各具有一遮光比率，且該些遮光比率中至少有五個大致相同。 A semiconductor element includes: an epitaxial stack having an upper surface composed of nine regions, and the nine regions have substantially the same area; and a first electrode, located on the upper surface, including a first electrode pad, a second electrode pad and an extended electrode connected to the first electrode pad, and the second electrode pad is connected to the first electrode pad through the extended electrode; wherein the extended electrode has nine parts respectively located on the nine regions, and the nine parts each have a shading ratio, and at least five of the shading ratios are substantially the same. 如申請專利範圍第1或2項所述之半導體元件，另包含複數絕緣部及一基底，該複數絕緣部位於該磊晶疊層及該基底之間。 The semiconductor device described in item 1 or 2 of the patent application scope further includes a plurality of insulating portions and a substrate, wherein the plurality of insulating portions are located between the epitaxial stack and the substrate. 如申請專利範圍第1或2項所述之半導體元件，其中，該九個部分中的至少五個部分皆具有端點，且該些端點互相分離。 A semiconductor device as described in item 1 or 2 of the patent application, wherein at least five of the nine parts have endpoints, and the endpoints are separated from each other. 如申請專利範圍第1或2項所述之半導體元件，其中，該上表面為正方形。 A semiconductor device as described in item 1 or 2 of the patent application, wherein the upper surface is a square. 如申請專利範圍第1或2項所述之半導體元件，其中，該上表面具有一邊長大於30mil且小於100mil。 A semiconductor device as described in item 1 or 2 of the patent application, wherein the upper surface has a side length greater than 30 mil and less than 100 mil. 如申請專利範圍第1或2項所述之半導體元件，其中，該上表面具有一中心區域，該第一電極墊位於該中心區域。 A semiconductor device as described in item 1 or 2 of the patent application, wherein the upper surface has a central area, and the first electrode pad is located in the central area. 如申請專利範圍第1或2項所述之半導體元件，其中，該第一電極具有一總遮光比率為6%~12%。 A semiconductor element as described in item 1 or 2 of the patent application, wherein the first electrode has a total light shielding ratio of 6% to 12%. 如申請專利範圍第1或2項所述之半導體元件，其中，該九個區域中定義一中心區域及一邊緣區域，且位於該中心區域的該延伸電極之該部分的該遮光比率大於位於該邊緣區域的該延伸電極之該部分的該遮光比率。 A semiconductor device as described in item 1 or 2 of the patent application, wherein a central region and an edge region are defined in the nine regions, and the shading ratio of the portion of the extended electrode located in the central region is greater than the shading ratio of the portion of the extended electrode located in the edge region. 如申請專利範圍第1或2項所述之半導體元件，更包含一第二電極，且該磊晶疊層位於該第一電極及該第二電極之間。 The semiconductor device as described in item 1 or 2 of the patent application scope further includes a second electrode, and the epitaxial stack is located between the first electrode and the second electrode.
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Publication number Priority date Publication date Assignee Title
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709432A (en) 2012-05-10 2012-10-03 施科特光电材料(昆山)有限公司 Network-shaped electrode applicable to high-power GaN-based LED chips

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