TWI740479B - 半導體封裝基材精細節距金屬凸塊及強化結構 - Google Patents

半導體封裝基材精細節距金屬凸塊及強化結構 Download PDF

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TWI740479B
TWI740479B TW109114444A TW109114444A TWI740479B TW I740479 B TWI740479 B TW I740479B TW 109114444 A TW109114444 A TW 109114444A TW 109114444 A TW109114444 A TW 109114444A TW I740479 B TWI740479 B TW I740479B
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metal
layer
build
smt
packaging substrate
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TW109114444A
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TW202111900A (zh
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徐潤忠
鍾智明
軍 翟
高一凡
永斗 全
金太貴
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美商蘋果公司
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Abstract

所描述者係半導體封裝基材及處理次序。在一實施例中，一封裝基材包括一增層結構及一圖案化金屬接觸層，該圖案化金屬接觸層部分埋置在該增層結構內並自該增層結構突出。該圖案化金屬接觸層可包括一晶片安裝區內之一表面安裝(SMT)金屬凸塊陣列、一金屬阻塞結構、或其組合。

Description

半導體封裝基材精細節距金屬凸塊及強化結構
本文描述的實施例係關於半導體封裝，且更具體地關於金屬凸塊及機械強化結構。
小型化係在半導體產業中驅動小的形狀因數更薄的趨勢。無芯基材(且尤其係具有基於Ajinomoto增層膜(Ajinomoto build-up film,ABF)之材料者)已使用在業界中以製作薄介電層而無需玻璃織造強化。然而，此類薄基材從機械觀點係本質上較弱的，特別係由於沒有厚的內芯。
額外地，先進的覆晶封裝基材需要較精細的凸塊節距，以支援較小晶圓節點技術。在一些實施方案中，由於產率及工具限制，習知墊上焊料(solder on pad,SOP)表面加工傾向於僅支援大於100μm的凸塊節距。已引入表面安裝(surface mount,SMT)金屬凸塊至業界以適應較精細的凸塊節距，其中封裝基材SMT金屬凸塊作用為用於晶粒連接之功能性通孔著陸墊。
描述用於形成一圖案化金屬基底層之封裝基材及製造方法，該圖案化金屬基底層包括一SMT金屬凸塊陣列、金屬阻塞結構、或其組合，其中該圖案化金屬基底層係部分埋置在一增層結構內並自該增層結構突出。根據實施例之該等SMT金屬凸塊及金屬阻塞結構可具有針對該圖案化金屬基底層經埋置在該增層結構中的一部分及該圖案化金屬基底層延伸在該增層結構側向相鄰於該SMT金屬凸塊或金屬阻塞結構之一最頂部表面上方的一部分之特徵筆直側壁。
根據實施例之該圖案化金屬基底層可使用回蝕技術表現，其中該回蝕操作可在形成一表面加工層之前或之後執行。
100:封裝基材/增層結構
110:增層結構
112:介電層
114:金屬佈線層/介電層
115:介電層
116:通孔
117:最頂部表面
118:接觸墊
119:頂部表面
120:圖案化金屬接觸層/金屬化層
122:表面安裝(SMT)金屬凸塊
123A:著陸區
123B:著陸區
124:金屬阻塞結構/主體金屬層
124A:金屬線
124B:幾何形狀
124C:金屬平面
125:支撐區/晶片安裝區
132:筆直側壁
132A:部分
132B:部分
134:筆直側壁
134A:部分
134B:部分
141:底部表面
142:主體金屬層
143:頂部表面
144:表面加工層
145:虛置金屬結構
146:無電鎳層/鎳層/頂部表面
148:無電鈀及浸金層
149:頂部表面
150:障壁層
151:開口
160:溝
162:底部表面
200:裝置
202:邊緣
210:底部填充材料
212:接觸件
214:焊料凸塊
300:載體基材
302:晶種層
304:阻塞層
305:圖案化金屬基底層
306:開口
310:乾膜光阻
320:遮罩層
4010:操作
4020:操作
4030:操作
4040:操作
4050:操作
4052:操作
4060:操作
4062:操作
KOZ1:禁入區
KOZ2:禁入區
KOZ3:禁入區
th:底部填充高度
tt:厚度
〔圖1〕係根據一實施例之封裝基材之特寫截面側視圖繪示，該封裝基材包括一增層結構及一圖案化金屬接觸層，該圖案化金屬接觸層部分埋置在該增層結構內並自該增層結構突出。
〔圖2〕係根據實施例之各種金屬阻塞結構之示意俯視圖繪示。
〔圖3A〕係根據一實施例之半導體封裝之特寫截面側視圖繪示，該半導體封裝包括安裝在封裝基材上之裝置，該封裝基材係在回蝕技術之後以表面加工製造。
〔圖3B〕係根據一實施例之半導體封裝之特寫截面側視圖繪示，該半導體封裝包括安裝在封裝基材上之裝置，該封裝基材係在回蝕技術之前以表面加工製造。
〔圖4〕係根據實施例之繪示在回蝕技術之後以表面加工及在回蝕技術之前以表面加工製造封裝基材之方法的流程圖。
〔圖5A〕至〔圖5G〕係根據一實施例之回蝕製造次序之後的表面加工之示意截面側視圖繪示。
〔圖6A〕至〔圖6G〕係根據一實施例之回蝕製造次序之前的表面加工之示意截面側視圖繪示。
〔圖7A〕至〔圖7C〕係根據一實施例之根據回蝕製造次序之後的表面加工製造之SMT金屬凸塊之示意截面側視圖繪示。
〔圖8A〕至〔圖8C〕係根據一實施例之根據回蝕製造次序之前的表面加工製造之SMT金屬凸塊之示意截面側視圖繪示。
〔圖9A〕至〔圖9B〕係根據實施例之封裝基材變化的特寫截面側視圖繪示，該等封裝基材變化包括突出在SMT金屬凸塊陣列上方的金屬阻塞結構。
〔圖10A〕至〔圖10G〕係根據一實施例之用以形成圖9A之結構的回蝕製造次序之後的表面加工之示意截面側視圖繪示。
〔圖11A〕至〔圖11G〕係根據一實施例之用以形成圖9B之結構的回蝕製造次序之後的表面加工之示意截面側視圖繪示。
〔圖12A〕至〔圖12B〕係根據實施例之封裝基材變化的特寫截面側視圖繪示，該等封裝基材變化包括形成在SMT金屬凸塊陣列及金屬阻塞結構之間的增層結構中的一溝
〔圖13A〕至〔圖13F〕係根據一實施例之用以形成圖12A之結構的回蝕製造次序之後的表面加工之示意截面側視圖繪示。
〔圖14A〕至〔圖14F〕係根據一實施例之用以形成圖12B之結構的回蝕製造次序之後的表面加工之示意截面側視圖繪示。
實施例描述半導體封裝基材處理次序及結構，其中表面安裝(SMT)金屬凸塊及強化結構兩者可係同時形成以達成精細凸塊節距及結構強化。
已觀察到SMT金屬凸塊技術面臨達到精確及可靠的凸塊直徑及高度的挑戰，尤其是用於在多晶片模組(multi-chip module,MCM)中具有多個大尺寸晶粒之應用。根據實施例之SMT金屬凸塊結構係使用其中SMT金屬凸塊(在本文中亦簡稱為金屬凸塊)係在封裝基材增層結構之蝕刻(薄化)之後表現的處理次序來製造。根據實施例，該等金屬凸塊可藉由微影程序來形成，該微影程序導致金屬凸塊埋置於介電層(諸如用於封裝基材增層結構之頂部介電層(封裝))中。例如，此可係無芯基材。此接著不攻擊金屬凸塊(墊)側壁及將墊尺寸保持為設計值的金屬晶種蝕刻。額外地，不需要額外的銅後電鍍。各種類的表面加工可與金屬凸塊形成(諸如無電鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)、有機可焊性保護劑(organic solderability preservatives,OSP))等整合。
已觀察到電氣故障可能在熱循環、墜落測試等期間由於在晶粒隅角處的通孔或跡線裂痕而發生於薄的封裝基材(諸如無芯基材)中。已額外觀察到晶粒隅角周圍的晶粒底部填充體積可係不一致的。根據實施例之強化結構可在指定位置處機械強化封裝基材以抵抗機械應力及在嚴峻條件下防止製造 及可靠性問題。此外，強化結構可在指定位置處限制底部填充材料流動，並維持形狀(例如鑲角片)。例如，強化結構可在晶粒隅角處維持足夠的底部填充材料以覆蓋晶粒矽厚度的至少50%。強化結構可額外地經工程設計以藉由各種類的表面加工或後處理(例如Ni/Au、Ni、結晶粒尺寸、及金屬有機塗層)來適應不同類型的底部填充材料。更重要地，強化結構可與提供用於精細節距晶粒附接及封裝基材強化的整合方法及結構的SMT金屬凸塊圖案同時形成。
在各種實施例中，參照圖式進行說明。然而，某些實施例可在無這些特定細節之一或多者的情況下實行或可與其他已知的方法及組態結合實行。在下列敘述中，為了提供對實施例的全面瞭解而提出眾多特定細節(例如，特定組態、尺寸、及程序等)。在其他例子中，為了避免不必要地使本實施例失焦，所以並未特別詳細地敘述公知的半導體程序及製造技術。此專利說明書通篇指稱的「一實施例(one embodiment)」係指與該實施例一同描述之具體特徵、結構、組態、或特性係包括在至少一實施例中。因此，此專利說明書通篇於各處出現之詞組「在一實施例中(in one embodiment)」不必然指稱相同實施例。此外，在一或多個實施例中，可以任何合適的方式結合特定特徵、結構、組態、或特性。
如本文所用之「在...上面(above)」、「在...上方(over)」、「至(to)」、「介於...之間(between)」、「橫跨(spanning)」、及「在...上(on)」之用語可指稱一層相對於其他層之一相對位置。一層在另一層「上面」、在另一層「上方」、「橫跨」另一層、或在另一層「上」或者一層接合「至」另一層或與另一層「接觸(contact)」可直接與另一層接觸或可具有一或多個中介層。一層介於(多個)層「之間」可直接與該等層接觸或可具有一或多個中介層。
現參照圖1，提供封裝基材100之特寫截面側視圖繪示，該封裝基材包括一增層結構110及一圖案化金屬接觸層120，該圖案化金屬接觸層部分埋置在增層結構110內並自該增層結構突出。應瞭解到圖1的此繪示僅係繪示數個相關特徵之封裝基材100的一部分。如所示，圖案化金屬接觸層120在著陸區123A、123B等中包括表面安裝(SMT)金屬凸塊122之陣列。根據實施例之SMT金屬凸塊122可作用為著陸墊，並且取決於待安裝之裝置結構而定尺寸及間隔。例如，在著陸區123A中的SMT金屬凸塊122可經定尺寸以接收晶片(或晶粒)，諸如SoC晶片。在著陸區123B中的SMT金屬凸塊122可較大且經定尺寸以接收晶片級封裝(chip scale package,CSP)。圖案化金屬接觸層120可在支撐區125中額外包括金屬阻塞結構124。金屬阻塞結構124可係形成而側向相鄰於在著陸123A、123B中之SMT金屬凸塊122。
增層結構110可包括一或多個介電層114及金屬佈線層114。通孔116可用以連接金屬佈線層114。通孔116可額外用以將金屬佈線層114連接至STM金屬凸塊122及封裝基材100之背側上的接觸墊118。例如，接觸墊118可係以接收用於安裝至電路板上的焊料凸塊(例如球柵陣列)。仍參照圖1，增層結構110可包括頂部介電層115，金屬化層120係埋置在該頂部介電層內。替代地，金屬化層可係埋置在增層結構110的多個層內。
根據實施例之增層結構110可使用薄膜處理技術形成。例如，增層結構100可係使用包括ABF樹脂之層壓及固化步驟的半加成ABF程序、雷射通孔開口形成、及用於形成通孔116及金屬佈線層114之銅電鍍來形成。根據實施例，介電層112、115可係非玻璃強化有機材料。此外，封裝基材100可係無芯基材。根據實施例之金屬阻塞結構124可提供結構完整性至封裝基材100，而不 需要來自芯或玻璃強化的額外機械支撐。然而，根據實施例之金屬阻塞結構124並不排除併入芯或玻璃強化。
現參照圖2，提供根據實施例之各種金屬阻塞結構之示意俯視圖繪示。在一實施例中，金屬阻塞結構124包括平行於安裝在SMT金屬凸塊122之陣列的裝置200之邊緣202行進的複數個平行金屬線124A。在一實施例中，金屬阻塞結構124包括重複幾何形狀124B之陣列或金屬平面124C，其相鄰於安裝在SMT金屬凸塊陣列上之裝置200的一隅角。在一實施例中，金屬阻塞結構124可側向圍繞(例如完全側向圍繞)晶片安裝區125中之SMT金屬凸塊122的陣列。各種金屬阻塞結構係可行的。
在一態樣中，金屬阻塞結構124可由於彎曲及熱循環而對封裝基材100提供機械完整性，且額外可作用以含有用於安裝在封裝基材上的裝置(例如晶片、CSP)之底部填充材料。例如，金屬線124A可作為加強筋(rebar)。在裝置(例如晶片、CSP)隅角之遮蔽處，金屬阻塞結構亦可係自訂的(諸如類似蜂巢)、金屬平面、網格等。具體而言，已觀察到應力可集中於所安裝之裝置(例如晶片、CSP)隅角處而導致跡線裂痕。在圖2所繪示之具體實施例中，金屬阻塞結構124在所安裝之裝置200隅角正下方。
金屬阻塞結構124及所安裝之裝置200配置可額外藉由各種禁入區(KOZ1、KOZ2、KOZ3)來特徵化。例如，金屬線124A可係放置在由KOZ1定義之遠離所安裝之裝置200邊緣202之一側向距離處。金屬阻塞結構124之遠邊緣可由KOZ2定義。額外地，在所安裝之裝置200下方最靠近最近的SMT金屬凸塊122之金屬阻塞結構124的侵入可界定出KOZ3。例如，此距離在施配側上可 小於800μm。在所安裝之裝置200隅角下方的金屬阻塞結構124的遮蔽可幫助保持底部填充材料及/或在此等高應力區處提供更密集的機械支撐結構。
金屬阻塞結構之表面能可額外經工程設計以藉由整合各種類之表面加工層或後處理來適應不同類型的底部填充材料。在一些實施例中，圖案化金屬接觸層120可包括相同的主體金屬層及在主體金屬層上方之相同的表面加工層，以用於SMT金屬凸塊122及金屬阻塞結構124兩者。使用根據實施例之回蝕製造技術，SMT金屬凸塊及金屬阻塞結構124兩者可具有針對經埋置在該增層結構中的一部分及延伸在該增層結構側向相鄰之最頂部表面117上方的一部分之特徵筆直側壁。SMT金屬凸塊及金屬阻塞結構124之最終結構特性可取決於在表面加工之前或之後是否執行回蝕。亦可添加額外的結構，包括在SMT金屬凸塊陣列與金屬阻塞結構之間形成增層結構中的溝，及升高金屬阻塞結構，使得其突出在SMT金屬凸塊陣列上方。
圖3A係根據一實施例之半導體封裝之特寫截面側視圖繪示，該半導體封裝包括安裝在封裝基材上之裝置200，該封裝基材係在回蝕技術之後以表面加工製造。圖3B係根據一實施例之半導體封裝之特寫截面側視圖，該半導體封裝包括安裝在封裝基材上之裝置200，該封裝基材係在回蝕技術之前以表面加工製造。參照圖3A至圖3B兩者，裝置200包括接觸件212(例如立柱、墊等)，其係安裝在SMT金屬凸塊122上且底部填充有一底部填充材料210。例如，裝置200可使用焊料凸塊214接合。金屬阻塞結構124可作用以保持在下方(及沿著裝置邊緣)的底部填充材料210，並且可防止底部填充材料210進一步擴散跨越封裝基材之表面。在一實施例中，底部填充材料沿著裝置邊緣吸附， 使得沿著裝置邊緣的底部填充高度(th)覆蓋裝置200厚度(tt)之至少50%，例如矽晶粒厚度的至少50%。
根據實施例之圖案化金屬接觸層120可係多層結構。如所繪示，圖案化金屬接觸層120可包括主體金屬層142(例如銅)及在主體金屬層142上方的表面加工層144。表面加工層亦可係多層結構。所繪示之具體實施例顯示ENEPIG結構，其包括無電鎳層146、及無電鈀及浸金層148。根據實施例，各SMT金屬凸塊包括針對該SMT金屬凸塊經埋置在該增層結構中的一部分132A及該SMT金屬凸塊延伸在該增層結構側向相鄰於SMT金屬凸塊122之一最頂部表面117上方的一部分132B之筆直側壁132。類似地，各金屬阻塞結構124包括針對金屬阻塞結構124經埋置在該增層結構中的一部分134A及該金屬阻塞結構延伸在該增層結構側向相鄰於金屬阻塞結構124之一最頂部表面117上方的一部分134B之筆直側壁134。
現具體參照圖3A，針對SMT金屬凸塊122及金屬阻塞結構124兩者，主體金屬層142之頂部表面143延伸於側向緊鄰之增層結構的最頂部表面117上方。額外地，針對SMT金屬凸塊122及金屬阻塞結構124兩者，筆直側壁132、134係由主體金屬層142界定，且表面加工層144分別覆蓋主體金屬層142之頂部表面146、及SMT金屬凸塊122與金屬阻塞結構124之部分132B、134B之筆直側壁132、134兩者，其等延伸於側向緊鄰的增層結構之最頂部表面117上方。以此方式，主體金屬層142(例如銅)係藉由增層結構及表面加工層144來完全封裝。
現具體參照圖3B，針對各SMT金屬凸塊122及各金屬阻塞結構124之筆直側壁132、134橫跨主體金屬層142及表面加工層144。如所示，針對 各SMT金屬凸塊122及各金屬阻塞結構124之主體金屬層142係完全埋置在增層結構中並且由表面加工層144覆蓋。額外地，針對各SMT金屬凸塊122及各金屬阻塞結構124之各表面加工層144係部分埋置在增層結構中並且部分延伸於側向緊鄰之增層結構之最頂部表面117上方。例如，此可與鎳層146一起。
仍參照圖3A至圖3B，根據實施例，底部填充材料210可自裝置200向外延伸或掠過，並且覆蓋一些(但非所有)相鄰金屬阻塞結構124。以此方式，多個金屬阻塞結構124(諸如平行線或重複幾何圖案)可用以彼此支撐。額外地，多個金屬阻塞結構124可作用以提供機械支撐而非含有底部填充材料210。額外地，金屬阻塞結構124可在裝置200遮蔽中，使得其等至少部分位於裝置200之側邊緣或(多個)隅角下方(及其內部)。
圖4係根據實施例之繪示在回蝕技術之後以表面加工及在回蝕技術之前以表面加工製造封裝基材之方法的流程圖。圖5A至圖5G係根據一實施例之回蝕製造次序之後的表面加工之示意截面側視圖繪示。圖6A至圖6G係根據一實施例之回蝕製造次序之前的表面加工之示意截面側視圖繪示。為了清楚及簡明起見，圖4之流程圖與圖5A至圖5G及圖6A至圖6G中繪示的次序同時描述。
在操作4010，圖案化金屬基底層305係形成於載體基材300上。例如，圖案化金屬基底層305可包括主體金屬層142及障壁層150。如圖5A至圖5B及圖6A至圖6B所示，此可藉由在載體基材300上形成晶種層302(例如銅)，接著形成乾膜光阻310及電鍍障壁層150及主體金屬層142來完成。在一實施例中，障壁層150可由在移除晶種層302期間作用為蝕刻障壁的材料所形成。障壁層150亦係促進回蝕技術之暫時層。如所繪示，障壁層150及主體金屬 層142之總高度可小於乾膜光阻310之總厚度，以控制SMT金屬凸塊高度。然而，亦可執行後續平面化。現參照圖5C及圖6C，乾膜光阻310經移除，且在操作4020，增層結構係形成在圖案化金屬基底層305上。在所繪示的具體實施例中，僅繪示該增層結構之單一頂部介電層115，雖然可形成圖1的完整增層結構。在此階段，圖案化金屬基底層305係埋置在增層結構(例如，頂部介電層115)中。
現參照圖5D至圖5E及圖6D至圖6E，在操作4030，載體基材300及晶種層302經移除。在移除銅晶種層302期間，障壁層150可保護銅主體金屬層142。接著障壁層150經移除，導致增層結構中的開口151或凹部。在此階段，主體金屬層142係凹陷在增層結構內部。
主體金屬層142的厚度可取決於具體處理次序。例如，在圖5A至圖5G中繪示的次序中，障壁層150可具有作用為蝕刻障壁所需的最小厚度。然而，在圖6A至圖6G中繪示的次序中，障壁層150可較厚，且障壁層之移除可在主體金屬層142上方在增層結構中留下一凹部，其足以形成表面加工層144。同樣地，主體金屬層142的相對厚度可取決於處理次序。
在圖5F中繪示之回蝕製造次序之後的表面加工中，增層結構(例如頂部介電層115)之厚度係在操作4050減少，使得主體金屬層142之頂部表面143自增層結構突出(例如在增層結構之最頂部表面117上方)。在一實施例中，回蝕係電漿乾式蝕刻或濕式化學蝕刻技術。例如，此可包括CF4化學或化學機械研磨(chemical mechanical polishing,CMP)。接著，表面加工層144可係在操作4052形成於經暴露之主體金屬層142上，如在圖5G中所繪示者。
在圖6G中繪示之回蝕製造次序之前的表面加工中，表面加工層144係接著形成在增層結構中之開口151(凹部)內之經暴露的主體金屬層142(其起因於移除障壁層150)上。在一實施例中，表面加工層144完全含有開口151以控制形狀及高度。增層結構(例如頂部介電層115)之厚度係在操作4062減少，使得表面加工層144之頂部表面149自該增層結構突出，且主體金屬層142之頂部表面143係埋置在該增層結構中，如在圖6G中所繪示者。在一實施例中，回蝕係電漿乾式蝕刻或濕式化學蝕刻技術。例如，此可包括CF4電漿化學或CMP。
針對回蝕製造次序之後的表面加工及回蝕製造次序之前的表面加工兩者，晶種層302蝕刻操作並不攻擊主體金屬層142側壁、或在增層結構(例如，頂部介電層115)中將變成凹部或開口151者內的側壁。此根據次序兩者將墊大小保持為設計值。
圖7A至圖7C係根據一實施例之根據回蝕製造次序之後的表面加工製造之SMT金屬凸塊122之示意截面側視圖繪示。圖8A至圖8C係根據一實施例之根據回蝕製造次序之前的表面加工製造之SMT金屬凸塊122之示意截面側視圖繪示。
參照圖7A，該結構繪示在操作4040移除障壁層150之後形成之開口151。亦繪示者係在主體金屬層142與形成在一或多個介電層115、112中之通孔116之間的電氣及實體連接。圖7B繪示在操作4050的回蝕之後升高在增層結構之最頂部表面117上方的主體金屬層142頂部表面143。圖7C繪示在操作4052之表面加工層144之形成，其亦可封裝主體金屬層142以提供化學保護。金屬阻塞結構124可類似地以類似的實體配置來處理。
參照圖8A，該結構繪示在操作4040移除障壁層150之後形成之開口151。值得注意的是，主體金屬層142比在圖7A中薄，並且凹部或開口151較深。亦繪示在主體金屬層142與形成在一或多個介電層115、112中之通孔116之間的電氣及實體連接。圖8B繪示在操作4060之表面加工層144之形成。如所示，開口151可並非完全填充的。此可幫助促進維持相同的SMT金屬凸塊122之大小。圖8C繪示在操作4062的回蝕之後的SMT金屬凸塊122。如所示，表面加工層144再次封裝主體金屬層142以提供化學保護。金屬阻塞結構124可類似地以類似的實體配置來處理。
現參照圖9A至圖9B，提供根據實施例之封裝基材變化的特寫截面側視圖繪示，該等封裝基材變化包括突出在SMT金屬凸塊陣列上方的金屬阻塞結構。根據一實施例，圖9A係使用在回蝕製造次序之後的表面加工來製造，諸如在圖10A至圖10G中提供者。根據一實施例，圖9B係使用在回蝕製造次序之前的表面加工來製造，諸如在圖11A至圖11G中提供者。封裝基材變化及處理次序變化具有對關於圖1至圖8C而已繪示及敘述之結構及處理次序的相似性。據此，為了清楚及簡明起見，以下敘述係聚焦於具體變化而非共用特徵與程序。
參照圖9A及圖9B兩者，金屬阻塞結構124係繪示為突出在SMT金屬凸塊122陣列上方。此外，增層結構(或更具體而言，頂部介電層115)突出至金屬阻塞結構124之內部部分中。此處，金屬阻塞結構124內部的增層結構之頂部表面119在側向緊鄰於金屬阻塞結構124的增層結構之最頂部表面117上方，且亦相鄰於SMT金屬凸塊122。在結構兩者中，金屬阻塞結構124可具有埋置在增層結構中之特徵倒置的U形或馬蹄形狀。
現參照圖10A至圖10B及圖11A至圖11B，處理次序類似於先前關於圖5A及圖6A所繪示及敘述而開始，其包括在載體基材300上形成晶種層302。圖案化阻塞層304接著係在晶種層302上方形成。在一實施例中，阻塞層304係導電層，且可係金屬層。例如，阻塞層304係電鍍銅層。阻塞層304可係藉由以下形成：形成圖案化光阻層(其中繪示開口306)，接著電鍍，然後剝除該光阻層以產生阻塞層304及開口306。圖10C至圖10G及圖11C至圖11G中之處理次序可接著類似於先前關於圖5B至圖5G及圖6B至圖6G分別描述及繪示者來處理。
圖12A至圖12B係根據實施例之另一封裝基材變化的特寫截面側視圖繪示，該另一封裝基材變化包括形成在SMT金屬凸塊陣列及金屬阻塞結構之間的增層結構中的一溝。根據一實施例，圖12A係使用在回蝕製造次序之後的表面加工來製造，諸如在圖13A至圖13F中提供者。根據一實施例，圖12B係使用在回蝕製造次序之前的表面加工來製造，諸如在圖14A至圖11F中提供者。封裝基材變化及處理次序變化具有對關於圖1至圖8C已繪示及敘述之結構及處理次序的相似性，據此，為了清楚及簡明起見，以下敘述係聚焦於具體變化而非共用特徵與程序。
參照圖12A及圖12B兩者，溝160係形成在SMT金屬凸塊122陣列及金屬阻塞結構124之間的增層結構(例如頂部介電層115)中。溝160可具有底部表面162，該底部表面低於可由主體金屬層142界定的SMT金屬凸塊122陣列及金屬阻塞結構124的底部表面141下方。溝160可完全圍繞著陸區123A、123B或僅在著陸區之一部分周圍。
現參照圖13A至圖13B及圖14A至圖14B，處理次序類似於先前關於圖5A至圖5E及圖6A至圖6E所繪示及敘述而開始。遮罩層320(例如，光阻)接著可係在主體金屬層142中之虛置金屬結構145上方形成(如圖13C及圖14C中繪示)，接著蝕刻以移除虛置金屬結構145(如圖13D及圖14D中繪示，其亦顯示移除遮罩層320)。圖13E至圖13F及圖14E至圖14F中之處理次序可接著類似於先前關於圖5F至圖5G及圖6F至圖6G分別描述及繪示者來處理。值得注意的是，在回蝕次序期間，溝160之底部表面162亦經回蝕，使得其等係降低至主體金屬層142之底部表面下方，且因此在SMT金屬凸塊122陣列及金屬陣列結構124的底部表面141下方。
應理解雖然已分開描述及繪示根據實施例之各種結構變化及處理次序，但可組合結構及處理次序之許多者。在使用實施例的各種態樣的過程中，所屬技術領域中具有通常知識者將明白上述實施例的組合或變化對於在封裝基材中形成SMT金屬凸塊及強化結構而言係可行的。雖然已經以結構特徵及/或方法動作之特定語言敘述實施例，應了解附加的申請專利範圍不必受限於所述的特定特徵或行為。替代地，所揭示之特定的特徵及動作應理解為可用於說明之申請專利範圍的實施例。
115:介電層
117:最頂部表面
122:表面安裝(SMT)金屬凸塊
124:金屬阻塞結構/主體金屬層
132:筆直側壁
132A:部分
132B:部分
134:筆直側壁
134A:部分
134B:部分
142:主體金屬層
143:頂部表面
144:表面加工層
146:無電鎳層/鎳層/頂部表面
148:無電鈀及浸金層
149:頂部表面
200:裝置
210:底部填充材料
212:接觸件
214:焊料凸塊
th:底部填充高度
tt:厚度

Claims (23)

  1. 一種封裝基材，其包含：一增層結構；及一圖案化金屬接觸層，其部分埋置在該增層結構內並自該增層結構突出，其中該圖案化金屬接觸層在一晶片安裝區中包括一表面安裝(SMT)金屬凸塊陣列以及一金屬阻塞結構，該金屬阻塞結構側向相鄰於該SMT金屬凸塊陣列；各SMT金屬凸塊包括針對該SMT金屬凸塊經埋置在該增層結構中的一部分及該SMT金屬凸塊延伸在該增層結構側向相鄰於該SMT金屬凸塊之一最頂部表面上方的一部分之多個筆直側壁；且該金屬阻塞結構包括針對該金屬阻塞結構經埋置在該增層結構中的一部分及該金屬阻塞結構延伸在該增層結構側向相鄰於該金屬阻塞結構之一最頂部表面上方的一部分之多個筆直側壁。
  2. 如請求項1之封裝基材，其中該經圖案化金屬接觸層包括一主體金屬層及在該主體金屬層上方之一表面加工層。
  3. 如請求項2之封裝基材，其中各SMT金屬凸塊的該等筆直側壁是連續的筆直側壁，該等筆直側壁橫跨該SMT金屬凸塊經埋置在該增層結構中的該部分及該SMT金屬凸塊延伸在該增層結構側向相鄰於該SMT金屬凸塊之一最頂部表面上方的該一部分。
  4. 如請求項3之封裝基材，其中針對各SMT金屬凸塊：該主體金屬層之一頂部表面延伸在該增層結構側向相鄰於該SMT金屬凸塊之該最頂部表面上方。
  5. 如請求項4之封裝基材，其中針對各SMT金屬凸塊： 該SMT金屬凸塊之該等筆直側壁係由該主體金屬層界定；且該表面加工層覆蓋該主體金屬層之該頂部表面及該SMT金屬凸塊延伸在該增層結構側向相鄰於該SMT金屬凸塊之該最頂部表面上方的該部分之該等筆直側壁。
  6. 如請求項5之封裝基材，其中該表面加工層包含一鎳層，且該主體金屬層包含銅。
  7. 如請求項6之封裝基材，其中該表面加工層包含一鎳-鈀-金層堆疊，且該主體金屬層包含銅。
  8. 如請求項3之封裝基材，其中針對各SMT金屬凸塊之該等筆直側壁橫跨該主體金屬層及該表面加工層。
  9. 如請求項8之封裝基材，其中針對各SMT金屬凸塊之該主體金屬層係完全埋置在該增層結構中，且由該表面加工層覆蓋。
  10. 如請求項9之封裝基材，其中針對各SMT金屬凸塊之各表面加工層係部分埋置在該增層結構中且部分延伸在該增層結構側向相鄰於該SMT金屬凸塊之該最頂部表面上方。
  11. 如請求項10之封裝基材，其中該表面加工層包含一鎳層，且該主體金屬層包含銅。
  12. 如請求項11之封裝基材，其中該表面加工層包含一鎳-鈀-金層堆疊，且該主體金屬層包含銅。
  13. 如請求項1之封裝基材，其中該金屬阻塞結構側向圍繞在該晶片安裝區中之該SMT金屬凸塊陣列。
  14. 如請求項13之封裝基材，其中該金屬阻塞結構包含複數個平行金屬線，該複數個平行金屬線平行於安裝在該SMT金屬凸塊陣列上之一晶粒之一邊緣行進。
  15. 如請求項1之封裝基材，其中該金屬阻塞結構包含一重複幾何形狀陣列，該重複幾何形狀陣列相鄰於安裝在該SMT金屬凸塊陣列上之一晶粒之一隅角。
  16. 如請求項1之封裝基材，其進一步包含形成在該SMT金屬凸塊陣列及該金屬阻塞結構之間的該增層結構中之一溝。
  17. 如請求項1之封裝基材，其中該金屬阻塞結構突出在該SMT金屬凸塊陣列上方，且該增層結構突出至該金屬阻塞結構之一內部部分中。
  18. 如請求項1之封裝基材，其中針對該金屬阻塞結構及各SMT金屬凸塊：該主體金屬層之一頂部表面延伸在該增層結構側向相鄰於對應之該金屬阻塞結構及對應之該SMT金屬凸塊之一最頂部表面上方。
  19. 如請求項1之封裝基材，其中針對該阻塞結構各SMT金屬凸塊之該等筆直側壁橫跨該主體金屬層及該表面加工層。
  20. 一種形成一封裝基材的方法，其包含：形成一圖案化金屬基底層在一載體基材上，該圖案化金屬基底層包括一圖案化金屬接觸層及在該障壁層上之一主體金屬層；形成一增層結構在該圖案化金屬基底層上；移除該載體基材；移除該障壁層； 減少該增層結構之一厚度，使得該主體金屬層之一頂部表面自該增層結構突出以形成一表面安裝(SMT)金屬凸塊陣列，該表面安裝(SMT)金屬凸塊陣列部分埋置在該增層結構內並自在一晶片安裝區中的該增層結構突出，以及一金屬阻塞結構，該金屬阻塞結構側向相鄰於該SMT金屬凸塊陣列，該SMT金屬凸塊陣列部分埋置在該增層結構內並自該增層結構突出；各SMT金屬凸塊包括針對該SMT金屬凸塊經埋置在該增層結構中的一部分及該SMT金屬凸塊延伸在該增層結構側向相鄰於該SMT金屬凸塊之一最頂部表面上方的一部分之多個筆直側壁；且該金屬阻塞結構包括針對該金屬阻塞結構經埋置在該增層結構中的一部分及該金屬阻塞結構延伸在該增層結構側向相鄰於該金屬阻塞結構之一最頂部表面上方的一部分之多個筆直側壁；以及形成一表面加工層在經暴露之該主體金屬層上。
  21. 如請求項20之方法，其中減少該增層結構之該厚度包含電漿蝕刻或濕式化學蝕刻。
  22. 一種形成一封裝基材的方法，其包含：形成一圖案化金屬基底層在一載體基材上，該圖案化金屬基底層包括一障壁層及在該障壁層上之一主體金屬層；形成一增層結構在該圖案化金屬基底層上；移除該載體基材；移除該障壁層；及在該增層結構中之一開口內形成一表面加工層在經暴露之該主體金屬層上，該開口先前由該障壁層佔據；及 減少該增層結構之一厚度，使得該表面加工層之一頂部表面自該增層結構突出，且該主體金屬層之一頂部表面係埋置在該增層結構中。
  23. 如請求項22之方法，其中減少該增層結構之該厚度包含電漿蝕刻或濕式化學蝕刻。
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