TWI719730B - 積體電路封裝及其製作方法 - Google Patents

積體電路封裝及其製作方法 Download PDF

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TWI719730B
TWI719730B TW108142994A TW108142994A TWI719730B TW I719730 B TWI719730 B TW I719730B TW 108142994 A TW108142994 A TW 108142994A TW 108142994 A TW108142994 A TW 108142994A TW I719730 B TWI719730 B TW I719730B
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integrated circuit
die
circuit die
dielectric layer
layer
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TW108142994A
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TW202046479A (zh
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陳明發
史朝文
吳念芳
葉松峯
劉醇鴻
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台灣積體電路製造股份有限公司
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Abstract

本發明提供一種積體電路封裝，包含：底部積體電路晶 粒，具有第一前側及第一背側；頂部積體電路晶粒，具有第二前側及第二背側，第二背側接合至第一前側，頂部積體電路晶粒不含基底穿孔(TSVs)；介電層，圍繞頂部積體電路晶粒，介電層安置在第一前側上，介電層與底部積體電路晶粒橫向共端；以及穿孔，延伸穿過介電層，穿孔電耦接至底部積體電路晶粒，穿孔、介電層以及頂部積體電路晶粒的表面為平坦的。

Description

積體電路封裝及其製作方法
本發明的實施例是有關於一種積體電路封裝及其製作方法。
由於積體電路(integrated circuit，IC)的發展，半導體行業已歸因於各種電子組件(亦即，電晶體、二極體、電阻器、電容器等)的整合密度(integration density)的持續改良而經歷持續快速增長。主要而言，整合密度的此等改良來自最小特徵大小的不斷減小，此允許將更多組件整合於給定區域中。此等整合改良在本質上為基本上二維(two-dimensional，2D)的，此係由於藉由積體式組件(integration components)佔據的區域基本上在半導體晶圓的表面上。
積體電路的密度增大及區域的對應減小已大體上超出將積體電路晶粒直接接合至基底上的能力。由於對於縮小的電子元件的需求已增長，故對於半導體晶粒的更小且更具創造性的封裝技術的需要已出現。併入有三維(three-dimensional，3D)態樣的封裝已使得能夠生產具有增強的功能性及較小佔據面積(small footprints)的半導體元件。
一種積體電路封裝，包括底部積體電路晶粒、頂部積體電路晶粒、介電層以及穿孔。底部積體電路晶粒，具有第一前側及第一背側。頂部積體電路晶粒，具有第二前側及第二背側，第二背側接合至第一前側，頂部積體電路晶粒不含基底穿孔(TSV)。介電層，圍繞頂部積體電路晶粒，介電層安置在第一前側上，介電層與底部積體電路晶粒橫向共端。穿孔，延伸穿過介電層，穿孔電耦接至底部積體電路晶粒，穿孔、介電層以及頂部積體電路晶粒的表面為平坦的。
一種積體電路封裝，包括晶粒堆疊以及重佈線結構。晶粒堆疊，包括底部積體電路晶粒、頂部積體電路晶粒、第一穿孔以及第一介電層。頂部積體電路晶粒，位於底部積體電路晶粒上，頂部積體電路晶粒的背側接合至底部積體電路晶粒的前側，底部積體電路晶粒寬於頂部積體電路晶粒，頂部積體電路晶粒包括第一晶粒連接件。第一穿孔，與頂部積體電路晶粒相鄰，第一穿孔實體地耦接且電耦接至底部積體電路晶粒。第一介電層，圍繞第一穿孔，第一介電層使第一穿孔與頂部積體電路晶粒實體地分離。重佈線結構，包括金屬化圖案以及第二介電層。金屬化圖案，位於晶粒堆疊上，金屬化圖案將第一晶粒連接件電耦接至第一穿孔。第二介電層，位於金屬化圖案及第一介電層上。其中晶粒堆疊不含焊料。
一種積體電路封裝的製作方法，包括：將第一積體電路晶粒的背側接合至晶圓的前側；將第一介電層沈積於晶圓及第一積體電路晶粒上；將第一介電層平坦化，使得第一積體電路晶粒及第 一介電層的表面為平坦的；形成延伸穿過第一介電層的導通孔，導通孔在不使用焊料的情況下電耦接至晶圓；以及將晶圓及第一介電層單一化，晶圓的單一化部分形成第二積體電路晶粒。
40、90:晶圓
40A、90A:第一元件區
50、50A、50B:積體電路晶粒
52:半導體基底
54:內連線結構
56:接觸墊
58:鈍化層
60:測試墊
62:晶粒連接件
64、82、106、110、206:介電層
66、70、74:接合層
68:載體基底
72:凹槽
76:對準標記
78:分割切道
80:晶粒堆疊
82A:第一氮化矽層
82B:第一TEOS層
82C:第二氮化矽層
82D:第二TEOS層
84:開口
86、208:穿孔
88、224:單一化製程
92:通孔晶粒
94:基底
96:基底穿孔
100、200:積體電路封裝
102、214:重佈線結構
104、108:金屬化圖案
112:凸塊下金屬
114、216、222:導電連接件
116、210:黏著劑
202:載體基底
204:釋放層
212:密封體
218:被動元件
220:底膠
T1、T2、T3、T4、T5、T6、T7、T8、T9、T10、T11、T12、T13、T14、T15、T16、T17:厚度
W1、W2、W3、W4:寬度
結合隨附圖式閱讀以下實施方式時會最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述明晰起見而任意地增大或縮小各種特徵的尺寸。
圖1至圖7為根據一些實施例的在處理晶圓以形成積體電路晶粒期間的中間步驟的橫截面視圖。
圖8至圖13為根據一些實施例的在用於形成晶粒堆疊的製程期間的中間步驟的橫截面視圖。
圖14及圖15為根據一些實施例的在用於形成積體電路封裝的製程期間的中間步驟的橫截面視圖。
圖16為根據一些其他實施例的積體電路封裝的橫截面視圖。
圖17至圖22為根據一些其他實施例的在用於形成積體電路封裝的製程期間的中間步驟的橫截面視圖。
圖23及圖24為根據其他實施例的在用於形成晶粒堆疊的製程期間的中間步驟的橫截面視圖。
圖25及圖26為根據其他實施例的在用於形成晶粒堆疊的製程期間的中間步驟的橫截面視圖。
圖27及圖28為根據其他實施例的在用於形成晶粒堆疊的製程期間的中間步驟的橫截面視圖。
圖29至圖31為根據其他實施例的在用於形成晶粒堆疊的製程期間的中間步驟的橫截面視圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複為出於簡單及清楚的目的，且自身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...之上」、「上部」以及類似者的空間相對術語，以描述如圖式中所示出的一個部件或特徵與另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語還意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例，晶粒堆疊(die stack)藉由在不使用焊料的情況下以背對面(back-to-face)方式堆疊積體電路晶粒(integrated circuit dies)來形成。晶粒堆疊可包含接合在一起的頂部積體電路晶粒及底部積體電路晶粒。積體電路晶粒可藉由例如 熔化接合(fusion bonding)直接接合。隨後，將晶粒堆疊封裝在包括重佈線結構(redistribution structure)的積體電路封裝中。重佈線結構的金屬化圖案可具有精細間距(fine pitches)，諸如在約0.8微米(micrometer，μm)至約5微米範圍內的間距。因此重佈線結構既可用於內連晶粒堆疊的積體電路晶粒，且亦可用於晶粒堆疊的扇出型(fan-out)電連接。因而，可將積體電路晶粒電內連，而無需在積體電路晶粒中形成基底穿孔(through substrate via，TSV)且無需在積體電路封裝中封裝***件(packaging interposers)。積體電路晶粒及積體電路封裝的製造成本可因此縮減。
圖1至圖7為根據一些實施例的在處理晶圓(wafer)40以形成積體電路晶粒50期間的中間步驟的橫截面視圖。積體電路晶粒50將自晶圓40單一化且在後續處理中堆疊以形成晶粒堆疊。出於說明性目的，繪示了一個積體電路晶粒50，但應瞭解，晶圓40可具有多個積體電路晶粒50。每一積體電路晶粒50可為邏輯晶粒(例如，中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、系統晶片(system-on-a-chip，SoC)、應用處理器(application processor，AP)、微控制器等(microcontroller))、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、信號處理晶粒(例如，數位信號處理(digital signal processing， DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end，AFE)晶粒)、類似者或其組合。
在圖1中，設置半導體基底52。半導體基底52可為經摻雜或未經摻雜的矽，或絕緣層上半導體(semiconductor-on-insulator，SOI)基底的主動層。半導體基底52可包含其他半導體材料，諸如鍺(germanium)；化合物半導體，包含碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度(gradient)基底。半導體基底52具有有時稱作前側的主動表面(例如，圖1中朝向上方的表面)及有時稱作背側的非主動表面(例如，圖1中朝向下方的表面)。元件形成於半導體基底的主動表面處。元件可為主動元件(例如，電晶體、二極體等)或被動元件(例如，電容器、電阻器、電感器等)。
晶圓40具有多個元件區，且積體電路晶粒50形成於元件區中之每一者中及/或元件區中之每一者上。示出第一元件區40A，但應瞭解，晶圓40可具有任何數目的元件區。元件區將在處理之後單一化以形成積體電路晶粒50。
內連線結構54形成於半導體基底52上方。內連線結構54將半導體基底52的元件內連以在元件區中之每一者中形成積體電路。內連線結構54可由例如介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個低k介電層中的金屬線及通孔。內連線結構54可由金屬鑲嵌製程(damascene)(諸如單金屬鑲嵌製 程、雙金屬鑲嵌製程或類似者)形成。內連線結構54的金屬化圖案電耦接至半導體基底52的元件。
接觸墊56形成於積體電路晶粒50的前側處，諸如內連線結構54中。接觸墊56可為進行外部連接的鋁墊、銅墊或類似者。在一些實施例中，接觸墊56為內連線結構54的最頂部金屬化圖案的部分。
一或多個鈍化層58形成於接觸墊56及內連線結構54上。鈍化層58可由一或多種合適的介電材料形成，諸如氧化矽(silicon oxide)、氮化矽(silicon nitride)、諸如摻碳氧化物的低k介電質、諸如摻多孔碳二氧化矽的極低k介電質、聚合物(諸如聚醯亞胺(polyimide)、阻焊劑、聚苯并噁唑(polybenzoxazole，PBO)、苯環丁烷(benzocyclobutene，BCB))、模製化合物、類似者或其組合。鈍化層58可藉由旋轉塗佈、層壓(lamination)、化學氣相沈積(chemical vapor deposition，CVD)、類似者或其組合形成。鈍化層58經形成為組合厚度T1，諸如在約1千埃至約10千埃範圍內的厚度T1。在一些實施例中，鈍化層58包含氮化矽層及在氮化矽層上的氧化矽層，其中氮化矽層可經形成為在約100埃至約750埃範圍內的厚度，且氧化矽層可經形成為在約1千埃至約10千埃範圍內的厚度。
測試墊60延伸穿過鈍化層58形成以實體地耦接(couple)且電耦接至接觸墊56。測試墊60用於元件測試，且在積體電路晶粒50的正常操作期間不電耦接或不活動。在一些實施例中，測試墊60由比接觸墊56或內連線結構54的金屬化圖案更低成本的導電材料(例如，鋁)形成。測試墊60可藉由金屬鑲嵌製程(諸如 單金屬鑲嵌製程)形成。測試墊60形成為厚度T2，諸如約在2千埃至約40千埃範圍內的厚度T2。
隨後，對積體電路晶粒50進行電路探針(Circuit probe，CP)測試以確定積體電路晶粒50是否為良裸晶粒(known good dies，KGDs)。積體電路晶粒50藉由使用探針來測試。探針藉由例如測試連接件實體地耦接且電耦接至測試墊60。僅為KGDs的積體電路晶粒50才經歷後續處理及封裝，且未通過CP測試的積體電路晶粒50不封裝。測試可包含對各種積體電路晶粒50的功能性的測試，或可包含針對基於積體電路晶粒50的設計來預期的已知開路或短路的測試。在測試完成之後，移除探針且可藉由例如蝕刻製程、化學機械研磨(chemical-mechanical polish，CMP)、磨削(grinding)製程或類似者移除測試墊60上的任何過剩可回填材料。
在圖2中，晶粒連接件62視情況形成於接觸墊56中的各別一者上。晶粒連接件62可為穿孔或導電柱，且可由諸如銅的金屬形成。晶粒連接件62實體地耦接且電耦接至接觸墊56中的各別一者，且電耦接至積體電路晶粒50的各別積體電路。作為形成晶粒連接件62的實例，開口可形成於鈍化層58中，且晶種層可沿鈍化層58及在穿過鈍化層58的開口中形成。開口可藉由可接受的微影及蝕刻(photolithography and etching)技術來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用(例如)物理氣相沉積(physical vapor deposition，PVD)或類似者形成晶種層。在晶種層上形成且圖案 化光阻。光阻可藉由旋轉塗佈或類似製程形成，且可暴露於光以用於圖案化。光阻的圖案對應於晶粒連接件62。圖案化形成穿過光阻的開口以暴露晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，諸如銅、鈦、鎢、鋁，或類似者。可藉由可接受的灰化(ashing)或剝離(stripping)製程，諸如使用氧電漿(oxygen plasma)或類似者移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分，諸如藉由濕式蝕刻或乾式蝕刻。晶種層及導電材料的剩餘部分形成晶粒連接件62。晶粒連接件62經形成為寬度W1及厚度T3，諸如在約1微米至約5微米範圍內的寬度W1，及在約0.5微米至約5微米範圍內的厚度T3。此外，晶粒連接件62可經形成為小間距，諸如在約2微米至約20微米範圍內的間距。
介電層64形成於積體電路晶粒50的前側上，諸如鈍化層58及測試墊60上。介電層64橫向(laterally)圍繞晶粒連接件62(當形成時)及測試墊60，且使測試墊60內埋，使得測試墊60在所得積體電路晶粒50中保持電隔離。介電層64可為聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)或類似者；正矽酸四乙酯(tetraethyl orthosilicate，TEOS)；類似者或其組合。介電層64可例如藉由旋轉塗佈、層壓、CVD或類似者形成。在一些實施例中，介電層64為TEOS層。在 初始形成之後，介電層64經平坦化，此暴露晶粒連接件62(當形成時)，但不暴露測試墊60。平坦化可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者進行。可進行回蝕以暴露晶粒連接件62的側壁。所得介電層64具有厚度T4，諸如在約0.5微米至約2.5微米範圍內的厚度T4。
如以下進一步論述，多個積體電路晶粒50將在後續處理中堆疊以形成晶粒堆疊。積體電路晶粒50以背對面方式接合在一起，例如，其中頂部積體電路晶粒的背側接合至底部積體電路晶粒的前側。接合在不使用焊料的情況下進行，且可藉由若干方法進行。在一些實施例中，直接接合可用以形成介電質至介電質接合(dielectric-to-dielcetric bonds)或介電質至半導體接合(dielectric-to-semiconductor bonds)。在一些實施例中，晶粒用黏著劑接合，諸如任何合適的黏著劑、環氧樹脂、晶粒貼合膜(die attach film，DAF)或類似者。
在其中積體電路晶粒50藉由直接接合堆疊的實施例中，一或多個接合層66可形成於介電層64上及晶粒連接件62周圍，例如晶粒連接件62的暴露的側壁上。接合層66可由一或多種合適的介電材料形成，諸如氧化矽、氮化矽、聚合物、類似者或其組合。接合層66可藉由旋轉塗佈、層壓或沈積製程(諸如CVD、高密度電漿CVD(high density plasma CVD，HDPCVD)類似者或其組合)形成。在初始形成之後，接合層66經平坦化，此暴露晶粒連接件62(當形成時)，但不暴露測試墊60。平坦化可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者進行。在平坦化之後，接合層66具有組合厚度T5，諸如在約1千埃至約10千埃範 圍內的厚度T5。接合層66由諸如摻氮氧化矽(例如，氮氧化矽)的摻氮氧化物形成，其可有助於增大將由接合層66形成的接合的強度。在一些實施例中，接合層66包含氮化矽層及氮化矽層上的氮氧化矽層，其中氮化矽層可經形成為在約100埃至約750埃範圍內的厚度，且氮氧化矽層可經形成為在約1千埃至約10千埃範圍內的厚度。
在圖3中，翻轉晶圓40且將載體基底68接合至介電層64。載體基底68可為經摻雜或未摻雜的矽，或可包含其他半導體材料，諸如鍺；化合物半導體；或其組合。載體基底68可具有較大厚度T6，諸如在約100微米至約775微米範圍內的厚度T6。
在一些實施例中，載體基底68藉由熔化接合來接合至介電層64。一或多個接合層70可形成於載體基底68上。接合層70可由一或多種合適的介電材料形成，諸如氧化矽、氮化矽、聚合物、類似者或其組合。接合層70可藉由旋轉塗佈、層壓或沈積製程(諸如CVD、高密度電漿CVD(HDPCVD)類似者或其組合)形成。接合層70由諸如氮氧化矽的摻氮氧化物形成，其可有助於增大將由接合層70形成的接合的強度。在形成之後，接合層70具有組合厚度T7，諸如在約1千埃至約5千埃範圍內的厚度T7。接合層66及接合層70隨後壓在一起以形成介電質至介電質接合，所述接合將積體電路晶粒50直接接合至載體基底68。接合層66及/或接合層70中氮的存在增大接合的強度。可進行退火製程以進一步加強接合。
在接合之後，使半導體基底52變薄。變薄可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者實現。使半導體基 底52變薄允許內連線結構54在用於在半導體基底52中形成對準標記的後續製程期間以光學方式定位。使半導體基底52變薄直至半導體基底52具有可為較小的厚度T8為止，諸如在約5微米至約10微米範圍內。在變薄之後，半導體基底52、內連線結構54、鈍化層58、介電層64以及接合層66具有組合厚度T9，所述厚度亦可為較小的，諸如在約10微米至約20微米範圍內。
在圖4中，一或多個凹槽72形成於半導體基底52的背側中。凹槽72可藉由可接受的微影及蝕刻技術形成，諸如藉由使用經圖案化的光阻作為蝕刻罩幕。凹槽72用於形成對準標記，且形成至預定深度及寬度。舉例而言，凹槽72可具有在約0.1微米至約1微米範圍內的深度及在約20微米至約100微米範圍內的寬度。凹槽72可在平面視圖中具有有規則及對稱的形狀。凹槽72的位置可藉由使用諸如紅外掃描儀的光學掃描儀感測內連線結構54的圖案來判定。
在圖5中，接合層74可形成於半導體基底52的背側上及凹槽72中。接合層74填充凹槽72以形成對準標記76，所述對準標記可用於後續處理，且亦將用於接合以形成晶粒堆疊。接合層74及對準標記76可由一或多種合適的介電材料形成，諸如氧化矽、氮化矽、聚合物、類似者或其組合。接合層74可藉由旋轉塗佈、層壓或沈積製程(諸如CVD、高密度電漿CVD(HDPCVD)類似者或其組合)形成。接合層74由氮化物形成，其可有助於增大將由接合層74形成的接合的強度。在一些實施例中，接合層74為氮化矽層。在形成之後，接合層74經平坦化。平坦化可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者進行。在平坦 化之後，接合層74具有厚度T10，所述厚度可在約0.2微米至約2微米範圍內。
在圖6中，分割切道78形成於晶圓40中，例如半導體基底52、內連線結構54、介電層64以及接合層66及接合層70中。分割切道78亦部分地延伸至載體基底68中。分割切道78藉由可接受的微影及蝕刻技術形成，諸如藉由使用經圖案化的光阻作為乾式蝕刻製程的蝕刻罩幕。對準標記76用於在形成分割切道78時使蝕刻罩幕的圖案化對準。藉由乾式蝕刻製程形成分割切道78有助於減小對單一化積體電路晶粒50造成的損壞的量。每一元件區(諸如第一元件區40A)藉由分割切道78分離。在乾式蝕刻製程之後，半導體基底52經單一化，但仍保持接合至未經單一化的載體基底68的部分。
在圖7中，晶圓40經翻轉且置放於載帶(tape)上。隨後，使載體基底68變薄直至暴露分割切道78為止，從而完成積體電路晶粒50的單一化。變薄可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者實現。可進行變薄後清潔以移除來自變薄製程的任何殘留物。在變薄之後，載體基底68的剩餘部分具有較小厚度T11，諸如在約5微米至約20微米範圍內的厚度T11，且積體電路晶粒50具有較小厚度T12，諸如在約10微米至約40微米範圍內的厚度T12。當完成處理時，積體電路晶粒50可自載帶移除。
圖8至圖13為根據一些實施例的在用於形成晶粒堆疊80(參見圖13)的製程期間的中間步驟的橫截面視圖。晶粒堆疊80藉由以背對面方式堆疊多個積體電路晶粒形成，其中頂部積體電 路晶粒的背側接合至底部積體電路晶粒的前側，且無需使用焊料。所示出的晶粒堆疊製程藉由將單一化積體電路晶粒50接合至未單一化晶圓90的元件區來進行。晶圓90類似於圖2的晶圓40，例如為在貼合載體基底68之前處於處理的中間階段的晶圓，且具有與晶圓40類似的特徵。示出將第一積體電路晶粒50A接合至晶圓90的第一元件區90A，但應瞭解，晶圓90可具有任何數目的元件區且任何數目的積體電路晶粒可接合至每一區。第二積體電路晶粒50B形成於晶圓90的第一元件區90A中，且經單一化以包含在所得晶粒堆疊80中。
在所繪示實施例中，頂部積體電路晶粒50A及底部晶圓90兩者包含晶粒連接件62。在其他實施例中(以下進一步論述)，頂部積體電路晶粒50A及/或底部晶圓90可省略晶粒連接件62。在其他實施例中(以下進一步論述)，晶粒連接件62的形成可推遲直至接合頂部積體電路晶粒50A及底部晶圓90之後為止。
所得晶粒堆疊80(參見圖13)的積體電路晶粒在單一化時被電隔離。晶粒堆疊80的積體電路晶粒可為用於形成計算系統的晶粒。舉例而言，底部積體電路晶粒50B可為積體電路晶粒的一種類型，諸如邏輯晶粒，且頂部積體電路晶粒50A可為積體電路晶粒的第二類型，諸如記憶體晶粒、積體被動元件或類似者。晶粒堆疊80將在後續處理中封裝以形成封裝組件，所述封裝組件電耦接晶粒堆疊80的積體電路晶粒。
在圖8中，頂部積體電路晶粒50A接合至底部晶圓90。使用例如取放技術將頂部積體電路晶粒50A置放於底部晶圓90上。在一些實施例中，頂部積體電路晶粒50A接合至不含晶粒連 接件62的第一元件區90A的區。對準標記76用於在置放期間對準。在其中頂部積體電路晶粒50A藉由熔化接合來接合至底部晶圓90的實施例中，接合層66及接合層74壓在一起以形成介電質至介電質接合，所述接合將頂部積體電路晶粒50A直接接合至底部晶圓90。在其中接合層66包含摻氮氧化矽層且接合層74為氮化矽層的實施例中，介電質至介電質接合為氧化物至氮化物接合。如上所指出，接合層66及/或接合層74中氮的存在增大介電質至介電質接合的強度。可進行退火製程以進一步加強接合。在一些實施例中，省略接合層66及接合層74中的一者。舉例而言，可省略接合層74，且頂部積體電路晶粒50A可藉由將頂部積體電路晶粒50A的半導體基底52壓至底部晶圓90的接合層66來接合至底部晶圓90。因此形成矽至介電質接合(silicon-to-dielectric bonds)，將頂部積體電路晶粒50A直接接合至底部晶圓90。在其中接合層66包含氧化矽層的實施例中，矽至介電質接合為矽至氧化物接合(silicon-to-oxide bonds)。如以下關於圖16進一步論述，在一些實施例中，接合層66及接合層74兩者可省略，且頂部積體電路晶粒50A可藉由其他構件接合至底部晶圓90。
在圖9中，使頂部積體電路晶粒50A的載體基底68變薄。變薄可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者實現。在變薄之後，載體基底68的剩餘部分具有較小厚度T13，諸如在約1微米至約5微米範圍內的厚度T13，且底部晶圓90具有較小厚度T14，諸如在約10微米至約25微米範圍內的厚度T14。
在圖10中，一或多個介電層82形成於底部晶圓90及頂部積體電路晶粒50A上方。隨後，介電層82經圖案化以形成暴露 頂部積體電路晶粒50A的開口84。介電層82中的每一者可為聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；正矽酸四乙酯(TEOS)；類似者，或其組合。介電層82可例如藉由旋轉塗佈、層壓、化學氣相沈積(CVD)或類似者形成。在形成之後，介電層82具有組合厚度T15，諸如在約12微米至約27微米範圍內的厚度T15。隨後，形成開口84，暴露頂部積體電路晶粒50A的載體基底68。開口84可藉由可接受的微影及蝕刻技術形成，諸如藉由使用經圖案化的光阻作為蝕刻罩幕。形成開口84可有助於減小後續平坦化製程中的圖案負載效應。
在一些實施例中，介電層82包含第一氮化矽層82A、第一氮化矽層82A上的第一TEOS層82B、第一TEOS層82B上的第二氮化矽層82C以及第二氮化矽層82C上的第二TEOS層82D。第一氮化矽層82A可經形成為在約100埃至約750埃範圍內的厚度，第一TEOS層82B可經形成為在約10千埃至約20千埃範圍內的厚度，第二氮化矽層82C可經形成為在約1千埃至約4千埃範圍內的厚度，且第二TEOS層82D可經形成為在約15微米至約25微米範圍內的厚度。
在圖11中，進行平坦化製程以移除位於頂部積體電路晶粒50A上方的介電層82的部分。平坦化可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者進行。平坦化移除載體基底68以及接合層66及接合層70。在平坦化之後，暴露晶粒連接件62(當形成時)，且介電層64及介電層82以及晶粒連接件62(當形 成時)的最頂部表面為平坦的。平坦化亦可使頂部積體電路晶粒50A變薄。在平坦化之後，頂部積體電路晶粒50A具有厚度T16，諸如在約5微米至約50微米範圍內的厚度T16。
在圖12中，形成延伸穿過介電層82的穿孔86。穿孔86可為晶粒連接件或導電柱，且可由諸如金屬的導電材料形成。穿孔86實體地耦接且電耦接至底部晶圓90的晶粒連接件62。穿孔86可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。作為形成穿孔86的實例，開口可形成於介電層82中從而暴露晶粒連接件62。開口可藉由可接受的微影及蝕刻技術形成，諸如藉由使用經圖案化的光阻作為蝕刻製程的蝕刻罩幕。晶種層可形成於開口中及晶粒連接件62的經暴露部分上。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用(例如)PVD或類似者形成晶種層。導電材料形成於介電層82的開口中及晶種層上。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，諸如銅、鈦、鎢、鋁，或類似者。開口外部的導電材料及晶種層的過剩部分可藉由例如磨削製程或CMP製程移除。晶種層及導電材料的剩餘部分形成穿孔86。穿孔86形成為厚度T16，且形成為寬度W2，諸如在約1微米至約10微米範圍內的寬度W2。在一些實施例中，穿孔86包含額外層，諸如障壁層、內襯層或類似者。穿孔86不包括(例如不含)焊料。
在圖13中，單一化製程88藉由沿例如第一元件區90A周圍的切割道區鋸切來進行。單一化製程88使第一元件區90A與 底部晶圓90的相鄰元件區(未繪示)分離。所得單一化晶粒堆疊80來自底部晶圓90的第一元件區90A，且包含以背對面方式堆疊的頂部積體電路晶粒50A及底部積體電路晶粒50B，而無需使用焊料。所得晶粒堆疊80因此不含焊料。在單一化之後，介電層82與底部積體電路晶粒50B橫向共端。在單一化製程88之後，底部積體電路晶粒50B具有寬度W3，且頂部積體電路晶粒50A具有寬度W4。寬度W3可在約10毫米至約100毫米範圍內且寬度W4可在約1毫米至約10毫米範圍內。寬度W3大於寬度W4，此有助於容納用於底部積體電路晶粒50B及穿孔86的晶粒連接件62。
圖14及圖15為根據一些實施例的在用於形成積體電路封裝100的製程期間的中間步驟的橫截面視圖。在形成積體電路封裝100(參見圖15)之後，頂部積體電路晶粒50A及底部積體電路晶粒50B電耦接以形成完整的系統。
在圖14中，重佈線結構102形成於晶粒堆疊80上方。特定言之，重佈線結構102形成於穿孔86、介電層82以及積體電路晶粒50A上方。重佈線結構102將頂部積體電路晶粒50A電耦接至底部積體電路晶粒50B。特定言之，重佈線結構102藉由晶粒連接件62電耦接至頂部積體電路晶粒50A，且藉由晶粒連接件62及穿孔86電耦接至底部積體電路晶粒50B。
重佈線結構102包含介電層106及介電層110；金屬化圖案104及金屬化圖案108，以及凸塊下金屬(under-bump metallurgies，UBM)112。金屬化圖案亦可稱為重佈層(redistribution layers)或重佈線(redistribution lines)。金屬化圖案104及金屬化圖案108具有精細間距，諸如在約0.8微米至約5微米範圍內的 間距。因而，金屬化圖案104及金屬化圖案108可用以將頂部積體電路晶粒50A及底部積體電路晶粒50B內連，而無需在積體電路晶粒50中使用TSV，且無需使用***件。換言之，重佈線結構102有利地允許積體電路晶粒50不含TSV，且允許積體電路封裝100(參見圖15)不含***件。
重佈線結構102繪示為具有兩個金屬化圖案層的實例。更多或更少介電層及金屬化圖案可形成於重佈線結構102中。若待形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若待形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
起初，形成金屬化圖案104。金屬化圖案104包含位於介電層82的主表面上且沿所述主表面延伸的線部分(亦稱為導電線)。在一些實施例中，介電層(未繪示)可形成於介電層82、積體電路晶粒50以及穿孔86上方，且金屬化圖案104延伸穿過介電層(未繪示)。金屬化圖案104將穿孔86實體地耦接且電耦接至頂部積體電路晶粒50A的晶粒連接件62。作為形成金屬化圖案104的實例，晶種層形成於穿孔86、介電層82以及頂部積體電路晶粒50A上方。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用(例如)PVD或類似者形成晶種層。隨後在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似製程形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案104。圖案化形成穿過光阻的開口以暴露晶種層。導電材料隨後在光阻的開口中及晶種層的暴露部分上形 成。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁，或類似者。導電材料與晶種層的下層部分的組合形成金屬化圖案104。光阻及晶種層的其上未形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分，諸如藉由濕式蝕刻或乾式蝕刻。
介電層106隨後沈積於金屬化圖案104、介電層82以及頂部積體電路晶粒50A上。在一些實施例中，介電層106由諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者的感光性材料形成，所述感光性材料可使用微影罩幕圖案化。介電層106可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成。介電層106隨後經圖案化。圖案化形成暴露金屬化圖案104的部分的開口。可藉由可接受的製程(諸如藉由當介電層106為感光性材料時將介電層106暴露於光或藉由使用例如非等向性蝕刻來進行蝕刻)來進行圖案化。若介電層106為感光性材料，則介電層106可在暴露之後顯影。
隨後形成金屬化圖案108。金屬化圖案108包含位於介電層106的主表面上且沿所述主表面延伸的線部分(亦稱為導電線)。金屬化圖案108更包含延伸穿過介電層106的穿孔部分(亦稱為導通孔)以實體地耦接且電耦接金屬化圖案104。作為形成金屬化圖案108的實例，晶種層形成於介電層106上方及延伸穿過介電層106的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實 施例中，晶種層包括鈦層及鈦層上方的銅層。可使用(例如)PVD或類似者形成晶種層。隨後在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似製程形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案108。圖案化形成穿過光阻的開口以暴露晶種層。導電材料隨後在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁，或類似者。導電材料與晶種層的下層部分的組合形成金屬化圖案108。光阻及晶種層的其上未形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分，諸如藉由濕式蝕刻或乾式蝕刻。
介電層110隨後沈積於金屬化圖案108及介電層106上。在一些實施例中，介電層110由諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者的感光性材料形成，所述感光性材料可使用微影罩幕圖案化。介電層110可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成。介電層110隨後經圖案化。圖案化形成暴露金屬化圖案108的部分的開口。可藉由可接受的製程(諸如藉由當介電層110為感光性材料時將介電層110暴露於光或藉由使用例如非等向性蝕刻來進行蝕刻)來進行圖案化。若介電層110為感光性材料，則介電層110可在暴露之後顯影。
UBM 112隨後形成以用於與重佈線結構102進行外部連接。UBM 112具有位於介電層110的主表面上且沿所述主表面延伸的凸塊部分，且具有延伸穿過介電層110以實體地耦接且電耦 接金屬化圖案108的穿孔部分。因此，UBM 112電耦接至頂部積體電路晶粒50A及底部積體電路晶粒50B。在一些實施例中，UBM 112經形成為與金屬化圖案104及金屬化圖案108不同的大小。作為形成UBM 112的實例，晶種層形成於介電層110上方及延伸穿過介電層110的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用(例如)PVD或類似者形成晶種層。隨後在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似製程形成，且可暴露於光以用於圖案化。光阻的圖案對應於UBM 112。。圖案化形成穿過光阻的開口以暴露晶種層。導電材料隨後在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁，或類似者。導電材料與晶種層的下層部分的組合形成UBM 112。光阻及晶種層的其上未形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分，諸如藉由濕式蝕刻或乾式蝕刻。
在圖15中，導電連接件114形成於UBM 112上。導電連接件114可為球柵陣列封裝(ball grid array，BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊或類似者。導電連接件114可包含導電材料，諸如焊 料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件114藉由最初經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者形成焊料層來形成。在焊料層已形成於結構上後，可進行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件114包括藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可並無焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層在金屬柱的頂部形成。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
儘管積體電路封裝100經描述為在晶粒堆疊80單一化之後形成，但步驟的次序可修改。舉例而言，在其中使用晶圓級封裝的實施例中，重佈線結構102可形成於未單一化的晶圓90(例如圖12的中間結構)上方。多個積體電路封裝100可因此在晶圓級下形成。可隨後進行單一化製程88(參見圖13)以將晶粒堆疊80及重佈線結構102單一化且因此形成積體電路封裝100。
圖16為根據一些其他實施例的積體電路封裝100的橫截面視圖。在此實施例中，省略接合層66及接合層74兩者，且頂部積體電路晶粒50A的半導體基底52藉由黏著劑116接合至底部晶圓90的介電層64。黏著劑116可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(DAF)，或類似者。
圖17至圖22為根據一些其他實施例的在用於形成積體電路封裝200的製程期間的中間步驟的橫截面視圖。積體電路封裝200藉由對單一化的晶粒堆疊80進行封裝來形成。在封裝之後，頂部積體電路晶粒50A及底部積體電路晶粒50B電耦接以形 成完整的系統。
在圖17中，提供載體基底202，且釋放層204形成於載體基底202上。載體基底202可為玻璃載體基底、陶瓷載體基底或類似者。載體基底202可為晶圓，以使得多個封裝可同時形成於載體基底202上。釋放層204可由聚合物類材料形成，可將所述聚合物類材料連同載體基底202一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層204為在加熱時損失其黏著性質的環氧基熱釋放材料，諸如光-熱轉換(light-to-heat-conversion，LTHC)釋放塗層。在其他實施例中，釋放層204可為在暴露於UV光時損失其黏著性質的紫外線(ultra-violet，UV)黏膠。釋放層204可以液體形式施配且經固化，可為疊層於載體基底202上的疊層膜，或可為類似者。釋放層204的頂部表面可經水平化，且可具有高度平坦性。
介電層206隨後形成於釋放層204上。介電層206的底部表面可與釋放層204的頂部表面接觸。在一些實施例中，介電層206由諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)或類似者的聚合物形成。在其他實施例中，介電層206由諸如氮化矽的氮化物、諸如氧化矽、PSG、BSG、BPSG或類似者的氧化物或類似者形成。介電層206可藉由任何可接受的沈積製程形成，諸如旋轉塗佈、CVD、層壓、類似者或其組合。
接著，穿孔208形成於介電層206上且遠離所述介電層延伸。作為形成穿孔208的實例，晶種層形成於介電層206上。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在特定實施例中，晶種層包括 鈦層及鈦層上方的銅層。可使用(例如)PVD或類似者形成晶種層。在晶種層上形成且圖案化光阻。光阻可藉由旋轉塗佈或類似製程形成，且可暴露於光以用於圖案化。光阻的圖案對應於穿孔。圖案化形成穿過光阻的開口以暴露晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆(諸如電鍍或化學鍍，或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁，或類似者。光阻及晶種層的其上未形成導電材料的部分經移除。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程來移除晶種層的經暴露部分，諸如藉由濕式蝕刻或乾式蝕刻。晶種層及導電材料的剩餘部分形成穿孔208。
在圖18中，晶粒堆疊80藉由黏著劑210黏著至介電層206。將期望類型及量的晶粒堆疊80黏著至介電層206。在所繪示實施例中，一個晶粒堆疊80黏著至介電層206。黏著劑210在晶粒堆疊80的背側上，例如在底部積體電路晶粒50B的背側上，且將晶粒堆疊80黏著至介電層206。黏著劑210可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(DAF)，或類似者。黏著劑210可塗覆至晶粒堆疊80的背側或可塗覆於載體基底202的表面上方。舉例而言，在將晶粒堆疊80單一化之前，黏著劑210可塗覆至晶粒堆疊80的背側。
在圖19中，密封體212形成於各種組件上及各種組件周圍。在形成之後，密封體212密封穿孔208及晶粒堆疊80。密封體212可為模製化合物、環氧樹脂或類似者。密封體212可藉由壓縮模製、轉移模製或類似者塗覆，且可形成於載體基底202上 方使得穿孔208及/或晶粒堆疊80內埋或覆蓋。密封體212可以液體或半液體形式塗覆且隨後經固化。
平坦化製程可在密封體212上進行以暴露穿孔208及晶粒堆疊80。平坦化製程可移除穿孔208、穿孔86、介電層82、介電層64及/或晶粒連接件62的材料直至暴露晶粒連接件62、穿孔86以及穿孔208為止。密封體212、穿孔86、穿孔208、介電層82、介電層64以及晶粒連接件62的頂部表面在平坦化製程之後共面。平坦化製程可為例如化學機械研磨(CMP)、磨削製程或類似者。
在圖20中，重佈線結構214形成於密封體212、穿孔208以及晶粒堆疊80上方。重佈線結構214電耦接頂部積體電路晶粒50A及底部積體電路晶粒50B。重佈線結構214包含介電層、金屬化圖案以及UBM。重佈線結構214的金屬化圖案可具有精細間距，諸如在約0.8微米至約5微米範圍內的間距。因而，金屬化圖案可用以將頂部積體電路晶粒50A及底部積體電路晶粒50B內連，而無需在積體電路晶粒50中使用TSV，且無需使用***件。重佈線結構214可使用與用於形成重佈線結構102的製程類似的製程形成。重佈線結構214繪示為具有三個金屬化圖案層的實例。更多或更少介電層及金屬化圖案可形成於重佈線結構214中。
在圖21中，導電連接件216形成於重佈線結構214上。舉例而言，導電連接件216可形成於UBM上，所述UBM為重佈線結構214的部分。導電連接件216可為球柵陣列封裝(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊或類似者。導電 連接件216可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件216藉由最初經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者形成焊料層來形成。在焊料層已形成於結構上後，可進行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件216包括藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可並無焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層在金屬柱的頂部形成。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
此外，被動元件218可貼合至重佈線結構214。舉例而言，被動元件218可貼合至UBM，所述UBM為重佈線結構214的部分。被動元件218可為積體被動元件(integrated passive devices，IPDs)或離散被動元件(discrete passive devices)。被動元件218可包含電阻器、電容器、電感器或類似者，且可藉由導電連接件貼合至重佈線結構214。在一些實施例中，底膠220形成於被動元件218與重佈線結構214之間。底膠220可在貼合被動元件218之後藉由毛細流動製程形成，或可在貼合被動元件218之前藉由合適的沈積方法形成。
在圖22中，進行載體基底脫結(de-bonding)以使載體基底202與介電層206脫離(或「脫結」)。根據一些實施例，脫結包含使諸如雷射光或UV光的光投射於釋放層204上，以使得釋放層204在光熱下分解且可移除載體基底202。隨後將結構翻轉且置放於載帶上。
隨後形成延伸穿過介電層206以接觸穿孔208的導電連接件222。穿過介電層206形成開口以暴露穿孔208的部分。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口。導電連接件222形成於開口中。在一些實施例中，導電連接件222包括助焊劑且形成於助焊劑浸漬製程中。在一些實施例中，導電連接件222包括諸如焊錫膏、銀膏或類似者的導電膏，且施配於列印製程中。在一些實施例中，導電連接件222以類似於導電連接件216的方式形成，且可由與導電連接件216類似的材料形成。
單一化製程224藉由沿切割道區鋸切來進行。單一化製程224使積體電路封裝200與相鄰積體電路封裝分離。所得的單一化積體電路封裝200可安裝至具有導電連接件216的封裝基底。其他封裝，諸如記憶體元件、被動元件或類似者可貼合至具有導電連接件222的積體電路封裝200。
圖23及圖24為根據其他實施例的在用於形成晶粒堆疊80的製程期間的中間步驟的橫截面視圖。圖23示出與圖11的中間結構處於類似處理狀態的晶粒堆疊80，除了在此實施例中，晶粒連接件62在底部晶圓90的形成期間經省略。因而，在接合之後僅頂部積體電路晶粒50A具有晶粒連接件62。
在圖24中，形成延伸穿過鈍化層58、接合層66以及介電層64及介電層82的穿孔86。穿孔86因此電耦接至底部晶圓90。穿孔86可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。穿孔86經形成為寬度W2，且可經形成為厚度T17，諸如在約10微米至約30微米範圍內的厚度T17。
在形成穿孔86之後，可進行諸如單一化製程88(參見圖 13)的單一化製程以將晶粒堆疊80單一化。晶粒堆疊80可經封裝以形成積體電路封裝。積體電路封裝電耦接頂部積體電路晶粒50A及底部積體電路晶粒50B。舉例而言，可進行如上文所描述的處理以形成類似於圖15的積體電路封裝100的封裝，或類似於圖22的積體電路封裝200的封裝。
圖25及圖26為根據其他實施例的在用於形成晶粒堆疊80的製程期間的中間步驟的橫截面視圖。圖25示出與圖11的中間結構處於類似處理狀態的晶粒堆疊80，除了在此實施例中，晶粒連接件62在頂部積體電路晶粒50A的形成期間經省略。因而，在接合之後僅底部晶圓90具有晶粒連接件62。
在圖26中，晶粒連接件62形成於頂部積體電路晶粒50A中。晶粒連接件62延伸穿過頂部積體電路晶粒50A的介電層64以實體地耦接且電耦接頂部積體電路晶粒50A。晶粒連接件62可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。
此外，形成延伸穿過介電層82的穿孔86。穿孔86因此電耦接至底部晶圓90的晶粒連接件62。穿孔86可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。在一些實施例中，用於頂部積體電路晶粒50A及穿孔86的晶粒連接件62同時形成於例如使用單一罩幕來使晶粒連接件62及穿孔86的開口圖案化的同一金屬鑲嵌製程中。在一些實施例中，用於頂部積體電路晶粒50A及穿孔86的晶粒連接件62形成於不同製程中，例如形成於使用不同罩幕來使晶粒連接件62及穿孔86的開口圖案化的不同金屬鑲嵌製程中。
在形成晶粒連接件62及穿孔86之後，可進行諸如單一 化製程88(參見圖13)的單一化製程以將晶粒堆疊80單一化。晶粒堆疊80可經封裝以形成積體電路封裝。積體電路封裝電耦接頂部積體電路晶粒50A及底部積體電路晶粒50B。舉例而言，可進行如上文所描述的處理以形成類似於圖15的積體電路封裝100的封裝，或類似於圖22的積體電路封裝200的封裝。
圖27及圖28為根據其他實施例的在用於形成晶粒堆疊80的製程期間的中間步驟的橫截面視圖。圖27示出與圖11的中間結構處於類似處理狀態的晶粒堆疊80，除了在此實施例中，晶粒連接件62在頂部積體電路晶粒50A及底部晶圓90兩者的形成期間經省略。因而，在接合之前兩個元件都不具有晶粒連接件62。
在圖28中，晶粒連接件62形成於頂部積體電路晶粒50A中。晶粒連接件62延伸穿過頂部積體電路晶粒50A的介電層64以實體地耦接且電耦接頂部積體電路晶粒50A。晶粒連接件62可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。
此外，形成延伸穿過鈍化層58、接合層66以及介電層64及介電層82的穿孔86。穿孔86因此電耦接至底部晶圓90。穿孔86可藉由金屬鑲嵌製程(諸如單金屬鑲嵌製程)形成。在一些實施例中，用於頂部積體電路晶粒50A及穿孔86的晶粒連接件62同時形成於例如使用單一罩幕來使晶粒連接件62及穿孔86的開口圖案化的同一金屬鑲嵌製程中。在一些實施例中，用於頂部積體電路晶粒50A及穿孔86的晶粒連接件62形成於不同製程中，例如形成於使用不同罩幕來使晶粒連接件62及穿孔86的開口圖案化的不同金屬鑲嵌製程中。
在形成晶粒連接件62及穿孔86之後，可進行諸如單一 化製程88(參見圖13)的單一化製程以將晶粒堆疊80單一化。晶粒堆疊80可經封裝以形成積體電路封裝。積體電路封裝電耦接頂部積體電路晶粒50A及底部積體電路晶粒50B。舉例而言，可進行如上文所描述的處理以形成類似於圖15的積體電路封裝100的封裝，或類似於圖22的積體電路封裝200的封裝。
圖29至圖31為根據其他實施例的在用於形成晶粒堆疊80的製程期間的中間步驟的橫截面視圖。圖29示出與圖9的中間結構處於類似處理狀態的晶粒堆疊80。在此實施例中，晶粒連接件62在頂部積體電路晶粒50A及底部晶圓90兩者的形成期間形成。
在圖29中，一或多個通孔晶粒92接合至與頂部積體電路晶粒50A相鄰的底部晶圓90的第一元件區90A。通孔晶粒92包含基底94及TSV 96。基底94可為半導體基底，諸如經摻雜或未摻雜的矽，或可包含其他半導體材料，諸如鍺；化合物半導體；或其組合。在另一實施例中，基底94可由介電材料形成。基底94可不含主動元件及被動元件，使得通孔晶粒92中唯一的導電特徵為TSV 96。TSV 96可包含一或多個導電材料層。導電材料可包括金屬，諸如銅、鈦、鎢、鋁，或類似者。通孔晶粒92為來自另一製造製程的預製晶粒，且可藉由例如熔化接合來接合至接合層66。舉例而言，可將每一基底94壓至接合層66以形成矽至介電質接合，所述接合將基底94直接接合至底部晶圓90。通孔晶粒92可在頂部積體電路晶粒50A之前、同時或之後接合至底部晶圓90。
在圖30中，介電層82形成於底部晶圓90、頂部積體電路晶粒50A以及通孔晶粒92上方。介電層82經圖案化以形成暴 露頂部積體電路晶粒50A的開口84，此可減小後續平坦化製程中的圖案負載效應。通孔晶粒92未藉由開口84暴露。
在圖31中，進行平坦化製程以移除頂部積體電路晶粒50A及通孔晶粒92上方的介電層82的部分。平坦化可藉由蝕刻製程、化學機械研磨(CMP)、磨削製程或類似者進行。在平坦化之後，頂部積體電路晶粒50A的晶粒連接件62及穿孔晶粒92的TSV 96經暴露。介電層82、頂部積體電路晶粒50A以及穿孔晶粒92的最頂部表面在平坦化之後為平坦的。
在暴露頂部積體電路晶粒50A及通孔晶粒92之後，可進行諸如單一化製程88(參見圖13)的單一化製程以將晶粒堆疊80單一化。晶粒堆疊80可經封裝以形成積體電路封裝。積體電路封裝電耦接頂部積體電路晶粒50A及底部積體電路晶粒50B。舉例而言，可進行如上文所描述的處理以形成類似於圖15的積體電路封裝100的封裝，或類似於圖22的積體電路封裝200的封裝。
實施例可達成優點。形成晶粒堆疊80允許若干類型的積體電路晶粒50(諸如邏輯晶粒及記憶體晶粒)經封裝至同一積體電路封裝中。晶粒堆疊80中的積體電路晶粒50的內連可藉由隨後形成的積體電路封裝中的重佈線結構實現，尤其在重佈線結構具有精細間距的金屬化圖案，諸如具有在約0.8微米至約5微米範圍內的間距的金屬化圖案時。舉例而言，積體電路封裝100的重佈線結構102或積體電路封裝200的重佈線結構214可用以電耦接晶粒堆疊80中的積體電路50。積體電路晶粒50的內連可因此實現，而無需在積體電路晶粒50中使用基底穿孔(TSV)，且無需在積體電路封裝中使用***件，從而降低封裝的製造成本。
在實施例中，一種積體電路封裝包括：底部積體電路晶粒，具有第一前側及第一背側；頂部積體電路晶粒，具有第二前側及第二背側，所述第二背側接合至所述第一前側，所述頂部積體電路晶粒不含基底穿孔(TSV)；介電層，圍繞所述頂部積體電路晶粒，所述介電層安置在所述第一前側上，所述介電層與所述底部積體電路晶粒橫向共端；以及穿孔，延伸穿過所述介電層，所述穿孔電耦接至所述底部積體電路晶粒，所述穿孔、所述介電層以及所述頂部積體電路晶粒的表面為平坦的。
在所述積體電路封裝的一些實施例中，所述第二背側藉由黏著劑接合至所述第一前側。在所述積體電路封裝的一些實施例中，所述頂部積體電路晶粒包括半導體基底，且所述底部積體電路晶粒包括所述第一前側處的第一接合層，所述半導體基底直接接合至所述第一接合層。在所述積體電路封裝的一些實施例中，所述底部積體電路晶粒包括所述第一前側處的第一接合層，且所述頂部積體電路晶粒包括第二背側處的第二接合層，所述第一接合層直接接合至所述第二接合層。在所述積體電路封裝的一些實施例中，所述頂部積體電路晶粒包括半導體基底及所述半導體基底中的對準標記，所述對準標記及所述第二接合層為連續的介電材料。在一些實施例中，所述積體電路封裝更包括：半導體基底，具有第三前側及第三背側，所述第三背側接合至所述第一前側，所述穿孔延伸穿過所述半導體基底，所述介電層及所述半導體基底的表面為平坦的，所述半導體基底不含主動元件及被動元件。在所述積體電路封裝的一些實施例中，所述底部積體電路晶粒包括：半導體基底；以及內連線結構，位於所述半導體基底上，所述內連線結 構包括接觸墊，所述穿孔實體地耦接且電耦接至所述接觸墊。在所述積體電路封裝的一些實施例中，所述底部積體電路晶粒包括：半導體基底；內連線結構，位於半導體基底上，所述內連線結構包括接觸墊；以及晶粒連接件，位於所述接觸墊上，所述穿孔實體地耦接且電耦接至所述晶粒連接件。在一些實施例中，所述積體電路封裝更包括：重佈線結構，位於所述頂部積體電路晶粒、所述介電層以及所述穿孔上，所述重佈線結構包括金屬化圖案，所述金屬化圖案實體地耦接且電耦接至所述穿孔及所述頂部積體電路晶粒。
在實施例中，一種積體電路封裝包括：晶粒堆疊，包括：底部積體電路晶粒；頂部積體電路晶粒，位於所述底部積體電路晶粒上，所述頂部積體電路晶粒的背側接合至所述底部積體電路晶粒的前側，所述底部積體電路晶粒寬於所述頂部積體電路晶粒，所述頂部積體電路晶粒包括第一晶粒連接件；第一穿孔，與所述頂部積體電路晶粒相鄰，所述第一穿孔實體地耦接且電耦接至所述底部積體電路晶粒；以及第一介電層，圍繞所述第一穿孔，所述第一介電層使所述第一穿孔與所述頂部積體電路晶粒實體地分離；以及重佈線結構，包括：金屬化圖案，位於所述晶粒堆疊上，所述金屬化圖案將所述第一晶粒連接件電耦接至所述第一穿孔；以及第二介電層，位於所述金屬化圖案及所述第一介電層上，其中所述晶粒堆疊不含焊料。
在所述積體電路封裝的一些實施例中，所述金屬化圖案包括具有在約0.8微米至約5微米範圍內的間距的導電特徵。在一些實施例中，所述積體電路封裝更包括：密封體，圍繞所述晶粒堆疊，所述密封體與所述第二介電層橫向共端。在一些實施例中， 所述積體電路封裝更包括：第二穿孔，延伸穿過所述密封體，所述第二穿孔電耦接至所述金屬化圖案。在所述積體電路封裝的一些實施例中，所述第一介電層、所述第二介電層以及所述底部積體電路晶粒橫向共端。
在實施例中，一種積體電路封裝的製作方法包括：將第一積體電路晶粒的背側接合至晶圓的前側；將第一介電層沈積於所述晶圓及所述第一積體電路晶粒上；將所述第一介電層平坦化，使得所述第一積體電路晶粒及所述第一介電層的表面為平坦的；形成延伸穿過所述第一介電層的導通孔，所述導通孔在不使用焊料的情況下電耦接至所述晶圓；以及將所述晶圓及所述第一介電層單一化，所述晶圓的單一化部分形成第二積體電路晶粒。
在一些實施例中，所述方法更包括：形成所述第一積體電路晶粒，所述第一積體電路晶粒包括第一晶粒連接件；以及在所述晶圓中形成所述第二積體電路晶粒，所述第二積體電路晶粒包括第二晶粒連接件，所述導通孔實體地耦接且電耦接至所述第二晶粒連接件。在一些實施例中，所述方法更包括：形成所述第一積體電路晶粒，所述第一積體電路晶粒包括第一晶粒連接件；以及在所述晶圓中形成所述第二積體電路晶粒，所述第二積體電路晶粒包括接觸墊及所述接觸墊上方的第二介電層，所述導通孔延伸穿過第二介電層，所述導通孔實體地耦接且電耦接至所述接觸墊。在一些實施例中，所述方法更包括：形成所述第一積體電路晶粒，所述第一積體電路晶粒包括接觸墊及所述接觸墊上方的第二介電層；在所述晶圓中形成所述第二積體電路晶粒，所述第二積體電路晶粒包括第一晶粒連接件，所述導通孔實體地耦接且電耦接至所述 第一晶粒連接件；以及在所述接合之後，形成延伸穿過所述第二介電層的第二晶粒連接件，所述第二晶粒連接件實體地耦接且電耦接至所述接觸墊。在一些實施例中，所述方法更包括：形成所述第一積體電路晶粒，所述第一積體電路晶粒包括第一接觸墊及所述第一接觸墊上方的第二介電層；以及在所述晶圓中形成所述第二積體電路晶粒，所述第二積體電路晶粒包括第二接觸墊及所述第二接觸墊上方的第三介電層，所述導通孔延伸穿過所述第三介電層，所述導通孔實體地耦接且電耦接至所述第二接觸墊；以及在所述接合之後，形成延伸穿過所述第二介電層的晶粒連接件，所述晶粒連接件實體地耦接且電耦接至所述第一接觸墊。在一些實施例中，所述方法更包括：在所述第一積體電路晶粒、所述第一介電層以及所述穿孔上形成重佈線結構，重佈線結構包括金屬化圖案，所述金屬化圖案實體地耦接且電耦接至所述穿孔及所述第一積體電路晶粒。
前文概述若干實施例的特徵，以使得所屬技術領域中具有通常知識者可更佳地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
50A、50B:積體電路晶粒
62:晶粒連接件
80:晶粒堆疊
82:介電層
86:穿孔
100:積體電路封裝
102:重佈線結構
112:凸塊下金屬
114:導電連接件
116:黏著劑

Claims (8)

  1. 一種積體電路封裝，包括：底部積體電路晶粒，具有第一前側及第一背側；頂部積體電路晶粒，具有第二前側及第二背側，所述第二背側接合至所述第一前側，所述頂部積體電路晶粒不含基底穿孔(TSV)，其中所述頂部積體電路晶粒包括：接合層設置於所述第二背側；半導體基底；以及所述半導體基底中的對準標記，所述對準標記及所述接合層為連續的介電材料；介電層，圍繞所述頂部積體電路晶粒，所述介電層安置在所述第一前側上，所述介電層與所述底部積體電路晶粒橫向共端；以及穿孔，延伸穿過所述介電層，所述穿孔電耦接至所述底部積體電路晶粒，所述穿孔、所述介電層以及所述頂部積體電路晶粒的表面為平坦的。
  2. 如申請專利範圍第1項所述的積體電路封裝，更包括：半導體基底，具有第三前側及第三背側，所述第三背側接合至所述第一前側，所述穿孔延伸穿過所述半導體基底，所述介電層及所述半導體基底的表面為平坦的，所述半導體基底不含主動元件及被動元件。
  3. 如申請專利範圍第1項所述的積體電路封裝，更包括：重佈線結構，位於所述頂部積體電路晶粒、所述介電層以及所述穿孔上，所述重佈線結構包括金屬化圖案，所述金屬化圖案實 體地耦接且電耦接至所述穿孔及所述頂部積體電路晶粒。
  4. 一種積體電路封裝，包括：晶粒堆疊，包括：底部積體電路晶粒；頂部積體電路晶粒，位於所述底部積體電路晶粒上，所述頂部積體電路晶粒的背側接合至所述底部積體電路晶粒的前側，所述底部積體電路晶粒寬於所述頂部積體電路晶粒，所述頂部積體電路晶粒包括第一晶粒連接件；第一穿孔，與所述頂部積體電路晶粒相鄰，所述第一穿孔實體地耦接且電耦接至所述底部積體電路晶粒；以及第一介電層，圍繞所述第一穿孔，所述第一介電層使所述第一穿孔與所述頂部積體電路晶粒實體地分離；以及重佈線結構，包括：金屬化圖案，位於所述晶粒堆疊上，所述金屬化圖案將所述第一晶粒連接件電耦接至所述第一穿孔；以及第二介電層，位於所述金屬化圖案及所述第一介電層上，其中所述晶粒堆疊不含焊料，其中所述第一介電層、所述第二介電層以及所述底部積體電路晶粒橫向共端。
  5. 如申請專利範圍第4項所述的積體電路封裝，更包括：密封體，圍繞所述晶粒堆疊，所述密封體與所述第二介電層橫向共端。
  6. 如申請專利範圍第5項所述的積體電路封裝，更包括：第二穿孔，延伸穿過所述密封體，所述第二穿孔電耦接至所 述金屬化圖案。
  7. 一種積體電路封裝的製作方法，包括：形成第一積體電路晶粒，所述第一積體電路晶粒包括接觸墊及所述接觸墊上方的第二介電層；將所述第一積體電路晶粒的背側接合至晶圓的前側；將第一介電層沈積於所述晶圓及所述第一積體電路晶粒上；將所述第一介電層平坦化，使得所述第一積體電路晶粒及所述第一介電層的表面為平坦的；形成延伸穿過所述第一介電層的導通孔，所述導通孔在不使用焊料的情況下電耦接至所述晶圓；將所述晶圓及所述第一介電層單一化，所述晶圓的單一化部分形成第二積體電路晶粒，其中所述第二積體電路晶粒包括第一晶粒連接件，所述導通孔實體地耦接且電耦接至所述第一晶粒連接件；以及形成延伸穿過所述第二介電層的第二晶粒連接件，所述第二晶粒連接件實體地耦接且電耦接至所述接觸墊。
  8. 如申請專利範圍第7項所述的方法，其中所述形成延伸穿過所述第二介電層的第二晶粒連接件的步驟在所述接合之後。
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