TWI741538B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TWI741538B
TWI741538B TW109109647A TW109109647A TWI741538B TW I741538 B TWI741538 B TW I741538B TW 109109647 A TW109109647 A TW 109109647A TW 109109647 A TW109109647 A TW 109109647A TW I741538 B TWI741538 B TW I741538B
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Taiwan
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die
conductive pillar
conductive
active device
dielectric layer
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TW109109647A
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TW202038354A (zh
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余振華
謝政傑
劉重希
郭鴻毅
蔡豪益
于宗源
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台灣積體電路製造股份有限公司
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Abstract

提供一種經封裝半導體元件及其形成方法，經封裝半導體元件包含：第一晶粒，貼合至重佈線結構：第二晶粒，貼合至第一晶粒；以及模塑化合物，包圍第一晶粒及第二晶粒。在一實施例中，一種方法包含：將第一導電柱形成在第一重佈線結構之上且電耦接至第一重佈線結構；將第一晶粒貼合至第一重佈線結構，第一晶粒包含第二導電柱；將第二晶粒貼合至第一晶粒，與第二導電柱相鄰；用包封體包封第一導電柱、第一晶粒以及第二晶粒；在包封體、第一導電柱、第一晶粒以及第二晶粒之上形成第二重佈線結構；以及將第三晶粒接合至第一重佈線結構。

Description

半導體元件及其形成方法
本發明實施例是有關於一種半導體元件及其形成方法。
半導體元件用於各種電子應用中，諸如(例如)個人電腦、蜂巢式電話、數位攝影機以及其他電子設備。通常藉由以下步驟來製造半導體元件：在半導體基底之上依序沈積絕緣層或介電層、導電層以及半導體材料層並使用微影來圖案化各種材料層以在其上形成電路組件及構件。
半導體工業持續藉由不斷減小最小特徵尺寸來提高各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度，此允許將更多組件整合至給定區域中。然而，隨著最小特徵尺寸減小，出現應解決的額外問題。
本發明實施例提供一種半導體元件的形成方法，包括：將第一導電柱形成在第一重佈線結構之上且電耦接至所述第一重佈線結構；將第一晶粒貼合至所述第一重佈線結構，所述第一晶粒包括第二導電柱；將第二晶粒貼合至所述第一晶粒，所述第二 晶粒與所述第二導電柱相鄰；用包封體包封所述第一導電柱、所述第一晶粒以及所述第二晶粒；在所述包封體、所述第一導電柱、所述第一晶粒以及所述第二晶粒之上形成第二重佈線結構；以及將第三晶粒接合至所述第一重佈線結構。
本發明實施例提供一種半導體元件，包括：第一元件、第二元件、第三元件、模塑化合物以及第二重佈線結構。第一元件接合至第一重佈線結構的第一側。第二元件貼合至所述第一重佈線結構的與所述第一側相對的第二側。第三元件貼合至所述第二元件。模塑化合物包圍所述第二元件及所述第三元件。第二重佈線結構位於所述第二元件、所述第三元件以及所述模塑化合物之上。所述第一元件及所述第二元件使用所述第二重佈線結構電耦接至所述第三元件。
本發明實施例提供一種半導體元件，包括：第一晶粒、第一模塑化合物、第一穿孔、第二重佈線結構、第二晶粒、第二模塑化合物、第二穿孔以及第三穿孔。第一晶粒貼合至第一重佈線結構。第一模塑化合物位於所述第一重佈線結構之上且包圍所述第一晶粒。第一穿孔延伸穿過所述第一模塑化合物。第二重佈線結構位於所述第一晶粒、所述第一模塑化合物以及所述第一穿孔之上。第二晶粒貼合至所述第二重佈線結構。第二模塑化合物位於所述第二重佈線結構之上且包圍所述第二晶粒。第二穿孔及第三穿孔延伸穿過所述第二模塑化合物。所述第二穿孔電耦接至所述第一穿孔。所述第二穿孔包括具有圓形橫截面的通孔。所述第三穿孔電耦接至所述第一晶粒，所述第三穿孔包括具有橢圓形 橫截面的通孔。
50A、50B、50C、50D:主動元件晶粒
52:半導體基底
54:元件
56:層間介電質
58:導電插塞
60:內連線結構
62:接墊
64:鈍化膜
66:晶粒連接件
68、108、112、130、134、138、142、172、176:介電層
70、115、116、117、121、125、125a、125b:導電柱
72、114、148、178:開口
74:切割道區域
102:載體基底
104:釋放層
106:背側重佈線結構
110、132、136、140、174:金屬化圖案
118、119、120、123、124:黏著劑
122:虛設晶粒
126、127、129:包封體
128:前側重佈線結構
133:第一區
135:第二區
144:UBM
146、152:導電連接件
150:封裝組件
170:中間重佈線結構
200、300:經封裝半導體元件
D1、D2、D4、D5:直徑
D3:距離
H1:高度
L1、L2、L4:長度
W1、W2、W3:寬度
結合隨附圖式閱讀以下實施方式時會最佳地理解本揭露內容的態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1至圖14示出根據一些實施例的在用於形成經封裝半導體元件的製程期間的中間步驟的橫截面視圖。
圖15至圖20示出根據一些實施例的在用於形成經封裝半導體元件的製程期間的中間步驟的橫截面視圖。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然，此等具體實例僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵之上或第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露內容可在各種實例中重複元件標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不規定所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可在本文中使用諸如「在......之下(beneath)」、「在......下方(below)」、「下部(lower)」、「在......上 方(above)」、「上部(upper)」以及類似者的空間相對術語來描述如在圖式中所示出的一個構件或特徵與另一構件或特性的關係。除圖式中所描繪的定向之外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
各種實施例提供改良的晶粒堆疊結構及包含所述晶粒堆疊結構的經封裝半導體元件。晶粒堆疊結構可藉由以下步驟形成：在背側重佈線結構上形成第一導電柱；將包含第二導電柱的第一主動元件晶粒貼合至背側重佈線結構；以及將第二主動元件晶粒貼合至第一主動元件晶粒。前側重佈線結構可形成於第一導電柱、第二導電柱以及第二主動元件晶粒之上，且封裝組件可貼合至背側重佈線結構。使用此方法允許以最小面積在經封裝半導體元件中內連第一主動元件晶粒、第二主動元件晶粒以及封裝組件。此外，模塑化合物可同時以單一模塑步驟及單一研磨步驟形成於第一主動元件晶粒及第二主動元件晶粒周圍。第一導電柱及第二導電柱中的任一者可為橢圓形或圓形的，以減小經封裝半導體元件中的應力。
圖1至圖14為根據一些實施例的在經封裝半導體元件200的製造中的中間階段的橫截面視圖。圖1示出根據一些實施例的主動元件晶粒50A。主動元件晶粒50A將在後續處理中經封裝以形成積體電路封裝體。在一實施例中，主動元件晶粒50A可為系統晶片(system-on-chip；SoC)。在另外的實施例中，主動元件晶粒50A可為邏輯晶粒(例如，中央處理單元(central processing unit；CPU)、圖像處理單元(graphics processing unit；GPU)、應用程式處理器(application processor；AP)、微控制器或類似者)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒、高頻寬記憶體(high bandwidth memory；HBM)晶粒或類似者)、輸入/輸出(input/output；I/O)介面晶粒、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒或類似者)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing；DSP)晶粒或類似者)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒或類似者)、類似者，或其組合。主動元件晶粒50A可具有在自上而下視圖中自約9毫米至約12毫米的長度及自約9毫米至約12毫米的寬度。
主動元件晶粒50A可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個主動元件晶粒的不同元件區。主動元件晶粒50A可根據可適用的製造製程來經處理以形成積體電路。舉例而言，主動元件晶粒50A包含半導體基底52，諸如經摻雜或未經摻雜的矽，或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底52可包含：其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP； 或其組合。亦可使用其他基底，諸如多層或梯度基底。半導體基底52具有有時稱為前側的主動表面(例如，在圖1中面朝上的表面)及有時稱為背側的非主動表面(例如，在圖1中面朝下的表面)。
元件54可形成於半導體基底52的前側處。元件54可為主動元件(例如，電晶體、二極體或類似者)、電容器、電阻器或類似者。層間介電質(inter-layer dielectric；ILD)56形成於半導體基底52的前側之上。ILD 56包圍且可覆蓋元件54。ILD 56可包含由材料形成的一或多個介電層，所述材料諸如磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)、未經摻雜矽酸鹽玻璃(undoped silicate glass；USG)或類似者。
導電插塞58延伸穿過ILD 56以電耦接且實體耦接元件54。舉例而言，當元件54為電晶體時，導電插塞58可耦接電晶體的閘極及源極/汲極區。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似者或其組合形成。內連線結構60位於ILD 56及導電插塞58之上。內連線結構60內連元件54以形成積體電路。內連線結構60可藉由例如ILD 56上的介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個低k介電層中的金屬線及通孔。內連線結構60的金屬化圖案藉由導電插塞58電耦接至元件54。
主動元件晶粒50A更包含進行外部連接的接墊62，諸如鋁接墊。接墊62在主動元件晶粒50A的主動側上，諸如在內連線 結構60中及/或在所述內連線結構60上。一或多個鈍化膜64位於主動元件晶粒50A上，諸如在部分內連線結構60及部分接墊62上。開口延伸穿過鈍化膜64至接墊62。諸如導電柱(例如，由諸如銅的金屬形成)的晶粒連接件66延伸穿過鈍化膜64中的開口，且實體耦接並電耦接至各別的接墊62。晶粒連接件66可藉由例如鍍覆或類似者形成。晶粒連接件66電耦接主動元件晶粒50A的各別積體電路。
可選地，焊料區(例如，焊料球或焊料凸塊)可安置於接墊62上。焊料球可用以對主動元件晶粒50A進行晶片探針(chip probe；CP)測試。對主動元件晶粒50A進行CP測試可以確定主動元件晶粒50A是否為良好晶粒(known good die；KGD)。因此，僅封裝經歷後續處理的為KGD的主動元件晶粒50A，且不封裝未通過CP測試的晶粒。在測試之後，可在後續處理步驟中移除焊料區。
介電層68可位於主動元件晶粒50A的前側上，諸如在鈍化膜64及晶粒連接件66上。介電層68橫向包封晶粒連接件66，且介電層68在橫向上與主動元件晶粒50A共端。最初，介電層68可掩埋晶粒連接件66，使得介電層68的最頂部表面在晶粒連接件66的最頂部表面上方。在焊料區安置於晶粒連接件66上的一些實施例中，介電層68亦可掩埋焊料區。或者，可在形成介電層68之前移除焊料區。
介電層68可為：聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者，或其組合。介電層68可 例如藉由旋轉塗佈、疊層、CVD或類似者形成。在一些實施例中，晶粒連接件66在主動元件晶粒50A的形成期間經由介電層68暴露。在一些實施例中，晶粒連接件66保持掩埋且在用於封裝主動元件晶粒50的後續製程期間暴露。暴露晶粒連接件66可移除可存在於晶粒連接件66上的任何焊料區。
在一些實施例中，主動元件晶粒50A為包含多個半導體基底52的堆疊元件。舉例而言，主動元件晶粒50A可為記憶體元件，諸如混合記憶體立方體(hybrid memory cube；HMC)模組、高頻寬記憶體(HBM)模組或包含多個記憶體晶粒的類似者。在此類實施例中，主動元件晶粒50A包含藉由基底穿孔(through-substrate via；TSV)內連的多個半導體基底52。半導體基底52中的每一者可具有內連線結構60。
圖2至圖4示出在用於形成主動元件晶粒50B的製程期間的中間步驟的橫截面視圖。主動元件晶粒50B可與圖1中所示出的主動元件晶粒50A相同或類似，其中主動元件晶粒50B包含導電柱70(在圖4中示出)而不是晶粒連接件66。在實施例中，主動元件晶粒50B可為寬輸入/輸出(wide input/output；WIO)記憶體晶粒。在本文中的論述中，除非另外規定，否則相同或類似標號指代藉由相同或類似方法使用相同或類似材料形成的相同或類似組件，於此便不再詳述。
在圖2中，兩個主動元件晶粒50B在單體化之前設置於同一半導體基底52上，所述半導體基底52可為晶圓。儘管在主動元件晶粒50B中的每一者中示出兩個接墊62，但可存在任何數目個接墊62。一或多個鈍化膜64形成於接墊62之上且介電層68 形成於鈍化膜64之上。介電層68及鈍化膜64可經圖案化以形成暴露出部分接墊62的開口72。所述圖案化可藉由可接受的製程進行，諸如藉由當介電層68為感光性材料時使介電層68暴露於光或藉由使用例如非等向性蝕刻來蝕刻而進行。在介電層68為感光性材料的實施例中，介電層68可在暴露於光之後顯影。
在圖3中，將導電柱70形成於開口72中且延伸於介電層68上方。作為實例，導電柱70可藉由首先在介電層68以及外露於開口72的部分鈍化膜64及部分接墊62之上形成晶種層來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及所述鈦層之上的銅層。晶種層可使用例如PVD或類似者來形成。光阻形成於晶種層上且在所述晶種層上經圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以供圖案化。光阻的圖案對應於導電柱70。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或化學鍍或類似者。導電材料可包括金屬，諸如銅、鈦、鎢、鋁或類似者。移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝除製程來移除光阻，所述製程諸如使用氧電漿或類似者的製程。一旦移除光阻，則使用可接受的蝕刻製程(諸如濕式或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成導電柱70。
圖3進一步示出導電柱70的橫截面。如圖3中所示出，導電柱70可具有圓形橫截面形狀或橢圓形橫截面形狀。導電柱70 中的一些可具有圓形橫截面形狀，而導電柱70中的其他者可具有橢圓形橫截面形狀。諸如正方形、矩形、多邊形或類似者的其他橫截面形狀亦為可能的。在導電柱70具有圓形橫截面形狀的實施例中，導電柱70可具有自約15微米至約40微米(諸如約20微米)的直徑D1。在導電柱70具有橢圓形橫截面形狀的實施例中，導電柱70在自上而下視圖中的長度L1可為自約20微米至約50微米，諸如約35微米，且導電柱70在自上而下視圖中的寬度W1可為自約15微米至約40微米，諸如約25微米。延伸於介電層68上方的部分導電柱70可具有約100微米至約120微米的高度H1，所述高度H1可大於隨後置放於主動元件晶粒50B之上的晶粒(例如，圖9中所示出的主動元件晶粒50A)的高度。
在圖4中，薄化半導體基底52並單體化主動元件晶粒50B。可使用機械研磨或化學機械研磨(chemical mechanical polishing；CMP)製程來薄化半導體基底。所述CMP製程利用化學蝕刻劑及磨料來反應並研磨掉半導體基底52，直至半導體基底52達到所需厚度。可使用分割製程，諸如鋸割、雷射鑽孔或類似者，來單體化主動元件晶粒50B。主動元件晶粒50B可沿圖3中所示出的切割道區域74來單體化。主動元件晶粒50B可各自具有在自上而下視圖中自約9毫米至約12毫米的長度及自約7毫米至約12毫米的寬度。在一些實施例中，可在薄化及單體化之前將主動元件晶粒50B的前側置放於載帶上，其中導電柱70延伸至載帶中。載帶可具有大於導電柱70的高度的厚度，使得導電柱70被載帶包圍。載帶可包括聚合物材料、黏著性材料或類似者。
在圖5中，提供載體基底102，且將釋放層104形成於載 體基底102上。載體基底102可為玻璃載體基底、陶瓷載體基底或類似者。載體基底102可為晶圓，使得多個封裝可同時形成於載體基底102上。
釋放層104可由聚合物類材料形成，可將所述聚合物類材料連同載體基底102一起自將形成於後續步驟中的上覆結構移除。在一些實施例中，釋放層104為在加熱時損失其黏著性質的環氧類熱釋放材料，諸如光熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時損失其黏著性質的紫外(ultra-violet；UV)黏膠。釋放層104可配製為液體且經固化，可為疊層至載體基底102上的疊層膜，或可為類似者。釋放層104的頂部表面可經水平化且可具有高度平面性。
在圖6中，可將背側重佈線結構106形成於釋放層104上。在所繪示實施例中，背側重佈線結構106包含介電層108、金屬化圖案110(有時稱為重佈線層或重佈線(redistribution line))以及介電層112。背側重佈線結構106為視情況選用的。在一些實施例中，不具有金屬化圖案的介電層代替背側重佈線結構106以形成於釋放層104上。
介電層108可形成於釋放層104上。介電層108的底部表面可與釋放層104的頂部表面接觸。在一些實施例中，介電層108由諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene；BCB)或類似者的聚合物形成。在其他實施例中，介電層108由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、 硼摻磷矽酸鹽玻璃(BPSG)或類似者；或類似者。介電層108可藉由任何可接受的沈積製程形成，諸如旋轉塗佈、化學氣相沈積(CVD)、疊層、類似者，或其組合。
金屬化圖案110可形成於介電層108上。作為實例，金屬化圖案110可藉由首先在介電層108之上形成晶種層來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及所述鈦層之上的銅層。可使用例如物理氣相沈積(physical vapor deposition；PVD)或類似者來形成晶種層。光阻接著形成於晶種層上且在所述晶種層上經圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以供圖案化。光阻的圖案對應於金屬化圖案110。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或化學鍍或類似者。導電材料可包括金屬，諸如銅、鈦、鎢、鋁或類似者。接著，移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝除製程來移除光阻，所述製程諸如使用氧電漿或類似者的製程。一旦移除光阻，則使用可接受的蝕刻製程(諸如濕式或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成金屬化圖案110。
介電層112可形成於金屬化圖案110及介電層108上。在一些實施例中，介電層112由聚合物形成，所述聚合物可為使用微影罩幕來圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層112由諸如氮化矽的氮化物、 諸如氧化矽、PSG、BSG、BPSG的氧化物或類似者形成。介電層112可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。介電層112可經圖案化以形成暴露金屬化圖案110的部分的開口114。圖案化可藉由可接受的製程進行，諸如藉由當介電層112為感光性材料時使介電層112暴露於光或藉由使用例如非等向性蝕刻來蝕刻而進行。在介電層112為感光性材料的實施例中，介電層112可在暴露於光之後顯影。
應瞭解，背側重佈線結構106可包含任何數目個介電層及金屬化圖案。若欲形成更多介電層及金屬化圖案，則可重複上文所述的步驟及製程。金屬化圖案可包含導電線及導通孔。導通孔可在金屬化圖案的形成期間藉由在之下的介電層的開口中形成晶種層及金屬化圖案的導電材料來形成。導通孔可內連及電耦接金屬化圖案的各種導電線。
在圖7中，將導電柱116形成於開口114(在圖6中示出)中且延伸於背側重佈線結構106的最頂部介電層(例如，圖6中所示出的實施例中的介電層112)上方。導電柱116可用以電耦接背側重佈線結構106與隨後形成的前側重佈線結構(例如，圖11中所示出的前側重佈線結構128)。在一些實施例中，導電柱116中的至少一些可能未電耦接至背側重佈線結構106及前側重佈線結構128，且可用於熱耗散。作為實例，導電柱116可藉由首先在背側重佈線結構106之上(例如，在介電層112及外露於開口114的部分金屬化圖案110上)形成晶種層來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及所述 鈦層之上的銅層。晶種層可使用例如PVD或類似者來形成。光阻形成於晶種層上且在所述晶種層上經圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以供圖案化。光阻的圖案對應於導電柱116。圖案化形成穿過光阻的開口以暴露晶種層。導電材料形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或化學鍍或類似者。導電材料可包括金屬，諸如銅、鈦、鎢、鋁或類似者。移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝除製程來移除光阻，所述製程諸如使用氧電漿或類似者的製程。一旦移除光阻，則使用可接受的蝕刻製程(諸如濕式或乾式蝕刻)來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成導電柱116。
圖7進一步示出導電柱116的橫截面。如圖7中所示出，導電柱116可具有圓形橫截面形狀或橢圓形橫截面形狀。導電柱116中的一些可具有圓形橫截面形狀，而導電柱116中的其他者可具有橢圓形橫截面形狀。諸如正方形、矩形、多邊形或類似者的其他橫截面形狀亦為可能的。在導電柱116具有圓形橫截面形狀的實施例中，導電柱116可具有自約40微米至約150微米(諸如約50微米或約90微米)的直徑D2。在導電柱116具有橢圓形橫截面形狀的實施例中，導電柱116在自上而下視圖中的長度L2可為自約40微米至約150微米，諸如約60微米，且導電柱116在自上而下視圖中的寬度W2可為自約20微米至約130微米，諸如約30微米。導電柱116可具有自約80微米至約250微米(諸如約200微米)的間距。
在一些實施例中，導電柱116可用以將隨後貼合的主動 元件晶粒(例如，圖9中所示出的主動元件晶粒50A)及隨後貼合的封裝組件(例如，圖14中所示出的封裝組件150)電耦接至隨後貼合的主動元件晶粒(例如，圖8中所示出的主動元件晶粒50B)。在一實施例中，電耦接至封裝組件150的導電柱116可為橢圓形的且可具有約80微米至約250微米的間距形式，且電耦接至主動元件晶粒50A的導電柱116可為圓形的且可具有約80微米至約250微米的間距形式。使用橢圓形導電柱116及圓形導電柱116可經由應力再分佈以減小應力，且可減少隨後完成的元件中的缺陷。
在圖8中，將主動元件晶粒50B藉由黏著劑118黏著至介電層112。可使用取放機或類似者將主動元件晶粒50B置放於背側重佈線結構106之上。黏著劑118在主動元件晶粒50B的背側上且使主動元件晶粒50B黏著至背側重佈線結構106，諸如黏著至介電層112。黏著劑118可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(die attach film；DAF)或類似者。可將黏著劑118施加至主動元件晶粒50B的背側或可施加於載體基底102上的介電層112的表面之上。舉例而言，可在單體化主動元件晶粒50B之前將黏著劑118施加至主動元件晶粒50B的背側。如圖8中所示出，在將主動元件晶粒50B貼合至背側重佈線結構106之後，導電柱116的頂部表面可與導電柱70的頂部表面齊平。
在圖9中，將主動元件晶粒50A藉由黏著劑120黏著至主動元件晶粒50B。可使用取放機或類似者將主動元件晶粒50A置放於主動元件晶粒50B之上。黏著劑120在主動元件晶粒50A的背側上且使主動元件晶粒50A黏著至主動元件晶粒50B，諸如 黏著至介電層68。黏著劑120可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(DAF)或類似者。可將黏著劑120施加至主動元件晶粒50A的背側。舉例而言，可單體化主動元件晶粒50B之前將黏著劑120施加至主動元件晶粒50B的背側。如圖9中所示出，在一實施例中，在將主動元件晶粒50A貼合至主動元件晶粒50B之後，主動元件晶粒50A的頂部表面(包含晶粒連接件66及介電層68的頂部表面)可與導電柱70及導電柱116的頂部表面齊平。在另外的實施例中，在將主動元件晶粒50A貼合至主動元件晶粒50B之後，晶粒連接件66、介電層68、導電柱70以及導電柱116的頂部表面可能未彼此齊平。
圖9進一步示出藉由黏著劑124黏著至介電層112的虛設晶粒122。在使主動元件晶粒50A黏著至主動元件晶粒50B及虛設晶粒122之前，使虛設晶粒122黏著至背側重佈線結構106。虛設晶粒122為可選的且可能或可能未包含。舉例而言，如圖9中所示出，可將主動元件晶粒50A置放於主動元件50B之上，使得主動元件晶粒50A的至少一部分突出於背側重佈線結構106之上，而無需虛設晶粒122***於所述主動元件晶粒50A與所述背側重佈線結構106之間。取決於主動元件晶粒50B的尺寸、主動元件晶粒50A的尺寸、突出的量以及黏著劑120的強度，虛設晶粒122可包含於主動元件晶粒50A與背側重佈線結構106之間，以便確保主動元件晶粒50A為水平的且未傾斜。在一些實施例中，當虛設晶粒的寬度W3與突出的距離D3的比為小於約2/3或小於約1/2時，可包含虛設晶粒122。在包含虛設晶粒122的實施例中，在使主動元件晶粒50A黏著至主動元件晶粒50B及虛設晶 粒122之前，使虛設晶粒122黏著至背側重佈線結構106。
可使用取放機或類似者將虛設晶粒122置放於背側重佈線結構106之上。黏著劑124在虛設晶粒122的背側上且使虛設晶粒122黏著至背側重佈線結構106，諸如黏著至介電層112。黏著劑124可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(DAF)或類似者。可將黏著劑124施加至虛設晶粒122的背側或可施加於載體基底102上的介電層112的表面之上。如圖8中所示出，在將虛設晶粒122貼合至背側重佈線結構106之後，虛設晶粒122的頂部表面可與主動元件晶粒50B的介電層68的頂部表面齊平。
虛設晶粒122不具有電功能且未電連接至背側重佈線結構106、主動元件晶粒50A或主動元件晶粒50B。虛設晶粒122可由諸如金屬或金屬合金的導電材料、半導體材料、介電材料或類似者形成。在一些實施例中，虛設晶粒122可由矽、玻璃、石英、銅、碳化矽(silicon carbide；SiC)或類似者形成。
在圖10中，將包封體126形成於背側重佈線結構106之上且包圍主動元件晶粒50A、主動元件晶粒50B、虛設晶粒122以及導電柱116。包封體126可為模塑化合物、環氧樹脂或類似者。包封體126可藉由壓縮模塑、轉移模塑或類似者施加，且可形成於背側重佈線結構106之上，以掩埋或覆蓋主動元件晶粒50A、主動元件晶粒50B、虛設晶粒122以及導電柱116。包封體126可以液體或半液體形式施加且隨後經固化。
另外在圖10中，對包封體126進行平坦化製程以暴露導電柱116、導電柱70、晶粒連接件66以及介電層68。平坦化製程亦可移除導電柱116、導電柱70、晶粒連接件66及/或介電層68 的材料。在一些實施例中，在平坦化製程之前，導電柱116、導電柱70、晶粒連接件66以及介電層68的頂部表面可能未彼此齊平，且可利用平坦化製程來使導電柱116、導電柱70、晶粒連接件66以及介電層68的頂部表面彼此齊平。平坦化製程可為例如CMP製程、研磨製程、回蝕刻製程或類似者。在一些實施例中，例如若已暴露出導電柱116、導電柱70、晶粒連接件66以及介電層68，則可省略平坦化製程。
在圖11中，將前側重佈線結構128形成於包封體126、導電柱116、導電柱70以及主動元件晶粒50A之上。前側重佈線結構128包含介電層130、介電層134、介電層138以及介電層142；以及金屬化圖案132、金屬化圖案136以及金屬化圖案140。金屬化圖案亦可稱為重佈線層或重佈線。圖11中所示出的前側重佈線結構128包含三層金屬化圖案及四層介電層；然而，更多或更少金屬化圖案及介電層可包含於前側重佈線結構128中。若欲形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若欲形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
介電層130沈積於包封體126、導電柱116、導電柱70以及主動元件晶粒50A上。在一些實施例中，介電層130由諸如PBO、聚醯亞胺、BCB或類似者的感光性材料形成，所述感光性材料可使用微影罩幕來圖案化。介電層130可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。介電層130接著經圖案化。圖案化形成暴露部分導電柱116、部分導電柱70以及部分晶粒連接件66的開口。所述圖案化可藉由可接受的製程進行，諸如藉由當 介電層130為感光性材料時使介電層130暴露於光或藉由使用例如非等向性蝕刻來蝕刻而進行。若介電層130為感光性材料，則介電層130可在暴露之後顯影。
接著形成金屬化圖案132。金屬化圖案132包含位於介電層130的主表面上且沿所述主表面延伸的線部分(亦稱為導電線)。金屬化圖案132更包含通孔部分(亦稱為導通孔)，所述通孔部分延伸穿過介電層130以實體耦接且電耦接導電柱116、主動元件晶粒50B的導電柱70以及主動元件晶粒50A的晶粒連接件66。作為實例，金屬化圖案132可藉由首先在介電層130之上及延伸穿過介電層130的開口中形成晶種層來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及所述鈦層之上的銅層。晶種層可使用例如PVD或類似者來形成。光阻接著形成於晶種層上且在所述晶種層上經圖案化。光阻可藉由旋轉塗佈或類似者形成，且可暴露於光以供圖案化。光阻的圖案對應於金屬化圖案132。圖案化形成穿過光阻的開口以暴露晶種層。導電材料接著形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆形成，所述鍍覆諸如電鍍或化學鍍或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料與晶種層的之下部分的組合形成金屬化圖案132。移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝除製程來移除光阻，諸如使用氧電漿或類似者。一旦移除光阻，則使用可接受的蝕刻製程(諸如濕式或乾式蝕刻)來移除晶種層的暴露部分。
介電層134沈積於金屬化圖案132及介電層130上。介電層134可以類似於介電層130的方式形成，且可由類似於介電層130的材料的材料形成。
接著形成金屬化圖案136。金屬化圖案136包含位於介電層134的主表面上且沿所述主表面延伸的線部分。金屬化圖案136更包含延伸穿過介電層134以實體耦接且電耦接金屬化圖案132的通孔部分。金屬化圖案136可以類似於金屬化圖案132的方式形成，且可由類似於金屬化圖案132的材料的材料形成。
介電層138沈積於金屬化圖案136及介電層134上。介電層138可以類似於介電層130的方式形成，且可由類似於介電層130的材料的材料形成。
接著形成金屬化圖案140。金屬化圖案140包含位於介電層138的主表面上且沿所述主表面延伸的線部分。金屬化圖案140更包含延伸穿過介電層138以實體耦接且電耦接金屬化圖案136的通孔部分。金屬化圖案140可以類似於金屬化圖案132的方式形成，且可由類似於金屬化圖案132的材料的材料形成。金屬化圖案140為前側重佈線結構128的最頂部金屬化圖案。因此，前側重佈線結構128的中間金屬化圖案(例如，金屬化圖案132及金屬化圖案136)中的所有者均安置於金屬化圖案140與包封體126、導電柱116、主動元件晶粒50B的導電柱70以及主動元件晶粒50A的晶粒連接件66之間。
介電層142沈積於金屬化圖案140及介電層138上。介電層142可以類似於介電層130的方式形成，且可由類似於介電層130的材料的材料形成。介電層142為前側重佈線結構128的 最頂部介電層。因此，前側重佈線結構128的金屬化圖案(例如，金屬化圖案132、金屬化圖案136以及金屬化圖案140)中的所有者均安置於介電層142與主動元件晶粒50A以及主動元件晶粒50B之間。另外，前側重佈線結構128的中間介電層(例如，介電層130、介電層134、介電層138)中的所有者均安置於介電層142與包封體126、導電柱116、主動元件晶粒50B的導電柱70以及主動元件晶粒50A的晶粒連接件66之間。
在圖12中，形成用於外部連接至前側重佈線結構128的UBM 144。UBM 144具有在介電層142的主表面上且沿所述主表面延伸的凸塊部分，且具有延伸穿過介電層142以實體耦接且電耦接至金屬化圖案140的通孔部分。因此，UBM 144電耦接至導電柱116、主動元件晶粒50A以及主動元件晶粒50B。UBM 144可由與金屬化圖案132相同的材料形成。在一些實施例中，UBM 144可具有與金屬化圖案132、金屬化圖案136以及金屬化圖案140不同的尺寸。
另外在圖12中，導電連接件146形成於UBM 144上。導電連接件146可為球柵陣列封裝(ball grid array；BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold；ENEPIG)形成的凸塊，或類似者。導電連接件146可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件146藉由經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者初始地形成焊料層來形成。一旦焊料層已形成於結構上， 則可進行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件146包括藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可為無焊料的且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可藉由鍍覆製程形成。
在圖13中，翻轉圖12的結構，將載體基底102自背側重佈線結構106(例如，介電層108)剝離，且將開口148形成於介電層108中。根據一些實施例，所述剝離包含將諸如雷射光或UV光的光投射於釋放層104上，使得釋放層104在光的熱量下分解且可移除載體基底102。接著翻轉所述結構。在一些實施例中，可將所述結構置放於載帶(未單獨示出)上。開口148形成並穿過介電層108以暴露部分金屬化圖案110。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口148。
在圖14中，將封裝組件150接合至背側重佈線結構106以形成經封裝半導體元件200。在一些實施例中，封裝組件150可為記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、低功率雙倍資料速率同步動態隨機存取記憶體(low-power double data rate synchronous dynamic random access memory；LPDDR)晶粒、靜態隨機存取記憶體(SRAM)晶粒、高頻寬記憶體(HBM)晶粒或類似者)。在其他實施例中，封裝組件150可為邏輯晶粒(例如，中央處理單元(CPU)、圖像處理單元(GPU)、系統晶片(SoC)、應用程式處理器(AP)、微控制器或類似者)、輸入/輸出(I/O)介面晶粒、功率管理晶粒(例如，功率管理積體電路(PMIC)晶 粒或類似者)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒或類似者)、前端晶粒(例如，類比前端(AFE)晶粒或類似者)、類似者，或其組合。
可使用導電連接件152將封裝組件150接合至背側重佈線結構106。導電連接件152可形成於開口148中，可設置於封裝組件150上，或其組合。導電連接件152可為球柵陣列封裝(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊，或類似者。導電連接件152可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件152藉由經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者的方法初始地形成焊料層來形成。一旦焊料層已形成於結構上，則可進行回焊以便將材料塑形成所需凸塊形狀。可使用取放機或類似者將封裝組件150置放於背側重佈線結構106之上。一旦封裝組件150經置放，則可回焊導電連接件152以將封裝組件150接合至背側重佈線結構106。
藉由在主動元件50B中形成導電柱70，主動元件50B及主動元件50A可在兩個水平面處貼合至背側重佈線結構106，從而需要佔據面積。此外，僅要求單一模塑及研磨步驟以形成包封主動元件50B及主動元件50A的包封體126。在經封裝半導體元件200中包含背側重佈線結構106及前側重佈線結構128允許將具有不同輸入/輸出接墊位置的主動元件晶粒50B(例如，WIO記憶體晶粒)及封裝組件150(例如，LPDDR晶粒或DRAM晶粒) 與主動元件晶粒50A(例如，SoC)整合，從而提供用於整合在經封裝半導體元件200中的晶粒的選擇上的靈活性。導電柱116與背側重佈線結構106與前側重佈線結構128之間的銅對銅界面減小導電柱116的電阻，從而降低經封裝半導體元件200的RC延遲且改良訊號完整性。此外，包含橢圓形及圓形的導電柱116、導電柱70減小經封裝半導體元件300中的應力。
圖15至圖20為根據一些實施例的在經封裝半導體元件300的製造中的中間階段的橫截面視圖。與在圖1至圖14中使用的元件標號相同的在圖15至圖20中使用的元件標號指示使用類似製程形成的相同或類似層及/或結構。因此，可使用與上文參考圖1至圖14所論述的材料及方法相同或類似的材料及方法來形成具有相同元件標號的層及結構，於此將不再贅述。在圖15中，提供載體基底102，將釋放層104形成於載體基底102上，且將背側重佈線結構106形成於釋放層104上。將導電柱115及導電柱117形成為延伸於背側重佈線結構106的最頂部介電層(例如，圖15中所示出的實施例中的介電層112)上方且延伸穿過介電層112以接觸金屬化圖案110。導電柱115及導電柱117可以類似於導電柱116的方式形成，且可由類似於導電柱116的材料的材料形成。
將主動元件晶粒50C經由黏著劑119貼合至背側重佈線結構106。主動元件晶粒50C可以類似於主動元件晶粒50A的方式形成，且可由類似於主動元件晶粒50A的材料的材料形成。在一些實施例中，主動元件晶粒50C的尺寸可不同於主動元件晶粒50A的尺寸。主動元件晶粒50C可具有在自上而下視圖中自約9毫米至約12毫米的長度及自約7毫米至約12毫米的寬度。在一 實施例中，主動元件晶粒50C可為WIO記憶體晶粒。黏著劑119可以類似於黏著劑118的方式形成，且可由類似於黏著劑118的材料的材料形成。
在一些實施例中，導電柱115可提供主動元件50C與主動元件(例如，圖18A中所示出的主動元件50D)及封裝組件(例如，圖20中所示出的封裝組件150)中的每一者之間的電耦接。導電柱117可提供散熱且可能電耦接或可能未電耦接至主動元件50C、主動元件50D以及封裝組件150中的任一者。導電柱115及/或導電柱117可具有圓形橫截面形狀或橢圓形橫截面形狀。亦為可能是諸如正方形、矩形、多邊形或類似者的其他橫截面形狀。在導電柱115及/或導電柱117具有圓形橫截面形狀的實施例中，導電柱115及/或導電柱117可具有自約20微米至約150微米(諸如約30微米或約90微米)的直徑。在導電柱115及/或導電柱117具有橢圓形橫截面形狀的實施例中，導電柱115及/或導電柱117在自上而下視圖中的長度可為自約40微米至約160微米，諸如約60微米，且導電柱115及/或導電柱117在自上而下視圖中的寬度可為自約30微米至約150微米，諸如約30微米。導電柱115可具有自約80微米至約250微米(諸如約150微米)的間距。導電柱117可具有自約80微米至約250微米(諸如約150微米)的間距。
在圖16中，將包封體127形成於背側重佈線結構106之上且包圍主動元件晶粒50C、導電柱115以及導電柱117。包封體127可以類似於包封體126的方式形成，且可由類似於包封體126的材料的材料形成。包封體127可經平坦化以暴露導電柱115、導 電柱117以及主動元件晶粒50C的晶粒連接件66。平坦化製程亦可移除晶粒連接件66的材料、主動元件晶粒50C的介電層68、導電柱115及/或導電柱117。平坦化製程可為例如CMP製程、研磨製程、回蝕刻製程或類似者。在一些實施例中，例如若已暴露導電柱115、導電柱117以及晶粒連接件66，則可省略平坦化製程。
在圖17中，將中間重佈線結構170形成於包封體127、導電柱115、導電柱117以及主動元件晶粒50C之上。中間重佈線結構170包含介電層172及介電層176；以及金屬化圖案174。金屬化圖案亦可被稱為重佈線層或重佈線。圖17中所示出的中間重佈線結構170包含一層金屬化圖案及兩層介電層；然而，更多或更少金屬化圖案及介電層可包含於中間重佈線結構170中。若欲形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若欲形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
介電層172沈積於包封體127、導電柱115、導電柱117以及主動元件晶粒50C上。介電層172可以類似於介電層130的方式形成，且可由類似於介電層130的材料的材料形成。
接著形成金屬化圖案174。金屬化圖案174包含位於介電層172的主表面上且沿所述主表面延伸的線部分。金屬化圖案174更包含延伸穿過介電層172以實體耦接且電耦接導電柱115、導電柱117以及晶粒連接件66的通孔部分。金屬化圖案174可以類似於金屬化圖案132的方式形成，且可由類似於金屬化圖案132的材料的材料形成。
介電層176沈積於金屬化圖案174及介電層172上。介電層176可以類似於介電層130的方式形成，且可由類似於介電層130的材料的材料形成。開口178可穿過介電層176形成以暴露金屬化圖案174的部分。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口178。
在圖18A中，將導電柱121及導電柱125形成為延伸於中間重佈線結構170的最頂部介電層(例如，圖17中所示出的實施例中的介電層176)上方且延伸穿過介電層176以接觸金屬化圖案174。導電柱121及導電柱125可以類似於導電柱116的方式形成，且可由類似於導電柱116的材料的材料形成。
將主動元件晶粒50D經由黏著劑123貼合至中間重佈線結構170。主動元件晶粒50D可以類似於主動元件晶粒50A的方式形成，且可由類似於主動元件晶粒50A的材料的材料形成。在一些實施例中，主動元件晶粒50D的尺寸可不同於主動元件晶粒50C的尺寸。主動元件晶粒50D可具有在自上而下視圖中自約9毫米至約12毫米的長度及自約7毫米至約12毫米的寬度。在一實施例中，主動元件晶粒50D可為SoC。黏著劑123可以類似於黏著劑118的方式形成，且可由類似於黏著劑118的材料的材料形成。
圖18B示出圖18A的包含第一區133中的導電柱121、第二區135中的導電柱125以及主動元件晶粒50D的結構的一部分的橫截面視圖。第一區133中的導電柱121及第二區中的導電柱125的圖案可以是連續的，使得在自上而下視圖中第一區133中的導電柱121合圍第二區135且第二區135中的導電柱125合 圍主動元件晶粒50D。第二區135中的導電柱125每單位面積的分佈可大於第一區133中的導電柱121每單位面積的分佈。舉例而言，第一區133中的導電柱121每單位面積的分佈可為自約20個柱/平方毫米至約80個柱/平方毫米，諸如約49個柱/平方毫米，而第二區135中的導電柱125每單位面積的分佈可為自約200個柱/平方毫米至約800個柱/平方毫米，諸如約625個柱/平方毫米。如圖18B中所示出，第一區133中的導電柱121可具有圓形橫截面形狀且第二區135可包含具有圓形橫截面形狀的導電柱125a以及具有橢圓形橫截面形狀的導電柱125b。導電柱125a及導電柱125b的圖案可以是連續的，使得在自上而下視圖中具有橢圓形橫截面形狀的導電柱125b合圍具有圓形橫截面形狀的導電柱125a。導電柱121可具有自約50微米至約120微米(諸如約90微米)的直徑D4。在另一實施例中，導電柱121具有自約25微米至約35微米的直徑D4。導電柱125a可具有自約20微米至約50微米(諸如約30微米)的直徑D5。導電柱125b在自上而下視圖中的長度L4可為自約35微米至約55微米，諸如約45微米，且導電柱125b在自上而下視圖中的寬度W3可為自約20微米至約35微米，諸如約25微米。在另一實施例中，導電柱125b可具有自約25微米至約50微米的長度L4及自約25微米至約37微米的寬度W3。
第一區133中的導電柱121可經由中間重佈線結構170及前側重佈線結構128來提供隨後接合的封裝組件(例如，圖20中所示出的封裝組件150)與主動元件晶粒50D之間的內連。第二區中的導電柱125可經由中間重佈線結構170及前側重佈線結構128來提供主動元件晶粒50C與主動元件晶粒50D之間的內 連。第一區133中的導電柱121及第二區135中的導電柱125的分佈、形狀以及尺寸可分別基於在封裝組件150與主動元件晶粒50D之間及主動元件晶粒50C與主動元件晶粒50D之間所發送的訊號的類型(例如，功率訊號、資料訊號或類似者)來選擇。包含橢圓形導電柱125b及圓形導電柱125a兩者可擴大用於形成元件的製程裕度，從而需要更少的控制，此簡化處理且增加元件產量。包含橢圓形導電柱125b及圓形導電柱125a兩者亦可減小完成的元件中的應力。
在圖19中，將包封體129形成於中間重佈線結構170之上且包圍主動元件晶粒50D、導電柱121以及導電柱125。包封體129可以類似於包封體126的方式形成，且可由類似於包封體126的材料的材料形成。包封體129可經平坦化以暴露導電柱121、導電柱125以及主動元件晶粒50D的晶粒連接件66。平坦化製程亦可移除晶粒連接件66的材料、主動元件晶粒50D的介電層68、導電柱121及/或導電柱125。平坦化製程可為例如CMP製程、研磨製程、回蝕製程或類似者。在一些實施例中，例如若已暴露導電柱121、導電柱125以及晶粒連接件66，則可省略平坦化製程。
另外在圖19中，將前側重佈線結構128形成於包封體129、導電柱121、導電柱125以及主動元件晶粒50D之上。前側重佈線結構128包含介電層130、介電層134、介電層138以及介電層142；以及金屬化圖案132、金屬化圖案136以及金屬化圖案140。金屬化圖案亦可稱為重佈線層或重佈線。圖19中所示出的前側重佈線結構128包含三層金屬化圖案及四層介電層；然而，更多或更少金屬化圖案及介電層可包含於前側重佈線結構128 中。若欲形成更少介電層及金屬化圖案，則可省略上文所論述的步驟及製程。若欲形成更多介電層及金屬化圖案，則可重複上文所論述的步驟及製程。
形成用於外部連接至前側重佈線結構128的UBM 144。UBM 144具有在介電層142的主表面上且沿所述主表面延伸的凸塊部分，且具有延伸穿過介電層142以實體耦接且電耦接至金屬化圖案140的通孔部分。因此，UBM 144電耦接至導電柱121、導電柱125以及主動元件晶粒50D。UBM 144可由與金屬化圖案132相同的材料形成。在一些實施例中，UBM 144可具有與金屬化圖案132、金屬化圖案136以及金屬化圖案140不同的尺寸。
導電連接件146形成於UBM 144上。導電連接件146可為球柵陣列封裝(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊，或類似者。導電連接件146可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件146藉由經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者初始地形成焊料層來形成。一旦焊料層已形成於結構上，則可進行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件146包括藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可為無焊料的且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可藉由鍍覆製程形成。
在圖20中，翻轉圖19的結構，將載體基底102自背側重佈線結構106(例如，介電層108)剝離，將開口(未單獨示出)形成於介電層108中，且將封裝組件150經由導電連接件152接合至背側重佈線結構以形成經封裝半導體元件300。根據一些實施例，剝離包含將諸如雷射光或UV光的光投射於釋放層104上，使得釋放層104在光的熱量下分解且可移除載體基底102。接著翻轉所述結構。在一些實施例中，可將所述結構置放於載帶(未單獨示出)上。開口形成並穿過介電層108以暴露部分金屬化圖案110。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口。
接著將封裝組件150接合至背側重佈線結構106。在一些實施例中，封裝組件150可為記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、低功率雙倍資料速率同步動態隨機存取記憶體(LPDDR)晶粒、靜態隨機存取記憶體(SRAM)晶粒、高頻寬記憶體(HBM)晶粒或類似者)。在其他實施例中，封裝組件150可為邏輯晶粒(例如，中央處理單元(CPU)、圖像處理單元(GPU)、系統晶片(SoC)、應用程式處理器(AP)、微控制器或類似者)、輸入/輸出(I/O)介面晶粒、功率管理晶粒(例如，功率管理積體電路(PMIC)晶粒或類似者)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒或類似者)、前端晶粒(例如，類比前端(AFE)晶粒或類似者)、類似者，或其組合。
使用導電連接件152將封裝組件150接合至背側重佈線結構106。導電連接件152可形成於介電層108中的開口中，可設置於封裝組件150上，或其組合。導電連接件152可為球柵陣列 封裝(BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(C4)凸塊、微型凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊，或類似者。導電連接件152可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者，或其組合。在一些實施例中，導電連接件152藉由經由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者的方法初始地形成焊料層來形成。一旦焊料層已形成於結構上，則可進行回焊以便將材料塑形成所需凸塊形狀。可使用取放機或類似者將封裝組件150置放於背側重佈線結構106之上。一旦封裝組件150經置放，則可回焊導電連接件152以將封裝組件150接合至背側重佈線結構106。
背側重佈線結構106、中間重佈線結構170以及前側重佈線結構128被包含在經封裝半導體元件300中可允許將具有不同輸入/輸出接墊位置的主動元件晶粒50C(例如，WIO記憶體晶粒)及封裝組件150(例如，LPDDR晶粒或DRAM晶粒)整合至主動元件晶粒50D(例如，SoC)，從而提供用於整合在經封裝半導體元件300中的晶粒的選擇上的靈活性。導電柱117提供改良的散熱性。導電柱115與背側重佈線結構106與中間重佈線結構170之間以及導電柱121/導電柱125與中間重佈線結構170與前側重佈線結構128之間的銅對銅界面減小導電柱115、導電柱121以及導電柱125的電阻，從而降低經封裝半導體元件300的RC延遲且改良訊號完整性。此外，包含橢圓形及圓形的導電柱115、導電柱117、導電柱121及/或導電柱125減小經封裝半導體元件300中的應力。
根據一實施例，一種方法包含：將第一導電柱形成在第 一重佈線結構之上且電耦接至所述第一重佈線結構；將第一晶粒貼合至所述第一重佈線結構，所述第一晶粒包含第二導電柱；將第二晶粒貼合至所述第一晶粒，所述第二晶粒與所述第二導電柱相鄰；用包封體包封所述第一導電柱、所述第一晶粒以及所述第二晶粒；在所述包封體、所述第一導電柱、所述第一晶粒以及所述第二晶粒之上形成第二重佈線結構；以及將第三晶粒接合至所述第一重佈線結構。在一實施例中，使用第一黏著劑將所述第一晶粒貼合至所述重佈線結構，且使用第二黏著劑將所述第二晶粒貼合至所述第一晶粒。在一實施例中，所述方法更包含將虛設晶粒貼合至所述第一重佈線結構，所述將所述第二晶粒貼合至所述第一晶粒更包含將所述第二晶粒貼合至所述虛設晶粒。在一實施例中，所述方法更包含形成所述第一晶粒，所述形成所述第一晶粒包含：在半導體基底之上形成所述第二導電柱；將所述半導體基底及所述導電柱貼合至載帶，所述載帶包圍所述第二導電柱；薄化所述半導體基底的與所述第二導電柱相對的背側；以及單體化所述第一晶粒。在一實施例中，所述方法更包含平坦化所述包封體使得所述包封體、所述第一導電柱、所述第二導電柱以及所述第二晶粒的頂部表面彼此齊平。在一實施例中，所述第一晶粒、所述第二晶粒以及所述包封體安置於所述第一重佈線結構的第一側上，且所述第三晶粒安置於所述第一重佈線結構的與所述第一側相對的第二側上。
根據另一實施例，一種元件包含：第一元件，接合至第一重佈線結構的第一側；第二元件，貼合至所述第一重佈線結構的與所述第一側相對的第二側；第三元件，貼合至所述第二元件； 模塑化合物，包圍所述第二元件及所述第三元件；以及第二重佈線結構，位於所述第二元件、所述第三元件以及所述模塑化合物之上，所述第一元件及所述第二元件使用所述第二重佈線結構電耦接至所述第三元件。在一實施例中，所述第一元件包含動態隨機存取記憶體(DRAM)元件，所述第二元件包含寬輸入/輸出(WIO)記憶體元件，且所述第三元件包含系統晶片(SoC)。在一實施例中，所述第一元件包含低功率雙倍資料速率同步動態隨機存取記憶體(LPDDR)元件，所述第二元件包含寬輸入/輸出(WIO)記憶體元件，且所述第三元件包含系統晶片(SoC)。在一實施例中，所述元件更包含延伸穿過所述模塑化合物的第一導電柱，所述第一導電柱電耦接至所述第一重佈線結構及所述第二重佈線結構，所述第一元件經由所述第一導電柱電耦接至所述第三元件。在一實施例中，所述元件更包含延伸穿過所述模塑化合物的第二導電柱，所述第二導電柱電耦接至所述第二元件及所述第二重佈線結構，所述第二元件經由所述第二導電柱電耦接至所述第三元件。在一實施例中，所述元件更包含安置於所述第三元件與所述第一重佈線結構之間的虛設晶粒，所述虛設晶粒包含矽。
根據又一實施例，一種元件包含：第一晶粒，貼合至第一重佈線結構；第一模塑化合物，位於所述第一重佈線結構之上且包圍所述第一晶粒；第一穿孔，延伸穿過所述第一模塑化合物；第二重佈線結構，位於所述第一晶粒、所述第一模塑化合物以及所述第一穿孔之上；第二晶粒，貼合至所述第二重佈線結構；第二模塑化合物，位於所述第二重佈線結構之上且包圍所述第二晶粒；以及第二穿孔及第三穿孔，延伸穿過所述第二模塑化合物， 所述第二穿孔電耦接至所述第一穿孔，所述第二穿孔包含具有圓形橫截面的通孔，所述第三穿孔電耦接至所述第一晶粒，所述第三穿孔包含具有橢圓形橫截面的通孔。在一實施例中，所述第三穿孔每單位面積的分佈大於所述第二穿孔每單位面積的分佈。在一實施例中，所述第二穿孔具有在自上而下視圖中自50微米至120微米的直徑，所述第三穿孔具有在所述自上而下視圖中自20微米至35微米的寬度，且所述第三穿孔具有在所述自上而下視圖中自35微米至50微米的長度。在一實施例中，所述元件更包含接合至所述第一重佈線結構而與所述第一晶粒相對的第三晶粒，所述第三晶粒電耦接至所述第一穿孔。在一實施例中，所述元件更包含位於所述第二穿孔、所述第三穿孔、所述第二晶粒以及所述第二模塑化合物之上的第三重佈線結構，所述第二穿孔及所述第三穿孔使用所述第三重佈線結構電耦接至所述第二晶粒。在一實施例中，所述第三晶粒包含低功率雙倍資料速率同步動態隨機存取記憶體(LPDDR)元件，所述第一晶粒包含寬輸入/輸出(WIO)記憶體元件，且所述第二晶粒包含系統晶片(SoC)。在一實施例中，所述第三晶粒使用焊料接合件接合至所述第一重佈線結構，所述第一晶粒使用第一黏著劑貼合至所述第一重佈線結構，且所述第二晶粒使用第二黏著劑貼合至所述第二重佈線結構。在一實施例中，所述元件更包含延伸穿過所述第一模塑化合物的第四穿孔，所述第四穿孔與所述第一晶粒及所述第二晶粒電隔離。
前文概述若干實施例的特徵，使得所屬技術領域中具有通常知識者可更好地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露內容作為設計或修改 用於實行本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
50A、50B:主動元件晶粒
66:晶粒連接件
70、116:導電柱
106:背側重佈線結構
108、112、130、134、138、142:介電層
110、132、136、140:金屬化圖案
122:虛設晶粒
126:包封體
128:前側重佈線結構
144:UBM
146、152:導電連接件
150:封裝組件
200:經封裝半導體元件

Claims (10)

  1. 一種半導體元件的形成方法，包括：將第一導電柱形成在第一重佈線結構之上且電耦接至所述第一重佈線結構；將第一晶粒貼合至所述第一重佈線結構，所述第一晶粒包括第二導電柱；將第二晶粒貼合至所述第一晶粒，所述第二晶粒與所述第二導電柱相鄰；用包封體包封所述第一導電柱、所述第一晶粒以及所述第二晶粒；在所述包封體、所述第一導電柱、所述第一晶粒以及所述第二晶粒之上形成第二重佈線結構；以及將第三晶粒接合至所述第一重佈線結構。
  2. 如請求項1所述的半導體元件的形成方法，更包括將虛設晶粒貼合至所述第一重佈線結構，其中所述將所述第二晶粒貼合至所述第一晶粒更包括將所述第二晶粒貼合至所述虛設晶粒。
  3. 如請求項1所述的半導體元件的形成方法，其中所述第一晶粒、所述第二晶粒以及所述包封體安置於所述第一重佈線結構的第一側上，且所述第三晶粒安置於所述第一重佈線結構的與所述第一側相對的第二側上。
  4. 一種半導體元件，包括：第一元件，接合至第一重佈線結構的第一側；第二元件，貼合至所述第一重佈線結構的與所述第一側相對 的第二側；第三元件，貼合至所述第二元件；模塑化合物，包圍所述第二元件及所述第三元件；以及第二重佈線結構，位於所述第二元件、所述第三元件以及所述模塑化合物之上，其中所述第一元件及所述第二元件使用所述第二重佈線結構電耦接至所述第三元件。
  5. 如請求項4所述的半導體元件，更包括延伸穿過所述模塑化合物的第一導電柱，所述第一導電柱電耦接至所述第一重佈線結構及所述第二重佈線結構，所述第一元件經由所述第一導電柱電耦接至所述第三元件。
  6. 如請求項5所述的半導體元件，更包括延伸穿過所述模塑化合物的第二導電柱，所述第二導電柱電耦接至所述第二元件及所述第二重佈線結構，所述第二元件經由所述第二導電柱電耦接至所述第三元件。
  7. 如請求項4所述的半導體元件，更包括安置於所述第三元件與所述第一重佈線結構之間的虛設晶粒，所述虛設晶粒包括矽。
  8. 一種半導體元件，包括：第一晶粒，貼合至第一重佈線結構；第一模塑化合物，位於所述第一重佈線結構之上且包圍所述第一晶粒；第一穿孔，延伸穿過所述第一模塑化合物；第二重佈線結構，位於所述第一晶粒、所述第一模塑化合物以及所述第一穿孔之上； 第二晶粒，貼合至所述第二重佈線結構；第二模塑化合物，位於所述第二重佈線結構之上且包圍所述第二晶粒；以及第二穿孔及第三穿孔，延伸穿過所述第二模塑化合物，所述第二穿孔電耦接至所述第一穿孔，所述第二穿孔包括具有圓形橫截面的通孔，所述第三穿孔電耦接至所述第一晶粒，所述第三穿孔包括具有橢圓形橫截面的通孔。
  9. 如請求項8所述的半導體元件，其中所述第三穿孔每單位面積的分佈大於所述第二穿孔每單位面積的分佈。
  10. 如請求項8所述的半導體元件，更包括接合至所述第一重佈線結構而與所述第一晶粒相對的第三晶粒，所述第三晶粒電耦接至所述第一穿孔。
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