TWI708344B - 重佈線路結構、扇出型積體電路封裝及電性連接於至少一導體的重佈線路結構的製造方法 - Google Patents

重佈線路結構、扇出型積體電路封裝及電性連接於至少一導體的重佈線路結構的製造方法 Download PDF

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TWI708344B
TWI708344B TW105127767A TW105127767A TWI708344B TW I708344 B TWI708344 B TW I708344B TW 105127767 A TW105127767 A TW 105127767A TW 105127767 A TW105127767 A TW 105127767A TW I708344 B TWI708344 B TW I708344B
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layer
conductor
conductive
dielectric layer
redistributed
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TW201733058A (zh
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李宗徽
郭宏瑞
何明哲
黃子芸
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台灣積體電路製造股份有限公司
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Abstract

一種重佈線路結構，電性連接於位於其下方的至少一導 體。重佈線路結構包括一介電層、一對位標記及一重佈導電層。介電層覆蓋導體且包括用來暴露該導體的至少一接觸開口。對位標記配置在介電層上，對位標記包括位在介電層上的一基部及位在基部上的一凸出部，其中凸出部的一最大厚度與基部的一厚度的比值小於25%。重佈導電層配置在介電層上，重佈導電層包括一導通孔，且導通孔透過接觸開口電性連接至導體。本發明一實施例更提供一種重佈線路結構及整合扇出型封裝的製造方法。

Description

重佈線路結構、扇出型積體電路封裝及電性連 接於至少一導體的重佈線路結構的製造方法
本發明是有關於一種線路結構，且特別是有關於一種重佈線路結構。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積體密度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件整合到一給定區域內。較小的電子元件會需要面積比以往的封裝更小的較小封裝。半導體元件的其中一部分較小型式的封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
目前，整合扇出型封裝(integrated fan-out package)由於其 密實度而趨於熱門，在整合扇出型封裝中，重佈線路結構的形成在封裝過程中扮演著重要的角色。
本發明一實施例的一種重佈線路結構，電性連接於位於其下方的至少一導體。重佈線路結構包括一介電層、一對位標記及一重佈導電層。介電層覆蓋導體且包括用來暴露該導體的至少一接觸開口。對位標記配置在介電層上，對位標記包括位在介電層上的一基部及位在基部上的一凸出部，其中凸出部的一最大厚度與基部的一厚度的比值小於25%。重佈導電層配置在介電層上，重佈導電層包括一導通孔，且導通孔透過接觸開口電性連接至導體。
α 1:第一鈍角
α 2:第二鈍角
α 3:第三鈍角
α 4:第四鈍角
A、A’:最小距離
B、B’:深度
C1、C’:直徑
C:載具
D:厚度
DB:剝離層
DI:介電層
DP、DP’:凹陷
E:最大厚度
O1、O2、O3、O4、O5:接觸開口
PR:圖案化光阻層
TV:導電穿孔
TR:溝渠
RDL:重佈線路結構
100:積體電路
100a:主動表面
102:接墊
104:鈍化層
110:導電柱
120、120’:保護層
130:絕緣材料
130’:絕緣包封體
140:介電層
150:種子層
150’:圖案化種子層
150A:第一種子圖案
150B:第二種子圖案
160:圖案化導電層
162:重佈導電層
162A、162B:導通孔
164:對位標記
164A:基部
164B:凸出部
170:球底金屬層圖案
172:連接接墊
174、180:導電球
176:被動元件
190:封裝
圖1至15是依照本發明一實施例的一些實施例的重佈線路結構的製造流程示意圖。
圖10’是重佈線路結構中的導通孔與對位標記的剖面示意圖。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本發明一實施例為目的。當然，僅僅為實 例而非用以限制。此外，本發明在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在...上」、「在...上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
此處所揭露的實施例是採用具體用語進行揭露。其他實施例考慮到其他應用，此領域具有通常知識者在閱讀本發明一實施例內容之後已經可以輕易地聯想到其他應用。值得注意的是，此處所揭露的實施例並無必要說明所有出現於結構中的元件或特徵。舉例而言，單個元件的複數型態可能於圖式中省略，例如單個元件的說明將足以傳達多個實施例中的不同樣態。此外，此處所討論的方法實施例可依照特定的順序進行；然而，其他方法實施例亦可依照任何一種符合邏輯的順序進行。
圖1至15是依照本發明一實施例的一些實施例的一種重佈線路結構的製造流程示意圖。圖10’是重佈線路結構中的導通孔與對位標記的剖面示意圖。
請參考圖1，提供一載具C，此載具C具有形成於其上的一剝離層DB及一介電層DI，其中剝離層DB位在載具C及介 電層DI之間。在一些實施例中，載具C例如為一玻璃基板，剝離層DB例如為形成於玻璃基板上的一光熱轉換(light-to-heat conversion，LTHC)釋放層，且介電層DI例如為形成於剝離層DB上的一光敏聚苯噁唑(photosensitive polybenzoxazole，PBO)層。
在提供具有剝離層DB及介電層DI形成於其上的載板C之後，於介電層DI上多個導電穿孔TV形成。在一些實施例中，這些導電穿孔TV透過微影技術、電鍍及去光阻製程所形成。導電穿孔TV例如包括銅柱(copper post)。
請參考圖2，積體電路100包括至少一導電柱110及形成於其上的一保護層120，積體電路100被拾起並且放置在介電層DI上。在本實施例中，多個導電柱110透過微影技術、電鍍及去光阻製程形成在積體電路100上。導電柱110被保護層120包封。 在一些實施例中，積體電路100可包括一主動表面100a、分佈在主動表面100a上的多個接墊102及一鈍化層104，其中鈍化層104覆蓋積體電路100的主動表面100a，且接墊102部分外露於鈍化層104。導電柱110形成在積體電路100的接墊102上，且保護層120覆蓋導電柱110及鈍化層104。導電柱110例如是電鍍銅柱，且鈍化層104例如是一光敏聚苯噁唑(photosensitive polybenzoxazole，PBO)層。舉例來說，如圖2所示，保護層120的上表面低於導電穿孔TV的上表面，且保護層120的上表面高於導電柱110的上表面，但本發明一實施例並不以此為限制。
在其他的實施例中，保護層120的上表面會實質上齊平於導電穿孔TV的上表面，且保護層120的上表面會高於導電柱110的上表面。
如圖1及圖2所示，可在形成導電穿孔TV之後，將積體電路100拾起並且放置在介電層DI上。但本發明一實施例並不以此為限制。在其他實施例中，也可以是在形成導電穿孔TV之前，將積體電路100拾起並且放置在介電層DI上。
請參考圖3，在介電層DI上形成一絕緣材料130以覆蓋積體電路100及導電穿孔TV。在一些實施例中，絕緣材料130為由模製方式(molding)所形成的一模製化合物(molding compound)。積體電路100的導電柱110及保護層120被絕緣材料130覆蓋。換句話說，積體電路100的導電柱110及保護層120在絕緣材料130形成的過程中未被外露且被絕緣材料130妥善地保護。在一些實施例中，絕緣材料130包括環氧化合物或其他適當的樹脂。
請參考圖4，研磨(grinded)絕緣材料130直到導電柱110的上表面、導電穿孔TV的上表面及保護層120的上表面外露。在研磨絕緣材料130之後，形成一絕緣包封體130’。在絕緣材料130的研磨過程中，部分的保護層120被研磨以形成一保護層120’。在一些實施例中，在絕緣材料130與保護層120的研磨過程中，部分的導電穿孔TV也被研磨。絕緣材料130及保護層120例如是透過化學式機械研磨法(chemical mechanical polishing process，CMP process)研磨。如圖4所示，需注意的是，導電穿孔TV的上表面、絕緣包封體130’的上表面、導電柱110的上表面及保護層120’的上表面實質上共平面。
請參考圖5至圖11，在形成絕緣包封體130’及保護層120’之後，電性連接於積體電路100的導電柱110的一重佈線路結 構RDL(顯示於圖11)形成在導電穿孔TV的上表面、絕緣包封體130’的上表面、導電柱110的上表面及保護層120’的上表面。重佈線路結構RDL(顯示於圖11)被製造來電性連接於下方的至少一導體。在此，前述的導體可以是積體電路100的導電柱110及/或嵌埋於絕緣包封體130’的導電穿孔TV。重佈線路結構RDL(顯示於圖11)的製造將在下面圖5至圖11的敘述中被詳細介紹。
請參考圖5，一介電層140形成於導電穿孔TV的上表面、絕緣包封體130’的上表面、導電柱110的上表面及保護層120’的上表面上。介電層140包括至少一接觸開口O1及至少一接觸開口O2。在本實施例中，於介電層140內形成用來暴露導電柱110的上表面的多個接觸開口O1及用來暴露導電穿孔TV的上表面的多個接觸開口O2。需注意的是，接觸開口O1的數量對應於導電柱110的數量，且接觸開口O2的數量對應於導電穿孔TV的數量。在一些實施例中，介電層140例如是一光敏聚苯噁唑(photosensitive polybenzoxazole，PBO)層。
請參考圖6，在形成具有接觸開口O1及接觸開口O2的介電層140之後，一種子層150例如共型地濺鍍在介電層140、導電柱110的被接觸開口O1所暴露的上表面及導電穿孔TV被接觸開口O2所暴露的上表面。在一些實施例中，種子層150例如是為一鈦/銅複合層，其中鈦濺鍍薄膜接觸介電層140、導電柱110的被接觸開口O1所暴露的上表面及導電穿孔TV被接觸開口O2所暴露的上表面。此外，銅濺鍍薄膜形成在鈦濺鍍薄膜上。
請參考圖7，一圖案化光阻層PR形成在種子層150上，其中圖案化光阻層PR包括至少一開口O3、至少一開口O4及至少 一溝渠TR。在本實施例中，在圖案化光阻層PR中形成多個開口O3及多個開口O4。需注意的是，開口O3的數量對應於接觸開口O1的數量，且開口O4的數量對應於接觸開口O2的數量。溝渠TR的數量並不以本發明一實施例為限。開口O3位在接觸開口O1的上方，且開口O4位在接觸開口O2的上方。如圖7所示，部分的種子層150被開口O3、開口O4及溝渠TR暴露。
請參考圖8，在形成圖案化光阻層PR之後，進行一多步驟電鍍製程以在種子層150被開口O3、開口O4及溝渠TR所暴露的部分上形成一圖案化導電層160。利用多步驟電鍍製程形成的圖案化導電層160可包括一重佈導電層162及至少一對位標記164，其中重佈導電層162形成在開口O3及開口O4內，且對位標記164形成在溝渠TR內。重佈導電層162包括透過接觸開口O1電性連接於導電柱110的至少一導通孔162A及透過接觸開口O2電性連接於導電穿孔TV的至少一導通孔162B。在本實施例中，多個導通孔162A及導通孔162B被電鍍在種子層150外露於圖案化光阻層PR的部分。需注意的是，導通孔162A的數量對應於導電柱110的數量，且導通孔162B的數量對應於導電穿孔TV的數量。此外，對位標記164的數量對應於溝渠TR的數量。
如圖8所示，於種子層150外露於接觸開口O1及開口O3的部分上電鍍導通孔162A，於種子層150外露於接觸開口O2及開口O4的部分上電鍍導通孔162B，且於種子層150外露於溝渠TR的部分上電鍍對位標記164。導通孔162A形成在導電柱110上方，且導通孔162B形成在導電穿孔TV上方。
在一些實施例中，形成圖案化導電層160的多步驟電鍍製程可包括兩電鍍製程，例如，進行一第一電鍍製程以在種子層150外露於開口O3、開口O4及溝渠TR的部分形成一第一電鍍導電層，且接著進行一第二電鍍製程以在第一電鍍導電層上形成一第二電鍍導電層。即便是第一電鍍導電層與第二電鍍導電層是利用不同的電鍍製程所形成，第一電鍍導電層與第二電鍍導電層之間可沒有明顯的介面。
需注意的是，第一電鍍製程在較高電鍍電流密度(例如大於2ASD)及/或低擾動(weak agitation)下進行，且第二電鍍製程在較低電鍍電流密度(例如小於2ASD)及/或高擾動下進行。
在其他的實施例中，多步驟電鍍製程包括超過兩個電鍍步驟，且超過兩個堆疊且電鍍導電層形成在種子層150上。
請參考圖9，在進行多步驟電鍍製程之後，剝除圖案化光阻層PR，以使種子層150上未被重佈導電層162及對位標記164覆蓋的部分外露。
請參考圖10，藉由使用重佈導電層162及對位標記164作為硬罩幕(hard mask)，移除種子層150尚未被重佈導電層162及對位標記164覆蓋的部分，以形成一圖案化種子層150’。圖案化種子層150’包括至少一第一種子圖案150A及至少一第二種子圖案150B，其中第一種子圖案150A形成於積體電路100的導電柱110及重佈導電層162的導通孔162A之間，且第二種子圖案150B形成於積體電路100的介電層140及對位標記164之間。在一些實施例中，種子層150利用蝕刻來圖案化，直到介電層140外露。
在種子層150的圖案化過程中，由於透過多步驟電鍍製程所形成的重佈導電層162的上表面及對位標記164的上表面是平坦且光滑的，重佈導電層162及對位標記164受蝕刻製程所造成的損害狀況可最小化。換句話說，應用於圖案化種子層150的蝕刻製程不會造成重佈導電層162的上表面及對位標記164的上表面的嚴重損害。據此，重佈導電層162的導通孔162A及162B具有良好的穿孔填充能力(via filling capability)，且在進行對位過程中，對位標記164能輕易地被辨識出來。
在一些實施例中，導電柱110至導通孔162A的上表面的最小距離大於對位標記164的最大厚度；且導電穿孔TV至導通孔162B的上表面的最小距離大於對位標記164的最大厚度。
在一些實施例中，透過多步驟電鍍製程所形成的導通孔162A及導通孔162B可包括平坦且光滑的上表面，且在導通孔162A及導通孔162B的上表面上幾乎沒有明顯的凹陷。然而，本發明一實施例並不以此為限制。在其他的實施例中，如圖10’所示，在進行多步驟電鍍製程之後，於導通孔162A及導通孔162B的上表面形成凹陷，且對位標記164可具有一穹頂型(dome-shaped)上表面。
請參考圖10’，導通孔162A包括在其上表面上的一凹陷DP，且導電柱110至導通孔162A的上表面或是導電柱110至凹陷DP的底部的最小距離A大於凹陷DP的深度B。例如，導電柱110至導通孔162A的上表面或是導電柱110至凹陷DP底部的最小距離A在2微米至12微米之間，且凹陷DP的深度B小於0.5 微米。導電柱110的暴露區域外露於接觸開口O1，且此暴露區域的直徑C1例如是小於等於50微米。
同樣地，在一些實施例中，導通孔162B包括在其上表面上的一凹陷DP’，且導電穿孔TV至導通孔162B的上表面或是導電穿孔TV至凹陷DP’的底部的最小距離A’大於凹陷DP’的深度B’。例如，導電穿孔TV至導通孔162B的上表面或是導電穿孔TV至凹陷DP’的底部的最小距離A’在2微米至12微米之間，且凹陷DP’的深度B’小於0.5微米。導電穿孔TV的暴露區域外露於接觸開口O2，且此暴露區域的直徑C’例如是小於等於50微米。
如圖10’所示，凹陷DP分佈於接觸開口O1的上方與外部，且凹陷DP’分佈於接觸開口O2的上方與外部。
如圖10’所示，其中一個導電柱110的一暴露區域外露於接觸開口O1，介電層140具有環繞接觸開口O1的一第一側牆，導電柱110的暴露區域與第一側牆之間夾有一第一鈍角α1。導通孔162A具有環繞凹陷DP的一第二側牆，凹陷DP的底部與第二側牆之間夾有一第二鈍角α2，且第二鈍角α2大於第一鈍角α1。同樣地，其中一個導電穿孔TV的一暴露區域外露於接觸開口O2，介電層140具有環繞接觸開口O2的一第三側牆，導電穿孔TV的暴露區域與第三側牆之間夾有一第三鈍角α3，導通孔162A具有環繞凹陷DP’的一第四側牆，凹陷DP’的底部與第四側牆之間夾有一第四鈍角α4，且第四鈍角α4大於第三鈍角α3。
請參考圖10’，對位標記164可包括介電層140上的一基部164A及基部164A上的一凸出部164B，其中凸出部164B包括穹頂型上表面，且凸出部164B的最大厚度E與基部164A的厚 度D的比值小於25%。在一些實施例中，導電柱110至導通孔162A的上表面或導電柱110至凹陷DP的底部的最小距離A大於凸出部164B的最大厚度E及基部164A的厚度D的總和(即D+E)。換句話說，最小距離A大於對位標記164的最大厚度。舉例來說，凸出部164B的最大厚度E小於0.5微米，且基部164A的厚度D在1.5微米至27微米之間。
在前述實施例中，由於重佈導電層162及對位標記164透過多步驟電鍍製程所形成，重佈導電層162的導通孔162A及162B可具有良好的穿孔填充能力、高印刷解析度(lithography resolution)及短訊號傳遞路徑的優點；且對位標記164可具有高印刷解析度及良好的表面輪廓(surface profile)的優點。
請參考圖11，在形成介電層140及圖案化導電層160之後，圖5至圖10的步驟可再重複至少一次，以在積體電路100及絕緣包封體130’上製作重佈線路結構RDL。重佈線路結構RDL包括交替堆疊的多個介電層及多個圖案化導電層。在一些實施例中，重佈線路結構RDL的最上層圖案化導電層可包括用來電性連接於導電球的多個球底金屬層圖案170及/或用來電性連接於至少一被動元件的至少一連接接墊172。在本實施例中，形成多個連接接墊172。球底金屬層圖案170及連接接墊172的數量並不以本發明一實施例為限制。
請參考圖12，在形成重佈線路結構RDL之後，在球底金屬層圖案170上放置多個導電球174，且在連接接墊172上裝配(mounted)多個被動元件176。在一些實施例中，導電球174可透 過植球製程(ball placement process)放置在球底金屬層圖案170上，且被動元件176可透過迴焊製程裝配在連接接墊172上。
請參考圖12及圖13，在形成導電球174及被動元件176之後，將介電層DI從剝離層DB移除，以使介電層DI分離於載板C。在一些實施例中，剝離層DB(例如，光熱轉換釋放層)可被紫外光雷射照射，而使介電層DI剝離於載板C。如圖13所示，接著圖案化介電層DI，以形成暴露導電穿孔TV的底表面的多個接觸開口O5。接觸開口O5的數量對應於導電穿孔TV的數量。
請參考圖14，在接觸開口O5形成於介電層DI之後，在被接觸開口O5所暴露的導電穿孔TV的底表面放置多個導電球180。並且，導電球180例如是透過回焊以連接於導電穿孔TV的底表面。如圖14所示，在形成導電球174及導電球180之後，具有雙側端子的積體電路100的一整合扇出型封裝完成。
請參考圖15，其提供另一種封裝190。在一些實施例中，封裝190例如是一記憶體裝置。封裝190堆疊且透過導電球180電性連接於圖14的整合扇出型封裝，以製造出一堆疊式封裝(package on package，POP)結構。
一種重佈線路結構，電性連接於位於其下方的至少一導體。重佈線路結構包括一介電層、一對位標記及一重佈導電層。介電層覆蓋導體且包括用來暴露該導體的至少一接觸開口。對位標記配置在介電層上，對位標記包括位在介電層上的一基部及位在基部上的一凸出部，其中凸出部的一最大厚度與基部的一厚度的比值小於25%。重佈導電層配置在介電層上，重佈導電層包括一導通孔，且導通孔透過接觸開口電性連接至導體。
一種扇出型積體電路封裝，包括一積體電路、一絕緣包封體、一重佈線路結構。積體電路包括至少一導電柱。絕緣包封體包封積體電路且外露積體電路的導電柱。重佈線路結構設置在積體電路與絕緣包封體上，且電性連接至積體電路的導電柱。重佈線路結構包括一介電層、一對位標記及一重佈導電層。介電層覆蓋積體電路與絕緣包封體且包括用來暴露導電柱的至少一接觸開口。對位標記配置在介電層上，對位標記包括位在介電層上的一基部及位在基部上的一凸出部，其中凸出部的一最大厚度與基部的一厚度的比值小於25%。重佈導電層配置在介電層上，重佈導電層包括一導通孔，且導通孔透過接觸開口電性連接至導體。
一種電性連接於位於其下方的至少一導體的重佈線路結構的製造方法，包括：形成覆蓋於導體的一介電層，介電層包括用來暴露該導體的至少一接觸開口；形成一種子層以覆蓋介電層與導體。於種子層上形成一圖案化光阻層，圖案化光阻層包括至少一開口及至少一溝渠，種子層外露於開口及溝渠；進行一多步驟電鍍製程以在種子層被開口及溝渠所暴露的部分上形成一圖案化導電層，圖案化導電層包括形成在開口的至少一重佈導電層及形成在溝渠的至少一對位標記，重佈導電層包括至少一導通孔，且導通孔透過接觸開口電性連接至導體，其中對位標記包括位在介電層上的一基部及位在基部上的一凸出部，其中凸出部的一最大厚度與基部的一厚度的比值小於25%；移除圖案化光阻層；在移除圖案化光阻層之後，移除未被重佈導電層與對位標記所覆蓋的種子層以形成一圖案化種子層。
以上概述了多個實施例的特徵，使本領域具有通常知識 者可更佳了解本發明一實施例的態樣。本領域具有通常知識者應理解，其可輕易地使用本發明一實施例作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本發明一實施例的精神與範疇，且本領域具有通常知識者在不悖離本發明一實施例的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
α 1:第一鈍角
α 2:第二鈍角
α 3:第三鈍角
α 4:第四鈍角
A、A’:最小距離
B、B’:深度
C1、C’:直徑
D:厚度
DP、DP’:凹陷
E:最大厚度
O1、O2:接觸開口
TV:導電穿孔
102:接墊
104:鈍化層
110:導電柱
120’:保護層
140:介電層
150A:第一種子圖案
150B:第二種子圖案
162A、162B:導通孔
164:對位標記
164A:基部
164B:凸出部

Claims (10)

  1. 一種重佈線路結構，電性連接於位於其下方的至少一導體，該重佈線路結構包括：一介電層，覆蓋該導體，且該介電層包括用來暴露該導體的至少一接觸開口；一對位標記，配置在該介電層上，該對位標記包括位在該介電層上的一基部以及位在該基部上的一凸出部，其中該凸出部的一最大厚度與該基部的一厚度的比值小於25%；以及一重佈導電層，配置在該介電層上，該重佈導電層包括一導通孔，其中該導通孔透過該接觸開口電性連接至該導體，該對位標記及該導體被該介電層隔開於彼此，且該導通孔包括在其上表面上的一凹陷，且該導體至該凹陷的一底部的最小距離大於該凹陷的深度。
  2. 如申請專利範圍第1項所述的重佈線路結構，其中該導體至該導通孔的一上表面的最小距離大於該凸出部的最大厚度及該基部的厚度的總和。
  3. 如申請專利範圍第1項所述的重佈線路結構，其中該導體的一暴露區域外露於該接觸開口，該介電層具有環繞該接觸開口的一第一側牆，該暴露區域與該第一側牆之間夾有一第一鈍角，該導通孔具有環繞該凹陷的一第二側牆，該凹陷的一底部與該第二側牆之間夾有一第二鈍角，且第二鈍角大於第一鈍角。
  4. 如申請專利範圍第1項所述的重佈線路結構，更包括： 一圖案化種子層，包括形成於該導體與該重佈導電層之間的至少一第一種子圖案以及形成於該介電層與該對位標記之間的至少一第二種子圖案。
  5. 一種扇出型積體電路封裝，包括：一積體電路，包括至少一導電柱；一絕緣包封體，包封該積體電路且外露該積體電路的該導電柱；以及一重佈線路結構，設置在該積體電路與該絕緣包封體上，且電性連接至該積體電路的該導電柱，該重佈線路結構包括：一介電層，覆蓋該積體電路與該絕緣包封體且包括用來暴露該導電柱的至少一接觸開口；一對位標記，配置在該介電層上，該對位標記包括位在該介電層上的一基部及位在該基部上的一凸出部，其中該凸出部的一最大厚度與該基部的一厚度的比值小於25%；以及一重佈導電層，配置在該介電層上，該重佈導電層包括一導通孔，且該導通孔透過該接觸開口電性連接至該導電柱，該對位標記及該導電柱被該介電層隔開於彼此，且該導通孔包括在其上表面上的一凹陷，且該導電柱至該凹陷的一底部的最小距離大於該凹陷的深度。
  6. 如申請專利範圍第5項所述的扇出型積體電路封裝，其中該導電柱至該導通孔的一上表面的最小距離大於該凸出部的最大厚度及該基部的厚度的總和。
  7. 如申請專利範圍第5項所述的扇出型積體電路封裝，其中該重佈線路結構更包括：一圖案化種子層，包括形成於該導電柱與該重佈導電層之間的至少一第一種子圖案以及形成於該介電層與該對位標記之間的至少一第二種子圖案。
  8. 一種電性連接於至少一導體的重佈線路結構的製造方法，包括：形成覆蓋於該導體的一介電層，該介電層包括用來暴露該導體的至少一接觸開口；形成一種子層以覆蓋該介電層與該導體；於該種子層上形成一圖案化光阻層，該圖案化光阻層包括至少一開口及至少一溝渠，該種子層外露於該至少一開口及該至少一溝渠；進行一多步驟電鍍製程以在該種子層被該至少一開口及該至少一溝渠所暴露的部分上形成一圖案化導電層，該圖案化導電層包括形成在該至少一開口的至少一重佈導電層及形成在該至少一溝渠的至少一對位標記，該重佈導電層包括至少一導通孔，且該至少一導通孔透過該至少一接觸開口電性連接至該導體，其中該多步驟電鍍製程包括多個電鍍步驟，在該些電鍍步驟中一先電鍍步驟的電鍍電流密度與擾動(agitation)大於一後電鍍步驟的電鍍電流密度與擾動；移除該圖案化光阻層；以及 在移除該圖案化光阻層之後，移除未被該重佈導電層與該對位標記所覆蓋的該種子層以形成一圖案化種子層。
  9. 一種電性連接於至少一導體的重佈線路結構的製造方法，包括：形成覆蓋於該導體的一介電層，該介電層包括用來暴露該導體的至少一接觸開口；形成一種子層以覆蓋該介電層與該導體；於該種子層上形成一圖案化光阻層，該圖案化光阻層包括至少一開口及至少一溝渠，該種子層外露於該至少一開口及該至少一溝渠；進行一多步驟電鍍製程以在該種子層被該至少一開口及該至少一溝渠所暴露的部分上形成一圖案化導電層，該圖案化導電層包括形成在該至少一開口的至少一重佈導電層及形成在該至少一溝渠的至少一對位標記，該重佈導電層包括至少一導通孔，該至少一導通孔透過該至少一接觸開口電性連接至該導體，其中該多步驟電鍍製程包括在一第一擾動下進行的一第一電鍍步驟及在一第二擾動下進行的一第二電鍍步驟，該第二擾動強於第一擾動；移除該圖案化光阻層；以及在移除該圖案化光阻層之後，移除未被該重佈導電層與該對位標記所覆蓋的該種子層以形成一圖案化種子層。
  10. 一種電性連接於至少一導體的重佈線路結構的製造方法，包括： 形成覆蓋於該導體的一介電層，該介電層包括用來暴露該導體的至少一接觸開口；形成一種子層以覆蓋該介電層與該導體；於該種子層上形成一圖案化光阻層，該圖案化光阻層包括至少一開口及至少一溝渠，該種子層外露於該至少一開口及該至少一溝渠；進行一多步驟電鍍製程以在該種子層被該至少一開口及該至少一溝渠所暴露的部分上形成一圖案化導電層，該圖案化導電層包括形成在該至少一開口的至少一重佈導電層及形成在該至少一溝渠的至少一對位標記，該重佈導電層包括至少一導通孔，且該至少一導通孔透過該至少一接觸開口電性連接至該導體，其中該對位標記包括位在該介電層上的一基部及位在該基部上的一凸出部，其中該凸出部的一最大厚度與該基部的一厚度的比值小於25%；移除該圖案化光阻層；以及在移除該圖案化光阻層之後，移除未被該重佈導電層與該對位標記所覆蓋的該種子層以形成一圖案化種子層。
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